Qubit array chip, quantum computer

Abstract

To accelerate the transition time of a current supplied to a quantum bit.SOLUTION: A quantum bit array chip comprises: a semiconductor layer; an insulating layer disposed on the semiconductor layer; a plurality of first gate electrodes which are disposed on the insulating layer and which apply voltage to trap electrons having a predetermined spin state in the semiconductor layer; a plurality of second gate electrodes which are adjacent to the first gate electrodes and alternately disposed with the first gate electrodes in order to allow a current for forming a magnetic field that acts on an electron to flow in an extension direction of the first gate electrodes when the spin state of the electron is changed; and a third gate electrode having substantially the same resistance as the second gate electrodes. If the spin state of the electron trapped by the first gate electrode is changed, the quantum bit array chip controls to allow a current to flow to the third gate electrode, and after the current has stabilized, to stop the current to the third gate electrode, and allow a current to flow to the second gate electrode.SELECTED DRAWING: Figure 8A

Description

[Technical Field]

[0001] The present invention relates to a quantum bit array chip and a quantum computer in which quantum bits are arranged and integrated in an array in order to perform quantum computing. [Background technology]

[0002] Quantum computers have been attracting attention in recent years. The miniaturization and performance of semiconductor elements, which have supported the advancement of computers to date, are reaching their limits, making it difficult to significantly improve the performance of conventional classical computers. Quantum computers are one attempt to overcome these limitations by using new computational principles and devices. Currently, hardware development is underway with the aim of realizing quantum computers, and various types of quantum bits, the computing elements at the heart of quantum computers, have been proposed, including superconducting, ion-trap, and silicon types.

[0003] The overall configuration of silicon quantum computer 1000 is shown in Figure 1. Quantum bits (Qubits) 102, which are quantum operation devices, are arranged in an array and mounted on a quantum bit array chip (QBA101), which is fabricated as a silicon chip. QBA101 controls the quantum bits for quantum operations and senses the quantum information of the operation results. A cryogenic analog control chip (CAC) 103 supplies quantum operation patterns, operation timing, bias voltage, and RF signals to QBA101. This CAC 103 is controlled by a host computer and a digital control chip (CDC) 104, which has a bridge function, and receives the results of operations performed by QBA101.

[0004] To ensure stable operation of the quantum bits, QBA101 is placed inside the dilution refrigerator DR and operates at an extremely low temperature of around 0.1 K. CAC103, which controls it, is placed inside the dilution refrigerator DR in an environment of around 4 K. The host computer and CDC104 operate at room temperature.

[0005] Figure 2A shows a cross-sectional view of the Qubit array mounted on the QBA. In this QBA, the Qubit is the spin S of a single electron trapped within a potential barrier PB formed in a Si channel C of a MOS structure. Figure 2A(a) shows the state in which an electron is trapped directly under the quantum dot control gate XQ201 by increasing the voltage of the quantum dot control gate XQ201 and decreasing the voltage of the interaction control gate XJ202. The operation of the Qubit is controlled by irradiating it with a high-frequency RF signal, as shown in Figure 2B(b). A magnetic field B is applied to the Qubit in the array, and the precession frequency f S is set to 20.01 GHz for the selected bits and 20 GHz for the unselected bits. When an RF signal with a frequency of 20.01 GHz is irradiated to the entire array, the spin of only the selected bits, whose precession frequency matches the RF frequency, is rotated, allowing quantum operations to be performed.

[0006] In a Qubit array, Qubits are arranged two-dimensionally in the X and Y directions, as shown in Figure 3. The first layer of gate wiring in the MOS structure consists of quantum dot control gate lines XQ2022 and interaction control gates XJ2021 arranged in multiple rows in the X direction, while the second layer of gate wiring consists of quantum dot control gate lines YQ2032 and interaction control gates YJ2031 arranged in multiple rows in the Y direction. To make the diagram easier to see, the diagram shows the space between the first layer of gate wiring and the silicon channel C expanded in the Z direction. This array structure enables large-scale integration of quantum bits while suppressing an increase in the total number of wiring lines.

[0007] As a technology using such quantum bits, for example, the technology described in Patent Document 1 is disclosed. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] WO2021 / 251175 Summary of the Invention [Problem to be solved by the invention]

[0009] The issues with the prior art typified by Patent Document 1 will be specifically explained using the circuit diagram of a Qubit array shown in Figure 4. In this circuit diagram, a pre-processing array 402 and a post-processing array 403 are arranged on either side of a central calculation array 401. The array alternates between quantum dot control gate MOSs (with gates connected to XQ or YQ) and interaction control gate MOSs (with gates connected to XJ). The silicon channels of the SOI structure are connected in the X direction, enabling electron movement and interaction between Qubits via transfer gates. In addition, an interaction control gate MOS (with gates connected to YJ) is arranged to connect the silicon channel in the Y direction, enabling electron movement and interaction in the Y direction as well.

[0010] The arithmetic array 401 has 128 MOS transistors used as qubits arranged in 8 rows x 16 columns. The pre-processing array 402 and post-processing array 403 also have 2 and 4 columns of MOS transistors for quantum dots, respectively. At the end of the array, one side of the silicon channel in both the X and Y directions is commonly connected to the reservoir terminal Nres, and the other side is separated as a DOE / DOS terminal. Although not shown as wiring, the RF signal RFQB is arranged on this array using multi-layer wiring.

[0011] First, we will explain the first problem that this invention solves. In this chip, the operations that target a single Qubit are spin rotation around the X axis (Rx) and spin rotation around the Y axis (Ry). These rotate the direction of the spin that holds the quantum information of the Qubit by 90 degrees around the X and Y axes of the Bloch sphere, respectively.

[0012] As an example of control when performing Rx / Ry calculations, control using a dynamic resonant frequency change method is shown in Figures 5A and 5B. Figure 5B(b) shows an example of the operating waveform when operating Qubit qb00 using the array circuit diagram in Figure 5A(a). First, a static magnetic field is applied to the entire chip, setting the resonant frequency of the precession of the electron spins in all quantum bits to 20 GHz.

[0013] When performing calculations, V is applied between terminals XJN1 and XJS1, and between terminals XJN2 and XJS2. L1 -V L2 A voltage of 20µA is applied from XJS1 to XJN1 and from XJN2 to XJS2. Furthermore, V is applied between terminals YJW0 and YJE0, and between terminals YJW1 and YJW1. L3 -V L4 A voltage of 1 mA is applied from YJW0 to YJE0 and from YJE1 to YJW1. The local magnetic field generated by this current causes the resonant frequency f of the spin precession of electrons in qb00. qb00 In this state, the RF signal RFQB of 20.01 GHz is applied to the entire chip with a period of Rabi oscillation t RB If the RF signal is applied for only a quarter of the time, only the electron spins in qb00 with the same resonance frequency can be selectively rotated by 90°. If the phase of the RF signal is matched to the phase of the spin precession, rotation around the X axis will occur, and if there is a 90° difference, rotation around the Y axis will be realized. Finally, the voltages applied between terminals XJN1 and XJS1, between XJN2 and XJS2, between YJW0 and YJE0, and between YJW1 and YJE1 are inverted, and f qb00 After setting the frequency to 19.99 GHz, the system waits for the same period of time to compensate for the phase change in the spin precession.

[0014] Figure 6 shows the relationship between the 20 GHz reference signal, RF signal, and spin phases as a result of this calculation. At t=0, the frequency of the RF wave f RF When the frequency is changed from 20 GHz to 20.01 GHz at time 0, the phase difference φ between the RF wave and the reference signal RFThe frequency increases at a rate of 0.5 ps per 1 ns. This frequency switching is performed inside the CAC and can be performed very quickly.

[0015] On the other hand, by supplying a current to the Qubit, the spin frequency f S To increase the current from 20 GHz to 20.01 GHz, the rise time t R The phase difference φ between the spin and the reference signal is S is t=t R Later, the spin frequency becomes 20.01 GHz, so it increases at 0.5 ps per 1 ns, just like RF, but from t=0 to t=t R Since the frequency has not reached 20.01 GHz until S The phase change of t is smaller than that. R The phase difference between RF and spin after t=t R The phase difference φ from each reference signal at RF0 , φ S0 Using φ RF0 -φ S0 becomes.

[0016] To maintain the fidelity of quantum computation, that is, the accuracy of computation, it is necessary to make the phase difference between the RF wave and the spin sufficiently small. S Assuming that varies linearly, φ RF0 -φ S0 To keep the rise time of the signal to 1 ps or less, which is 2% of the RF period of 50 ps, ​​the signal rise time must be 4 ns or less. Although the waveform during current transitions is expected to change due to the control circuit, to sufficiently increase fidelity, the signal transition time must be kept to a few ns or less.

[0017] Figure 7A(a) shows the current supply path from the CAC to the Qubit array in the QBA. The CAC is in the 4K chamber of the dilution refrigerator, and the QBA is in the 100mK chamber, so they are connected by a coaxial or twisted cable several meters long. Therefore, the voltage V L3 , VL4 The cable that supplies the power has a parasitic resistance R of the order of several tens of ohms. W and a parasitic capacitance C of several hundred pF W is attached.

[0018] In the QBA, the quantum bit control gates in the Qubit array (here, the gates connecting YJW0 and YJE0) have a parasitic resistance R Q The current switches SW0 and SE0 that control the current flowing through them also have parasitic resistance R S have.

[0019] The operating waveforms are shown in Figure 7B(b). First, during the period (1), the two voltage buffers in the CAC supply voltage V L3 ,V L4 However, since all the switches are OFF, the voltage supply nodes NW and NE are V L3 , V L4 Then, in the period (2), the current switches SW0 and SE0 are turned on to allow current to flow between the quantum bit gates YJW0 and YJE0. W , switch on resistance R S , the gate wiring resistance R of the Qubit array Q The potentials of NH and NL are V L3I , V L4I and a stable 1mA current I0 begins to flow. After that, an RF signal is emitted and rotation around the X and Y axes is calculated. Finally, during the period (3), the switch is turned off and the device returns to standby mode.

[0020] However, in this case, the parasitic capacitance of the cable, C W Because of the large potential, it takes time t for the potential to stabilize and the current value of the Qubit array to stabilize at 1 mA, which is sufficient for the frequency change. R0 Therefore, it is difficult to maintain a sufficiently high level of fidelity with this method.

[0021] A first problem to be solved by the present invention is to speed up the transition time of the current supplied to the quantum bit in order to increase the fidelity of the calculation of the spin rotation around the X axis and the spin rotation around the Y axis. One aspect of the present invention aims to provide a quantum bit array chip and a quantum computer for solving the problem.

[0022] Next, we will discuss the second problem that this invention solves. As shown in Figure 4, a Qubit array has more than 100 control lines. When performing quantum computations, it is necessary to apply approximately eight types of bias voltages to the terminals of each control line and switch them over time. Therefore, if the connection between the control terminals and the bias voltages were simply switched using a signal input from outside the QBA, the number of required signals would exceed 800. On the other hand, it is desirable to limit the number of input / output terminals of a QBA to around 100 to 200 from the perspective of chip size.

[0023] A second problem to be solved by the present invention is to realize control that enables switching between multiple bias voltages for a large number of quantum bit arrays while reducing the number of external input terminals of the QBA. One aspect of the present invention aims to provide a quantum bit array chip and a quantum computer that solves this problem. [Means for solving the problem]

[0024] A quantum bit array chip according to one aspect of the present invention comprises: a semiconductor layer; an insulating layer disposed on the semiconductor layer; a plurality of first gate electrodes disposed on the insulating layer, the first gate electrodes configured to trap electrons of a predetermined spin state in the semiconductor layer by applying a voltage; a plurality of second gate electrodes adjacent to the first gate electrodes and arranged alternately with the first gate electrodes, the second gate electrodes configured to pass a current in the extension direction of the first gate electrodes to form a magnetic field acting on the electrons when the spin state of the electrons is to be changed; and a third gate electrode having substantially the same resistance as the second gate electrodes, wherein when the spin state of the electrons trapped in the first gate electrodes is to be changed, a current is passed through the third gate electrodes, and after the current has stabilized, the current through the third gate electrodes is stopped and a current is passed through the second gate electrodes.

[0025] a first-direction second gate electrode and a second-direction second gate electrode adjacent to the first gate electrode, the first-direction second gate electrode and the second-direction second gate electrode being adjacent to the first gate electrode, respectively; a quantum bit array chip according to one embodiment of the present invention includes a semiconductor layer, an insulating layer disposed on the semiconductor layer, a plurality of first gate electrodes disposed on the insulating layer and configured to trap electrons of a predetermined spin state in the semiconductor layer by applying a voltage thereto; and a plurality of second gate electrodes adjacent to the first gate electrode and arranged alternately with the first gate electrodes, wherein, when changing the spin state of the electrons, currents are passed in different directions through two of the second gate electrodes adjacent to the first gate electrode, namely, a first-direction second gate electrode and a second-direction second gate electrode, thereby strengthening the magnetic field acting on the electrons; and a plurality of third gate electrodes having substantially the same resistance as the second gate electrodes, wherein, when changing the spin state of the electrons trapped in the first gate electrode, currents are passed through two of the third gate electrodes, namely, a first-direction third gate electrode and a second-direction third gate electrode, and after the current has stabilized, the current through the third gate electrode is stopped, and control is performed to pass currents in different directions through the two first-direction second gate electrode and the second-direction second gate electrode.

[0026] Furthermore, a quantum bit computer according to one aspect of the present invention is configured as a quantum bit computer comprising: a semiconductor layer; an insulating layer disposed on the semiconductor layer; a plurality of first gate electrodes disposed on the insulating layer, the first gate electrodes configured to trap electrons of a predetermined spin state in the semiconductor layer by applying a voltage thereto; and a plurality of second gate electrodes adjacent to the first gate electrodes and arranged alternately with the first gate electrodes to pass a current in the extension direction of the first gate electrodes to form a magnetic field acting on the electrons when the spin state of the electrons is changed; a first chip carrying the quantum bit array; a second chip controlling the first chip; and a cable connecting the first chip and the second chip; wherein, when a current is supplied from a voltage output buffer of the second chip to the second gate electrodes of the quantum bit array on the first chip, the voltage output buffer outputs a first voltage during standby, outputs a second voltage in the initial stage of supplying the current, and outputs a third voltage that is substantially the same as the first voltage when the current has stabilized.

[0027] a switch matrix that controls a voltage to be output to the gate electrodes in accordance with a voltage supplied from an external chip; bias voltage supply terminals that output the controlled voltage to the gate electrodes; and a register for generating an array control signal for the quantum bit array chip, wherein bias voltages are supplied to the gate electrodes from the plurality of bias voltage supply terminals via the switch matrix, and the register is capable of selecting a voltage to be supplied to each of the gate electrodes, and stores the bias voltages to be supplied in correspondence with the gate electrodes to which the bias voltages are supplied. [Effects of the Invention]

[0028] According to one aspect of the present invention, the resonant frequency of a quantum bit can be switched at high speed, and high fidelity can be maintained when performing rotation operations around the X axis and rotation operations around the Y axis, which are types of quantum operations.

[0029] Furthermore, according to one aspect of the present invention, it is possible to supply multiple bias voltages to a large number of quantum bit control lines while reducing the number of chip input terminals and increasing processing speed. Problems, configurations, and effects other than those described above will become apparent from the following description of the preferred embodiment of the present invention. [Brief explanation of the drawings]

[0030] [Figure 1] FIG. 1 illustrates a silicon quantum computer. [Figure 2A] FIG. 1 illustrates a silicon qubit structure. [Figure 2B] 2B is a diagram illustrating a quantum operation scheme in the silicon qubit structure shown in FIG. 2A. [Figure 3] FIG. 1 illustrates a silicon qubit array structure. [Figure 4] FIG. 1 is a circuit diagram of a quantum bit array. [Figure 5A] FIG. 1 is a circuit diagram of a dynamic resonant frequency change method. [Figure 5B] 5B is an operational waveform in the circuit diagram of the dynamic resonant frequency changing method shown in FIG. 5A. [Figure 6] FIG. 1 is a diagram illustrating the phase of spin precession. [Figure 7A] FIG. 1 is a circuit diagram of a current supply path to a conventional QBA. [Figure 7B] 7B is an operational waveform in the circuit diagram of the current supply path to the conventional QBA shown in FIG. 7A. [Figure 8A] FIG. 10 is a circuit diagram of a current supply path to the first QBA of the present embodiment. [Figure 8B] 8B is an operational waveform in the circuit diagram of the current supply path to the first QBA of the present embodiment shown in FIG. 8A. [Figure 9A]FIG. 10 is a circuit diagram of a current supply path to a second QBA in this embodiment. [Figure 9B] 10 is an operational waveform in a circuit diagram of a current supply path to the second QBA of the present embodiment. [Figure 10A] FIG. 10 is a diagram showing the results of a circuit simulation. [Figure 10B] FIG. 10 is a diagram showing the results of a circuit simulation. [Figure 11A] FIG. 10 is a circuit diagram of a current supply path to the third QBA of the present embodiment. [Figure 11B] 10 is an operational waveform in a circuit diagram of a current supply path to the third QBA of the present embodiment. [Figure 12] FIG. 1 is a diagram illustrating the configuration of a QBA. [Figure 13] FIG. 1 is a diagram illustrating an interface method between CAC and QBA. [Figure 14] FIG. 2 is a diagram illustrating a block configuration of a switch control register and a switch matrix according to the present embodiment. [Figure 15] FIG. 2 is a diagram illustrating a configuration of a switch control register according to the present embodiment. [Figure 16] FIG. 1 is a diagram illustrating a silicon quantum bit structure in this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0031] Each embodiment will be described below with reference to the drawings. In each embodiment shown below, a QBA having a Qubit array in which quantum dot control gate MOS (gates connected to XQ or YQ) and interaction control gate MOS (gates connected to XJ) are alternately arranged as shown in FIG. [Example]

[0032] A first embodiment of the present invention is shown in Figures 8A and 8B. Figure 8A(a) shows the current supply path from the CAC to the Qubit array in the QBA of this embodiment. As in Figure 7A, the CAC 803 is in the 4K chamber of the dilution refrigerator, and the QBA 801 is in the 100mK chamber, so the two are connected by a coaxial cable or twisted cable several meters long. Therefore, the voltage V L3 , V L4 The cable that supplies the power has a parasitic resistance R of the order of several tens of ohms. W and a parasitic capacitance C of several hundred pF W is attached.

[0033] In the QBA, the quantum bit control gates in the Qubit array (here, the gates connecting YJW0 and YJE0) have a parasitic resistance R Q The current switches SW0 and SE0 that control the current flowing through them also have parasitic resistance R S have.

[0034] In this embodiment, a dummy path 8012 is provided that has the same structure as the Qubit array 8011. The dummy path 8012 is connected to the terminals YJW D , Y.J.E. D This gate has the same parasitic resistance R as the Qubit Array 8011. Q and a current switch SW D , S.E. D The same parasitic resistance R S The dummy path may use a specific quantum bit control gate within the Qubit array, or may be created as a separate physical path.

[0035] FIG. 8B(b) shows the operational waveforms during calculation using the current dummy path of this embodiment. First, in the time period (1), the two voltage buffers in CAC803 supply voltage V L3 ,V L4 However, since all the switches are OFF, the voltage supply nodes NW and NE are V L3 , V L4 is being charged.

[0036] During the time period (2), before a current is passed between the gates YJW0-YJE0 of the Qubit array 8011, the gate YJW D - YJE D To pass current to D , S.E. D When this is turned on, the current flows through the cable resistance R W , switch on resistance R S , the gate wiring resistance R of the Qubit array Q By this, the potentials of the voltage supply nodes NW and NE are VL 3I , V.L. 4I At this time, the parasitic capacitance of the cable, C W is large at about 300 pF, so the time t RD must be 10 ns or more.

[0037] Next, during time period (3), the switch of dummy path 8012 is turned OFF, and the current switches SW0 and SE0 of selected Qubit array 8011 are turned ON. Then, current from the voltage buffer of CAC 803 flows from voltage supply node NW through the Qubit array to voltage supply node NE, but voltage supply nodes NW and NE are already at voltage VL 3I , V.L. 4I Since the current is stable at t R0 = It stabilizes at 1 mA in a short time of about 1 ns. After that, the RF signal is emitted, the rotation around the X-axis and Y-axis is calculated, and finally, in the time period (4), the current switch is turned off and the device returns to the standby state.

[0038] Therefore, by using this embodiment, the current applied to the quantum bit can be rapidly increased, and the quantum bit's resonant frequency can be rapidly switched, thereby maintaining high fidelity when performing Rx / Ry calculations. To achieve the first objective of fast current supply to the Qubit array, the inventors devised a current dummy path method. A dummy path with the same structure as the Qubit array is provided adjacent to the Qubit array, and current is first supplied to this path, thereby pre-charging the parasitic capacitance of the CAC-QBA connection cable, etc., to the final voltage. Then, by switching the current path to the gate of the selected quantum bit in the Qubit array in this state, it is possible to shorten the current transition time. This makes it possible to provide a QBA with higher calculation accuracy than conventional ones, and a quantum computer equipped with this QBA. [Example]

[0039] A second embodiment of the present invention is shown in Figure 9. In this example, when generating a local magnetic field for a quantum bit, currents are applied in opposite directions to adjacent gate wiring as shown in Figure 5, and a driving method is shown in which a current dummy path is applied to strengthen the magnetic field. Figure 9A(a) shows the current supply path from the CAC to the Qubit array in QBA901 of this example. In this figure, the CAC is omitted and only the internal voltage buffer is shown. As in Figures 7A, 7B, 8A, and 8B, the CAC is in the 4K chamber of the dilution refrigerator and QBA901 is in the 100mK chamber, so the two are connected by a coaxial cable or twisted cable of several meters. Therefore, the voltage V from the voltage buffer of the CAC L3 , V L4 The cable that supplies the power has a parasitic resistance R of the order of several tens of ohms. W and a parasitic capacitance C of several hundred pF W is attached.

[0040] In QBA901, a two-wire example is shown, with gate 9011a connecting YJW0 and YJE0, which are two of the quantum bit control gates 9011 in the Qubit array, and gate 9011b connecting YJW1 and YJE1. These have parasitic resistance R QThe end YJW0 of the gate wiring has a current switch SW 0A , S.W. 0B are connected to voltage supply nodes NW3 and NW4, which are connected via cables to voltage buffers that supply voltages VL3 and VL4 within the CAC. Similarly, a switch SW 1A , S.W. 1B is connected to the voltage supply nodes NW3 and NW4. A current switch SE is connected to the end YJE0 of the gate wiring. 0A , S.E. 0B are connected to voltage supply nodes NE3 and NE4 which are connected via cables to voltage buffers that supply voltages VL4 and VL3 of the CAC. Similarly, the end YJE1 is connected to a current switch SE 1A , S.E. 1B are connected to the voltage supply nodes NE4 and NE3. These switches have parasitic resistance R S It has the following characteristics.

[0041] In this embodiment, a dummy path 9012 having the same structure as the Qubit array is further provided. The dummy path 9012 is an end YJW. D0 , end YJE D0 qubit control gate 9012a connecting the D1 , Y.J.E. D1 These have the same parasitic resistance R as the Qubit array. Q have.

[0042] Also, the end of the gate wiring YJW D0 The current switch SW D0 is connected to the voltage supply node NW3. D1 The current switch SW D1 is connected to the voltage supply node NW4. Similarly, the end YJE of the gate wiring D0 The current switch SE D0 is connected to the voltage supply node NE4. D1 The current switch SE D1are connected to the voltage supply node NE3. These switches also have the same parasitic resistance R S This dummy path may use a specific qubit control gate within the Qubit array, or may be created as a separate physical path.

[0043] FIG. 9B(b) shows the operational waveforms using the current dummy path of this embodiment. First, during the period (1), the voltage buffer in the CAC supplies the voltage V L3 ,V L4 However, since all the switches are OFF, the voltage supply node NW3 / NE3 is V L3 and the voltage supply node NW4 / NE4 is charged to V L4 During the period (2), before a current is passed through the quantum bit control gate 9011 of the Qubit array, a switch SW D0 , S.E. D0、 SW D1 , S.E. D1 When this happens, a current I flows through the two dummy paths. D0 , I D1 flows in the direction shown by the arrow in the figure, and the cable resistance R W , the on-resistance of the analog switch R S , the gate wiring resistance R of the Qubit array Q By this, the potential of the voltage supply nodes NW3 and NE3 becomes VL 3I The potential of the voltage supply nodes NW4 and NE4 is VL 4I At this time, the parasitic capacitance of the cable, C W is large at about 300 pF, so the time t RD must be 10 ns or more.

[0044] Next, during the time period (3), the switch of the dummy path 9012 is turned off, and the current switch SW of the selected Qubit array is turned off. 0A , S.E. 0A , S.W. 1B , S.E. 1BThen, current from the voltage buffer of the CAC flows from voltage supply nodes NW3 and NE3 through the Qubit array to voltage supply nodes NE4 and NW4, but these terminals are already at voltage VL 3I , V.L. 4I Since the current I0 and I1 indicated by the arrows (3) in the figure are stable at t R0 = It stabilizes at 1mA in a short time of about 1ns. After that, an RF signal is emitted and the rotation around the X-axis and Y-axis is calculated.

[0045] Furthermore, during time period (4), the current switch SW of the selected Qubit array 0A , S.E. 0A , S.W. 1B , S.E. 1B Turn OFF the current switch SW of the selected Qubit array. 0B , S.E. 0B , S.W. 1A , S.E. 1A Then, the direction of currents I0 and I1 from the voltage buffer of the CAC is reversed and they flow from voltage supply nodes NW3 and NE3 to voltage supply nodes NE4 and NW4 via the Qubit array, but these terminals are already at voltage VL 3I , V.L. 4I Since it is stable at t, the current values ​​I0 and I1 are R0 This current stabilizes at 1 mA in a short time of about 1 ns. This current weakens the magnetic field of the selected qubit, lowering the frequency of the spin precession to 19.99 GHz, thereby restoring the phase that led to the reference signal when the frequency was increased to 20.01 GHz in period (3). Finally, during time period (5), the current switch is turned off, returning to the standby state.

[0046] Therefore, by using this embodiment, the resonant frequency of the quantum bit can be switched at high speed, and high fidelity can be maintained when performing rotation operations around the X-axis and Y-axis. This makes it possible to provide a quantum bit array (QBA) with higher calculation accuracy than conventional quantum bit arrays, and a quantum computer equipped with this QBA. This method can also be applied when the current flowing through the Qubit array is reversed to perform spin phase compensation.

[0047] To verify the effectiveness of this method, the results of a circuit simulation are shown in Figures 10A and 10B. In the conventional method or dummy path shown in Figure 10A, it takes 7 ns from the start of current flow for the voltage at the voltage supply nodes NW and NE to stabilize and for the current value to reach 1.1 mA, which is within a 10% error of 1 mA. In contrast, in this embodiment shown in Figure 10B, the voltage supply nodes NW and NE are stable from the start, so the time required to switch the current direction and change to -0.9 mA is significantly faster at 1 ns. [Example]

[0048] A third embodiment of the present invention is shown in Figures 11A and 11B. Figure 11A(a) shows the current supply path from the CAC to the Qubit array in the QBA of this embodiment. As in Figures 7A and 7B, the CAC is in the 4K chamber of the dilution refrigerator, and the QBA is in the 100mK chamber, so they are connected by a coaxial cable or twisted cable several meters long. Therefore, the voltage V L3 , V L4 The cable that supplies the power has a parasitic resistance R of the order of several tens of ohms. W and a parasitic capacitance C of several hundred pF W In QBA1101, the qubit control gates in the Qubit array (here, the gates connecting YJW0 and YJE0) have a parasitic resistance R Q The current switches SW0 and SE0 that control the current flowing there also have parasitic resistance R S It is followed by .

[0049] 11B(b) shows the operation waveform of the driving method of this embodiment. First, in the period (1), the two voltage buffers in the CAC supply the voltage V L3I ,V L4I These voltages are the stable voltages of the voltage supply nodes NW and NE in QBA when the current is stabilized at 1 mA in Example 1. Since all the switches are OFF, the output buffer end NW1 of the cable and the voltage supply node NW0 are V L3I The output buffer end NE1 of the cable and the voltage supply node NE0 are charged to VL4I is being charged.

[0050] During the period (2), the current switches SW0 and SE0 are turned on to allow current to flow between the gates YJW0-YJE0 of the Qubit array. Furthermore, the voltage buffer connected to the output buffer terminal NW1 is set to V L3 Higher voltage V L3O After overdriving with a voltage of V L3 Similarly, the voltage buffer connected to the output buffer terminal NE1 outputs V L4 Lower voltage V L4O After overdriving with a voltage of V L4 This overdrive operation cancels out the potential change caused by charging and discharging the cable, and the voltage supply nodes NW0 and NE0 are set to V L3I , V L4I Since the current I0 can be maintained at this level, the current I0 can be output at high speed. After that, an RF signal is emitted and rotation around the X-axis and Y-axis is calculated. Finally, the current switch is turned off during the period (3) and the system returns to the standby state.

[0051] Therefore, by using this embodiment, the resonant frequency of the quantum bit can be switched at high speed, and high fidelity can be maintained when applying an RF signal and performing Rx / Ry operations, making it possible to provide a QBA with higher calculation accuracy than conventional ones and a quantum computer equipped with the QBA. [Example]

[0052] To explain the switch matrix / switch control register configuration that realizes the supply of multiple bias voltages to a large number of quantum bit array control lines, which is the second subject of the present invention, the configuration of the QBA is shown in FIG.

[0053] The CAC supplies 50 different array bias voltages V_DAC to the QBA1201. To control how these bias voltages are applied to each quantum bit array control line in the Qubit array 1202, The signal BSPT and strobe signal BSTR are input to the QBA1201. Inside the QBA1201, a 9-bit signal consisting of a 6-bit control line address SID and a 3-bit control line voltage SWNO defines the combination of quantum bit array control lines and control voltages. The bias pattern signal BSPT allows three control line information to be input simultaneously using a total of 27 signals in three groups: X, Y, and S, indicated by the quantum bit array control line address SID.

[0054] These pieces of information are decoded by decoders 1203a and 1203b, respectively, and then stored in switch control register 1204. Based on the state of switch control register 1204, switch matrix 1205 is switched to output the desired bias voltage to the quantum bit array control line. The timing of this is defined by control signal enable SWEN.

[0055] The RF signal for quantum operation is input via RF and then propagates through the wiring on the Qubit array 1202. The result of the quantum operation performed by the Qubit array 1202 is converted into classical digital information by the sense amplifier 1206 and output to the CAC via the EXRT.

[0056] To explain the signal interface method that defines the operation of the QBA, an example timing chart is shown in Figure 13. The CAC outputs a bias pattern signal BSPT in synchronization with the system clock CLK, and also outputs a strobe signal BSTR that controls the output timing of the bias pattern. The QBA 1201 latches and decodes the bias pattern signal BSPT at the falling edge of the strobe signal BSTR, and then stores it in the switch control register 1204 within the QBA 1201. In the switch matrix 1205, which is an analog matrix switch, a voltage selected from the bias voltage V_DAC is connected to the quantum bit array control line, and the timing of this connection is determined by the control signal enable SWEN. Here, pattern 1 input at clock 2 is output 1301 to the switch control register 1204, and is output 1302 as an array control signal at clock 3. For quantum bit array control lines to which no information has been input at the time the strobe signal BSTR is input, the previously set bias voltage continues to be output from the switch matrix 1205.

[0057] A maximum of three sets of control signal patterns can be input in one cycle, and to change three or more control signals, the switch control register 1204 must be updated over multiple cycles. Here, it is shown that control patterns 2 and 3 input at clocks 6 and 8 are output 1303 as array control signals by the control signal enable SWEN activated at clock 9. The control signal enable SWEN can also be used to transition control signals at timing independent of the system clock. An example is shown in which control pattern 4 input at clock 12 is output 1304 as an array control signal with finely adjusted timing.

[0058] In this way, by supplying information about the bias voltages to be applied to a large number of quantum bit array control lines to the QBA1201 in a time-division manner, it is possible to limit the number of input signals to the QBA1201. If eight types of bias voltages were assigned to each of the 128 array control signals and all combinations were input from outside the chip, more than 1,000 signals would be required, but with this configuration, only a total of 29 signals are required: 27 bias pattern signals BSPT, strobe signals BSTR, and two control signal enable signals SWEN.

[0059] Furthermore, by inputting the strobe signal BSTR and control signal enable SWEN, which determine the operation timing of the internal circuits of the QBA1201, from the CAC, it is possible to omit the timing generation circuit within the QBA, thereby reducing the power consumption of the QBA.

[0060] The RF signal is applied from RFQB at a timing specified in the CAC and is used for the qubit calculation process. The calculation result is read 1305 from the data output terminal EXRT by inputting the sense amplifier control signal pattern 6-9 to the clock 20-32.

[0061] The main circuitry used in the Qubit array is shown in Figure 14. In Figure 14, the circuitry is configured as a register-switch block 1401 having switch control registers 1204 and switch matrices 1205 for generating array control signals, and the switch control registers 1204 and switch matrices 1205 are grouped by signal and arranged around the Qubit array 1202 and sense amplifiers 1206.

[0062] The bias pattern signal BSPT is divided into Groups X, Y, and S, and input to the corresponding register groups. The Group X signals are supplied to switch control registers 1204 (switch control registers 1204X1, 1204X2, and 1204X3) corresponding to the switch (Group X-1) that outputs the array signal XQ, the switch (Group X-2) that outputs the array signal XJN, and the switch (Group X-3) that outputs the array signal XJS. The Group Y signals are supplied to switch control registers 1204 (switch control registers 1204Y1, 1204Y2, and 1204Y3) corresponding to the switch (Group Y-1) that outputs the array signal YQW, the switch (Group Y-2) that outputs the array signals DOS and DOE, the switch (Group Y-3) that outputs the array signal YJW, and the switch (Group Y-4) that outputs the array signal YJE. The signals of Group S are supplied to switch control registers 1204 (switch control registers 1204S1, 1204S2, 1204S3) corresponding to the switches (Group S-1, Group S-2) that output control signals and the switches (Group S-3) that output sensing signals.

[0063] In this way, grouping and distributing the quantum bit array control lines facilitates the connection between switch matrix 1205 and the array control signals. Also, by dividing the bias pattern signals BSPT into three groups, X, Y, and S, it is possible to simultaneously update the information of three sets of quantum bit array control lines, thereby shortening the time required to set the bias voltage.

[0064] As an example, the configuration of the switch control register 1204 and switch matrix 1205 of Groups Y-3 and Y-4 is shown in Figure 15. This register-switch block 1501 controls the bias voltage V L , V L3As shown in the figure, a 6-to-1 switch matrix 1205 is configured to connect six types of bias voltages such as the above. As shown in the figure, a 6-bit SID is assigned to each control line.

[0065] When a bias pattern signal BSPT is input from the CAC and captured by the QBA with the strobe signal BSTR, the control line addresses SID and control line voltages SWNO corresponding to Groups X, Y, and S are decoded, and the bits of the bias voltages to be output are stored in the switch control registers 1204 for the corresponding quantum bit array control lines. In the figure, YJW[0] and YJE[0] are set 1502, 1503 to output VH, and the other YJW[1]-YJW[8] and YJE[1]-YJE[8] are set to output VL 1503. If you want to rewrite only the control signals for Groups X and S, input SID=0 for Group X, and this switch control register 1204 is considered unselected, and no register writing is performed. Also, if a bit corresponding to HZ is stored, all switches for that quantum bit array control line are turned off and enter a high-impedance state.

[0066] When a control signal enable SWEN is input from the CAC, the contents of the switch control register 1204 are output to the switch matrix 1205, the switch on the corresponding control line is switched, and a predetermined bias voltage is output to the array control signal.

[0067] In this way, the number of input signals to the QBA can be reduced by storing information on the bias voltages to be applied to a large number of quantum bit array control lines in the switch control register 1204 and rewriting it in a time-division manner. Also, by inputting the strobe signal BSTR, which defines the operation timing of the QBA internal circuitry, and the control signal enable SWEN from the CAC, it is possible to omit the timing generation circuit within the QBA, thereby reducing the power consumption of the QBA.

[0068] To achieve the second objective of supplying multiple bias voltages to multiple quantum bit control lines, the inventors devised a switch matrix / switch control register configuration. Information on the correspondence between control lines and bias voltages is stored in the switch control register, and the switch matrix is ​​switched according to the contents of this register, enabling the desired bias voltage to be supplied to the quantum bit control line. This makes it possible to supply multiple bias voltages to multiple quantum bit control lines while also accelerating processing.

[0069] 8A, 8B, etc., a quantum bit array chip according to one aspect of the present invention includes a semiconductor layer, an insulating layer disposed on the semiconductor layer, a plurality of first gate electrodes (e.g., quantum dot control gates XQ) disposed on the insulating layer and configured to trap electrons of a predetermined spin state in the semiconductor layer by applying a voltage, a plurality of second gate electrodes (e.g., interaction control gates XJ) adjacent to the first gate electrodes and arranged alternately with the first gate electrodes to pass a current in the extension direction of the first gate electrodes to form a magnetic field acting on the electrons when the spin state of the electrons is to be changed, and a third gate electrode (e.g., a dummy quantum bit control gate of a dummy path 8012 in the X direction) having approximately the same resistance as the second gate electrodes. When the spin state of the electrons trapped in the first gate electrodes is to be changed, a current is passed through the third gate electrode, and after the current has stabilized, the current through the third gate electrode is stopped and a current is passed through the second gate electrode.

[0070] In addition, the third gate electrode in the dummy gate has the same structure as the second gate electrode, and the fourth gate electrode (for example, in Figure 16, gate 1604 when there is a quantum dot control gate XQ1601, an interaction control gate XJ1602, and a dummy quantum bit control gate 1603 of dummy path 8012) arranged adjacent to the third gate electrode has the same structure as the first gate electrode, and controls the electrons trapped below the fourth gate electrode so that they are not used for quantum operations in accordance with instructions from outside the quantum bit array chip (for example, CAC803).

[0071] Furthermore, a first current switch (for example, a current switch SW0) is connected to one side of the second gate electrode, a second current switch (for example, a current switch SE0) is connected to the other side of the second gate electrode, and a third current switch (for example, a current switch SW D ), and a fourth current switch (for example, current switch SE D ) are connected, the terminals opposite to the terminals connected to the gate electrodes of the first current switch and the third current switch are connected to a first common terminal (e.g., a voltage supply node NW), the terminals opposite to the terminals connected to the gate electrodes of the second current switch and the fourth current switch are connected to a second common terminal (e.g., a voltage supply node NE), and a current is supplied to the first common terminal from outside the quantum bit array chip (e.g., CAC803) via wiring, and a current flows out from the second common terminal to outside the quantum bit array chip via wiring.

[0072] Furthermore, the semiconductor device has a plurality of fifth gate electrodes (e.g., interaction control gates YJ) arranged above the first gate electrode and the second gate electrode in the stacking direction with an insulating film sandwiched therebetween, extending in a direction perpendicular to the first gate electrode and the second gate electrode, and a sixth gate electrode (e.g., a dummy quantum bit control gate of the dummy path 8012 in the Y direction) having approximately the same resistance as the fifth gate electrode, and when changing the spin state of an electron trapped in the first gate electrode, a current is passed through the sixth gate electrode, and after the current has stabilized, the current through the sixth gate electrode is stopped and a current is passed through the fifth gate electrode.

[0073] In addition, the fifth gate electrode has the same structure as the sixth gate electrode, and in accordance with instructions from outside the quantum bit array chip, controls the electrons trapped below the sixth gate electrode (e.g., the dummy quantum bit control gate 1603 in the Y direction) in the stacking direction so that they are not used in quantum operations.

[0074] Furthermore, a fifth current switch (for example, a current switch SW0) is connected to one side of the fifth gate electrode, a sixth current switch (for example, a current switch SE0) is connected to the other side of the fifth gate electrode, and a seventh current switch (for example, a current switch SW D ), and an eighth current switch (for example, current switch SE D ) are connected, the terminals opposite to the terminals connected to the gate electrodes of the fifth current switch and the seventh current switch are connected to a third common terminal (e.g., voltage supply node NW), the terminals opposite to the terminals connected to the gate electrodes of the sixth current switch and the eighth current switch are connected to a fourth common terminal (e.g., voltage supply node NE), and current is supplied to the third common terminal from outside the quantum bit array chip (e.g., CAC803) via wiring, and current flows out from the fourth common terminal to the outside of the quantum bit array chip via wiring.

[0075] As described with reference to FIG. 9 and the like, the present invention has a semiconductor layer, an insulating layer disposed on the semiconductor layer, a plurality of first gate electrodes (e.g., quantum dot control gates XQ) disposed on the insulating layer and configured to trap electrons of a predetermined spin state in the semiconductor layer by applying a voltage, and a plurality of second gate electrodes (e.g., interaction control gates XJ) adjacent to the first gate electrodes and arranged alternately with the first gate electrodes, and when changing the spin state of the electrons, two of the second gate electrodes adjacent to the first gate electrodes and a gate 9011b connecting YJW1 and YJE1) that are connected to the first gate electrode, the magnetic field acting on the electrons is strengthened by passing currents in mutually different directions through the first direction second gate electrode (for example, gate 9011a connecting YJW0 and YJE0) and the second direction second gate electrode (for example, gate 9011b connecting YJW1 and YJE1). When changing the spin state of the electrons trapped in the first gate electrode, the first direction third gate electrode (for example, end YJW D0 , end YJE D0 qubit control gate 9012a connecting the qubits) and a second direction third gate electrode (e.g., end YJW D1 , end YJE D1 After the current has stabilized, the current in the third gate electrode is stopped, and control is performed to pass currents in different directions through the two first-direction second gate electrodes and the two second-direction second gate electrodes.

[0076] Furthermore, the third gate electrode has the same structure as the second gate electrode, and a fourth gate electrode (for example, in FIG. 16, gate 1604 in the case where quantum dot control gate XQ1601, interaction control gate XJ1602, and dummy quantum bit control gate 1603 of dummy path 8012 are present) arranged adjacent to the third gate electrode has the same structure as the first gate electrode, and controls the electrons trapped below the fourth gate electrode so that they are not used for quantum operations in accordance with instructions from outside the quantum bit array chip.

[0077] In addition, a first current switch (for example, a current switch SW 0A , S.W. 0B ), a second current switch (for example, current switch SE 0A , S.E. 0B ) is connected to one of the second direction second gate electrodes, and a third current switch (for example, current switch SW 1A , S.W. 1B ), and a fourth current switch (for example, current switch SE 1A , S.E. 1B ) is connected to one side of the first direction third gate electrode, and a fifth current switch (for example, current switch SW D0 ), and a sixth current switch (for example, current switch SE D0 ) is connected to one of the second direction third gate electrodes, and a seventh current switch (for example, current switch SW D1 ), and an eighth current switch (for example, current switch SE D1 ) are connected, terminals opposite to the terminals connected to the gate electrodes of the first current switch and the fifth current switch are connected to a first common terminal (e.g., voltage supply node NW3), terminals opposite to the terminals connected to the gate electrodes of the third current switch and the seventh current switch are connected to a second common terminal (e.g., voltage supply node NW4), terminals opposite to the terminals connected to the gate electrodes of the second current switch and the sixth current switch are connected to a third common terminal (e.g., voltage supply node NE3), terminals opposite to the terminals connected to the gate electrodes of the fourth current switch and the eighth current switch are connected to a fourth common terminal (e.g., voltage supply node NE4), current is supplied to the first common terminal and the third common terminal from outside the quantum bit array chip (e.g., CAC803) via wiring, and current flows out from the second common terminal and the fourth common terminal to the outside of the quantum bit array chip via wiring.

[0078] As described with reference to FIG. 10 and the like, the present invention includes a semiconductor layer, an insulating layer disposed on the semiconductor layer, a plurality of first gate electrodes (e.g., quantum dot control gates XQ) disposed on the insulating layer and configured to trap electrons in a predetermined spin state in the semiconductor layer by applying a voltage, and a plurality of second gate electrodes (e.g., interaction gates XQ) disposed adjacent to the first gate electrodes and arranged alternately with the first gate electrodes in order to pass a current in the extension direction of the first gate electrodes to form a magnetic field acting on the electrons when changing the spin state of the electrons. 11B ) in the quantum bit array; a first chip (e.g., QBA1101) on which the quantum bit array is mounted; a second chip (e.g., CAC1103) that controls the first chip; and a cable that connects the first chip and the second chip (e.g., CAC1103). When a current is supplied from a voltage output buffer (e.g., output buffer terminal NW1) of the second chip to the second gate electrode of the quantum bit array of the first chip, the voltage output buffer outputs a first voltage (e.g., voltage V L3I ) and outputs a second voltage (for example, the voltage V in FIG. 11B) at the initial stage of supplying the current. L3O ), and when the current is stabilized, a third voltage (for example, the voltage V in FIG. 11B) that is substantially the same as the first voltage is output. L3 ) is output.

[0079] This configuration allows the resonant frequency of the quantum bit to be switched at high speed, and makes it possible to maintain high fidelity when performing rotation around the X axis and rotation around the Y axis, which are types of quantum operations.

[0080] 12, 15, etc., the device includes a semiconductor layer, an insulating layer disposed on the semiconductor layer, a plurality of gate electrodes (e.g., quantum dot control gates YQ) disposed on the insulating layer and configured to trap electrons of a predetermined spin state in the semiconductor layer by applying a voltage thereto, a switch matrix (e.g., switch matrix 1205) that controls a voltage to be output to the gate electrodes in accordance with a voltage supplied from an external chip (e.g., CAC803), a bias voltage supply terminal SWEN that outputs the controlled voltage to the gate electrodes, and a register (e.g., switch control register 1204) for generating an array control signal for the quantum bit array chip, wherein bias voltages are supplied to the gate electrodes from the plurality of bias voltage supply terminals via the switch matrix, and the register is capable of selecting a voltage to be supplied to each of the gate electrodes, and stores the supplied bias voltages in association with the gate electrodes to which the bias voltages are supplied.

[0081] As explained using Figures 13, 15, etc., a bias pattern signal and BSPT for controlling how the bias voltage is applied to the quantum bit array chip, a strobe signal BSTR for controlling the output timing of the bias pattern signal, and a control enable signal SWEN for controlling the timing of switching the switch matrix based on the state of the register to output a desired bias voltage are input from outside the quantum bit array chip, the bias pattern signal is taken into the quantum bit array chip by the strobe signal and the register is updated, and the control enable signal switches the connection of the switch matrix according to the value of the register, thereby outputting a desired bias voltage to the gate electrode.

[0082] Furthermore, the bias pattern signal is composed of a control line address SID of the quantum bit array control line and a bias voltage SWNO to be applied to the quantum bit array control line at that control line address, and one of the registers is selected according to the control line address decoded by decoder 1203a, and a bit of the one register is activated according to the bias voltage decoded by decoder 1203b.

[0083] As explained with reference to FIG. 14 etc., the decoder and the register are configured with a plurality of groups (for example, groups X, Y, S corresponding to register groups), and by inputting the bias pattern signals corresponding to each of the groups at the same timing, it is possible to set the bias voltages for the plurality of gate electrodes at the same timing all at once.

[0084] This configuration makes it possible to supply multiple bias voltages to a large number of quantum bit control lines, while reducing the number of chip input terminals and speeding up processing.

[0085] The present invention is not limited to the above-described embodiment, and various modifications are possible within the scope of the invention. [Explanation of symbols]

[0086] 801, 901, 1101, 1201 QBA (Quantum Bit Array Chip) 803, 1103 CAC (Cryogenic Control Chip) 8011, 9011, 1202 Qubit Arrays 8012, 9012 dummy pass 1203 decoder 1204 Switch Control Register 1205 switch matrix 1206 Sense Amplifier f S spin precession frequency f RF RF signal frequency φ RF RF-reference phase difference φ S Spin-reference phase difference t R , t RD , t R0 Signal Stabilization Time V L3 , V L4 bias voltage SW, SE switch R W Cable Parasitic Resistance C W Cable Parasitic Capacitance R S Switch Parasitic Resistance R Q Gate parasitic resistance in the array t RB Rabi oscillation period I0, I1 qubit array currents I D , I D0 , I D1 Current dummy path current NW, NE Current supply node within the chip V_DAC bias voltage BSPT Bias Pattern Signal SID Control Line Address SWNO control line voltage BSTR Bias pattern strobe SWEN control signal enable EXRT calculation result output

Claims

1. a semiconductor layer, an insulating layer disposed on the semiconductor layer, and a plurality of first gate electrodes disposed on the insulating layer, the first gate electrodes trapping electrons of a predetermined spin state in the semiconductor layer by applying a voltage thereto; a plurality of second gate electrodes adjacent to the first gate electrodes and arranged alternately with the first gate electrodes, for passing a current in an elongated direction of the first gate electrodes to form a magnetic field acting on the electrons when changing the spin state of the electrons; a third gate electrode arranged parallel to the second gate electrode and having substantially the same resistance as the second gate electrode; In a quantum bit array chip, when changing the spin state of an electron trapped in the first gate electrode, a current is passed through the third gate electrode, and after the current has stabilized, the current through the third gate electrode is stopped and a current is passed through the second gate electrode; the third gate electrode has the same structure as the second gate electrode, a fourth gate electrode disposed adjacent to the third gate electrode on the second gate electrode side has the same structure as the first gate electrode; According to an instruction from outside the quantum bit array chip, the electrons trapped below the fourth gate electrode are not used for quantum computation; a first current switch is connected to one of the second gate electrodes, and a second current switch is connected to the other of the second gate electrodes; a third current switch is connected to one of the third gate electrodes, and a fourth current switch is connected to the other of the third gate electrodes; the first current switch and the third current switch have terminals opposite to the terminals connected to the gate electrodes thereof connected to a first common terminal; the second current switch and the fourth current switch have terminals opposite to the terminals connected to the gate electrodes thereof connected to a second common terminal; a current is supplied to the first common terminal via a wiring from outside the quantum bit array chip; a current flows out from the second common terminal to the outside of the quantum bit array chip via a wiring; 1. A quantum bit array chip comprising:

2. A semiconductor layer, an insulating layer disposed on the semiconductor layer, and a plurality of first gate electrodes disposed on the insulating layer, which trap electrons of a predetermined spin state in the semiconductor layer by applying a voltage thereto; a plurality of second gate electrodes adjacent to the first gate electrodes and arranged alternately with the first gate electrodes, for passing a current in an elongated direction of the first gate electrodes to form a magnetic field acting on the electrons when changing the spin state of the electrons; a third gate electrode arranged parallel to the second gate electrode and having substantially the same resistance as the second gate electrode; In a quantum bit array chip, when changing the spin state of an electron trapped in the first gate electrode, a current is passed through the third gate electrode, and after the current has stabilized, the current through the third gate electrode is stopped and a current is passed through the second gate electrode; a plurality of fifth gate electrodes disposed above the first gate electrode and the second gate electrode in a stacking direction with an insulating film interposed therebetween and extending in a direction perpendicular to the first gate electrode and the second gate electrode; a sixth gate electrode disposed parallel to the fifth gate electrode and having substantially the same resistance as the fifth gate electrode; When changing the spin state of electrons trapped in the first gate electrode, a current is caused to flow through the sixth gate electrode, and after the current has stabilized, the current through the sixth gate electrode is stopped and a current is caused to flow through the fifth gate electrode; the fifth gate electrode has the same structure as the sixth gate electrode, in accordance with an instruction from outside the quantum bit array chip, the electrons trapped below the sixth gate electrode in the stacking direction are not used for quantum computation; a fifth current switch is connected to one of the fifth gate electrodes, and a sixth current switch is connected to the other of the fifth gate electrodes; a seventh current switch is connected to one of the sixth gate electrodes, and an eighth current switch is connected to the other of the sixth gate electrodes; the fifth current switch and the seventh current switch have terminals opposite to the terminals connected to the gate electrodes thereof connected to a third common terminal; the sixth current switch and the eighth current switch have terminals opposite to the terminals connected to the gate electrodes thereof connected to a fourth common terminal; a current is supplied to the third common terminal from outside the quantum bit array chip via a wiring; a current flows out from the fourth common terminal to the outside of the quantum bit array chip via a wiring; 1. A quantum bit array chip comprising:

3. A semiconductor layer, an insulating layer disposed on the semiconductor layer, and a plurality of first gate electrodes disposed on the insulating layer, which trap electrons of a predetermined spin state in the semiconductor layer by applying a voltage thereto; a plurality of second gate electrodes adjacent to the first gate electrodes and arranged alternately with the first gate electrodes; When changing the spin state of the electrons, currents are passed through two second gate electrodes, a first direction second gate electrode and a second direction second gate electrode, adjacent to the first gate electrode, in directions different from each other, thereby strengthening the magnetic field acting on the electrons; a plurality of third gate electrodes arranged in parallel to the second gate electrodes and having substantially the same resistance as the second gate electrodes; when changing the spin state of the electrons trapped in the first gate electrode, currents are caused to flow through the two third gate electrodes, that is, a first direction third gate electrode and a second direction third gate electrode, and after the currents are stabilized, the current through the third gate electrode is stopped, and currents in different directions are caused to flow through the two first direction second gate electrode and the second direction second gate electrode; the third gate electrode has the same structure as the second gate electrode, a fourth gate electrode disposed adjacent to the third gate electrode on the second gate electrode side has the same structure as the first gate electrode; According to an instruction from outside the quantum bit array chip, the electrons trapped below the fourth gate electrode are not used for quantum computation; a first current switch is connected to one of the first direction second gate electrodes, and a second current switch is connected to the other of the first direction second gate electrodes; a third current switch is connected to one of the second direction second gate electrodes, and a fourth current switch is connected to the other of the second direction second gate electrodes; a fifth current switch is connected to one of the first direction third gate electrodes, and a sixth current switch is connected to the other of the first direction third gate electrodes; a seventh current switch is connected to one of the second direction third gate electrodes, and an eighth current switch is connected to the other of the second direction third gate electrodes; the first current switch and the fifth current switch have terminals opposite to the terminals connected to the gate electrodes thereof connected to a first common terminal; the third current switch and the seventh current switch have terminals opposite to the terminals connected to the gate electrodes thereof connected to a second common terminal; the second current switch and the sixth current switch have terminals opposite to the terminals connected to the gate electrodes thereof connected to a third common terminal; the fourth current switch and the eighth current switch have terminals opposite to the terminals connected to the gate electrodes thereof connected to a fourth common terminal; a current is supplied to the first common terminal and the third common terminal from outside the quantum bit array chip via wiring; a current flows out from the second common terminal and the fourth common terminal to the outside of the quantum bit array chip via wiring; 1. A quantum bit array chip comprising:

4. A quantum bit array having a semiconductor layer, an insulating layer disposed on the semiconductor layer, a plurality of first gate electrodes disposed on the insulating layer for trapping electrons of a predetermined spin state in the semiconductor layer by applying a voltage, and a plurality of second gate electrodes disposed adjacent to the first gate electrodes and alternately arranged with the first gate electrodes for passing a current in the extension direction of the first gate electrodes to form a magnetic field acting on the electrons when the spin state of the electrons is changed; a first chip that includes the quantum bit array, a second chip that controls the first chip, and a cable that connects the first chip and the second chip; when supplying current from the voltage output buffer of the second chip to the second gate electrode of the quantum bit array included in the first chip, the voltage output buffer outputs a first voltage during standby, outputs a second voltage higher than the first voltage in an initial stage of supplying the current, and outputs a third voltage lower than the second voltage and substantially the same as the first voltage when the current has stabilized; A quantum bit computer characterized by:

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