Normally-on gallium nitride-based transistor with p-type gate

Abstract

The semiconductor device (100) includes a gallium nitride-based low-threshold depletion-mode transistor (GaN FET) (102) having a threshold potential between -10 volts and -0.5 volts. The GaN FET (102) has a channel layer (108) of III-N semiconductor material containing gallium and nitrogen, supporting a two-dimensional electron gas (2DEG) (114). The GaN FET (102) has a barrier layer (112) of III-N semiconductor material containing aluminum and nitrogen over the channel layer (108). The GaN FET (102) further includes a p-type gate (124) of III-N semiconductor material containing gallium and nitrogen. A bottom surface (136) of the gate (124) adjacent to the barrier layer (112) does not extend beyond a top surface (138) of the barrier layer (112) opposite the channel layer (108). The GaN FET (102) does not have a dielectric layer between the gate (124) and the barrier layer (112).

Description

[Technical Field]

[0001] The present description relates to the field of semiconductor devices. More particularly, but not exclusively, the present description relates to gallium nitride transistors in semiconductor devices. [Background technology]

[0002] Normally-on gallium nitride-based field-effect transistors (GaN FETs) can be used for power switching applications. Normally-on GaN FETs are also known as depletion-mode GaN FETs. Depletion-mode GaN FETs typically have a gate insulating film of a dielectric material, such as silicon nitride, silicon dioxide, and / or aluminum oxide, between the gate and barrier layer to reduce gate leakage and ensure product reliability. Normally-off operation, also known as enhancement-mode operation, is desired for power switching applications. To operate in normally-off mode, a normally-on GaN FET can be paired with a low-voltage silicon transistor in a cascode circuit. In a cascode circuit, the GaN FET and the silicon transistor are connected in series. The threshold potential of a GaN FET (i.e., the bias potential on the gate relative to the source) to turn the GaN FET on is typically a negative voltage greater than 10 volts. The size of the Si transistor is primarily determined by the magnitude of the threshold voltage of the normally-on GaN FET; a larger threshold potential requires a larger silicon transistor, which translates into higher cost, an increased overall on-resistance contribution, and a reduction in the available space for the GaN transistor in a given package. Summary of the Invention

[0003] This description introduces a semiconductor device including a gallium nitride-based low-threshold depletion-mode transistor (GaN FET). The GaN FET has a channel layer of III-N semiconductor material containing gallium and nitrogen, which supports a two-dimensional electron layer commonly referred to as a two-dimensional electron gas (2DEG). The GaN FET has a barrier layer of III-N semiconductor material containing aluminum and nitrogen over the channel layer. The GaN FET also has a p-type gate of III-N semiconductor material containing gallium and nitrogen. The bottom surface of the gate adjacent to the barrier layer does not extend beyond the top surface of the barrier layer opposite the channel layer. The GaN FET does not have a dielectric layer between the gate and the barrier layer. [Brief explanation of the drawings]

[0004] [Figure 1A] 1A-1C are cross-sectional views of an example semiconductor device including a low-threshold depletion-mode gallium nitride field effect transistor depicted at various stages in its formation. [Figure 1B] 1A-1C are cross-sectional views of an example semiconductor device including a low-threshold depletion-mode gallium nitride field effect transistor depicted at various stages in its formation. [Figure 1C] 1A-1C are cross-sectional views of an example semiconductor device including a low-threshold depletion-mode gallium nitride field effect transistor depicted at various stages in its formation. [Figure 1D] 1A-1C are cross-sectional views of an example semiconductor device including a low-threshold depletion-mode gallium nitride field effect transistor depicted at various stages in its formation. [Figure 1E] 1A-1C are cross-sectional views of an example semiconductor device including a low-threshold depletion-mode gallium nitride field effect transistor depicted at various stages in its formation. [Figure 1F] 1A-1C are cross-sectional views of an example semiconductor device including a low-threshold depletion-mode gallium nitride field effect transistor depicted at various stages in its formation. [Figure 1G]1A-1C are cross-sectional views of an example semiconductor device including a low-threshold depletion-mode gallium nitride field effect transistor depicted at various stages in its formation. [Figure 1H] 1A-1C are cross-sectional views of an example semiconductor device including a low-threshold depletion-mode gallium nitride field effect transistor depicted at various stages in its formation. [Figure 1I] 1A-1C are cross-sectional views of an example semiconductor device including a low-threshold depletion-mode gallium nitride field effect transistor depicted at various stages in its formation. [Figure 1J] 1A-1C are cross-sectional views of an example semiconductor device including a low-threshold depletion-mode gallium nitride field effect transistor depicted at various stages in its formation. [Figure 1K] 1A-1C are cross-sectional views of an example semiconductor device including a low-threshold depletion-mode gallium nitride field effect transistor depicted at various stages in its formation.

[0005] [Figure 2] 1 is a top view of an example semiconductor device including a low-threshold depletion-mode gallium nitride field effect transistor and a silicon metal oxide semiconductor field effect transistor.

[0006] [Figure 3] 1 is a circuit schematic of an exemplary semiconductor device including a low-threshold depletion-mode gallium nitride field effect transistor and a silicon metal oxide semiconductor field effect transistor. DETAILED DESCRIPTION OF THE INVENTION

[0007] The present description will be described with reference to the accompanying drawings. The figures are not drawn to scale and are provided merely to illustrate the present description. Several aspects of the present description are described below in connection with example applications for illustration. Many specific details, relationships, and methods are set forth to facilitate understanding of the description. The description is not limited to the order of acts or events shown, as some acts may occur in different orders and / or concurrently with other acts or events. Additionally, not all illustrated acts or events are required to implement a methodology in accordance with the present description.

[0008] Additionally, while some of the embodiments illustrated in this description are shown in two-dimensional views with various regions having depths and widths, these regions are illustrative of only a portion of a device that is actually a three-dimensional structure. Thus, these regions, when fabricated on an actual device, have three dimensions, including length, width, and depth. Additionally, while the present invention is illustrated by embodiments directed to active devices, these illustrations are not intended to be limitations on the scope or applicability of the present invention. The active devices of the present invention are not limited to the physical structures illustrated. These structures are included to demonstrate the utility and application of the present invention to the presently preferred embodiments.

[0009] The semiconductor device includes a gallium nitride-based low-threshold depletion-mode transistor (GaN FET). The GaN FET has a channel layer of III-N semiconductor material containing gallium and nitrogen, which supports a two-dimensional electron layer commonly referred to as a two-dimensional electron gas (2DEG). The GaN FET has a barrier layer of III-N semiconductor material containing aluminum and nitrogen over the channel layer. The GaN FET further has a p-type gate of III-N semiconductor material containing gallium and nitrogen. The bottom surface of the gate adjacent to the barrier layer does not extend beyond the top surface of the barrier layer opposite the channel layer. No dielectric layer is present between the gate and the barrier layer. The GaN FET has a gate-source threshold potential (referred to herein as threshold potential) of -10 volts to -0.1 volts.

[0010] For purposes of this description, the term "III-N" refers to a semiconductor material in which Group III elements (e.g., aluminum, gallium, and indium, and sometimes boron) contribute some of the atoms in the semiconductor material, and nitrogen atoms contribute another portion of the atoms in the semiconductor material. Examples of III-N semiconductor materials are gallium nitride, boron gallium nitride, aluminum gallium nitride, indium nitride, and indium aluminum gallium nitride. Terms describing the composition of a material do not imply a particular stoichiometry of the elements. For example, aluminum gallium nitride can be written as AlGaN, which encompasses a range of relative proportions of aluminum and gallium.

[0011] It should be noted that terms such as top, bottom, on, above, and below may be used in this description. These terms do not limit the location or orientation of a structure or element, but rather provide a spatial relationship between the structures or elements. The terms "lateral" and "laterally" refer to a direction parallel to the plane of the top surface of the channel layer.

[0012] 1A-1K are cross-sectional views of an example semiconductor device 100 shown at various stages of formation, including a low-threshold depletion-mode gallium nitride field effect transistor 102, referred to in this example as a GaN FET 102. Referring to FIG. 1A, the semiconductor device 100 may be formed on a substrate 104, such as a silicon wafer, a sapphire wafer, or a silicon carbide wafer.

[0013] A buffer layer 106 of one or more layers of III-N semiconductor material may be formed on the substrate 104. In versions of this example in which the substrate 104 is implemented as a silicon or sapphire wafer, the buffer layer 106 may include a nucleation layer with an aluminum-containing stoichiometry to match the lattice constant of the substrate 104. The buffer layer 106 may further include a sublayer of gallium aluminum nitride with reduced aluminum content, resulting in an unintentionally doped gallium nitride layer. The buffer layer 106 on silicon or sapphire may be one to several microns thick. In versions of this example in which the substrate 104 is implemented as a silicon carbide wafer, the buffer layer 106 may be thinner due to the closer lattice constant match between gallium nitride and silicon carbide. The buffer layer 106 may be formed by a buffered metalorganic vapor phase epitaxy (MOVPE) process involving several operations to form the nucleation layer and sublayers. The buffer layer 106 overlaps the area for the GaN FET 102.

[0014] Referring to FIG. 1B, a channel layer 108 of III-N semiconductor material is formed on the buffer layer 106. The channel layer 108 includes gallium and nitrogen, and may comprise primarily gallium nitride with optional trace amounts of other group III elements, such as aluminum or indium. The channel layer 108 may be formed by a channel MOVPE process using a gallium-containing gas reagent and a nitrogen-containing gas reagent, labeled "Ga reagent" and "N reagent," respectively, in FIG. 1B. The substrate 104 may be heated to 900°C to 1100°C during the channel MOVPE process. The gallium-containing gas reagent may be implemented, for example, as trimethylgallium or triethylgallium. The nitrogen-containing gas reagent may be implemented, for example, as ammonia, hydrazine, or 1,1-dimethylhydrazine. The channel MOVPE process uses a carrier gas, labeled "H2 carrier" in FIG. 1B. The carrier gas may comprise primarily hydrogen gas or may contain hydrogen along with another gas, such as nitrogen. The channel layer 108 may be, by way of example, 1 nanometer to 10 nanometers thick. In an alternative version of this example, the channel layer 108 may be formed as the final portion of the buffer layer 106. During operation of the GaN FET 102, the channel layer supports the 2DEG.

[0015] 1C, an optional high bandgap sublayer 110 of III-N semiconductor material may be formed on the channel layer 108. The high bandgap sublayer 110 comprises primarily aluminum and nitrogen to provide a higher bandgap than the subsequently formed barrier layer 112, as shown in FIG. 1D. In some versions of this example, the high bandgap sublayer 110 may consist essentially of aluminum nitride with trace amounts of other group III elements, such as gallium.

[0016] The high bandgap sublayer 110 can be formed by a high bandgap MOVPE process using an aluminum-containing gas reagent and a nitrogen-containing gas reagent, labeled "Al reagent" and "N reagent," respectively, in FIG. 1C. The aluminum-containing gas reagent can be implemented, for example, as trimethylaluminum or triethylaluminum. The nitrogen-containing gas reagent can be implemented, for example, as ammonia, hydrazine, or 1,1-dimethylhydrazine, as described with respect to the formation of the channel layer 108. The substrate 104 can be heated to 900°C to 1100°C during the high bandgap MOVPE process. The high bandgap MOVPE process uses a carrier gas, labeled "H2 carrier" in FIG. 1C. The carrier gas can include primarily hydrogen gas or can include hydrogen along with other gases, such as nitrogen. The high bandgap sublayer 110 can have a thickness, for example, of 0.5 nanometers to 3 nanometers. If formed, the optional high bandgap sublayer 110 can improve charge confinement in the subsequently formed 2DEG 114 shown in FIG. 1D by providing a deeper quantum well in the channel layer 108, advantageously providing an increased free charge carrier density in the 2DEG 114.

[0017] 1D, a barrier layer 112 of III-N semiconductor material is formed over the channel layer 108 and, if present, over the optional high bandgap sublayer 110. The barrier layer 112 includes aluminum and nitrogen. In one version of this example, the barrier layer 112 may include gallium at a lower atomic percentage than aluminum. In another version of this example, the barrier layer 112 may include, within a few atomic percent, Al .83 In .17 N stoichiometry, providing a close lattice match to gallium nitride. In a further version, barrier layer 112 can include gallium and indium, where gallium can improve the uniformity of indium in barrier layer 112. Barrier layer 112 can have a thickness between 1 nanometer and 60 nanometers.

[0018] The barrier layer 112 may be formed by a barrier MOVPE process using an aluminum-containing gas reagent and a nitrogen-containing gas reagent, respectively, labeled "Al Reagent" and "N Reagent" in FIG. 1D. The aluminum-containing gas reagent may be implemented as, for example, trimethylaluminum or triethylaluminum. The nitrogen-containing gas reagent may be implemented as ammonia, hydrazine, or 1,1 dimethylhydrazine, as described with respect to the formation of the channel layer 108.

[0019] In versions of this example in which the barrier layer 112 includes gallium, the barrier MOVPE process uses a gallium-containing gas reagent labeled "Ga Reagent" in FIG. 1D. The gallium-containing gas reagent may be implemented as trimethylgallium or triethylgallium, as described with respect to the formation of the channel layer 108. In versions of this example in which the barrier layer 112 includes indium, the barrier MOVPE process uses an indium-containing gas reagent labeled "In Reagent" in FIG. 1D. The indium-containing gas reagent may be implemented as trimethylindium or triethylindium, for example. The barrier MOVPE process uses a carrier gas labeled "H2 Carrier" in FIG. 1D. The carrier gas may include primarily hydrogen gas or may include hydrogen along with other gases, such as nitrogen. The substrate 104 may be heated to 900°C to 1100°C during the barrier MOVPE process.

[0020] The barrier layer 112 induces a 2DEG 114 in the channel layer 108 adjacent to the barrier layer 112. The stoichiometry and thickness of the barrier layer 112 are selected to provide the desired on-state resistance for the GaN FET 102. 12 cm -2 ~2×10 13 cm -2 can provide a free charge carrier density of

[0021] 1E, an optional etch stop layer 116 may be formed on the barrier layer 112. The etch stop layer 116 has a higher aluminum content than the barrier layer 112. The etch stop layer 116 may comprise primarily aluminum nitride. The etch stop layer 116 may be 0.5 nanometers to 3 nanometers thick and may be formed by an etch stop MOVPE process similar to the high bandgap MOVPE process used to form the high bandgap sublayer 110. The etch stop layer 116 may advantageously reduce or eliminate etching of the barrier layer 112 during a subsequent gate etch process.

[0022] 1F, a gate layer 118 of p-type III-N semiconductor material is formed over the barrier layer 112 and, if present, over the optional etch stop layer 116. The gate layer 118 may comprise primarily gallium nitride with a magnesium dopant to provide p-type conductivity. In some versions of this example, the gate layer 118 may also comprise less than 10 atomic percent of other group III elements, such as aluminum or indium.

[0023] The gate layer 118 may be formed by a gate MOVPE process using a gallium-containing gas reagent, a nitrogen-containing gas reagent, and a p-type dopant gas reagent, labeled "Ga reagent," "N reagent," and "Mg reagent," respectively, in FIG. 1F. The gallium-containing gas reagent may be implemented, for example, as trimethylgallium or triethylgallium. The nitrogen-containing gas reagent may be implemented, for example, as ammonia, hydrazine, or 1,1 dimethylhydrazine, as described with respect to the formation of the channel layer 108. The p-type dopant gas reagent may be implemented, for example, as bis(cyclopentadienyl)magnesium. Other sources of the magnesium-containing gas reagent are within the scope of this example. Other implementations of p-type dopant gases to provide p-type dopants other than magnesium are also within the scope of this example. In a version of this example in which the p-type dopant is implemented as magnesium, the magnesium concentration in the gate layer 118 is 1×10 to provide the desired threshold potential for the GaN FET 102. 17 cm-3 ~1×10 20 cm -3 It is possible.

[0024] In versions of this example in which the gate layer 118 includes aluminum, the gate MOVPE process uses an aluminum-containing gas reagent labeled "Al Reagent" in FIG. 1F. The aluminum-containing gas reagent may be implemented as trimethylaluminum or triethylaluminum, as described with respect to the formation of the barrier layer 112. In versions of this example in which the gate layer 118 includes indium, the gate MOVPE process uses an indium-containing gas reagent labeled "In Reagent" in FIG. 1F. The indium-containing gas reagent may be implemented as trimethylindium or triethylindium, as described with respect to the formation of the barrier layer 112. The barrier MOVPE process uses a carrier gas labeled "H Carrier" in FIG. 1F. The carrier gas may include primarily hydrogen gas or may include hydrogen along with other gases, such as nitrogen. The substrate 104 may be heated to 900° C. to 1100° C. during the gate MOVPE process.

[0025] Gate layer 118 may be 5 nanometers to 500 nanometers thick to provide a desired threshold potential for GaN FET 102. Gate layer 118 reduces the free charge carrier density in 2DEG 114 by 25 percent to 99 percent as a result of the work function of gate layer 118 reducing the quantum well in channel layer 108. 2DEG 114 retains a finite free charge carrier density of electrons after gate layer 118 is formed.

[0026] Referring to FIG. 1G, a gate mask 120 is formed on the gate layer 118. The gate mask covers an area of ​​the gate layer 118 for a later-formed gate 124, as shown in FIG. 1H. In one version of this example, the gate mask 120 may include photoresist formed directly by a photolithography process. The gate mask 120 may include an organic antireflective material, such as a bottom antireflective coating (BARC) layer, below the photoresist. The BARC layer may be patterned after the photolithography process is complete. In another version of this example, the gate mask 120 may include an inorganic hard mask material, such as silicon dioxide or silicon nitride. In a further version, the gate mask 120 may include a metallic hard mask material, such as nickel. The hard mask material, inorganic or metal, may be patterned by forming a photoresist pattern on the hard mask material, followed by etching the hard mask material using a reactive ion etching (RTE) process or an ion milling process using fluorine radicals. The hard mask material in the gate mask 120 may provide improved control over the lateral dimensions of the gate 124 .

[0027] Referring to FIG. 1H, a gate etching process 122 removes the gate layer 118 exposed by the gate mask 120, leaving the gate layer 118 beneath the gate mask 120 to form a gate 124. The gate etching process 122 may be performed in an inductively coupled plasma (ICP) etcher, which generates a plasma containing chemically reactive neutral species, ions, and electrons. The gate etching process 122 includes chemical etchant species, physical etchant species, and aluminum passivation species. The chemical etchant species may be implemented, for example, as chlorine radicals, labeled "Cl" in FIG. 1H, or bromine radicals. The chlorine radicals may be provided by chlorine gas, silicon tetrachloride, boron trichloride, or a combination thereof. The bromine radicals may be provided, for example, by boron tribromide.

[0028] The physical etchant species may be implemented by one or more ionic species. Examples of physical etchant species include fluorine ions, noble gas ions such as argon ions, helium ions, and oxygen ions. Other ionic species among the physical etchant species are also within the scope of this example. Fluorine ions may be provided by, for example, silicon hexafluoride, carbon tetrafluoride, or nitrogen trifluoride. Noble gas ions may be provided by argon gas or helium gas. Oxygen ions may be provided by, for example, oxygen gas or carbon monoxide gas. The physical etchant species is labeled "P" in FIG. 1H to indicate the physical etchant species and may include multiple ionic species.

[0029] The aluminum passivating species may be implemented as oxygen radicals, labeled "O" in FIG. 1H, or fluorine radicals. Oxygen radicals may be provided by oxygen gas. Fluorine radicals may be provided by, for example, silicon hexafluoride, carbon tetrafluoride, or nitrogen trifluoride.

[0030] The chemical etchant species bond to gallium and nitrogen atoms in the gate layer 118. The physical etchant species bombard the gate layer 118, imparting sufficient energy to facilitate dissociation of the gallium and nitrogen atoms bound to the chemical etchant species from the gate layer 118. The dissociated gallium and nitrogen atoms from the gate layer 118 are removed by an ICP etcher. The ICP etcher has a first power supply for forming a plasma that generates chemical etchant species, physical etchant species, and aluminum passivation species, and a second power supply for independently controlling the potential difference between the plasma and the substrate 104. The first power supply can be operated at a power of 250 to 500 watts, for example, for a 150 mm wafer. The second power supply can be initially adjusted to operate at 20 to 100 watts to provide sufficient impact energy of the physical etchant species to facilitate dissociation of the gallium and nitrogen atoms from the gate layer 118. As the gate etch process 122 nears completion, the power level of the second power supply may be reduced to 20 Watts to 50 Watts to reduce the power for the chemical reaction, which significantly reduces the removal of aluminum over the removal of gallium, thus providing etch selectivity. Thus, reducing the power level of the second power supply may reduce the etch rate of the etch stop layer 116, if present, or the barrier layer 112, if the etch stop layer 116 is not present, relative to the gate layer 118, since the gate layer 118 contains more gallium and less aluminum than the etch stop layer 116 and the barrier layer 112.

[0031] The gate etch process 122 may be performed at a pressure between 10 mTorr and 50 mTorr to improve etch selectivity. The aluminum passivating species further improves etch selectivity by preferentially combining with aluminum in the etch stop layer 116, if present, or in the barrier layer 112, if the etch stop layer 116 is not present, minimizing available sites for chemical etchant species to react with gallium and nitrogen. Thus, the gate etch process 122 may completely remove the gate layer 118 in locations exposed by the gate mask 120 without removing a significant amount of the etch stop layer 116 or the barrier layer 112. FIG. 1H shows the gate etch process 122 partially completed.

[0032] 2DEG 114 includes a channel region 126 beneath gate 124. Because the thickness of gate layer 118 remains constant within gate 124, when gate layer 118 is removed, the free charge carrier density in the channel region remains at the low value described with reference to FIG. 1F.

[0033] The 2DEG 114 includes an access region 128 adjacent to a channel region 126. Because the thickness of the gate layer 118 decreases outside the gate 124, the free charge carrier density of the 2DEG 114 increases in the access region 128 when the gate layer 118 is removed.

[0034] The 2DEG 114 includes a source region 130 in an area intended for the source of the GaN FET 102. The source region 130 is laterally separated from the channel region 126 by one of the access regions 128. The 2DEG 114 includes a drain region 132 in an area intended for the drain of the GaN FET 102. The drain region 132 is laterally separated from the channel region 126 by another of the access regions 128 and is located on the opposite side from the source region 130.

[0035] 1I, the gate etch process 122 may continue with an over-etch step after the gate layer 118 has been removed outside of the gate 124. Reducing the power level of the second power supply and providing an aluminum passivating species advantageously allows for the complete elimination of the gate layer 118 across the substrate 104 without removing a significant amount of the etch stop layer 116 or the barrier layer 112, despite variations in the thickness of the gate layer 118 across the substrate 104.

[0036] The free charge carrier density of the 2DEG 114 in the access region 128 can be increased to a value comparable to the free charge carrier density before the gate layer 118 is formed. The free charge carrier density of the 2DEG 114 in the access region 128 can be increased to a value comparable to the free charge carrier density before the gate layer 118 is formed. 12 cm -2 ~2×10 13 cm -2 , providing a desired on-state resistance for the GaN FET 102. The channel region 126 of the 2DEG 114 holds a non-zero electron density that is between 1 percent and 75 percent of the free charge carrier density of the 2DEG 114 in the access region 128.

[0037] The gate mask 120 is then removed. Photoresist and other organic materials in the gate mask 120 can be removed by an oxygen plasma process, a wet etching process, or a combination of both. Inorganic hard mask materials in the gate mask 120 can be removed by an RIE process or a wet etching process using fluorine radicals, for example, using an aqueous solution of hydrofluoric acid. Metals in the gate mask 120 can be removed by a wet etching process using a combination of nitric acid, acetic acid, and sulfuric acid, or a solution of ferric chloride.

[0038] The gate etching process 122 and removal of the gate mask 120 may remove a small amount of gate layer 118 from gate 124, or may not remove gate layer 118 from gate 124, resulting in gate 124 that may be between 5 nanometers and 500 nanometers thick.

[0039] 1J, a dielectric layer 134 may be formed on the barrier layer 112 adjacent to the gate 124. The dielectric layer 134 may include one or more sublayers of silicon dioxide, silicon nitride, aluminum oxide, or any combination thereof. The dielectric film 134 may be formed, for example, by one or more low-pressure chemical vapor deposition (LPCVD) processes, plasma-enhanced chemical vapor deposition (PECVD) processes, high-density plasma (HDP) processes, or atomic layer deposition (ALD) processes. The dielectric layer 134 may advantageously protect the barrier layer 112 from physical or chemical degradation. The dielectric layer 134 may extend over the gate 124, as shown in FIG. 1J.

[0040] A bottom surface 136 of the gate 124 adjacent the barrier layer 112 does not extend beyond a top surface 138 of the barrier layer 112 opposite the channel layer 108, advantageously allowing the GaN FET 102 to be formed without a gate recess etch, which would increase manufacturing cost and complexity. The GaN FET does not include any dielectric material between the gate 124 and the barrier layer 112, advantageously allowing the GaN FET 102 to be formed without forming a gate dielectric layer, which would also increase manufacturing cost and complexity. The GaN FET does not include III-N semiconductor material adjacent to the gate 124 and extends above the bottom surface 136 of the gate 124, advantageously allowing the GaN FET 102 to be formed without forming a barrier regrowth layer, which would further increase manufacturing cost and complexity.

[0041] 1K, a gate contact 140 is formed on the gate 124 through the dielectric layer 134. The gate contact 140 may be aligned with the opening through the dielectric layer 134 as shown in FIG. 1K, or may extend partway up the dielectric layer 134 around the opening. A source contact 142 is formed on the dielectric layer 134 and the barrier layer 112 and contacts the 2DEG 114 in the source region 130. A drain contact 144 is formed on the dielectric layer 134 and the barrier layer 112 and contacts the 2DEG 114 in the drain region 132. The gate contact 140, the source contact 142, and the drain contact 144 are electrically conductive and may include one or more metals, such as titanium, tungsten, or aluminum, or may include other electrically conductive materials, such as carbon nanotubes or graphene.

[0042] During operation of the GaN FET 102, a positive voltage bias is applied to the drain contact 144 relative to the source contact 142, while a negative voltage bias is applied to the gate contact 140 relative to the source contact 142. The negative voltage bias applied to the gate contact 140 is sufficiently negative so that the free charge carrier density of electrons in the channel region 126 of the 2DEG 114 is essentially zero. For example, the free charge carrier density of electrons in the channel region 126 is at least four orders of magnitude less than the free charge carrier density of electrons in the access region 128 of the 2DEG 114. The gate 124 is said to be biased below threshold. Because the free charge carrier density of electrons in the channel region 126 is essentially zero, essentially no current flows from the drain contact 144 through the GaN FET 102 to the source contact 142 (e.g., less than 10 microamperes per micron of width of the channel region 126). The GaN FET 102 is in an off state when the gate 124 is biased below threshold.

[0043] During operation of the GaN FET 102, the voltage bias applied to the gate contact 140 increases above a threshold potential between −10 volts and −0.1 volts, causing electrons to accumulate in the channel region 126. The gate 124 is said to be biased above the threshold. A positive voltage bias is applied to the drain contact 144 relative to the source contact 142, while the gate 124 is biased above the threshold, causing current to flow from the drain contact 144 through the GaN FET 102 to the source contact 142. The GaN FET 102 is in an on state when the gate 124 is biased above the threshold. Having a threshold potential between −10 volts and −0.1 volts may advantageously allow for the use of a smaller driver to apply the bias voltage to the gate contact 140 compared to the driver required for a GaN FET with a threshold potential between −50 volts and −20 volts, for example.

[0044] FIG. 2 is a top view and FIG. 3 is a circuit diagram of an example semiconductor device 200, which includes a low-threshold depletion-mode gallium nitride field-effect transistor 202, referred to in this example as a GaN FET 202, and a silicon metal-oxide-semiconductor field-effect transistor (MOSFET) 246 connected in series with the GaN FET 202. The semiconductor device 200 may optionally include a driver integrated circuit (IC) 248 connected to the GaN FET 202 and the MOSFET 246. As shown in FIG. 2, the semiconductor device 200 may be in a quad flat-pack no-lead (QFN) package or may be packaged in another package type. The encapsulant 250 is removed from over the GaN FET 202, the MOSFET 246, and the driver IC in FIG. 3. The semiconductor device 200 has external leads 252 that provide connection to external components (not shown). A drain contact 244 of the GaN FET 202 is connected to a drain lead 252 a of the external lead 252 by a wire bond 254. A source contact 242 of the GaN FET 202 is connected to a drain terminal 256 of the MOSFET 246 by an additional wirebond 254. A source terminal 258 of the MOSFET 246 is connected to a source lead 252b of the external lead 252 by a further wirebond 254. In this example, a driver IC 248 may be connected to the gate contact 240 of the GaN FET 202 and to a gate terminal 260 of the MOSFET 246. Alternatively, the gate terminal 260 of the MOSFET 246 may be connected to one of the external leads 252. An input terminal 262 of the driver IC 248 is connected to a control lead 252c of the external lead 252 by a further wirebond 254.

[0045] GaN FET 202 has a structure as shown in FIG. 1K and has a threshold potential between −10 volts and −0.5 volts. During operation of semiconductor device 200, MOSFET 246 operates with a drain-source potential difference corresponding to the magnitude of the threshold potential of GaN FET 202. Having a threshold potential between −10 volts and −0.5 volts allows for a smaller size of MOSFET 246 compared to a comparable semiconductor device having a GaN FET with a threshold potential between −50 volts and −20 volts. As an example, MOSFET 246 may be two to five times smaller than a MOSFET required for a GaN FET with a threshold potential of −30 volts. Reducing the size of MOSFET 246 may advantageously reduce the cost of semiconductor device 200.

[0046] While various embodiments of the present disclosure have been described above, they have been presented by way of example only, and not limitation. Many modifications to the described embodiments can be made in accordance with the teachings of the present disclosure without departing from the spirit or scope of the disclosure. Thus, the breadth and scope of the present disclosure should not be limited by any of the above-described embodiments. Rather, the scope of the disclosure is defined by the following claims and their equivalents.

Claims

1. 1. A method of forming a semiconductor device, comprising: forming a channel layer of III-N semiconductor material for a gallium nitride field effect transistor (GaN FET), the channel layer comprising gallium and nitrogen; forming a barrier layer of a III-N semiconductor material over the channel layer, the barrier layer comprising aluminum and nitrogen, and wherein forming the barrier layer results in formation of a two-dimensional electron gas (2DEG) having a first density of free charge carriers in the channel layer adjacent the barrier layer; forming an etch stop layer of III-N semiconductor material directly over the barrier layer, the etch stop layer comprising a greater aluminum content than the barrier layer; forming a p-type gate layer of III-N semiconductor material directly over the etch stop layer, the p-type gate layer comprising gallium and nitrogen; forming a gate mask on the p-type gate layer, the gate mask covering the p-type gate layer over an area for a p-type gate of the GaN FET; removing the p-type gate layer on the etch stop layer exposed by the gate mask to form the p-type gate; removing the gate mask; Including, the 2DEG under the p-type gate has a second non-zero free charge carrier density that is lower than the first free charge carrier density; a 2DEG under the p-type gate is connected to the 2DEG having the first free charge carrier density outside the footprint of the p-type gate such that the GaN FET is normally on.

2. 10. The method of claim 1, The method wherein the barrier layer has a thickness of from 1 nanometer to 60 nanometers.

3. 10. The method of claim 1, The method, wherein forming the barrier layer includes using a gallium-containing gas reagent such that the barrier layer includes gallium.

4. 10. The method of claim 1, The method, wherein forming the barrier layer includes using an indium-containing gas reagent such that the barrier layer includes indium.

5. 10. The method of claim 1, The method, wherein the p-type gate layer is between 5 nanometers and 500 nanometers thick.

6. 10. The method of claim 1, The formation of the p-type gate layer is carried out such that the p-type gate is 1×10 １７ cm －３ ~1 x 10 ２０ cm －３ 4. The method of claim 1, wherein the magnesium-containing gas reagent has a magnesium concentration of

7. 10. The method of claim 1, The method, wherein removing the p-type gate layer exposed by the gate mask is performed using an inductively coupled plasma (ICP) process.

8. 8. The method of claim 7, The method, wherein the ICP process uses oxygen ions, chloride ions, argon ions, or a combination thereof.

9. 10. The method of claim 1, The method wherein the etch stop layer is between 0.5 nanometers and 3 nanometers thick.

10. 10. The method of claim 1, The method further includes, after removing the gate mask, forming a dielectric layer over the etch stop layer and the p-type gate.

11. 11. The method of claim 10, forming source and drain contacts through the dielectric layer, the source and drain contacts respectively extending through the etch stop layer and the barrier layer and further extending partially into the channel layer.

12. 10. The method of claim 1, forming the barrier layer forming an aluminum nitride layer on the channel layer; forming an aluminum gallium nitride layer on the aluminum nitride layer; A method comprising:

13. 13. The method of claim 12, The method wherein the etch stop layer has a greater aluminum content than the aluminum gallium nitride layer of the barrier layer.

14. 10. The method of claim 1, the first free charge carrier density is 3×10 １２ cm －２ Way bigger than that.

15. 10. The method of claim 1, The method of claim 1, wherein the second free charge carrier density is between 1 percent and 75 percent of the first free charge carrier density.

16. 10. The method of claim 1, the first free charge carrier density is 3×10 １２ cm －２ and the second free charge carrier density is between 1 percent and 75 percent of the first free charge carrier density.

17. 1. A method comprising: forming a channel layer of a gallium nitride field effect transistor (GaN FET), the channel layer comprising gallium and nitrogen; forming a barrier layer on the channel layer, the barrier layer comprising aluminum and nitrogen, wherein forming the barrier layer results in a two-dimensional electron gas (2DEG) being formed in the channel layer adjacent the barrier layer, the 2DEG having a first density of free charge carriers; forming a p-type gate layer on the barrier layer, the p-type gate layer comprising gallium and nitrogen; patterning the p-type gate layer to form a p-type gate of the GaN FET; forming a dielectric layer over the p-type gate and the barrier layer; forming source and drain contacts for the GaN FET, the source and drain contacts respectively extending through the dielectric layer and the barrier layer and further extending partially into the channel layer; Including, the 2DEG under the p-type gate has a second non-zero free charge carrier density that is lower than the first free charge carrier density; a 2DEG under the p-type gate is connected to the 2DEG having the first free charge carrier density outside the footprint of the p-type gate such that the GaN FET is normally on.

18. 18. The method of claim 17, The method further comprises forming an etch stop layer on the barrier layer, the etch stop layer comprising a greater aluminum content than the barrier layer.

19. 18. The method of claim 17, forming the barrier layer forming an aluminum nitride layer on the channel layer; forming an aluminum nitride gallium layer on the aluminum nitride layer; A method comprising:

20. 20. The method of claim 19, The method further comprises forming an etch stop layer on the aluminum gallium nitride layer, the etch stop layer comprising a greater aluminum content than the aluminum gallium nitride layer.

21. 18. The method of claim 17, The p-type gate layer is 1×10 １７ cm －３ From 1 x 10 ２０ cm －３ having a magnesium concentration of

22. 15. The method of claim 14, the first free charge carrier density is 3×10 １２ cm －２ Way bigger than that.

23. 15. The method of claim 14, The method of claim 1, wherein the second free charge carrier density is between 1 percent and 75 percent of the first free charge carrier density.

24. 15. The method of claim 14, the first free charge carrier density is 3×10 １２ cm －２ and the second free charge carrier density is between 1 percent and 75 percent of the first free charge carrier density.

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