A method and program for calculating the VC dimension bounds in quantum circuits

Abstract

Provided is a method for calculating the VC dimension boundary in a quantum circuit, the method comprising: a step in which a computer acquires the depth L of the quantum circuit; a step in which the computer acquires the width n of the quantum circuit; and a step in which the computer identifies the VC dimension boundary of the quantum circuit on the basis of the depth L and the width n.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on U.S. Provisional Patent Application No. 63 / 158,743, filed March 9, 2021, the contents of which are incorporated herein by reference. [Technical Field]

[0002] The present invention relates to a method and program for calculating a VC dimensional boundary in a quantum circuit. [Background technology]

[0003] Machine learning models are expected to be applied to solving complex problems in a variety of situations. One of the factors that hinders the improvement of the accuracy of conventional machine learning models is overfitting. Overfitting is a phenomenon in which, once learning accuracy reaches a certain level, the model loses its ability to adapt to unknown data, resulting in a decline in the model's learning ability. To address this issue, conventional machine learning models use methods such as regularization and dropout to limit learning and prevent overfitting from occurring. In this way, in machine learning using classical computers, overfitting is a bottleneck in improving the accuracy of the model.

[0004] On the other hand, although it has been suggested that quantum computers have the property of suppressing overfitting due to their quantum characteristics, this has not been theoretically supported or verified in detail (for example, Non-Patent Document 1). For this reason, it has not been possible to grasp the extent to which quantum circuits are actually less susceptible to overfitting, and they could not be used with confidence as a replacement for existing machine learning models. [Prior art documents] [Non-patent literature]

[0005] [Non-Patent Document 1] Kosuke Mitarai, Makoto Negoro, Masahiro Kitagawa, Keisuke Fujii, “Quantum Circuit Learning”, Phys. Rev. A 98 (2018) 032309, September 10, 2018, http: / / dx.doi.org / 10.1103 / PhysRevA.98.032309 Summary of the Invention

[0006] Therefore, an object of the present invention is to provide a means for verifying that overlearning is unlikely to occur in quantum circuits.

[0007] A method for calculating a VC dimension boundary in a quantum circuit according to one aspect of the present invention includes the steps of: acquiring a depth L of a quantum circuit; acquiring a width n of the quantum circuit; and identifying a VC dimension boundary of the quantum circuit based on the depth L and the width n. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a means for verifying that overlearning is unlikely to occur in quantum circuits. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 2 is a diagram illustrating an example of a quantum learning circuit according to the present embodiment. [Figure 2] FIG. 10 is a diagram illustrating the light-cone restriction of a tensor network of an HEA quantum circuit according to the present embodiment. [Figure 3] FIG. 10 is a diagram illustrating the bounds of the VC dimension in a quantum circuit according to the present embodiment. [Figure 4] 10 is a diagram illustrating the upper limit of VC dimension (d* VC) and the saturation of KL expressibility (D* KL) with respect to the depth of the circuit according to the present embodiment. [Figure 5]10 is a diagram illustrating the upper limit of the VC dimension (d* VC) and the saturation of KL expressibility (D* KL) with respect to the depth of the circuit when the light cone restriction is taken into account according to the present embodiment. FIG. [Figure 6] FIG. 10 is a diagram illustrating the relationship of the upper bound on VC dimension d* VC, the KL representability D* KL, the training error, the test error, and the generalization error to the depth of the circuit, according to the present embodiment. [Figure 7] 1 is a diagram showing a schematic configuration of an information processing device 100 that implements a quantum circuit according to an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. (Using quantum circuits in machine learning algorithms) Quantum circuits are used as subroutines for classical machine learning algorithms. One of the problems with classical machine learning is overfitting. One of the causes of overfitting is the complexity of the model, and in classical machine learning, overfitting is prevented by limiting the expressive power of the model using methods such as normalization. On the other hand, in quantum machine learning using quantum circuits, it has been suggested that quantum characteristics have the ability to suppress overfitting, but this has not yet been theoretically supported or verified in detail.

[0011] In this embodiment, we investigated the influence of the number of qubits (quantum circuit width) and the number of calculation steps (quantum circuit depth) on overfitting for general-purpose quantum circuits that are used in many quantum algorithms. The depth of a quantum circuit corresponds to the number of layers in a neural network in classical machine learning.

[0012] Verification results confirmed that increasing the depth of the quantum circuit saturates the expressive power of the learning model at a certain value. As the expressive power of the model increases, the generalization performance decreases. In other words, saturation of the expressive power of the model means that even if the circuit parameters (circuit depth and width) are further increased, the model will not become more complex and overfitting will not occur.

[0013] (VC dimension of quantum circuits) In this embodiment, to quantify the resistance of a learning model based on a quantum circuit to overfitting, we quantify the upper limit of the VC (Vapnik-Chervonenkis) dimension of the quantum circuit. The VC dimension is an index of the complexity of a learning model, and is a numerical representation of the maximum number of data points that a learning model can perfectly classify in a classification problem. For example, in a two-dimensional space, up to three points can be classified using a straight line, so the VC dimension of a linear classifier in a two-dimensional space is "3." It is known that a large VC dimension makes overfitting more likely to occur. In this embodiment, the VC dimension is calculated based on the depth L and width n of the quantum circuit.

[0014] (Learning circuit) FIG. 1 is a diagram showing an example of a quantum learning circuit according to this embodiment. In the diagram, (a) is a part that encodes an input vector x, where the input vector x is encoded as a rotation angle of one quantum bit. Specifically, an input vector x (x∈[-1,1]) of feature dimension d is d ) is encoded with one feature dimension at a time by the Ry gate (12) and the Rz gate (13) for each quantum bit, as shown in the following equation.

[0015]

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[0016] If the number of quantum bits n is greater than the feature dimension d (for example, as shown in Figure 1(d), the number of quantum bits n = 6 and the feature dimension d = 2), the encoding is repeated. In this case, the i-th quantum bit is x i mod d This encodes the input state ψ in (x)(14) is expressed by the following formula.

number

[0017] (b) in the figure is the part of the learning circuit (variational circuit). The learning circuit consists of a single-qubit rotation gate layer U(θ) (15) with a variational parameter θ and an entanglement gate layer U ent (16) is repeated alternately. The rotating gate layer is expressed as the first equation below. Also, the variational circuit combining the rotating gate layer and the entangled gate layer can be expressed as the second equation below.

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[0018] In this embodiment, the entanglement gate U ent (16) uses a Hardware Efficient Ansatz (HEA) quantum circuit in which the two nearest neighboring qubits are coupled under the periodic boundary condition (PBC), as shown in (c) of the figure, and is expressed as follows:

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[0019] The output state ψ obtained by the above circuit out Using (x)(17), calculate the expected value Z using the following formula.

[0020]

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[0021] Using the calculated expected value Z, classification is performed using the following learning model.

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[0022] (Calculating the bounds of the VC dimension of HEA quantum circuits) Next, a method for calculating the boundary of the VC dimension of the HEA quantum circuit according to this embodiment will be described. First, the upper limit of the VC dimension in a quantum circuit where the feature space is one-dimensional and the input part is only Ry gates will be described. Specifically, it can be calculated by the computer executing the following calculation steps (steps).

[0023] (Step 1) First, assuming a shallow quantum circuit where the number of qubits (width) is n and the depth of the layer is L, satisfying L + 1 < n. Here, in the case of an L-layer circuit, only L + 1 qubits are involved, independent of the number of qubits n. This is due to the locality and singularity of the HEA quantum circuit. Specifically, as shown in FIG. 2, it is due to the limitation of the light cone (LC) of the tensor network. In the HEA quantum circuit where the entangling gate is a short-range controlled-Z gate (CZ gate), in the region not covered by the light cone, all single-bit gates are canceled out by unitarity. Also, all CZ gates are canceled out outside the light cone. Due to these characteristics, in an L-layer circuit, only L + 1 qubits are involved in the calculation and it is independent of the number of qubits.

[0024] (Step 2) Under the above assumption, the following equation is obtained as the density matrix of the effective input state. [Equation]

[0025] (Step 3) By inference, d VC ≦ 2(L + 1)+1 (or <Z0> is the trivial zero matrix) is derived.

[0026] (Step 4) Furthermore, considering the case of a deep quantum circuit, since it also depends on n, d VC≦2min(n,L+1)+1. This bound is for the case of a short-distance two-qubit entanglement gate. Also, we assume that the data is one-dimensional, and the input encoding gate has the same Ry(θ in (x)) and the gate U loc (θ q,l ) is arbitrary. Also, this boundary is the case of open boundary condition (OBC), and in the case of periodic boundary condition, d VC ≦2min(n,2L+1)+1. In addition, in the case of a long-distance qubit entanglement gate, d VC Only ≦2n+1 are obtained.

[0027] Next, a calculation process for the VC dimension when the feature space is high-dimensional will be described. Specifically, the calculation can be performed by a computer by executing the following calculation process (steps).

[0028] (Step 1) First, assume the following (1) to (4). (1) The dimension of the feature space is d. For simplicity, let n≧d, n mod d=0. (2) The only input gate is Ry. Each qubit has x0,...,x d-1 ,x0,...,x d-1 ,..., one feature x i Only Ry(θ in (x i )) and encode it as (3) Each feature is encoded into the same number of qubits (n / d). (4) The following function f(〈Z i 〉) is defined as the threshold. i 〉) is 〈Z i 〉, and γ i is a real number.

number

[0029] (Step 2) Under the above assumptions, the function f is a d-dimensional real trigonometric polynomial, so the degree of each dimension is at most (n / d), and the total number of linearly independent vectors is at most (2(n / d)+1). d is.

[0030] (Step 3) From the above, the upper limit of the VC dimension is d VC ≦(2(n / d)+1) d It is calculated that:

[0031] (Step 4) Furthermore, we calculate an upper limit that takes into account the light cone limitation. Specifically, assuming a method that performs iterative encoding, we obtain the following equation as a density matrix.

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[0032] (Step 5) By inference, for one-dimensional periodic boundary conditions, the following upper bound is derived:

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[0033] (Step 6) Furthermore, in the case of input via Ry and Rz gates, the density matrix is ​​obtained as follows:

number

[0034] This gives us a trigonometric polynomial of two variables with the same highest degree. As a result, the upper bound in the general case is given by

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[0035] In addition, the upper limit in the case of one-dimensional periodic boundary conditions is expressed by the following formula.

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[0036] In addition, by using calculations for the results of only the Ry gate with one qubit, we have found that the lower bound of the VC dimension of the HEA quantum circuit is 2≦d VC Specifically, the calculation can be performed by a computer executing the following calculation steps 1 to 3.

[0037] (Step 1) θ so that the 0th qubit in the 0th layer is Ry(θ) and all other 1-bit quantum gates are identity operators. q,l Select.

[0038] (Step 2) It can be simplified to the case of 0 layers and 1 qubit (L=0, n=1), and the lower limit is 2≦d VC This becomes:

[0039] (Step 3) In the case of d dimensions, consider data on the first feature axis x=(x0,0,...,0).

[0040] From the above, the bounds of the VC dimension in quantum circuits can be summarized as shown in Figure 3. Figure 4 shows the upper bounds of the VC dimension (d * VC ) and the representability (D * KL The figure shows the saturation of the KL expressibility. * VC ) is calculated using the formula (CZ-HEA 1D PBC) shown in Figure 3.

[0041] Figure 4(a) shows the d when the number of quantum bits n is 4, 8, and 12. * VC Figure 4(b) to (d) show the results of the case where n is 4, 8, and 12. * VC and D *KL In Fig. 4(b) to (d), for comparison, * KL is rescaled using the following formula:

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[0042] As is clear from Fig. 4(b) to (d), the rescaled D * KL The saturation of is determined by the upper limit of the VC dimension d * VC This suggests that the VC dimension can be a complementary measure of model complexity.

[0043] Furthermore, Fig. 5 shows the KL representability D when considering the light cone constraint as shown in Fig. 2. * KL and, d * VC 5(a) to (c) show examples where the number of quantum bits n is 4, 8, and 12, respectively.

[0044] (Suppression of overlearning) Figure 6 shows the upper bound d of the VC dimension for the depth of quantum circuits. * VC and KL representability D * KL and the training error, testing error, and generalization error (E out -E in 6(a) to (b) illustrate the case where the number of quantum bits n is 4, and FIGS. 6(c) to (d) illustrate the case where the number of quantum bits n is 8. Also, FIG. 6(e) illustrates the generalization error (E out -E in ) is shown. The larger the generalization error, the greater the degree of overfitting. From Figure 6, the upper limit of the VC dimension d * VC and KL representability D * KLIt is shown that overfitting is suppressed when saturates.

[0045] As described above, according to this embodiment, the boundary of the VC dimension of a quantum circuit can be identified based on the depth L (number of steps) and width n (number of quantum bits) of the quantum circuit. Furthermore, it has been confirmed that overfitting in a quantum learning circuit is less likely to occur due to saturation of the upper limit of the VC dimension. This makes it possible to quantitatively demonstrate that a quantum circuit is a model that prevents overfitting in machine learning.

[0046] (Hardware configuration) 7 is a diagram showing an example of the configuration of a computer system 10 that implements a quantum circuit according to the present invention. The computer system 10 includes a classical computer 100 and a quantum computer 200. Therefore, the computer system 10 is configured as a hybrid system having classical computer functions and quantum computer functions. The classical computer 100 and the quantum computer 200 are communicatively connected via a communication network N. The communication network N is a wired or wireless communication network, and may be, for example, the Internet, or may be a LAN (Local Area Network) or the like.

[0047] The classical computer 100 executes a classical program to perform various types of information processing. A classical program is code that expresses an algorithm that can be executed by a classical computer. A classical program is a program written in a programming language such as C. The classical computer 100 includes a memory unit 110, a processing unit 120, and a communication unit 130.

[0048] The storage unit 110 stores various types of information. Specifically, the storage unit 110 stores information such as classical programs for the processing unit 120 to execute various processes, information to be processed by the processing unit 120, results of the processing by the processing unit 120, and data generated by the quantum computer 200. The various types of information stored in the storage unit 110 are referenced by the processing unit 120 as necessary.

[0049] The processing unit 120 has a function of performing various types of information processing, and can store the results of the processing in the storage unit 110.

[0050] The communication unit 130 can transmit and receive various types of information. The communication unit 130 can transmit data generated by the processing unit 120 to the quantum computer 200. The communication unit 130 can also receive the results of execution of a quantum computing algorithm by the quantum computer 200. The communication unit 130 can also store the received information in the storage unit 110.

[0051] The quantum computer 200 is a computer that performs calculations using quantum mechanical phenomena of matter, and may be a quantum gate quantum computer. The quantum computer 200 may be configured with any hardware.

[0052] The quantum computer 200 can execute quantum computing algorithms based on quantum programs. Quantum programs are codes that express various quantum algorithms. Quantum programs may be expressed, for example, as quantum circuits according to the present invention. Note that quantum programs, like classical programs, may include programs written in a programming language.

[0053] The quantum computer 200 includes a storage unit 210, a control unit 220, a quantum unit 230, and a communication unit 240. Here, the storage unit 210, the control unit 220, and the communication unit 240 may include classical computer functions.

[0054] The storage unit 210 stores various types of information. For example, the storage unit 210 stores a quantum program used by the quantum unit 230 to execute a quantum computing algorithm. The various types of information stored in the storage unit 210 are referenced by the control unit 220 as necessary.

[0055] The control unit 220 can control the quantum unit 230 based on the quantum program. Specifically, the control unit 220 can cause the quantum unit 230 to execute a quantum computing algorithm based on the parameters generated by the processing unit 120 and feature data corresponding to the input data.

[0056] The quantum unit 230 is the core part of the quantum computer 200 and can execute quantum computing algorithms based on the control by the control unit 220.

[0057] The communication unit 240 has a function of transmitting and receiving various types of information. For example, the communication unit 240 transmits the execution result of the quantum unit 230 to the classical computer 10.

[0058] It should be noted that the present invention is not limited to the above-described embodiment, and can be embodied in various other forms without departing from the spirit of the present invention. Therefore, the above-described embodiment is merely an example in all respects and should not be interpreted as being limiting. [Explanation of symbols]

[0059] 11...initial state, 12...Ry gate, 13...Rz gate, 14...input state ψ in , 15...single qubit rotation gate layer U(θ), ​​16...entanglement gate layer U ent , 17...output state ψ out , 10... computer system, 100... classical computer, 110... memory unit, 120... processing unit, 130... communication unit, 200... quantum computer, 210... memory unit, 220... control unit, 230... quantum unit, 240... communication unit

Claims

1. The computer Obtaining the depth L of the quantum circuit; obtaining a width n of the quantum circuit; and identifying a boundary of the VC dimension of the quantum circuit based on the depth L and the width n; If the dimension of the feature space is d, The boundary of the VC dimension d VC is specified by the following formula (1), which is a calculation method for the VC dimension boundary in a quantum circuit. [Equation 1]

2. A computer comprising: Obtaining the depth L of the quantum circuit; obtaining a width n of the quantum circuit; and identifying a boundary of the VC dimension of the quantum circuit based on the depth L and the width n; the quantum circuit is a HEA quantum circuit, If the dimension of the feature space is d, When the periodic boundary condition of the quantum circuit is one-dimensional, The boundary of the VC dimension d VC is specified by the following formula (2), which is a calculation method for the VC dimension boundary in a quantum circuit. [Equation 2]

3. 3. The method for calculating a VC dimensional boundary in a quantum circuit according to claim 1, wherein the depth L is the number of calculation steps, and the width n is the number of quantum bits.

4. The specified VC dimension d VC 3. The method for calculating a VC dimension boundary in a quantum circuit according to claim 1, further comprising: obtaining an upper limit on a generalization error of learning by the quantum circuit based on an upper limit of .

5. On the computer, Obtaining the depth L of the quantum circuit; obtaining a width n of the quantum circuit; Identifying a boundary of the VC dimension of the quantum circuit based on the depth L and the width n; If the dimension of the feature space is d, The boundary of the VC dimension d VC is specified by the following equation (1): [Equation 3]

6. On the computer, Obtaining the depth L of the quantum circuit; obtaining a width n of the quantum circuit; Identifying a boundary of the VC dimension of the quantum circuit based on the depth L and the width n; the quantum circuit is a HEA quantum circuit, If the dimension of the feature space is d, When the periodic boundary condition of the quantum circuit is one-dimensional, The boundary of the VC dimension d VC is specified by the following equation (2): [Equation 4]

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