Systems and methods for multi-level pulsing in RF plasma tools

Abstract

SOLUTION: To provide a system and a method for multi-level pulsing which include generating four or more states during each of which, a radio frequency (RF) generator generates an RF signal, in which an RF signal has four or more power levels, the respective four or more power levels corresponds to the four or more states, and the multi-level pulsing facilitates finer control in processing a substrate.SELECTED DRAWING: Figure 9

Description

[Technical Field]

[0001] The present embodiments relate to systems and methods for multi-level pulsing in radio frequency (RF) plasma tools. [Background technology]

[0002] The background provided in this section is for the purpose of generally presenting the context of the present disclosure. The works of the inventors named in this Background section are not admitted, expressly or impliedly, as prior art to the present disclosure, to the extent that they are described in this section and in a manner that might not otherwise qualify as prior art at the time of filing.

[0003] In a plasma tool, one or more radio frequency (RF) generators are coupled to an impedance matching network. The impedance matching network is coupled to a plasma chamber. An RF signal is provided from the RF generator to the impedance matching network. The impedance matching network receives the RF signal and outputs an RF signal. The RF signal is provided from the impedance matching network to the plasma chamber to process wafers in the plasma chamber. However, the wafers are not processed to the desired level of detail.

[0004] It is within this context that the embodiments described in this disclosure arise. Summary of the Invention

[0005] Embodiments of the present disclosure provide an apparatus, method, and computer program for multi-level pulsing in a radio frequency (RF) plasma tool. It should be understood that the embodiments can be implemented in multiple ways, such as a process, an apparatus, a system, a piece of hardware, or a method on a computer-readable medium. Several embodiments are described below.

[0006] In the following description, several embodiments of multi-level pulsing are provided, along with several benefits associated with multi-level pulsing. Two or more embodiments described herein can be combined to operate with each other, or each of the embodiments described herein can operate independently of each other to provide a particular embodiment associated with multi-level pulsing.

[0007] An RF generator that facilitates multi-level pulsing is described. The RF generator generates an RF signal having four or more power levels and supplies the RF signal to an impedance matching circuit, which is coupled to an electrode of a plasma chamber. The RF signal achieves multi-level pulsing during a clock cycle. For example, the RF signal transitions from a first power level to a second power level, then from the second power level to a third power level, and then from the third power level to a fourth power level during one clock cycle. At the end of the clock cycle, the RF signal transitions from the fourth power level back to the first power level. The multi-level pulsing repeats periodically for multiple clock cycles.

[0008] Each of the first power level, the second power level, the third power level, and the fourth power level is an individual power level. For example, one or more power values ​​of the first power level are dedicated or different from one or more power values ​​of the second power level, one or more power values ​​of the third power level, and one or more power values ​​of the fourth power level. Also, one or more power values ​​of the second power level are different from one or more power values ​​of the third power level and one or more power values ​​of the fourth power level. One or more power values ​​of the third power level are different from one or more power values ​​of the fourth power level.

[0009] Multi-state pulsing is not limited to four power levels. For example, several power levels, three or less, may be generated. Illustratively, two or three power levels may be generated by the RF generator. As another example, several power levels, five or more, such as five, six, or seven power levels may be generated by the RF generator.

[0010] Multi-state pulsing is performed to achieve a balance between various stages of a processing operation, such as a balance between a deposition stage during an etching operation and an etching stage during an etching operation. lower Multi-state pulsing of power levels is applied to perform a deposition phase, and multi-state pulsing of two higher power levels is applied to perform an etching phase. The two lower power levels have lower power than the higher power level. In one example, the etching operation is conductor etching performed in an inductively coupled plasma (ICP) chamber. An RF generator is coupled to an electrode of the ICP plasma chamber, such as a transformer coupled plasma (TCP) electrode or a bias electrode, through an impedance matching network.

[0011] In one embodiment, a pulse train calibration method is described that reduces power losses in a line. The pulse train calibration method includes simulating a multi-state power pulse train to be generated, applying the train to a known 50 ohm load, and measuring the voltage or power of the multi-state power pulse train. For example, the voltage or power is measured for each state of the multi-state power pulse train. The power of each state of the power pulse train can be modified to account for losses based on the measured voltage or power line or measured complex voltage and current. An example of a line includes a radio frequency (RF) cable coupling the output of an RF generator to the input of a matcher, or a combination of an RF cable and an RF transmission line coupling the output of the matcher to an electrode of a plasma chamber.

[0012] In one embodiment, a voltage pulse equalization method is described that reduces line power losses. The voltage pulse equalization method involves measuring or determining the pulse shape with a known load and compensating the power to achieve a square RF pulse response. The pulse shape is measured using a voltage or power probe, or a complex voltage-power probe. This involves voltage control within the pulse. The pulse is divided into multiple sub-pulses. Voltage or power control is performed on each sub-pulse. For example, for portions of the pulse where the voltage or power is too low, the power is changed to achieve a square, flat pulse. The voltage pulse equalization method is performed to account for power losses in the line.

[0013] In one embodiment, a duty cycle calibration method for reducing power losses in a line is described, which includes measuring the duty cycle and adjusting the duty cycle duration of each state in a multi-state pulsing to account for line power losses.

[0014] In the case of multi-level pulsing (eg, four or more power levels), matchers may have difficulty reducing reflected power.

[0015] In one embodiment, a transformer-coupled capacitively tuned (TCCT) matcher is provided to reduce reflected power during multi-state pulsing. The TCCT matcher is used with a source RF generator and modified for use with multi-level pulsing, such as four or more levels of pulsing. The TCCT matcher provides timing information for the multi-level pulsing, allowing the TCCT matcher to be tuned to the multi-level pulsing.

[0016] In one embodiment, a state matcher tuning method is described, which includes tuning a TCCT matcher during one state and tuning a frequency (e.g., tuning an RF generator) to reduce reflected power during the remaining three, four, or five states.

[0017] In one embodiment, solid-state matching devices are used rather than source TCCT or bias matchers to allow for faster tuning with multi-state pulsing and reduced reflected power, and the solid-state matching devices may be fabricated from transistors or semiconductor diodes or a combination thereof.

[0018] In the case of multi-level pulsing, it is difficult for the matcher to handle the multi-level pulsing and minimize the reflected power.

[0019] In one embodiment, a matcher tuning method with a fixed frequency is described. In a four-state scenario, the matcher is tuned in the first state, and the fixed frequency of the RF generator is maintained in the other three states. The frequency is determined to minimize the sum of the products of the weights and the reflected power for the four states. For example, the frequency is such that C1P1 + C2P2 + C3P3 + C4P4 is minimum through states 1 to 4, where C1 to C4 are weights and P1 to P4 are the reflected power between each state. The weights C1 to C4 can be the percentage of the duty cycle between each state. Instead of the reflected power, the power reflection coefficient can be minimized.

[0020] It is desirable to achieve uniformity in process rates, such as etch rates or deposition rates, when one or more transformer coupled plasma (TCP) electrodes, such as TCP coils, and bias electrodes are pulsed to have multiple states (e.g., four or more power levels).

[0021] In one embodiment, a clock synchronization method between the TCP and the bias electrode is provided. In the clock synchronization method, a multi-state fine resolution clock is provided. The fine resolution clock supplies a pulse signal having multiple states, such as four or more states, to an RF generator, which supplies power to the TCP electrode and the bias electrode. The synchronization facilitates achieving uniformity.

[0022] In one embodiment, an Ethernet for Control Automation Technology (EtherCAT®) synchronization method and system are provided to achieve uniformity. An EtherCAT cable is used to synchronize various devices, such as a TCP RF generator, a bias RF generator, and a matching device. The EtherCAT cable is used to transmit a communication pulse train to communicate with various devices. As an example, the communication pulse train has a start time and a stop time. The start time is the start of the series of pulses, and the stop time is the time when the series of pulses stops. The start time and stop time are repeated. Information about multiple states of various devices can be embedded in the pulse train. The information includes the start time and stop time for each state of each device. Furthermore, using an EtherCAT cable for synchronization eliminates the need to supply TTL signals to various devices via multiple synchronization cables to synchronize them. Each synchronization cable carries a TTL signal. Synchronization cables are no longer necessary. An example of an EtherCAT cable is an Ethernet cable.

[0023] It is also desirable to control the process uniformity and achieve a process rate or etch depth in multi-state (eg, four or more states) pulsing.

[0024] In one embodiment, a synchronization master, such as a pulse master, is provided to control processing uniformity and achieve processing rates. As an example, the pulse master includes an analog-to-digital voltage control interface (ADVCI) that synchronizes the TCP generator and the bias RF generator. For example, the ADVCI can generate a digital pulse signal or a TTL signal with two states and supply it to the TCP RF generator, and another digital pulse signal or a TTL signal with four states and supply it to the bias RF generator. The two states and four states are generated during a clock cycle of the clock signal. As another example, the ADVCI can generate a digital pulse signal or a TTL signal with four states and supply it to the TCP RF generator, and another digital pulse signal or a TTL signal with four states and supply it to the bias RF generator. The four states are generated during a clock cycle of the clock signal.

[0025] In one embodiment, a pulse master is used with endpoint detection to control process uniformity and achieve process rate. The pulse master is used to synchronize an optical emission spectrometer (OES) and a Lam spectroreflectometer with multi-state, such as multi-level, pulsing. Endpoint or process point detection is performed by the OES and Lam spectroreflectometer. The Lam spectroreflectometer (LSR) or OES measures the intensity of light reflected from the wafer.

[0026] One embodiment provides an on / off time modification method with selective synchronization between the source RF generator and the bias RF generator. The on / off time modification method includes changing two plasma impedance states to four plasma impedance states, changing four plasma impedance states to eight plasma impedance states, or delaying or advancing the on and off times of RF power in each state. The on / off times can be adjusted or changed within each state to achieve two to four plasma impedance states. For example, the on time for applying RF power can be slightly delayed in state S1 and / or the off time can be achieved slightly earlier in state S1. When the on and off times of RF power for both the TCP generator and the bias RF generator are changed, both the TCP generator and the bias RF generator are synchronized with each other. As an example, when a multi-state power having four or eight states is generated by the source RF generator, the bias RF generator operates in continuous wave (CW) mode. As another example, when a multi-state power having four states or eight states is generated by the bias RF generator, the source RF generator operates in a continuous wave (CW) mode. Also, as an example, different processes are performed in each state. For example, deposition on a wafer may occur in one state, and etching of the wafer may occur in another state.

[0027] The process is controlled to minimize defects to the wafer due to spikes at the edges of the transitions and to protect the RF generator when it is operated in four or more states.

[0028] In one embodiment, a pulse shaping method is provided to achieve process control. As one example, the pulse shaping method includes shaping a rising power edge and / or a falling power edge of an RF signal generated by an RF generator. As another example, the pulse shaping method includes shaping a rising frequency edge and / or a falling frequency edge of the RF signal. As yet another example, the pulse shaping method includes shaping a rising power edge and / or a falling frequency edge of the RF signal.

[0029] It is further desirable to control the process to achieve uniformity when processing substrates.

[0030] In one embodiment, to achieve uniformity, a system is provided having multiple power controllers and multiple automatic frequency tuners (AFTs).

[0031] In one embodiment, a method for tuning the frequency of trajectories at the microsecond level to achieve uniformity is described. In this method, the frequency of each RF signal is tuned at the microsecond level to reduce reflected power for each recipe, generating RF signal trajectories that are applied during the application of the recipe to process a wafer. The trajectories are generated to learn the trajectory that will be applied next during wafer processing.

[0032] In one embodiment, a method for establishing an OFF state is described. In the OFF state establishment method, the OFF state is provided anywhere in a multi-level pulse sequence. The OFF state can be anywhere in the pulse sequence. It is not necessary to achieve the OFF state before repeating the first state in the pulse sequence.

[0033] Some advantages of the systems and methods described herein include using a two-state RF generator to create a multi-state plasma impedance, e.g., four or more plasma impedance states. The multi-state plasma impedance is created by generating various combinations of parameter levels for the source RF generator and the bias RF generator. The multi-state plasma impedance is used to achieve uniformity in processing substrates and also for finer control during substrate processing.

[0034] Additionally, some advantages of the systems and methods described herein with respect to multi-state pulsing include increased levels of substrate processing control. By implementing four or more variable levels of states during substrate processing, finer control of substrate processing is achieved. Furthermore, by controlling state transitions that transition between two of the variable levels, even finer control of substrate processing is achieved to achieve a desired processing result.

[0035] Advantages of the systems and methods described herein using EtherCAT cables include achieving rapid information transfer between various components of a plasma tool or system. Data, such as parameter levels measured during four or more states, is rapidly transferred from the processor to the EtherCAT frame. Also, data, such as parameter levels that generate four or more states, is rapidly transferred from the EtherCAT frame to the processor. Faster transfer allows for more rapid data transfer when using multi-state pulsing, thereby enabling control during substrate processing.

[0036] Other aspects will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief explanation of the drawings]

[0037] The embodiments are understood with reference to the following description taken in conjunction with the accompanying drawings.

[0038] [Figure 1] FIG. 1 is a diagram of one embodiment of a plasma system showing the use of a two-state radio frequency (RF) generator to create a multi-state plasma impedance.

[0039] [Figure 2] FIG. 2 is a diagram of one embodiment of the system, showing details of the RF generator.

[0040] [Figure 3A] FIG. 3A is a graph of one embodiment showing a synchronization signal.

[0041] [Figure 3B] FIG. 3B is a graph of one embodiment showing a parameter of a source signal versus time.

[0042] [Figure 3C] FIG. 3C is a graph of one embodiment showing parameters of the bias RF signal versus time.

[0043] [Figure 4A] FIG. 4A is a graph of one embodiment of FIG. 3A showing the synchronization signals of FIG. 3A.

[0044] [Figure 4B] FIG. 4B is a graph of one embodiment of FIG. 3B.

[0045] [Figure 4C] FIG. 4C is a graph of one embodiment showing parameters of another bias RF signal versus time.

[0046] [Figure 5A] FIG. 5A is a graph of one embodiment showing a synchronization signal.

[0047] [Figure 5B] FIG. 5B is a graph of one embodiment showing a parameter of a source RF signal versus time.

[0048] [Figure 5C] FIG. 5C is a graph of one embodiment showing parameters of the bias RF signal versus time.

[0049] [Figure 6A] FIG. 6A is a graph of one embodiment showing a synchronization signal.

[0050] [Figure 6B] FIG. 6B is a graph of one embodiment showing a parameter of a source RF signal versus time.

[0051] [Figure 6C] FIG. 6C is a graph of one embodiment showing parameters of the bias RF signal versus time.

[0052] [Figure 6D] FIG. 6D is a diagram of one embodiment for on-off time correction with selective synchronization between the source RF generator and the bias RF generator.

[0053] [Figure 7] Figure 7 is a diagram of one embodiment of a plasma system showing multi-level parameter pulsing.

[0054] [Figure 8] Figure 8 is a diagram of one embodiment of a plasma system showing multi-level frequency pulsing.

[0055] [Figure 9] Figure 9 is a diagram of one embodiment of a plasma system showing simultaneous multi-level parameter pulsing and frequency pulsing.

[0056] [Figure 10A] FIG. 10A is a graph of one embodiment of FIG. 3A showing the synchronization signal of FIG. 3A.

[0057] [Figure 10B]FIG. 10B is a graph of one embodiment showing the parameters of the RF signal of FIG. 9 versus time.

[0058] [Figure 10C] FIG. 10C is a graph of one embodiment showing the parameters of the RF signal of FIG. 9 versus time.

[0059] [Figure 10D] FIG. 10D is a graph of one embodiment illustrating the variation of the RF signal of FIG. 9 versus time t.

[0060] [Figure 10E] FIG. 10E is a graph of one embodiment showing the parameters of the RF signal of FIG. 9 versus time.

[0061] [Figure 10F] FIG. 10F is a graph of one embodiment showing the parameters of the RF signal of FIG. 9 versus time.

[0062] [Figure 10G] FIG. 10G is a graph of one embodiment illustrating the variable of the RF signal of FIG. 9 versus time t.

[0063] [Figure 10H] FIG. 10H is a graph of one embodiment showing the parameters of the RF signal of FIG. 9 versus time.

[0064] [Figure 10I] FIG. 10I is a graph of one embodiment showing the parameters of the RF signal of FIG. 9 versus time.

[0065] [Figure 10J] FIG. 10J is a diagram of one embodiment of a system having multiple power controllers and multiple automatic frequency tuners (AFTs).

[0066] [Figure 10K] FIG. 10K is a diagram of one embodiment showing an RF signal having four states S(n-3), S(n-2), S(n-1) and Sn, showing the power levels of the RF signal.

[0067] [Figure 10L] FIG. 10L is a diagram of one embodiment showing another RF signal having four states S(n-3), S(n-2), S(n-1) and Sn, showing the power levels of the RF signals.

[0068] [Figure 10M] FIG. 10M is a diagram of an embodiment showing yet another RF signal having four states S(n-3), S(n-2), S(n-1) and Sn, showing the power levels of the RF signal.

[0069] [Figure 10N] FIG. 10N is a diagram of one embodiment showing another RF signal having four states S(n-3), S(n-2), S(n-1) and Sn, showing the power levels of the RF signals.

[0070] [Figure 10O] FIG. 10O is a diagram of one embodiment showing yet another RF signal having four states S(n-3), S(n-2), S(n-1) and Sn, showing the power levels of the RF signal.

[0071] [Figure 10P] FIG. 10P is a diagram of one embodiment of a method illustrating that a zero power level is achieved during one or more of states S(nA) through Sn, where (nA) is an integer less than n.

[0072] [Figure 11A] Figure 11A is a diagram of one embodiment of a plasma system showing gradient control of state transitions.

[0073] [Figure 11B] FIG. 11B is a diagram of one embodiment of the system of FIG. 11A, illustrating the functionality of the system.

[0074] [Figure 12A] FIG. 12A is a graph of one embodiment showing the synchronization signal of FIG. 3A.

[0075] [Figure 12B] FIG. 12B is a graph of one embodiment showing the variables of the RF signals of FIGS. 11A and 11B versus time.

[0076] [Figure 12C] FIG. 12C is a graph of one embodiment showing the variables of the RF signals of FIGS. 11A and 11B versus time.

[0077] [Figure 12D] FIG. 12D is a graph of one embodiment illustrating various types of transitions for variables versus time for the RF signals of FIGS. 11A and 11B.

[0078] [Figure 12E] FIG. 12E is a graph of one embodiment illustrating various types of transitions for variables versus time for the RF signals of FIGS. 11A and 11B.

[0079] [Figure 12F] FIG. 12F is a diagram of one embodiment of a pulse shaping method.

[0080] [Figure 12G] FIG. 12G is a diagram of an embodiment of another pulse shaping method.

[0081] [Figure 12H] FIG. 12H is a diagram of an embodiment of yet another pulse shaping method.

[0082] [Figure 12I] FIG. 12I is a diagram of yet another embodiment of a pulse shaping method.

[0083] [Figure 12J] FIG. 12J is a diagram of an embodiment of another pulse shaping method.

[0084] [Figure 12K]FIG. 12K is a diagram of an embodiment of yet another pulse shaping method.

[0085] [Figure 12L] FIG. 12L is a diagram of an embodiment of another pulse shaping method.

[0086] [Figure 13A] FIG. 13A is a diagram of one embodiment of the system, showing the transmission of information between various components of the plasma system via one or more EtherCAT cables.

[0087] [Figure 13B] FIG. 13B is a diagram of one embodiment of the system, showing the transmission of information between the various components of the plasma system via one or more EtherCAT cables.

[0088] [Figure 14] FIG. 14 is a diagram of one embodiment of an EtherCAT frame.

[0089] [Figure 15A] FIG. 15A is a diagram of one embodiment of the system, showing the transmission of information between various components of the plasma system via one or more EtherCAT cables.

[0090] [Figure 15B] FIG. 15B is a diagram of one embodiment of the system, showing the transmission of information between the various components of the plasma system via one or more EtherCAT cables.

[0091] [Figure 16] FIG. 16 is a diagram of one embodiment of an EtherCAT frame.

[0092] [Figure 17] FIG. 17 is a diagram of one embodiment of the system, showing an RF generator coupled to an EtherCAT cable.

[0093] [Figure 18] FIG. 18 is a diagram of one embodiment of the system showing a matcher coupled to the RF generator of FIG. 17 via an RF cable and coupled to an EtherCAT cable.

[0094] [Figure 19A] Figure 19A is a diagram of one embodiment of an EtherCAT synchronization system, where an EtherCAT cable is coupled between two components of a plasma system.

[0095] [Figure 19B] FIG. 19B is a diagram of one embodiment of an EtherCAT synchronization system in which an EtherCAT cable is coupled between a source radio frequency (RF) generator and a bias RF generator, and another EtherCAT cable is coupled between the source RF generator and a source matching box.

[0096] [Figure 19C] Figure 19C is a diagram of one embodiment of an EtherCAT synchronous system in which the plasma system components are daisy-chained together.

[0097] [Figure 19D] Figure 19D is a diagram of one embodiment of an EtherCAT synchronous system in which the plasma system components are daisy-chained together.

[0098] [Figure 20] FIG. 20 is a diagram of one embodiment of a system illustrating the pulse train calibration method.

[0099] [Figure 21] FIG. 21 is a diagram of one embodiment of a system illustrating the voltage pulse leveling method.

[0100] [Figure 22] Figure 22 is a diagram of one embodiment of a system illustrating the duty cycle calibration method.

[0101] [Figure 23] FIG. 23 is a diagram of a system illustrating the use of a transformer-coupled capacitively tuned (TCCT) matcher.

[0102] [Figure 24A] FIG. 24A is a diagram of one embodiment of a system illustrating the matcher tuning method of the state.

[0103] [Figure 24B] FIG. 24B is a diagram of one embodiment of a system illustrating another state of the matcher tuning method.

[0104] [Figure 25A] Figure 25A is a diagram of one embodiment of the system showing the source solid-state matcher.

[0105] [Figure 25B] Figure 25B is a diagram of one embodiment of the system illustrating the use of bias solid-state matchers rather than bias matchers.

[0106] [Figure 26A] FIG. 26A is a diagram of one embodiment of a system illustrating a matcher tuning method with a fixed frequency.

[0107] [Figure 26B] FIG. 26B is a diagram of one embodiment of a system illustrating a matcher tuning method with a fixed frequency.

[0108] [Figure 27] FIG. 27 is a diagram of one embodiment of a system illustrating a clock synchronization method between a transformer coupled plasma (TCP) electrode and a bias electrode.

[0109] [Figure 28A] FIG. 28A is a diagram of one embodiment of a system showing a synchronization master.

[0110] [Figure 28B] FIG. 28B is a diagram of one embodiment of a system showing a synchronization master.

[0111] [Figure 29] FIG. 29 is a diagram of one embodiment of a system illustrating the use of multi-state control with endpoint detection.

[0112] [Figure 30] FIG. 30 is a diagram of a system including a power controller, an automatic frequency tuner, a processor, and a power supply, showing how to tune the frequency or power of an orbit at the microsecond level. DETAILED DESCRIPTION OF THE INVENTION

[0113] The following embodiments describe systems and methods for multi-level pulsing in radio frequency (RF) plasma tools. It will be apparent that the embodiments may be practiced without some or all of the specific details of the embodiments. In other instances, well-known process operations will not be described in detail so as not to unnecessarily obscure the embodiments.

[0114] In the following description, several embodiments for multi-level pulsing are provided. Two or more embodiments described herein can be combined to operate with each other, or each of the embodiments described herein can operate independently of each other to provide a particular embodiment related to multi-level pulsing.

[0115] An RF generator that facilitates multi-level pulsing is described. The RF generator generates an RF signal having four or more power levels and supplies the RF signal to an impedance matching circuit, which is coupled to an electrode of a plasma chamber. The RF signal achieves the multi-level pulsing during a clock cycle. For example, the RF signal transitions from a first power level to a second power level, further transitions from the second power level to a third power level, and transitions from the third power level to a fourth power level during a single clock cycle. The multi-level pulsing repeats periodically for multiple clock cycles.

[0116] The first power level, the second power level, the third power level, and the fourth power level are each a separate power level. For example, one or more power values ​​of the first power level are dedicated or different from one or more power values ​​of the second power level, one or more power values ​​of the third power level, and one or more power values ​​of the fourth power level. Also, one or more power values ​​of the second power level are different from one or more power values ​​of the third power level and one or more power values ​​of the fourth power level. One or more power values ​​of the third power level are different from one or more power values ​​of the fourth power level. For example, the difference between the highest power value of the power level of the RF signal and the lowest power value of the power level of the RF signal is less than a predetermined percentage. For example, the highest power value of the first power level is at most 20% greater than the lowest power value of the first power level. Similarly, the highest power value of the second power level is at most 20% greater than the lowest power value of the second power level.

[0117] In one embodiment, the same power level is applied during two or more states, for example, one power level is applied during a first state and a second state, a different power level is applied during a third state, and yet another power level is applied during a fourth state.

[0118] Multi-state pulsing is performed to achieve a balance between various phases during processing operations, such as deposition, etching, cleaning, and sputtering. For example, a first power level and a second power level of an RF signal are used to perform a deposition phase during an etching operation, and a third power level and a fourth power level are used to perform an etching phase during an etching operation. As another example, a different phase is performed during each state of the multi-state pulsing. As yet another example, one phase is performed during one or more states of the multi-state pulsing, and another phase is performed during one or more remaining states of the multi-state pulsing. As one example, the etching operation is conductor etching performed in an inductively coupled plasma (ICP) chamber. An RF generator is coupled to an electrode of the ICP plasma chamber, such as a transformer coupled plasma (TCP) electrode or a bias electrode, via an impedance matching circuit.

[0119] The RF generator receives a digital pulse signal indicating a duty cycle, such as a duration, for each power level of the RF signal generated by the RF generator. The digital pulse signal indicates a time period for each power level provided by the RF generator. The digital pulse signal has multiple states, such as four or more states. For example, the digital pulse signal has a first logic level during a first state, a second logic level during a second state, a third logic level during a third state, and a fourth logic level during a fourth state. Each logic level is defined by a voltage level of a voltage signal generated by a digital pulse source. The digital pulse source is coupled to the RF generator and provides the digital pulse signal to the RF generator. The RF generator further receives a clock signal having multiple clock cycles to facilitate the repetition of the multiple levels of pulsing. The clock signal is generated by a digital pulse source or a clock source, and the clock source is coupled to the RF generator to provide the clock signal to the RF generator.

[0120] It should be noted that the above description of four power levels is an example. In one embodiment, the RF generator generates a greater number of power levels, such as five, six, seven, or eight power levels, during a clock cycle, and the power levels are repeated over multiple clock cycles. As the number of power levels increases, finer control is achieved during substrate processing in the plasma chamber. For example, as the number of power levels increases during a clock cycle, optimal etching of the substrate, optimal deposition of material on the substrate, or a combination thereof, is achieved. In one embodiment, fewer than three power levels are generated, such as three power levels or two power levels.

[0121] The plasma chamber may also be an ICP chamber. For example, an RF generator is coupled to an electrode of the plasma chamber, such as a TCP electrode or a bias electrode, via an impedance matching circuit. To illustrate multiple states, such as multiple levels, an RF signal may be supplied to the TCP electrode via a matcher, while a continuous wave (CW) RF signal or a dual-state RF signal may be supplied to the bias electrode via a separate matcher. As another example, a multi-level RF signal may be supplied to the bias electrode via a matcher, while a CW RF signal or a dual-state RF signal may be supplied to the TCP electrode via a separate matcher. As yet another example, a multi-level RF signal may be supplied to the bias electrode via a matcher, and a multi-level RF signal may be supplied to the TCP electrode via a separate matcher. The bias electrode may be a lower electrode located within a chuck or substrate support of the plasma chamber.

[0122] Two-state RF generator to generate four or more plasma impedance states

[0123] 1 is a diagram of one embodiment of a plasma system 100 illustrating the use of a two-state radio frequency (RF) generator, such as a source RF generator 102 or a bias RF generator 104, to generate a plasma impedance having four or more states. The system 100 includes a host computer 106, a source RF generator 102, a bias RF generator 104, a source matcher 108, a bias matcher 110, and a plasma chamber 112.

[0124] As used herein, examples of a host computer include a desktop computer, a tablet, a smart phone, and a laptop computer. As used herein, examples of an RF generator include an RF generator having an operating frequency of 400 kilohertz (kHz), or an operating frequency of 2 megahertz (MHz), or an operating frequency of 27 MHz, or an operating frequency of 60 MHz. For example, the bias generator 104 has an operating frequency of 2 MHz, and the source RF generator 102 has an operating frequency of 60 MHz, or vice versa. As another example, the bias generator 104 has an operating frequency of 400 kHz, and the source RF generator 102 has an operating frequency of 60 MHz, or vice versa.

[0125] As used herein, examples of a matcher include a network of components coupled together, such as inductors, capacitors, and resistors. For example, a matcher may include multiple series circuits and multiple branch circuits, each of which includes a capacitor, an inductor, or a combination thereof, and each of which includes a capacitor, an inductor, or a combination thereof. Note that in one embodiment, the terms matcher, impedance matching circuit, and impedance matching network are used interchangeably herein. Examples of the plasma chamber 112 include a transformer-coupled plasma (TCP) plasma chamber and an inductively coupled plasma (ICP) plasma chamber.

[0126] The host computer 106 includes a processor 118 and a memory device 120, with the processor 118 coupled to the memory device 120. Examples of a processor, as used herein, include a central processing unit (CPU), a microcontroller, a controller, a microprocessor, an application specific integrated circuit (ASIC), and a programmable logic device (PLD). Examples of a memory device, as used herein, include a read-only memory, a random access memory, or a combination thereof. Illustratively, the memory device is a flash memory or a redundant array of independent disks.

[0127] The plasma chamber 112 includes a dielectric window 124, and above the dielectric window 124 is a TCP coil 126. For example, the dielectric window 124 forms the top surface of the plasma chamber 112. The TCP coil 126 is an example of an electrode of the plasma chamber 112. The plasma chamber 112 further includes a substrate support 128, such as a chuck, on which a substrate S is placed for processing. The substrate support 128 is an example of an electrode of the plasma chamber 112. The substrate S is placed on the top surface of the substrate support 128. The substrate support 128 is embedded in a lower electrode. For example, the lower electrode is made of a metal such as aluminum or an aluminum alloy.

[0128] The processor 118 is coupled to the source RF generator 102 via a transmission cable system 130. Similarly, the processor 118 is coupled to the bias RF generator 104 via a transmission cable system 134. As used herein, a transmission cable system includes one or more transmission cables. As an example, a transmission cable as used herein includes a serial transmission cable that transmits data serially between the processor 118 and an RFG coupled to the processor 118. When transmitting data serially, one bit is transmitted at a time. Another example of a transmission cable includes a parallel transmission cable that transmits data in parallel between the processor 118 and an RFG coupled to the processor 118. When transmitting data in parallel, multiple bits are transmitted simultaneously. Yet another example of a transmission cable includes a universal serial bus (USB) cable.

[0129] An output 154 of the source RF generator 102 is coupled to an input 156 of the source matcher 108 via an RF cable 138, and an output 158 ​​of the source matcher 108 is coupled to the TCP coil 126 via an RF transmission line 140. Similarly, an output 160 of the bias RF generator 104 is coupled to an input 162 of the bias matcher via an RF cable 142, and an output 164 of the bias matcher 110 is coupled to the substrate support 128 via an RF transmission line 144. An example of an RF transmission line includes an RF rod. The RF rod is surrounded by an insulating material, which is further surrounded by an RF sheath of the RF transmission line. The insulating material of the RF transmission line is between the RF rod and the RF sheath. Another example of an RF transmission line includes an RF sheath that surrounds the insulating material, the RF rod, and one or more RF straps coupled to the RF rod. Yet another example of an RF transmission line includes an RF sheath surrounding an insulating material, an RF rod, one or more RF straps, and an RF cylinder coupled to the RF sheath via at least one of the one or more RF straps.

[0130] The processor 118 includes a clock source that generates a synchronization signal 146, such as a digital clock signal or a digital pulse signal, and transmits it to the source RF generator 102 via the transmission cable system 130. One example of a clock source includes a phase-locked loop circuit that generates a synchronization signal with a 50% duty cycle. Another example of a clock source includes a phase-locked loop circuit coupled at its output with a duty cycle control circuit that modifies the duty cycle of the synchronization signal from 50% to more than or less than 50%, such as 80% or 10%, to output a synchronization signal with a modified duty cycle. The clock source of the processor 118 also transmits the synchronization signal 146 to the bias RF generator 104 via the transmission cable system 134.

[0131] Additionally, the processor 118 transmits source variables, such as the frequency of the RF signal 152 to be generated or parameters of the RF signal 152, to the source RF generator 102 via the transmission cable system 130. Examples of variables as used herein include frequency and parameters. Illustratively, the variable is frequency or power. Examples of parameters as used herein include voltage and power. Illustratively, the parameter is voltage or power. The processor 118 also transmits bias variables, such as the frequency of the RF signal 168 and parameters of the RF signal 168, to the bias RF generator 104 via the transmission cable system 134.

[0132] The source RF generator 102 generates an RF signal 152 upon receiving the synchronization signal 146 and the source variables via the transmission cable system 130. The RF signal 152 has a frequency and a source variable, such as power or voltage, received by the source RF generator 102 from the processor 118. The RF signal 152 is transmitted from an output 154 of the source RF generator 102 to an input 156 of the source matching circuit 108 via an RF cable 138. The source matching circuit 108 receives the RF signal 152 and modifies the impedance of the RF signal 152 to match the impedance of a load coupled to the output 158 ​​of the source matching circuit 108 with the impedance of a source coupled to the input 156 of the source matching circuit 108. The source matching circuit 108 modifies the impedance of the RF signal 152 and outputs a modified RF signal 166 at the output 158 ​​of the source matching circuit 108. The modified RF signal 166 is transmitted from the output 158 ​​to the TCP coil 126 via the RF transmission line 140.

[0133] Similarly, the bias RF generator 104 ·system The bias RF generator 104 generates an RF signal 168 upon receiving the synchronization signal 146 and the source variable via 134. The RF signal 168 has a frequency and a bias variable, such as power or voltage, received by the bias RF generator 104 from the processor 118. The RF signal 168 is transmitted from an output 160 of the bias RF generator 104 to an input 162 of the bias matcher 110 via an RF cable 142. The bias matcher 110 receives the RF signal 168 and modifies the impedance of the RF signal 168 to match the impedance of a load coupled to the output 164 of the bias matcher 110 with the impedance of a source coupled to the input 162 of the bias matcher 110. The bias matcher 110 modifies the impedance of the RF signal 168 and outputs a modified RF signal 170 at the output 164 of the bias matcher 110. The modified RF signal 170 is transmitted from the output 164 via an RF rod of the RF transmission line 144 to a bottom electrode embedded in the substrate 128.

[0134] Note that in one embodiment, modified RF signal 166 has the same number of parameter levels as RF signal 152, generating modified RF signal 166 from RF signal 152. For example, RF signals 152 and 166 each have two parameter levels during a cycle of synchronization signal 146. Also, in one embodiment, RF signal 152 and modified RF signal 166 each transition simultaneously from one parameter level to another. For example, when RF signal 152 transitions from one parameter level to another, modified RF signal 166 transitions from one parameter level to another. In one embodiment, modified RF signal 166 has the same parameter levels as the parameter levels of RF signal 152. For example, if RF signal 152 has a first parameter level, the modified RF signal has the same first parameter level.

[0135] Note that in one embodiment, modified RF signal 170 has the same number of parameter levels as RF signal 168, and modified RF signal 170 is generated from RF signal 168. For example, RF signals 168 and 170 each have three parameter levels during a cycle of synchronization signal 146. Also, in one embodiment, RF signal 168 and modified RF signal 170 each transition simultaneously from one parameter level to another. For example, when RF signal 168 transitions from one parameter level to another, modified RF signal 170 transitions from one parameter level to another. In one embodiment, modified RF signal 170 has the same parameter levels as the parameter levels of RF signal 168. For example, if RF signal 168 has a first parameter level, the modified RF signal has the same first parameter level.

[0136] Supplying one or more process gases, such as an oxygen-containing gas, a fluorine-containing gas, or a combination thereof, to the enclosure or housing of the plasma chamber 112 along with the modified RF signals 166 and 170 creates or sustains a plasma within the enclosure or housing of the plasma chamber 112. The plasma is used to process the substrate S and has an impedance. For example, the plasma may be used to deposit material on the substrate S, etch the substrate S, sputter the substrate S, clean the substrate S, or a combination thereof.

[0137] In one embodiment, instead of the TCP coil 126, multiple TCP coils are placed on the dielectric window 124. In one embodiment, in addition to the TCP coil 126, one or more TCP coils are placed on the side of the plasma chamber 112.

[0138] FIG. 2 is a diagram of one embodiment of a system 200, showing details of an RF generator 202. The system 200 includes the RF generator 202 and the host computer 106. The system 200 further includes a matcher 216 and an RF cable 218. The RF generator 202 is an example of the source RF generator 102 or the bias RF generator 104 (FIG. 1). The matcher 216 is an example of the source matcher 108 or the bias matcher 110 (FIG. 1). The RF cable 218 is an example of the RF cable 138 or the RF cable 142 (FIG. 1) and is coupled to an output 217 of an RF power supply 222. The RF generator 202 includes a digital signal processor (DSP) 204 and a Parameters a controller (PRS1) 206; Parameters It includes a controller (PRS2) 208, a frequency controller (FC) 210, a driver system 212, and an RF power supply 222.

[0139] As used herein, examples of digital signal processors include controllers, microprocessors, and microcontrollers, and these terms may be used interchangeably herein. As used herein, examples of parameter controllers include a combination of a processor and a memory device. The processor of a parameter controller is coupled to the memory device of the parameter controller. Similarly, as used herein, examples of frequency controllers include a combination of a processor and a memory device. The processor of a frequency controller is coupled to the memory device of the frequency controller. As used herein, an example of a driver system includes a circuit having one or more drivers, such as one or more transistors coupled to each other. As used herein, an example of an RF power source includes an electronic oscillator that generates a periodic oscillating RF signal, such as a sine wave.

[0140] The processor 118 is coupled to the DSP 204 via a transmission cable system 214. The transmission cable system 214 is an example of the transmission cable system 130 or the transmission cable system 134 (FIG. 1). 4 are coupled to parameter controllers 206 and 208 and to frequency controller 210. Parameter controllers 206 and 208 are coupled to driver system 212, which is coupled to RF power supply 222. Frequency controller 210 is also coupled to driver system 212. RF power supply 222 is coupled to matching box 216 via RF cable 218.

[0141] The processor 118 provides variables, such as a source variable or a bias variable, and a synchronization signal 146 to the DSP 204 via the transmission cable system 214. Upon receiving the variables, the DSP 204 provides parameters, such as a power level or a voltage level, of the RF signal 220 in state S1 to the parameter controller 206 and stores the parameters of state S1 in the memory device of the parameter controller 206. As an example, a parameter level, such as a power level or a voltage level, is an envelope of the RF signal. As an example, a parameter level is a distinct horizontal level that is higher or lower than the distinct horizontal level of another parameter level. As another example, a parameter level is one or more zero-to-peak magnitudes, one or more peak-to-peak magnitudes, or one or more peak-to-peak magnitudes of the RF signal. The amplitudes of the parameter levels are within a predetermined range, such as 0 to 5%, from each other, excluding the amplitudes of other or different parameter levels. As another example, a parameter level has a maximum value and a minimum value. The maximum value is the maximum of all the parameter level values, and the minimum value is the minimum of all the parameter level values. A first parameter level is less than a second parameter level if the maximum value of the first parameter level is less than the minimum value of the second parameter level, and a first parameter level is greater than a second parameter level if the minimum value of the first parameter level is greater than the maximum value of the second parameter level.

[0142] In response to receiving the variables, the DSP 204 also provides parameters, such as the power level or voltage level, of the RF signal 220 for the state S2 to the parameter controller 208 and stores the parameters for the state S2 in a memory device of the parameter controller 208. 2 Similarly, upon receiving the variables, the DSP 204 provides the frequency levels to the frequency controller 210 for storage in the memory device of the frequency controller 210.

[0143] In one embodiment, a level, such as a level of a variable, includes one or more values. For example, a power level includes one or more power values ​​within a predetermined range of each other, and a voltage level includes one or more voltage values ​​within a predetermined range of each other. As another example, a variable level of an RF signal is one or more zero-to-peak magnitudes, one or more peak-to-peak magnitudes, or one or more peak-to-peak magnitudes of the RF signal. The amplitudes of the variable levels are within a predetermined range of each other, such as 0 to 5%, and exclude the amplitudes of other or different parameter levels. As yet another example, a variable level is a distinct horizontal level that is higher or lower than the distinct horizontal level of another variable level.

[0144] In one embodiment, the values ​​of the first variable level are different from the values ​​of the second variable level. For example, the values ​​of the first variable level exclude the values ​​of the second variable level. As another example, none of the values ​​of the first variable level are the same as any of the values ​​of the second variable level.

[0145] Upon receiving the synchronization signal 146, the DSP 204 identifies cycles of the synchronization signal 146. For example, the DSP 204 determines that cycle 1 of the synchronization signal 146 started at a first time and ended or stopped at a second time, and that cycle 2 of the synchronization signal 146 started at a second time and ended or stopped at a third time. Illustratively, the DSP 204 determines that the logic level of the synchronization signal 146 transitioned from 0 to 1 at the start time and again from 0 to 1 at the stop time, and that there were no other transitions from 0 to 1 between the transitions between the start and stop times, identifying a cycle of the synchronization signal 146. The DSP 204 counts each cycle and determines the number of cycles of the synchronization signal 146.

[0146] Also, upon identifying the cycle, during each cycle of the synchronization signal 146, the DSP 204 transmits a command signal for state S1 to the parameter controller 206. For example, the DSP 204 transmits a command signal for state S1 to the parameter controller 206 upon a transition from state S2 or a transition from state S0 to state S1. The command signal for state S1 transmitted to the parameter controller 206 includes the time period of state S1 during each cycle, and the parameter controller 206 provides the parameter levels for state S1 to the driver system 212. Upon receiving the command signal for state S1, the parameter controller 206 accesses the parameter levels for state S1 from its memory device and transmits the parameter levels for the time period of state S1 to the driver system 212. For example, the parameter controller 206 transmits the parameter levels for state S1 to the driver system 212 upon a transition from state S2 or a transition from state S0 to state S1. After the time period for state S1, during the cycle of the synchronization signal 146, the parameter controller 206 does not send the parameter levels for state S1 to the driver system 212.

[0147] Similarly, upon receiving the synchronization signal 146, the DSP 204 transmits a state S2 command signal to the parameter controller 208 during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a state S2 command signal to the parameter controller 208 upon a transition from state S1 or a transition from state S0 to state S2. The state S2 command signal transmitted to the parameter controller 208 includes the time period of state S2 during each cycle, and the parameter controller 208 provides the parameter levels for state S2 to the driver system 212. Upon receiving the state S2 command signal, the parameter controller 208 accesses the parameter levels for state S2 from the memory device of the parameter controller 208 and transmits the parameter levels for the time period of state S2 to the driver system 212. For example, the parameter controller 208 8Upon transitioning from state S1 or from state S0 to state S2, the parameter controller 208 transmits the parameter levels for state S2 to the driver system 212. After the time period in state S2, for a cycle of the synchronization signal 146, the parameter controller 208 does not transmit the parameter levels for state S2 to the driver system 212.

[0148] Additionally, upon receiving the synchronization signal 146, the DSP 204 sends a command signal to the frequency controller 210 during each cycle of the synchronization signal 146. Upon receiving the command signal, the frequency controller 210 accesses a frequency level from its memory device and sends the frequency level to the driver system 212.

[0149] In response to receiving the parameter levels and frequency levels for state S1, driver system 212 generates a drive signal for state S1 for the time period of state S1 and transmits the drive signal to RF power supply 222. For example, upon receiving the parameter levels and frequency levels for state S1 when transitioning from S2 or from state S0 to state S1, driver system 212 generates a drive signal for state S1 for the time period of state S1 and transmits the drive signal to RF power supply 222. When RF power supply 222 receives the drive signal for state S1 from driver system 212, it generates state S1 of RF signal 220. For example, upon receiving the drive signal for state S1 from driver system 212, RF power supply 222 transitions RF signal 220 from state S0 or state S2 to state S1. State S1 of RF signal 220 has the parameter levels and frequency levels of state S1 for the time period of state S1.

[0150] Similarly, in response to receiving the frequency level and parameter level for state S2, driver system 212 generates a drive signal for state S2 for the time period of state S2 and transmits the drive signal to RF power supply 222. For example, upon transitioning from S1 or transitioning from state S0 to state S2, upon receiving the parameter level and frequency level for state S2, driver system 212 generates a drive signal for state S2 for the time period of state S2 and transmits the drive signal to RF power supply 222. Upon receiving the drive signal for state S2 from driver system 212, RF power supply 222 generates state S2 of RF signal 220. For example, upon receiving the drive signal for state S2 from driver system 212, RF power supply 222 transitions RF signal 220 from state S0 or state S1 to state S2. State S2 of RF signal 220 has the parameter level and frequency level of state S2 for the time period of state S2.

[0151] Also, in one embodiment, during each cycle of the synchronization signal 146, there is a time period during which the RF signal 220 has a parameter level of zero. The RF signal 220 has a parameter level of zero during a no state (NS), such as state S0. By way of example, the parameter level of the RF signals described herein is zero if the parameter level is near or substantially zero. Illustratively, the parameter level is zero if the parameter level is less than a predetermined value. One example of a predetermined value for the parameter level is 1 watt. Another example of a predetermined value for the parameter level is 0.25 watts. Yet another example of a predetermined value for the parameter level is 0.5 watts. Upon receiving the synchronization signal 146, during each cycle of the synchronization signal 146, the DSP 204 does not send command signals for states S1 and S2 to the parameter controllers 206 and 208 during the time period during the no state.

[0152] During the time period between states S1 and S2 when no command signals are received, the parameter controllers 206 and 208 do not transmit or stop transmitting the parameter levels for states S1 and S2 to the driver system 212. For example, after the time period for state S1, the parameter controller 206 does not transmit the parameter levels for state S1 to the driver system 212. As another example, after the time period for state S2, the parameter controller 208 does not transmit the parameter levels for state S2 to the driver system 212.

[0153] If the driver system 212 does not receive the parameter levels for states S1 and S2, it does not send a drive signal to the RF power supply 222. If the driver system 212 does not receive a drive signal during a time period without a state, the RF power supply 222 generates the RF signal 220 with a parameter level of zero during the time period without a state. For example, if the driver system 212 does not receive a drive signal, it transitions the RF signal 220 from state S1 or state S2 to the non-state S0.

[0154] In one embodiment, one or more controllers, such as parameter controller 208 and frequency controller 210, one or more processors, rather than parameter controller 206, are used to perform the functions described herein performed by parameter controllers 206 and 208 and frequency controller 210. Each of the one or more controllers includes a processor and a memory device, and the processor is coupled to the memory device.

[0155] In one embodiment, rather than DSP 204, one or more controllers, such as parameter controller 206, parameter controller 208 and frequency controller 210, one or more processors, are used to perform the functions described herein performed by DSP 204, parameter controllers 206 and 208, and frequency 210. Each of the one or more controllers includes a processor and a memory device, the processor coupled to the memory device.

[0156] 3A is a graph 300 of one embodiment illustrating a synchronization signal 302. Graph 300 plots the logic level of synchronization signal 302 versus time t. Synchronization signal 302 is an example of synchronization signal 146 (FIG. 1). The logic level of synchronization signal 302 is plotted on the y-axis, and time t is plotted on the x-axis. As used herein, logic levels range from 0 to 1, with logic level 0 corresponding to 0 volts (V) direct current (DC) and logic level 1 corresponding to 5 volts DC. As used herein, a synchronization signal is a digital pulse signal, such as a square wave, having logic levels 1 and 0.

[0157] Synchronization signal 302 has a 50% duty cycle. For example, synchronization signal 302 has a logic level 1 from time t0 to time t5. Synchronization signal 302 has a logic level 0 from time t5 to time t10, a logic level 1 from time t10 to time t15, and a logic level 0 from time t15 to time t20.

[0158] The time interval between times t0 and t20 is divided into equal time intervals, for example, a first time interval between times t0 and t1, a second time interval between times t1 and t2, a third time interval between times t2 and t3, a fourth time interval between times t3 and t4, a fifth time interval between times t4 and t5, a sixth time interval between times t5 and t6, a seventh time interval between times t6 and t7, an eighth time interval between times t7 and t8, a ninth time interval between times t8 and t9, a tenth time interval between times t9 and t10, a tenth time interval between times t10 and t11, and a sixth time interval between times t11 and t12. The time interval is divided into an eleventh time interval between time t11, a twelfth time interval between time t11 and time t12, a thirteenth time interval between time t12 and time t13, a fourteenth time interval between time t13 and time t14, a fifteenth time interval between time t14 and time t15, a sixteenth time interval between time t15 and time t16, a seventeenth time interval between time t16 and time t17, an eighteenth time interval between time t17 and time t18, a nineteenth time interval between time t18 and time t19, and a twentieth time interval between time t19 and time t20. Each of the first to twelfth time intervals is equal or the same.

[0159] Synchronization signal 302 has multiple cycles, such as cycle 1 and cycle 2, and alternates between logic levels 1 and 0 during each cycle. For example, synchronization signal 302 transitions from logic level 1 to logic level 0 at time t5 during cycle 1, and transitions from logic level 1 to logic level 0 at time t15 during cycle 2. As another example, at time t0 of cycle 1, synchronization signal 302 transitions from logic level 0 in cycle 0 to logic level 1 in cycle 1. Cycle 0 is synchronization signal 302 and precedes cycle 1 of synchronization signal 302. Similarly, at time t10 of cycle 1, synchronization signal 302 transitions from logic level 0 in cycle 1 to logic level 1 in cycle 2. Times t0 to t10 occur during cycle 1 of the synchronization signal described herein, and times t10 to t20 occur during cycle 2 of the synchronization signal. Cycle 1 begins at time t0 and ends at time t10, and cycle 2 begins at time t10 and ends at time t20.

[0160] Each cycle of the synchronization signals described herein is repeated periodically. For example, cycle 1 of the synchronization signal is followed by cycle 2 of the synchronization signal, and so on. 1 followed by cycle 0 of the synchronization signal.

[0161] 3B is an embodiment of a graph 304 illustrating a parameter 306 versus time t of RF signal 152. Parameter 306 is graphed on the y-axis and time t is graphed on the x-axis.

[0162] Parameter 306 periodically transitions between parameter levels PR1 and PR2 in synchronization with synchronization signal 302. For example, parameter 306 transitions between parameter levels PR1 and PR2 during cycle 1 of synchronization signal 302, and again transitions between parameter levels PR1 and PR2 during cycle 2 of synchronization signal 302. For example, parameter 306 has parameter level PR1 during an instance of state S1 from time t0 to time t5, has parameter level PR2 during an instance of state S2 from time t5 to time t10, has parameter level PR1 during another instance of state S1 from time t10 to time t15, and has parameter level PR2 during another instance of state S2 from time t15 to time t20. During cycle 1 of synchronization signal 302, parameter 306 transitions from parameter level PR2 to parameter level PR1 at time t0, and from parameter level PR1 to parameter level PR2 at time t5. During cycle 2 of synchronization signal 302, parameter 306 again transitions from parameter level PR2 to parameter level PR1 at time t10 and from parameter level PR1 to parameter level PR2 at time t15. Parameter level PR1 is an example of a parameter level for state S1 of RF signal 152, and parameter level PR2 is an example of a parameter level for state S2 of RF signal 152.

[0163] Parameter level PR1 is less than parameter level PR2. For example, the power value of parameter level PR1 is less than the power value of parameter level PR2. As another example, none of the power values ​​of parameter level PR1 exceed the power values ​​of parameter level PR2. Parameter level PR1 is greater than zero.

[0164] In one embodiment, the transition time, which is the time to transition between two parameter levels, is the time period between two times. For example, rather than transitioning from power level PR1 to power level PR2 at time t5, parameter 306 begins transitioning from parameter level PR1 at a first time and finishes transitioning to parameter level PR2 at a second time. The first time is before time t5, between times t2 and t5, and the second time is after time t5, between times t5 and t8. The transition time period is the transition time between the first time and the second time.

[0165] In one embodiment, rather than transitioning between parameter levels PR1 and PR2, parameter 306 transitions between parameter levels 0 and PR2 or between parameter levels 0 and PR1.

[0166] In one embodiment, in addition to the synchronization signal 302, a digital pulse signal is received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 302 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal similarly periodically transitions between two logic levels, and the parameter 306 transitions between parameter levels PR1 and PR2. For example, during cycle 1 of the synchronization signal 302, the digital pulse signal transitions from logic level 1 to logic level 0 at time t0 and from logic level 0 to logic level 1 at time t5. During cycle 2 of the synchronization signal 302, the digital pulse signal transitions from logic level 1 to logic level 0 at time t10 and from logic level 0 to logic level 1 at time t15. Upon receiving the digital pulse signal, DSP 204 identifies the time periods S1 and S2 of parameter 306 from the digital pulse signal and generates a command signal having these time periods. For example, the time period of state S1 of parameter 306 is the same as the time period of logic level 1 of the digital pulse signal, and the time period of state S2 of parameter 306 is the same as the time period of logic level 2 of the digital pulse signal.

[0167] 3C is a graph 308 of one embodiment illustrating a parameter 310 versus time t of an RF signal, RF signal 168 (FIG. 1). Parameter 310 is graphed on the y-axis, and time t is graphed on the x-axis. Parameter 310 periodically transitions between parameter levels 0, PR1, and PR2 in synchronization with synchronization signal 302. For example, parameter 310 transitions between parameter levels 0, PR2, and PR1 during cycle 1 of synchronization signal 302, and again transitions between parameter levels 0, PR2, and PR1 during cycle 2 of synchronization signal 302. Illustratively, parameter 310 transitions between parameter levels 0, PR2, and PR1 during cycle 2 of synchronization signal 302. 10 has parameter level 0 during the instance of state S0 from time t0 to time t2, and has parameter level 1 during the instance of state S0 from time t2 to time t8. 2During this instance, the parameter level PR2 is in state S from time t8 to time t10. 1 During cycle 1 of synchronization signal 302, parameter 310 has parameter level PR1. Parameter levels of 0, PR2, and PR1 are repeated during cycle 2 of synchronization signal 302. During cycle 1 of synchronization signal 302, parameter 310 transitions from parameter level PR1 to parameter level 0 at time t0, from parameter level 0 to parameter level PR2 at time t2, from parameter level PR2 to parameter level PR1 at time t8, and from parameter level PR1 to parameter level 0 at time t10. During cycle 2 of synchronization signal 302, parameter 310 also transitions from parameter level PR1 to parameter level 0 at time t10, from parameter level 0 to parameter level PR2 at time t12, from parameter level PR2 to parameter level PR1 at time t18, and from parameter level PR1 to parameter level 0 at time t20.

[0168] Parameter level 0 is the parameter level for state S0 of RF signal 168, parameter level PR1 is an example of a parameter level for state S1 of RF signal 168, and parameter level PR2 is an example of a parameter level for state S2 of RF signal 168.

[0169] If the combination of parameter levels of parameters 306 and 310 during a first time period is different from the combination of parameter levels of parameters 306 and 310 during a second time period, the plasma impedance state during the first time period is different from the plasma impedance state during the second time period. For example, during the time period between times t0 and t2, the parameter level of parameter 306 of the source RF signal is PR1, and during the time period between times t0 and t2, the parameter level of parameter 310 of the bias RF signal is 0, defining a plasma impedance state PS1 in the plasma chamber 112 (FIG. 1). The plasma impedance state in the plasma chamber 112 is sometimes referred to herein as the plasma impedance state (PS). During the time period between times t2 and t5, the parameter level of parameter 306 of the source RF signal is PR1, and during the time period between times t2 and t5, the parameter level of parameter 310 of the bias RF signal is PR2, defining another plasma impedance state PS2.

[0170] As another example, during the time period between times t5 and t8, the parameter level of parameter 306 of the source RF signal is PR2, and during the time period between times t5 and t8, the parameter level of parameter 310 of the bias RF signal is PR2, defining another plasma impedance state PS3, which is different from each of plasma impedance states PS1 and PS2.

[0171] As another example, during the time period between times t8 and t10, the parameter level of parameter 306 of the source RF signal is PR2, and during the time period between times t8 and t10, the parameter level of parameter 310 of the bias RF signal is PR1, defining another plasma impedance state PS4, which is different from each of plasma impedance states PS1, PS2, and PS3. Thus, during each cycle of synchronization signal 302, multiple plasma impedance states, such as four plasma impedance states PS1 through PS4, are generated due to the changes in the parameter levels of the bias RF signal and the source RF signal. The plasma impedance in plasma chamber 112 (FIG. 1) having multiple plasma impedance states PS1 through PS4 is an example of a multi-state plasma impedance.

[0172] In one embodiment, the parameters 306 are of the RF signal 168 and the parameters 310 are of the RF signal 152 .

[0173] In one embodiment, in addition to the synchronization signal 302, a digital pulse signal is received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 302 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal similarly periodically transitions between three logic levels, and the parameter 310 transitions between parameter levels 0, PR2, and PR1. For example, during cycle 1 of the synchronization signal 302, the digital pulse signal transitions from logic level 1 to logic level 0 at time t0, from logic level 0 to logic level 2 at time t2, and from logic level 2 to logic level 1 at time t8. Logic level 2 is greater than logic level 1. Illustratively, logic levels 0, 1, 2, and 3 are respectively 0, 1, 2, 3, and 4. 2has a DC voltage greater than logic level 1. During cycle 2 of synchronization signal 302, the digital pulse signal transitions from logic level 1 to logic level 0 at time t10, from logic level 0 to logic level 2 at time t12, and from logic level 2 to logic level 1 at time t18. Upon receiving the digital pulse signal, DSP 204 identifies the time periods of S0, S2, and S1 of parameters 310 from the digital pulse signal and generates a command signal having these time periods. For example, the time period of state S0 of parameter 310 is the same as the time period of logic level 0 of the digital pulse signal, the time period of state S1 of parameter 310 is the same as the time period of logic level 1 of the digital pulse signal, and the time period of state S2 of parameter 310 is the same as the time period of logic level 2 of the digital pulse signal.

[0174] FIG. 4A is a graph 300 of one embodiment.

[0175] FIG. 4B is a graph 304 of one embodiment.

[0176] FIG. 4C is a graph 400 of one embodiment illustrating a parameter 402 versus time t of RF signal 168 (FIG. 1). Parameter 402 is graphed on the y-axis, and time t is graphed on the x-axis. Parameter 402 periodically transitions between parameter levels 0, PR2, and PR1 in synchronization with synchronization signal 302. For example, parameter 402 transitions between parameter levels 0, PR2, and PR1 during cycle 1 of synchronization signal 302, and again transitions between parameter levels 0, PR2, and PR1 during cycle 2 of synchronization signal 302. Illustratively, parameter 402 has parameter level 0 during an instance of state S0 from time t0 to time t2, and transitions between parameter levels 0, PR2, and PR1 during an instance of state S0 from time t2 to time t8. 2 During this instance, the parameter level PR2 is in state S from time t8 to time t9. 1During one instance of state S0, from time t9 to time t10, the state has a parameter level PR1, and during another instance of state S0, from time t9 to time t10, the state has a parameter level 0. The parameter levels 0, PR2, and PR1 are repeated during cycle 2 of synchronization signal 302. 02 During cycle 1 of the synchronization signal 310, the parameter 402 transitions from parameter level 0 to parameter level PR2 at time t2, from parameter level PR2 to parameter level PR1 at time t8, and from parameter level PR1 to parameter level 0 at time t9. During cycle 2 of the synchronization signal 310, the parameter 402 also transitions from parameter level 0 to parameter level PR2 at time t12, from parameter level PR2 to parameter level PR1 at time t18, and from parameter level PR1 to parameter level 0 at time t19.

[0177] If the combination of parameter levels of parameters 306 and 402 during a first time period is different from the combination of parameter levels of parameters 306 and 402 during a second time period, the plasma impedance state during the first time period is different from the plasma impedance state during the second time period. For example, during the time period between times t0 and t2, the parameter level of parameter 306 of the source RF signal is PR1, and during the time period between times t0 and t2, the parameter level of parameter 402 of the bias RF signal is 0, defining a plasma impedance state PS1. During the time period between times t2 and t5, the parameter level of parameter 306 of the source RF signal is PR1, and during the time period between times t2 and t5, the parameter level of parameter 402 of the bias RF signal is PR2, defining a different plasma impedance state PS2.

[0178] As another example, during the time period between times t5 and t8, the parameter level of parameter 306 of the source RF signal is PR2, and during the time period between times t5 and t8, the parameter level of parameter 402 of the bias RF signal is PR2, defining another plasma impedance state PS3, which is different from each of plasma impedance states PS1 and PS2.

[0179] As yet another example, during the time period between times t8 and t9, the parameter level of parameter 306 of the source RF signal is PR2, and during the time period between times t8 and t9, the parameter level of parameter 402 of the bias RF signal is PR1, defining another plasma impedance state PS4, which is different from each of plasma impedance states PS1, PS2, and PS3.

[0180] As another example, during the time period between times t9 and t10, the parameter level of parameter 306 of the source RF signal is PR2, and during the time period between times t9 and t10, the parameter level of parameter 402 of the bias RF signal is 0, defining another plasma impedance state PS5, which is different from each of plasma impedance states PS1, PS2, PS3, and PS4.

[0181] Thus, multiple plasma impedance states, such as five plasma impedance states PS1 through PS5, are generated due to changes in the parameter levels of the bias RF signal and the source RF signal during each cycle of the synchronization signal 302. The plasma impedance in the plasma chamber 112 (FIG. 1) having multiple plasma impedance states PS1 through PS5 is an example of a multi-state plasma impedance.

[0182] In one embodiment, parameters 306 are of RF signal 168 and parameters 402 are of RF signal 152 .

[0183] In one embodiment, synchronization signal 3 02 In addition, a digital pulse signal is received by DSP 204 from processor 118 via transmission cable system 214. For example, synchronization signal 302 is received via a first transmission cable of transmission cable system 214, and digital pulse signal 304 is received via a second transmission cable of transmission cable system 214. The digital pulse signal similarly periodically transitions between three logic levels, and parameter 402 transitions between parameter levels 0, PR2, and PR1. For example, during cycle 1 of synchronization signal 302, the digital pulse signal transitions from logic level 0 to logic level 2 at time t2, from logic level 2 to logic level 1 at time t8, and from logic level 1 to logic level 0 at time t9. During cycle 2 of synchronization signal 302, the digital pulse signal transitions from logic level 0 to logic level 2 at time t12, from logic level 2 to logic level 1 at time t18, and from logic level 1 to logic level 0 at time t19. Upon receiving the digital pulse signal, the DSP 204 identifies the time periods S0, S2, and S1 of the parameter 402 from the digital pulse signal and generates a command signal having these time periods. For example, the time period of the state S0 of the parameter 402 is the same as the time period of the logic level 0 of the digital pulse signal, the time period of the state S1 of the parameter 402 is the same as the time period of the logic level 1 of the digital pulse signal, and the time period of the state S2 of the parameter 402 is the same as the time period of the logic level 2 of the digital pulse signal.

[0184] 5A is a graph 500 of one embodiment showing a synchronization signal 502. The graph 500 plots the logic level of the synchronization signal 502 versus time t. The synchronization signal 502 is an example of the synchronization signal 146 (FIG. 1). The logic level of the synchronization signal 502 is plotted on the y-axis, and time t is plotted on the x-axis.

[0185] The synchronization signal 502 has a 70% duty cycle. For example, the synchronization signal 502 has a logic level 1 from time t0 to time t7. 5 02 has a logic level 0 from time t7 to time t10, a logic level 1 from time t10 to time t17, and a logic level 0 from time t17 to time t20.

[0186] Synchronization signal 502 has multiple cycles, alternating between logic levels 1 and 0 during each cycle. For example, synchronization signal 502 transitions from logic level 1 to logic level 0 at time t7 during cycle 1, and transitions from logic level 1 to logic level 0 at time t17 during cycle 2. As another example, at time t0 of cycle 1, synchronization signal 502 transitions from logic level 0 in cycle 0 of synchronization signal 502 to logic level 1 in cycle 1. Similarly, at time t10 of cycle 1, synchronization signal 502 transitions from logic level 0 in cycle 1 to logic level 1 in cycle 2. Cycle 0 of synchronization signal 502 precedes cycle 1 of synchronization signal 502, which precedes cycle 2 of synchronization signal 502.

[0187] In one embodiment, synchronization signal 502 has a different duty cycle, such as a 50% duty cycle or a 60% duty cycle, rather than a 70% duty cycle.

[0188] 5B is an embodiment of a graph 504 showing a parameter 506 versus time t of RF signal 152. Parameter 506 is graphed on the y-axis and time t is graphed on the x-axis.

[0189] Parameter 506 periodically transitions between parameter levels 0, PR1, and PR2 in synchronization with synchronization signal 502. For example, parameter 506 transitions between parameter levels 0, PR2, and PR1 during cycle 1 of synchronization signal 502, and again transitions between parameter levels 0, PR2, and PR1 during cycle 2 of synchronization signal 502. Illustratively, parameter 506 has parameter level 0 during an instance of state S0 from time t0 to time t3, and transitions between parameter levels 0, PR2, and PR1 during an instance of state S0 from time t3 to time t8. 2 During this time, the parameter level PR2 is maintained, and the state S 1 During cycle 1 of synchronization signal 502, parameter 506 transitions from parameter level 0 to parameter level PR2 at time t3, from parameter level PR2 to parameter level PR1 at time t8, and from parameter level PR1 to parameter level 0 at time t9. Parameter 506 repeats the sequence of occurrence of states S0, S2, S1, and S0 during cycle 2 of synchronization signal 502. During cycle 1 of synchronization signal 502, parameter 506 transitions from parameter level 0 to parameter level PR2 at time t3, from parameter level PR2 to parameter level PR1 at time t8, and from parameter level PR1 to parameter level 0 at time t9. Parameter 506 repeats the transitions between parameter levels 0, PR2, and PR1 during cycle 2 of synchronization signal 502.

[0190] In one embodiment, in addition to synchronization signal 502, a digital pulse signal is received by DSP 204 from processor 118 via transmission cable system 214. For example, synchronization signal 502 is received via a first transmission cable of transmission cable system 214, and the digital pulse signal is received via a second transmission cable of transmission cable system 214. The digital pulse signal similarly periodically transitions between three logic levels, and parameter 506 transitions between parameter levels 0, PR2, and PR1. For example, during cycle 1 of synchronization signal 502, the digital pulse signal transitions from logic level 0 to logic level 2 at time t3, from logic level 2 to logic level 1 at time t8, and from logic level 1 to logic level 0 at time t9. During cycle 2 of synchronization signal 502, the digital pulse signal transitions from logic level 0 to logic level 2 at time t13, transitions from logic level 2 to logic level 1 at time t18, and transitions from logic level 1 to logic level 0 at time t19. Upon receiving the digital pulse signal, DSP 204 derives parameter 50 6 and generating a command signal having these time periods. For example, the time period of state S0 of parameter 506 is equal to the time period of logic level 0 of the digital pulse signal, the time period of state S2 of parameter 506 is equal to the time period of logic level 2 of the digital pulse signal, and the time period of state S1 of parameter 506 is equal to the time period of logic level 1 of the digital pulse signal.

[0191] FIG. 5C illustrates an embodiment of a graph 508 showing a parameter 510 of an RF signal, RF signal 168 (FIG. 1), versus time t. Parameter 510 is graphed on the y-axis, and time t is graphed on the x-axis. Parameter 510 periodically transitions between parameter levels PR1, PR2, and 0 in synchronization with synchronization signal 502. For example, parameter 510 transitions between parameter levels PR1, PR2, and 0 during cycle 1 of synchronization signal 502, and again transitions between parameter levels PR1, PR2, and 0 during cycle 2 of synchronization signal 502. Illustratively, parameter 510 has parameter level PR1 during an instance of state S1 from time t0 to time t2, parameter level PR2 during state S2 from time t2 to time t5, parameter level PR1 during another instance of state S1 from time t5 to time t9, and parameter level 0 during state S0 from time t9 to time t10. The parameter levels PR1, PR2, and 0 are repeated during cycle 2 of synchronization signal 502. During cycle 1 of synchronization signal 502, parameter 510 transitions from parameter level 0 to parameter level PR1 at time t0, from parameter level PR1 to parameter level PR2 at time t2, from parameter level PR2 to parameter level PR1 at time t5, and from parameter level PR1 to parameter level 0 at time t9. During cycle 2 of synchronization signal 502, parameter 510 again transitions from parameter level 0 to parameter level PR1 at time t10, from parameter level PR1 to parameter level PR2 at time t12, from parameter level PR2 to parameter level PR1 at time t15, and from parameter level PR1 to parameter level 0 at time t19.

[0192] If the combination of parameter levels of parameters 506 and 510 during a first time period is different from the combination of parameter levels of parameters 506 and 510 during a second time period, the plasma impedance state during the first time period is different from the plasma impedance state during the second time period. For example, during the time period between times t0 and t2, the parameter level of parameter 506 of the source RF signal is 0, and during the time period between times t0 and t2, the parameter level of parameter 510 of the bias RF signal is PR1, defining a plasma impedance state PS1. During the time period between times t2 and t3, the parameter level of parameter 506 of the source RF signal is 0, and during the time period between times t2 and t3, the parameter level of parameter 510 of the bias RF signal is PR2, defining a different plasma impedance state PS2.

[0193] As another example, during the time period between times t3 and t5, the parameter level of the parameter 506 of the source RF signal is PR2, and during the time period between times t3 and t5, the parameter level of the parameter 510 of the bias RF signal is PR2, and another plasma impedance state PS 3 As another example, during the time period between times t5 and t8, the parameter level of parameter 506 of the source RF signal is PR2, and during the time period between times t5 and t8, the parameter level of parameter 510 of the bias RF signal is PR1, defining another plasma impedance state PS4, which is different from each of plasma impedance states PS1, PS2, and PS3.

[0194] As another example, during the time period between times t8 and t9, the parameter level of parameter 506 of the source RF signal is PR1, and during the time period between times t8 and t9, the parameter level of parameter 510 of the bias RF signal is PR1, defining another plasma impedance state PS5, which is different from each of plasma impedance states PS1, PS2, PS3, and PS4. As yet another example, during the time period between times t9 and t10, the parameter level of parameter 506 of the source RF signal is 0, and during the time period between times t9 and t10, the parameter level of parameter 510 of the bias RF signal is 0, defining another plasma impedance state PS6, which is different from each of plasma impedance states PS1, PS2, PS3, PS4, and PS5. Thus, during each cycle of synchronization signal 502, multiple plasma impedance states, such as six plasma impedance states PS1 through PS6, are generated due to the changes in the parameter levels of the bias RF signal and the source RF signal. The plasma impedance in plasma chamber 112 (FIG. 1), which has multiple plasma impedance states PS1 through PS6, is an example of a multi-state plasma impedance.

[0195] In one embodiment, the parameters 506 are of the RF signal 168 and the parameters 510 are of the RF signal 152 .

[0196] In one embodiment, in addition to synchronization signal 502, a digital pulse signal is received by DSP 204 from processor 118 via transmission cable system 214. For example, synchronization signal 502 is received via a first transmission cable of transmission cable system 214, and the digital pulse signal is received via a second transmission cable of transmission cable system 214. The digital pulse signal similarly periodically transitions between three logic levels, and parameter 510 transitions between parameter levels 0, PR1, and PR2. For example, during cycle 1 of synchronization signal 502, the digital pulse signal transitions from logic level 0 to logic level 1 at time t0, from logic level 1 to logic level 2 at time t2, from logic level 2 to logic level 1 at time t5, and from logic level 1 to logic level 0 at time t9. During cycle 2 of synchronization signal 502, the digital pulse signal transitions from logic level 0 to logic level 1 at time t10, from logic level 1 to logic level 2 at time t12, from logic level 2 to logic level 1 at time t15, and from logic level 1 to logic level 0 at time t19. Upon receiving the digital pulse signal, DSP 204 identifies the time periods S0, S1, and S2 of parameters 510 from the digital pulse signal and generates a command signal having these time periods. For example, the time period of state S0 of parameter 510 is the same as the time period of logic level 0 of the digital pulse signal, the time period of state S2 of parameter 510 is the same as the time period of logic level 2 of the digital pulse signal, and the time period of state S1 of parameter 510 is the same as the time period of logic level 1 of the digital pulse signal.

[0197] 6A is a graph 600 of one embodiment showing a synchronization signal 602. Graph 600 plots the logic level of synchronization signal 602 versus time t. Synchronization signal 602 is an example of synchronization signal 146 (FIG. 1). The logic level of synchronization signal 602 is plotted on the y-axis, and time t is plotted on the x-axis.

[0198] Synchronization signal 602 has a 30% duty cycle. For example, synchronization signal 602 has a logic level 1 from time t0 to time t3. Synchronization signal 602 has a logic level 0 from time t3 to time t10, a logic level 1 from time t10 to time t13, and a logic level 0 from time t13 to time t20.

[0199] Synchronization signal 602 has multiple cycles, alternating between logic levels 1 and 0 during each cycle. For example, synchronization signal 602 transitions from logic level 1 to logic level 0 at time t3 during cycle 1, and transitions from logic level 1 to logic level 0 at time t13 during cycle 2. As another example, at time t0 of cycle 1, synchronization signal 602 transitions from logic level 0 in cycle 0 of synchronization signal 602 to logic level 1 in cycle 1. Similarly, at time t10 of cycle 1, synchronization signal 602 transitions from logic level 0 in cycle 1 to logic level 1 in cycle 2. Cycle 0 of synchronization signal 602 precedes cycle 1 of synchronization signal 602, which precedes cycle 2 of synchronization signal 602.

[0200] In one embodiment, synchronization signal 602 has a different duty cycle, such as a 50% duty cycle or a 60% duty cycle, rather than a 30% duty cycle.

[0201] 6B is an embodiment of a graph 604 illustrating a parameter 606 versus time t of RF signal 152. Parameter 606 is graphed on the y-axis and time t is graphed on the x-axis.

[0202] Parameter 606 periodically transitions between parameter levels PR2, PR1, and 0 in synchronization with synchronization signal 602. For example, parameter 606 transitions between parameter levels PR2, PR1, and 0 during cycle 1 of synchronization signal 602, and again transitions between parameter levels PR2, PR1, and 0 during cycle 2 of synchronization signal 602. Illustratively, parameter 606 has parameter level PR2 during state S2 from time t0 to time t3, has parameter level PR1 during state S1 from time t3 to time t7, and has parameter level 0 during state S0 from time t7 to time t10. Parameter 606 repeats the sequence of states S2, S1, and S0 occurring during cycle 2 of synchronization signal 602. Also, during cycle 1 of synchronization signal 602, parameter 606 transitions from parameter level 0 to parameter level PR2 at time t0, from parameter level PR2 to parameter level PR1 at time t3, and from parameter level PR1 to parameter level 0 at time t7. 6 06 indicates that during cycle 2 of the synchronization signal 602, the parameter levels PR2, PR1 and Bi0 For example, during cycle 2 of synchronization signal 602, parameter 606 transitions from parameter level 0 to parameter level PR2 at time t10, from parameter level PR2 to parameter level PR1 at time t13, and from parameter level PR1 to parameter level 0 at time t17.

[0203] In one embodiment, in addition to the synchronization signal 602, a digital pulse signal is received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 602 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal similarly periodically transitions between three logic levels, and the parameter 606 transitions between parameter levels 0, PR2, and PR1. For example, during cycle 1 of the synchronization signal 602, the digital pulse signal transitions from logic level 0 to logic level 2 at time t0, from logic level 2 to logic level 1 at time t3, and from logic level 1 to logic level 0 at time t7. During cycle 2 of synchronization signal 602, the digital pulse signal transitions from logic level 0 to logic level 2 at time t10, from logic level 2 to logic level 1 at time t13, and from logic level 1 to logic level 0 at time t17. Upon receiving the digital pulse signal, DSP 204 calculates the value of parameter 60 from the digital pulse signal. 6 and generating a command signal having these time periods. For example, the time period of state S0 of parameter 606 is equal to the time period of logic level 0 of the digital pulse signal, the time period of state S2 of parameter 606 is equal to the time period of logic level 2 of the digital pulse signal, and the time period of state S1 of parameter 606 is equal to the time period of logic level 1 of the digital pulse signal.

[0204] FIG. 6C illustrates an embodiment of a graph 608 showing a parameter 610 of an RF signal, RF signal 168 (FIG. 1), versus time t. Parameter 610 is graphed on the y-axis, and time t is graphed on the x-axis. Parameter 610 periodically transitions between parameter levels 0, PR1, and PR2 in synchronization with synchronization signal 602. For example, parameter 610 transitions between parameter levels 0, PR1, and PR2 during cycle 1 of synchronization signal 602, and again transitions between parameter levels 0, PR1, and PR2 during cycle 2 of synchronization signal 602. Illustratively, parameter 610 has parameter level 0 during state S0 from time t0 to time t1, parameter level PR1 during state S1 from time t1 to time t5, parameter level PR2 during another instance of state S2 from time t5 to time t8, and parameter level 0 during another instance of state S0 from time t8 to time t10. The parameter levels 0, PR1, and PR2 are repeated during cycle 2 of synchronization signal 602. During cycle 1 of synchronization signal 602, parameter 610 transitions from parameter level 0 to parameter level PR1 at time t1, from parameter level PR1 to parameter level PR2 at time t5, and from parameter level PR2 to parameter level 0 at time t8. During cycle 2 of synchronization signal 602, parameter 610 again transitions from parameter level 0 to parameter level PR1 at time t11, from parameter level PR1 to parameter level PR2 at time t15, and from parameter level PR2 to parameter level 0 at time t18.

[0205] If the combination of parameter levels of parameters 606 and 610 during a first time period is different from the combination of parameter levels of parameters 606 and 610 during a second time period, the plasma impedance state during the first time period is different from the plasma impedance state during the second time period. For example, during the time period between times t0 and t1, the parameter level of parameter 606 of the source RF signal is PR2, and during the time period between times t0 and t1, the parameter level of parameter 610 of the bias RF signal is 0, defining a plasma impedance state PS1. During the time period between times t1 and t3, the parameter level of parameter 606 of the source RF signal is PR2, and during the time period between times t1 and t3, the parameter level of parameter 610 of the bias RF signal is PR1, defining a different plasma impedance state PS2.

[0206] As another example, during the time period between times t3 and t5, the parameter level of parameter 606 of the source RF signal is PR1, and during the time period between times t3 and t5, the parameter level of parameter 610 of the bias RF signal is PR1, defining another plasma impedance state PS3, which is different from each of plasma impedance states PS1 and PS2. As yet another example, during the time period between times t5 and t7, the parameter level of parameter 606 of the source RF signal is PR1, and during the time period between times t5 and t7, the parameter level of parameter 610 of the bias RF signal is PR2, defining another plasma impedance state PS4, which is different from each of plasma impedance states PS1, PS2, and PS3.

[0207] As another example, during the time period between times t7 and t8, the parameter level of parameter 606 of the source RF signal is 0, and during the time period between times t7 and t8, the parameter level of parameter 610 of the bias RF signal is PR2, defining another plasma impedance state PS5, which is different from each of plasma impedance states PS1, PS2, PS3, and PS4. As yet another example, during the time period between times t8 and t10, the parameter level of parameter 606 of the source RF signal is 0, and during the time period between times t8 and t10, the parameter level of parameter 610 of the bias RF signal is 0, defining another plasma impedance state PS6, which is different from each of plasma impedance states PS1, PS2, PS3, PS4, and PS5. Thus, during each cycle of synchronization signal 602, multiple plasma impedance states, such as six plasma impedance states PS1 through PS6, are generated due to the changes in the parameter levels of the bias RF signal and the source RF signal. The plasma impedance in plasma chamber 112 (FIG. 1), which has multiple plasma impedance states PS1 through PS6, is an example of a multi-state plasma impedance.

[0208] In one embodiment, the parameters 606 are for the RF signal 168 and the parameters 610 are for the RF signal 152 .

[0209] In one embodiment, in addition to the synchronization signal 602, a digital pulse signal is received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 602 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal similarly periodically transitions between three logic levels, and the parameter 610 transitions between parameter levels 0, PR1, and PR2. For example, the synchronization signal 6During cycle 1 of synchronization signal 602, the digital pulse signal transitions from logic level 0 to logic level 1 at time t1, from logic level 1 to logic level 2 at time t5, and from logic level 2 to logic level 1 at time t8. During cycle 2 of synchronization signal 602, the digital pulse signal transitions from logic level 0 to logic level 1 at time t11, from logic level 1 to logic level 2 at time t15, and from logic level 2 to logic level 1 at time t18. Upon receiving the digital pulse signal, DSP 204 identifies the time periods of S0, S2, and S1 of parameters 610 from the digital pulse signal and generates a command signal having these time periods. For example, the time period of state S0 of parameter 610 is the same as the time period of logic level 0 of the digital pulse signal, the time period of state S2 of parameter 610 is the same as the time period of logic level 2 of the digital pulse signal, and the time period of state S1 of parameter 610 is the same as the time period of logic level 1 of the digital pulse signal.

[0210] In one embodiment, parameter level PR3 is used for any of parameters 310 (FIG. 3C), 402 (FIG. 4C), 510 (FIG. 5C), and 610 (FIG. 6C) instead of parameter level PR1. Parameter level PR3 is greater than or less than parameter level PR1. Similarly, parameter level PR4 is used for any of parameters 310, 402, 510, and 610 instead of parameter level PR2. Parameter level PR4 is greater than or less than parameter level PR1. 2 greater than or less than.

[0211] 6D is a diagram of one embodiment for on-off time correction by selective synchronization between a source RF generator and a bias RF generator. As shown with respect to FIG. 6D, Turn onWhen the first RF generator is turned on, there is a time delay from time t1 to time t2 compared to a second RF generator, such as a bias RF generator or a source RF generator. Also, the time at which the RF power supplied to the first RF generator is turned off is advanced from time t4 to time t3. Thus, instead of two plasma impedance states S1 and S0, three or more plasma impedance states are generated, such as six, eight, ten, or twenty plasma impedance states.

[0212] Multi-state pulsed components

[0213] FIG. 7 is a diagram of one embodiment of a plasma system 700 illustrating multi-level parameter pulsing. The plasma system 700 includes an RF generator 702 and a host computer 106. The RF generator 702 is an example of the source RF generator 102 (FIG. 1) or the bias RF generator 104 (FIG. 1). The RF generator 702 includes a DSP 204 and multiple parameter controllers PRS1a, PRS2a, PRS3a,..., PRSna, where n is an integer greater than or equal to 4. For example, n is greater than or equal to 4. As an example, the RF generator 702 includes four parameter controllers, one for state S1a, another for state S2a, another for state S3a, and another for state S4a. As another example, RF generator 702 includes five parameter controllers, one for state S1a, one for state S2a, one for state S3a, one for state S4a, and one for state S5a. RF generator 702 further includes frequency controller FC210, driver system 710, and RF power supply 222.

[0214] DSP 204 is coupled to each of parameter controllers PRS1a to PRSna of RF generator 702. Parameter controllers PRS1a to PRSna are coupled to driver system 710, which is coupled to RF power supply 222. Frequency controller 210 is also coupled to driver system 710.

[0215] Processor 118 provides parameters, such as parameter levels for states S1a through Sna, and synchronization signal 146 to DSP 204 via transmission cable system 214. Upon receiving the parameter levels for states S1a through Sna, DSP 204 provides parameters, such as the power level or voltage level of state S1a of RF signal 712 to parameter controller PRS1a and stores the parameters for state S1a in the memory device of parameter controller PRS1a. RF signal 712 is an example of RF signal 152 or RF signal 168 (FIG. 1).

[0216] Also, in response to receiving the parameter levels for states S1a through Sna, the DSP 204 controls the parameter levels, such as the power level or voltage level, of the RF signal 712 for state S2a to the parameter controller 716. PR S2a and parameter controller PRIn response to receiving the parameter levels for states S1a through Sna, DSP 204 provides parameter levels, such as power levels or voltage levels, for state S3a of RF signal 712 to parameter controller PRS3a and stores the parameters for state PRS3a in the memory device of parameter controller S3a. In response to receiving the parameters for states S1a through Sna, DSP 204 provides parameter levels, such as power levels or voltage levels, for state Sna of RF signal 712 to parameter controller PRSna and stores the parameters for state Sna in the memory device of parameter controller PRSna. Similarly, upon receiving the parameters for states S1a through Sna, DSP 204 provides frequency levels, such as a single frequency level, for all states S1a through Sna to frequency controller 210 and stores them in the memory device of frequency controller 210.

[0217] In one embodiment, the values ​​of the (n-1)th parameter level are different from the values ​​of the nth parameter level. For example, the values ​​of the (n-1)th parameter level exclude the values ​​of the nth parameter level. As another example, none of the values ​​of the (n-1)th parameter level are the same as any of the values ​​of the nth parameter level.

[0218] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S1a to the parameter controller PRS1a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S1a to the parameter controller PRS1a when transitioning to state S1a from a state other than or different from state S1a, such as state Sna or state S0. The command signal for state S1a transmitted to the parameter controller PRS1a includes the time period of state S1a during each cycle, and the parameter controller PRS1a provides the parameter levels for state S1a to the driver system 710. Upon receiving the command signal for state S1a, the parameter controller PRS1a accesses the parameter levels for state S1a from the memory device of the parameter controller PRS1a and transmits the parameter levels for the time period of state S1a to the driver system 710. For example, when the parameter controller PRS1a transitions to state S1a from a state different from state S1a, it transmits the parameter levels of state S1a to the driver system 710. After the time period of state S1a, for a cycle of the synchronization signal 146, the parameter controller PRS1a does not transmit the parameter levels of state S1a to the driver system 710.

[0219] Similarly, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S2a to the parameter controller PRS2a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S2a to the parameter controller PRS2a when transitioning to state S2a from a state other than state S2a, such as state S1a, state S3a, or state S0. The command signal for state S2a transmitted to the parameter controller PRS2a includes the time period of state S2a during each cycle, and the parameter controller PRS2a provides the parameter levels for state S2a to the driver system 710. Upon receiving the command signal for state S2a, the parameter controller PRS2a accesses the parameter levels for state S2a from the memory device of the parameter controller PRS2a and transmits the parameter levels for the time period of state S2a to the driver system 710. For example, when the parameter controller PRS2a transitions to state S2a from a state different from state S2a, it transmits the parameter levels of state S2a to the driver system 710. After the time period of state S2a, for a cycle of the synchronization signal 146, the parameter controller PRS2a does not transmit the parameter levels of state S2a to the driver system 710.

[0220] Additionally, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S3a to the parameter controller PRS3a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits the command signal for state S3a to the parameter controller PRS3a when transitioning to state S3a from a state other than state S3a, such as state S2a, state S1a, or state S0. The command signal for state S3a transmitted to the parameter controller PRS3a includes the time period of state S3a during each cycle, and the parameter controller PRS3a provides the parameter levels for state S3a to the driver system 710. Upon receiving the command signal for state S3a, the parameter controller PRS3a accesses the parameter levels for state S3a from the memory device of the parameter controller PRS3a and transmits the parameter levels for the time period of state S3a to the driver system 710. For example, when the parameter controller PRS3a transitions to state S3a from a state different from state S3a, it transmits the parameter levels of state S3a to the driver system 710. After the time period of state S3a, for a cycle of the synchronization signal 146, the parameter controller PRS3a does not transmit the parameter levels of state S3a to the driver system 710.

[0221] Furthermore, upon receiving the synchronization signal 146, the DSP 204 transmits a state Sna command signal to the parameter controller PRSna during each cycle of the synchronization signal 146. For example, the DSP 204 transmits the state Sna command signal to the parameter controller PRSna when transitioning to state Sna from a state other than or different from state Sna, such as state S(n-1)a or state S0. The state Sna command signal transmitted to the parameter controller PRSna includes the time period of state Sna during each cycle, and the parameter controller PRSna provides the parameter levels of state Sna to the driver system 710. Upon receiving the state Sna command signal, the parameter controller PRSna accesses the parameter levels of state Sna from the memory device of the parameter controller PRSna and transmits the parameter levels for the time period of state Sna to the driver system 710. For example, when the parameter controller PRSna transitions to state Sna from a state different from state Sna, it transmits the parameter levels of state Sna to the driver system 710. After the time period of state Sna, for a cycle of the synchronization signal 146, the parameter controller PRSna does not transmit the parameter levels of state Sna to the driver system 710.

[0222] Additionally, upon receiving the synchronization signal 146, the DSP 204 sends a command signal to the frequency controller 210 during each cycle of the synchronization signal 146. Upon receiving the command signal, the frequency controller 210 accesses a frequency level from its memory device and sends the frequency level to the driver system 710.

[0223] In response to receiving the parameter levels and frequency levels for state S1a, driver system 710 generates a drive signal for state S1a for the time period of state S1a and transmits the drive signal to RF power supply 222. For example, when transitioning to state S1a from a state other than or different from state S1a, such as state Sna, state S2a, state S3a, or state S0, upon receiving the parameter levels and frequency levels for state S1a, driver system 710 generates a drive signal for state S1a for the time period of state S1a and transmits the drive signal to RF power supply 222. Upon receiving the drive signal for state S1a from driver system 710, RF power supply 222 generates state S1a for RF signal 712. For example, upon receiving the drive signal for state S1a from driver system 710, RF power supply 222 transitions RF signal 712 from a state other than state S1a to state S1a. State S1a of RF signal 712 has parameter levels and frequency levels of state S1a for the time period of state S1a.

[0224] Similarly, in response to receiving the parameter levels and frequency levels for state S2a, driver system 710 generates a drive signal for state S2a for the time period of state S2a and transmits the drive signal to RF power supply 222. For example, when transitioning to state S2a from a state other than or different from state S2a, such as state S1a, state S3a, state Sna, or state S0, upon receiving the parameter levels and frequency levels for state S2a, driver system 710 generates a drive signal for state S2a for the time period of state S2a and transmits the drive signal to RF power supply 222. Upon receiving the drive signal for state S2a from driver system 710, RF power supply 222 generates state S2a for RF signal 712. For example, upon receiving the drive signal for state S2a from driver system 710, RF power supply 222 transitions RF signal 712 from a state other than state S2a to state S2a. State S2a of RF signal 712 has parameter levels and frequency levels of state S2a for the time period of state S2a.

[0225] Additionally, in response to receiving the parameter levels and frequency levels for state S3a, driver system 710 generates a drive signal for state S3a for the time period of state S3a and transmits the drive signal to RF power supply 222. For example, when transitioning to state S3a from a state other than or different from state S3a, such as state S2a, state S4a, state Sna, or state S0, upon receiving the parameter levels and frequency levels for state S3a, driver system 710 generates a drive signal for state S3a for the time period of state S3a and transmits the drive signal to RF power supply 222. Upon receiving the drive signal for state S3a from driver system 710, RF power supply 222 generates state S3a for RF signal 712. For example, upon receiving the drive signal for state S3a from driver system 710, RF power supply 222 transitions RF signal 712 from a state other than state S3a to state S3a. State S3a of RF signal 712 has parameter levels and frequency levels of state S3a for the time period of state S3a.

[0226] Further, in response to receiving the parameter level and frequency level for state Sna, the driver system 710 generates a drive signal for state Sna for the time period of state Sna and transmits the drive signal to the RF power supply 222. For example, in state S(n-1)a, state S0, or state S3 a Or state S2 a When transitioning to state Sna from a state other than or different from state Sna, such as when receiving the parameter levels and frequency levels of state Sna, driver system 710 generates a drive signal for state Sna for the time period of state Sna and transmits the drive signal to RF power supply 222. When RF power supply 222 receives the drive signal for state Sna from driver system 710, it generates state Sna of RF signal 712. For example, when receiving the drive signal for state Sna from driver system 710, RF power supply 222 transitions RF signal 712 from a state other than state Sna to state Sna. State Sna of RF signal 712 has the parameter levels and frequency levels of state Sna for the time period of state Sna.

[0227] Also, in one embodiment, there is a time period during each cycle of the synchronization signal 146 during which the RF signal 712 has a parameter level of zero. The RF signal 712 has a parameter level of zero during no state, such as state S0. Upon receiving the synchronization signal 146, during each cycle of the synchronization signal 146, the DSP 204 does not send command signals for states S1a through Sna to parameter controllers PRS1a through PRSna during the time period during no state.

[0228] During the time period between states S1a and Sna when no command signal is received, parameter controllers PRS1a through PRSna do not transmit or stop transmitting the parameter levels for states S1a through Sna to driver system 710. For example, after the time period of state S1a, parameter controller PRS1a does not transmit the parameter levels for state S1a to driver system 710. As another example, after the time period of state S2a, parameter controller PRS2a does not transmit the parameter levels for state S2a to driver system 710.

[0229] If the driver system 710 does not receive a parameter level for states S1a through Sna, it does not send a drive signal to the RF power supply 222. If it does not receive a drive signal during the no state time period, it 222 generates an RF signal 712 having a parameter level of zero during State No. For example, when not receiving a drive signal, the power supply 222 transitions the RF signal 712 to State No. S0 from a state other than or different from State No. S0, such as State S1a or State S2a or State Sna.

[0230] States S1a through Sna and State None are parameter states of RF signal 712. For example, each of states S1a through Sna and State None described with reference to Figure 7 represents a parameter level of RF signal 712. For example, state S1a of RF signal 712 identifies a first parameter level of RF signal 712, and state S2a of RF signal 712 identifies a second parameter level of RF signal 712.

[0231] In one embodiment, rather than parameter controllers PRS1a to PRSna and frequency controller 210, one or more controllers, such as one or more processors, are used to perform the functions described herein that are performed by parameter controllers PRS1a to PRSna and frequency controller 210.

[0232] In one embodiment, rather than DSP 204, parameter controllers PRS1a to PRSna, and frequency controller 210, one or more controllers, such as one or more processors, are used to perform the functions described herein that are performed by DSP 204, parameter controllers PRS1a to PRSna, and frequency controller 210.

[0233] FIG. 8 is a diagram of one embodiment of a plasma system 800 illustrating multi-level frequency pulsing. The plasma system 800 includes an RF generator 802 and a host computer 106. The RF generator 802 is an example of the source RF generator 102 (FIG. 1) or the bias RF generator 104 (FIG. 1). The RF generator 802 includes a DSP 204 and multiple frequency controllers FCS1a, FCS2a, FCS3a,..., FCSna, where n is an integer greater than or equal to 4. For example, n is greater than or equal to 4. As an example, the RF generator 802 includes four frequency controllers, one in state S1a, another in state S2a, another in state S3a, and another in state S4a. As another example, RF generator 802 includes five frequency controllers, one frequency controller in state S1a, one frequency controller in state S2a, another frequency controller in state S3a, another frequency controller in state S4a, and one frequency controller in state S5a. RF generator 802 further includes parameter controller 814, driver system 810, and RF power supply 222.

[0234] DSP 204 is coupled to each of frequency controllers FCS1a to FCSna of RF generator 802. Frequency controllers FCS1a to FCSna are coupled to driver system 810, which is coupled to RF power supply 222. In addition, parameter controller 814 is coupled to driver system 810.

[0235] Processor 118 provides frequencies, such as frequency levels for states S1a through Sna, and synchronization signal 146 to DSP 204 via transmission cable system 214. Upon receiving the frequency levels for states S1a through Sna, DSP 204 provides frequencies, such as the frequency level for state S1a, of RF signal 812 to frequency controller FCS1a and stores the frequency for state S1a in a memory device of frequency controller FCS1a. RF signal 812 is an example of RF signal 152 or RF signal 168 (FIG. 1).

[0236] In response to receiving the frequency levels for states S1a through Sna, DSP 204 also provides the frequency level for state S2a of RF signal 812 to frequency controller FCS2a and stores the frequency level for state S2a in the memory device of frequency controller FCS2a. In response to receiving the frequency levels for states S1a through Sna, DSP 204 also provides the frequency level for state S3a of RF signal 812 to frequency controller FCS3a and stores the frequency level for state S3a in the memory device of frequency controller FCS3a. In response to receiving the frequency levels for states S1a through Sna, DSP 204 also provides the frequency level for state Sna of RF signal 812 to frequency controller FCSna and stores the frequency level for state Sna in the memory device of frequency controller FCSna. Similarly, upon receiving a parameter level, such as a single parameter level for all of states S1a through Sna, DSP 204 provides the parameter level to parameter controller 814 for storage in the memory device of parameter controller 814.

[0237] In one embodiment, the value of the (n-1)th frequency level is different from the value of the nth frequency level. For example, the value of the (n-1)th frequency level is exclusive of the value of the nth frequency level. As another example, none of the values ​​of the (n-1)th frequency level are the same as any of the values ​​of the nth frequency level.

[0238] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S1a to the frequency controller FCS1a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S1a to the frequency controller FCS1a when transitioning to state S1a from a state other than state S1a, such as state S2a, state S0, or state S3a. The command signal for state S1a transmitted to the frequency controller FCS1a includes the time period of state S1a during each cycle, and the frequency controller FCS1a provides the frequency level for state S1a to the driver system 810. Upon receiving the command signal for state S1a, the frequency controller FCS1a accesses the parameter level for state S1a from the memory device of the frequency controller FCS1a and transmits the frequency level for the time period of state S1a to the driver system 810. For example, when the frequency controller FCS1a transitions to state S1a from a state different from state S1a, it transmits the frequency level of state S1a to the driver system 810. After the time period of state S1a, for a cycle of the synchronization signal 146, the frequency controller FCS1a does not transmit the frequency level of state S1a to the driver system 810.

[0239] Similarly, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S2a to the frequency controller FCS2a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S2a to the frequency controller FCS2a when transitioning to state S2a from a state other than state S2a, such as state S1a, state S0, or state S3a. The command signal for state S2a transmitted to the frequency controller FCS2a includes the time period of state S2a during each cycle, and the frequency controller FCS2a provides the frequency level for state S2a to the driver system 810. Upon receiving the command signal for state S2a, the frequency controller FCS2a accesses the parameter level for state S2a from the memory device of the frequency controller FCS2a and transmits the frequency level for the time period of state S2a to the driver system 810. For example, when the frequency controller FCS2a transitions to state S2a from a state different from state S2a, it transmits the frequency level of state S2a to the driver system 810. After the time period of state S2a, for a cycle of the synchronization signal 146, the frequency controller FCS2a does not transmit the frequency level of state S2a to the driver system 810.

[0240] Additionally, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state S3a to the frequency controller FCS3a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state S3a to the frequency controller FCS3a when transitioning to state S3a from a state other than state S3a, such as state S2a, state S1a, or state S0. The command signal for state S3a transmitted to the frequency controller FCS3a includes the time period of state S3a during each cycle, and the frequency controller FCS3a provides the frequency level for state S3a to the driver system 810. Upon receiving the command signal for state S3a, the frequency controller FCS3a accesses the parameter level for state S3a from the memory device of the frequency controller FCS3a and transmits the frequency level for the time period of state S3a to the driver system 810. For example, when the frequency controller FCS3a transitions to state S3a from a state different from state S3a, it transmits the frequency level of state S3a to the driver system 810. After the time period of state S3a, for a cycle of the synchronization signal 146, the frequency controller FCS3a does not transmit the frequency level of state S3a to the driver system 810.

[0241] Furthermore, upon receiving the synchronization signal 146, the DSP 204 transmits a state Sna command signal to the frequency controller FCSna during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a state Sna command signal to the frequency controller FCSna when transitioning to state Sna from a state other than or different from state Sna, such as state S(n-1)a or state S0. The state Sna command signal transmitted to the frequency controller FCSna includes the time period of state Sna during each cycle, and the frequency controller FCSna provides the frequency level of state Sna to the driver system 810. Upon receiving the state Sna command signal, the frequency controller FCSna accesses the parameter level of state Sna from the memory device of the frequency controller FCSna and transmits the frequency level for the time period of state Sna to the driver system 810. For example, when the frequency controller FCSna transitions to state Sna from a state different from or other than state Sn, it transmits the frequency level of state Sna to the driver system 810. After the time period of state Sna, during the cycle of the synchronization signal 146, the frequency controller FCSna does not transmit the frequency level of state Sna to the driver system 810.

[0242] Additionally, upon receiving the synchronization signal 146, the DSP 204 sends a command signal to the parameter controller 814 during each cycle of the synchronization signal 146. Upon receiving the command signal, the parameter controller 814 accesses the parameter levels from the memory device of the parameter controller 814 and sends the parameter levels to the driver system 810.

[0243] In response to receiving the frequency level and parameter level for state S1a, driver system 810 generates a drive signal for state S1a for the time period of state S1a and transmits the drive signal to RF power supply 222. For example, when transitioning to state S1a from a state other than or different from state S1a, such as state S2a, state S3a, state Sna, or state S0, upon receiving the frequency level and parameter level for state S1a, driver system 810 generates a drive signal for state S1a for the time period of state S1a and transmits the drive signal to RF power supply 222. Upon receiving the drive signal for state S1a from driver system 810, RF power supply 222 generates state S1a for RF signal 812. For example, upon receiving the drive signal for state S1a from driver system 810, RF power supply 222 transitions RF signal 812 from a state other than state S1a to state S1a. State S1a of RF signal 812 has the frequency level and parameter levels of state S1a for the time period of state S1a.

[0244] Similarly, in response to receiving the frequency level and parameter level for state S2a, driver system 810 generates a drive signal for state S2a for the time period of state S2a and transmits the drive signal to RF power supply 222. For example, when transitioning to state S2a from a state other than or different from state S2a, such as state S1a, state S0, or state S3a, upon receiving the frequency level and parameter level for state S2a, driver system 810 generates a drive signal for state S2a for the time period of state S2a and transmits the drive signal to RF power supply 222. Upon receiving the drive signal for state S2a from driver system 810, RF power supply 222 generates state S2a for RF signal 812. For example, upon receiving the drive signal for state S2a from driver system 810, RF power supply 222 transitions RF signal 812 from a state other than state S2a to state S2a. State S2a of RF signal 712 has the frequency and parameter levels of state S2a for the time period of state S2a.

[0245] Additionally, in response to receiving the frequency level and parameter level for state S3a, driver system 810 generates a drive signal for state S3a for the time period of state S3a and transmits the drive signal to RF power supply 222. For example, when transitioning to state S3a from a state other than or different from state S3a, such as state S2a, state S0, state S1a, or state S4a, upon receiving the frequency level and parameter level for state S3a, driver system 810 generates a drive signal for state S3a for the time period of state S3a and transmits the drive signal to RF power supply 222. Upon receiving the drive signal for state S3a from driver system 810, RF power supply 222 generates state S3a for RF signal 812. For example, upon receiving the drive signal for state S3a from driver system 810, RF power supply 222 transitions RF signal 812 from a state other than state S3a to state S3a. State S3a of RF signal 812 has the frequency and parameter levels of state S3a for the time period of state S3a.

[0246] Further, in response to receiving the frequency level and parameter level of state Sna, the driver system 810 generates a drive signal for state Sna for the time period of state Sna and transmits the drive signal to the RF power supply 222. For example, when transitioning to state Sna from a state other than or different from state Sna, such as state S(n-1)a or state S0, upon receiving the frequency level and parameter level of state Sna, the driver system 810 generates a drive signal for state Sna for the time period of state Sna and transmits the drive signal to the RF power supply 222. Upon receiving the drive signal for state Sna from the driver system 810, the RF power supply 222 generates state Sna for the RF signal 812. For example, upon receiving the drive signal for state Sna from the driver system 810, the RF power supply 222 transitions the RF signal 812 from a state other than state Sna to state Sna. State Sna of the RF signal 812 has the frequency level and parameter level of state Sna for the time period of state Sna.

[0247] Also, in one embodiment, there is a time period during each cycle of the synchronization signal 146 during which the RF signal 812 has a frequency level of zero. The RF signal 812 has a frequency level of zero during no state, such as state S0. Upon receiving the synchronization signal 146, during each cycle of the synchronization signal 146, the DSP 204 does not send command signals for states S1a to Sna to the frequency controllers FCS1a to FCSna and the parameter controller 814 during the time period during no state.

[0248] During the time period between states S1a to Sna not receiving a command signal, frequency controllers FCS1a to FCSna do not transmit or stop transmitting the frequency levels of states S1a to Sna to driver system 810, and parameter controller 814 stops transmitting parameter levels to driver system 810. For example, after the time period of state S1a, frequency controller FCS1a does not transmit the frequency level of state S1a to driver system 810. As another example, after the time period of state S2a, frequency controller FCS2a does not transmit the frequency level of state S2a to driver system 810.

[0249] If the frequency and parameter levels of states S1a through Sna are not received, the driver system 810 does not send a drive signal to the RF power supply 222. If no drive signal is received during the no state time period, the RF power supply 222 generates an RF signal 812 having a parameter level of zero during State No. For example, when not receiving a drive signal, the power supply 222 transitions the RF signal 812 to State No. S0 from a state other than or different from State No. S0, such as State S1a or State S2a or State Sna.

[0250] States S1a to Sna and State None are frequency states of the RF signal 812. For example, each of states S1a to Sna and State None described with reference to Figure 8 represents a frequency level of the RF signal 812. For example, state S1 of the RF signal 812 identifies a first frequency level of the RF signal 812, and state S2 of the RF signal 812 identifies a second frequency level of the RF signal 812.

[0251] In one embodiment, rather than frequency controllers FCS1a to FCSna and parameter controller 814, one or more controllers, such as one or more processors, are used to perform the functions described herein that are performed by frequency controllers FCS1a to FCSna and parameter controller 814.

[0252] In one embodiment, rather than DSP 204, frequency controllers FCS1a to FCSna, and parameter controller 814, one or more controllers, such as one or more processors, are used to perform the functions performed by DSP 204, frequency controllers FCS1a to FCSna, and parameter controller 814 described herein.

[0253] 9 is a diagram of one embodiment of a plasma system 900 illustrating simultaneous multi-level parameter pulsing and multi-level frequency pulsing. The plasma system 900 includes an RF generator 902 and a host computer 106. The RF generator 902 is an example of the source RF generator 102 (FIG. 1) or the bias RF generator 104 (FIG. 1). The RF generator 902 includes the DSP 204, frequency controllers FCS1a through FCSna, and parameter controllers PRS1a through PRSna. The RF generator 902 further includes a driver system 910 and an RF power supply 222.

[0254] DSP 204 is coupled to each of frequency controllers FCS1a to FCSna and each of parameter controllers PRS1a to PRSna of RF generator 902. Frequency controllers FCS1a to FCSna and power controllers PRS1 to PRSna are coupled to driver system 910, which is coupled to RF power supply 222.

[0255] Processor 118 provides the frequency levels for states S1a through Sna and the parameter levels for states S1a through Sna, as well as synchronization signal 146, to DSP 204 via transmission cable system 214. As described above with reference to FIG. 8, in response to receiving the frequency levels for states S1a through Sna, DSP 204 provides the frequency levels for states S1a through Sna in RF signal 912 to frequency controllers FCS1a through FCSna and stores the frequency levels for states S1a through Sna in the memory devices of frequency controllers FCS1a through FCSna. RF signal 912 is an example of RF signal 152 or RF signal 168 (FIG. 1). Similarly, as described above with reference to FIG. 7, in response to receiving the parameter levels for states S1a through Sna, DSP 204 provides the parameter levels for states S1a through Sna of RF signal 912 to parameter controllers PRS1a through PRSna and stores the parameter levels for states S1a through Sna in the memory devices of parameter controllers PRS1a through PRSna.

[0256] Upon receiving the synchronization signal 146, the DSP 204 transmits command signals for states S1a through Sna to frequency controllers FCS1a through FCSna during each cycle of the synchronization signal 146, as described above with reference to Figure 8. Additionally, upon receiving the synchronization signal 146, the DSP 204 transmits command signals for states S1a through Sna to parameter controllers PRS1a through PRSna during each cycle of the synchronization signal 146, as described above with reference to Figure 7.

[0257] As described above with reference to Figure 8, upon receiving a command signal for states S1a to Sna, frequency controllers FCS1a to FCSna access frequency levels for states S1a to Sna from their memory devices and transmit the frequency levels for the time period of states S1a to Sna to driver system 910. Similarly, as described above with reference to Figure 7, upon receiving a command signal for states S1a to Sna, parameter controllers PRS1a to PRSna access parameter levels for states S1a to Sna from their memory devices and transmit the parameter levels for the time period of states S1a to Sna to driver system 910.

[0258] As described above with reference to Figures 7 and 8, in response to receiving the frequency levels of states S1a to Sna and the parameter levels of states S1a to Sna, the driver system 9The driver system 910 generates drive signals for the frequency level state S1a to Sna and the parameter level state S1a to Sna and transmits the drive signals to the RF power supply 222. For example, when transitioning to state Sna from a state other than or different from state Sna, such as state S(n-1)a or state S0, upon receiving the frequency level and parameter level of state Sna, the driver system 910 generates drive signals for the frequency level state Sna and the parameter level state Sna for the time period of state Sna and transmits the drive signals to the RF power supply 222. Upon receiving the drive signal for the frequency level and parameter level state Sna from the driver system 910, the RF power supply 222 generates the frequency level state Sna and the parameter level state Sna of the RF signal 912. For example, upon receiving the drive signal for the frequency level state Sna from the driver system 910, the RF power supply 222 transitions the frequency level of the RF signal 912 from a state other than or different from state Sna to state Sna. The state Sna of the RF signal 912 has a frequency level of the state Sna. When the drive signal for the parameter level state Sna is received from the driver system 910, the RF power supply 222 transitions the parameter level of the RF signal 912 from a state different from the state Sna to the state Sna. The state Sna of the RF signal 912 has a parameter level of the state Sna.

[0259] Also, in one embodiment, there is a time period during each cycle of the synchronization signal 146 during which the RF signal 912 has a zero frequency level and a zero parameter level. The RF signal 912 has a zero frequency level and a zero parameter level during no state, such as state S0. Upon receiving the synchronization signal 146, during each cycle of the synchronization signal 146, the DSP 204 does not send command signals for states S1a through Sna to frequency controllers FCS1a through FCSna and does not send command signals for states S1a through Sna to parameter controllers PRS1a through PRSna during the time period during no state.

[0260] As explained above with reference to Figure 8, during the time period between the frequency level states S1a to Sna not receiving a command signal, the frequency controllers FCS1a to FCSna do not transmit or stop transmitting the frequency levels of states S1a to Sna to the driver system 910. Similarly, as explained above with reference to Figure 7, during the time period between the parameter level states S1a to Sna not receiving a command signal, the parameter controllers PRS1a to PRSna do not transmit or stop transmitting the parameter levels of states S1a to Sna to the driver system 910.

[0261] If the driver system 910 does not receive a frequency level from states S1a to Sna and a parameter level from states S1a to Sna, the driver system 910 does not send a drive signal to the RF power supply 222. If the drive signal is not received during a time period of no state, the RF power supply 222 generates an RF signal 912 having a zero parameter level and a zero frequency level during the no state. For example, if the drive signal is not received, the power supply 222 transitions the RF signal 912 from a state other than or different from no state S0, such as frequency level state S1a, frequency level state S2a, or frequency level state Sna, to frequency level state S0. Similarly, if the drive signal is not received, the power supply 222 transitions the RF signal 912 from a state other than or different from parameter level state S0, such as parameter level state S1a, parameter level state S2a, or parameter level state Sna, to parameter level state S0.

[0262] In one embodiment, rather than the frequency controllers FCS1a to FCSna and the parameter controllers PRS1a to PRSna, one or more controllers, such as one or more processors, are used to perform the functions described herein performed by the frequency controllers FCS1a to FCSna and the parameter controllers PRS1a to PRSna.

[0263] In one embodiment, rather than DSP 204, frequency controllers FCS1a to FCSna, and parameter controllers PRS1a to PRSna, one or more controllers, such as one or more processors, are used to perform the functions described herein performed by DSP 204, frequency controllers FCS1a to FCSna, and parameter controllers PRS1a to PRSna.

[0264] In one embodiment, when the source RF generator generates RF signal 152 (FIG. 1) having multiple variable levels, such as four variable levels, bias RF generator 104 generates RF signal 168, which is a continuous wave signal, and RF signal 168 has the single variable level of RF signal 152 or a different number of variable levels, such as two or three or eight or ten. As another example, when the bias RF generator generates RF signal 168 (FIG. 1) having multiple variable levels, such as four variable levels, source RF generator 102 generates RF signal 152, which is a continuous wave signal, and RF signal 152 has the single variable level of RF signal 168 or a different number of variable levels, such as two or three or eight or ten.

[0265] In one embodiment, RF signals 152 and 168 have the same number of variable levels, such as six variable levels or eight variable levels.

[0266] FIG. 10A is a graph 300 of one embodiment showing a synchronization signal 302.

[0267] 10B is an embodiment graph 1004 showing a variable 1006 of the RF signal 912 (FIG. 9) versus time t. The variable 1006 is graphed on the y-axis and time t is graphed on the x-axis.

[0268] The variable 1006 periodically transitions between variable levels V8a, 0, V6a, and V2a in a state synchronized with the synchronization signal 302. For example, the variable 1006 transitions between variable levels V8a, 0, V6a, and V2a during cycle 1 of the synchronization signal 302, and again transitions between variable levels V8a, 0, V6a, and V2a during cycle 2 of the synchronization signal 302. Illustratively, the variable 1006 has variable level V8a during state S4a from time t0 to time t2.5, a variable level of zero during state none from time t2.5 to time t5, variable level V6a during state S3a from time t5 to time t7.5, and variable level V2a during state S1a from time t7.5 to time t10. Time t2.5 occurs between times t2 and t3. Similarly, time t7.5 occurs between times t7 and t8. During cycle 1 of the synchronization signal 302, the variable 1006 transitions from variable level V2a to variable level V8a at time t0, from variable level V8a to a variable level of zero at time t2.5, from a variable level of zero to variable level V6a at time t5, and from variable level V6a to variable level V2a at time t7.5. During cycle 2 of the synchronization signal 302, the variable 1006 also transitions from variable level V2a to variable level V8a at time t10, from variable level V8a to a variable level of zero at time t12.5, from a variable level of zero to variable level V6a at time t15, and from variable level V6a to variable level V2a at time t17.5. Time t12.5 occurs between times t12 and t13. Similarly, time t17.5 occurs between times t17 and t18. The variable level V8a is a variable level for state S4a of the RF signal 912, the variable level of zero is an example of a variable level for state 0 of the RF signal 912, the variable level V6a is an example of a variable level for state S3a of the RF signal 912, and the variable level V2a is an example of a variable level for state S1a of the RF signal 912.

[0269] Variable level V2a is greater than variable level 0. Also, variable level V6a is greater than variable level V2a, and variable level V8a is greater than variable level V6a. For example, the power value of variable level V6a is less than the power value of variable level V8a. As another example, none of the power values ​​of variable level V6a exceeds the power value of variable level V8a. As another example, the variable levels have maximum and minimum values. The maximum value is the maximum of all values ​​of the variable level, and the minimum value is the minimum of all values ​​of the variable level. A first variable level is less than a second variable level if the maximum value of the first variable level is less than the minimum value of the second variable level, and a first variable level is greater than a second variable level if the minimum value of the first variable level is greater than the maximum value of the second variable level.

[0270] In one embodiment, rather than achieving variable level V2a, variable 1006 has a variable level of zero. For example, variable 1006 has a variable level of zero from time t7.5 to time t10 and from time t17.5 to time t20.

[0271] In one embodiment, the transition time between two variable levels is the time period between the transition start time and the transition end time. For example, rather than transitioning from variable level V8a to a variable level of zero at time t2.5, variable 1006 begins transitioning from variable level V8a at a first time and finishes transitioning to a variable level of zero at a second time. The first time is before time t2.5, between times t1 and t2.5, and the second time is after time t2.5, between times t2.5 and t4. The transition time period is the transition time between the first time and the second time.

[0272] In one embodiment, in addition to the synchronization signal 302, a digital pulse signal is received by the DSP 204 from the processor 118 via the transmission cable system 214. For example, the synchronization signal 302 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal similarly periodically transitions among four variable levels, with the parameter 1006 transitioning between variable levels V8a and zero, V6a and V2a. For example, during cycle 1 of the synchronization signal 302, the digital pulse signal transitions from logic level 1 to logic level 3 at time t0, from logic level 3 to logic level 0 at time t2.5, from logic level 0 to logic level 2 at time t5, and from logic level 2 to logic level 1 at time t7.5. Logic level 3 is greater than logic level 2. For example, logic level 3 has a greater DC voltage than logic level 2. Upon receiving the digital pulse signal, the DSP 204 identifies the time periods of S4a, no state, S3a, and S1a of the variable 1006 from the digital pulse signal and generates a command signal having these time periods. For example, the time period of the state S4a of the variable 1006 is the same as the time period of logic level 3 of the digital pulse signal, the time period of the state S0 of the variable 1006 is the same as the time period of logic level 0 of the digital pulse signal, the time period of the state S3a of the variable 1006 is the same as the time period of logic level 2 of the digital pulse signal, and the time period of the state S1a of the variable 1006 is the same as the time period of logic level 1 of the digital pulse signal.

[0273] 10C is a graph 1008 of one embodiment showing a variable 1010 of the RF signal 912 (FIG. 9) versus time t, where the variable 1010 is graphed on the y-axis and time t is graphed on the x-axis.

[0274] The variable 1010 periodically transitions between variable levels V8a, V6a, V4a, and V2a in a state synchronized with the synchronization signal 302. For example, the variable 1010 transitions between variable levels V8a, V6a, V4a, and V2a during cycle 1 of the synchronization signal 302, and also transitions between variable levels V8a, V6a, V4a, and V2a during cycle 2 of the synchronization signal 302. By way of example, the variable 1010 has a variable level V8a during state S4a from time t0 to time t2.5, a variable level V6a during state S3a from time t2.5 to time t5, a variable level V4a during state S2a from time t5 to time t7.5, and a variable level V2a during state S1a from time t7.5 to time t10. During cycle 1 of the synchronization signal 302, the variable 1010 transitions from variable level V2a to variable level V8a at time t0, from variable level V8a to variable level V6a at time t2.5, from variable level V6a to variable level V4a at time t5, and from variable level V4a to variable level V2a at time t7.5. During cycle 2 of the synchronization signal 302, the variable 1010 also transitions from variable level V2a to variable level V8a at time t10, from variable level V8a to variable level V6a at time t12.5, from variable level V6a to variable level V4a at time t15, and from variable level V4a to variable level V2a at time t17.5. The variable level V4a is an example of a variable level for state S2a of the RF signal 912.

[0275] Variable level V4a is greater than variable level V2a and less than variable level V6a. For example, the power value of variable level V4a is less than the power value of variable level V6a and greater than the power value of variable level V2a. As another example, none of the power values ​​of variable level V4a is greater than the power value of variable level V6a, and none of the power values ​​of variable level V2a is greater than the power value of variable level V4a.

[0276] In one embodiment, rather than achieving variable level V2a, variable 1010 has a variable level of zero. For example, variable 1010 has a variable level of zero from time t7.5 to time t10 and from time t17.5 to time t20.

[0277] 10D is a graph 1012 of one embodiment showing a variable 1014 of the RF signal 912 (FIG. 9) versus time t, where the variable 1014 is graphed on the y-axis and time t is graphed on the x-axis.

[0278] The variable 1014 periodically transitions between variable levels V8a, V2a, V6a, and zero in a state synchronized with the synchronization signal 302. For example, the variable 1014 transitions between variable levels V8a, V2a, V6a, and zero during cycle 1 of the synchronization signal 302, and also transitions between variable levels V8a, V2a, V6a, and zero during cycle 2 of the synchronization signal 302. By way of example, the variable 1014 has variable level V8a during state S4a from time t0 to time t2.5, variable level V2a during state S1a from time t2.5 to time t5, variable level V6a during state S3a from time t5 to time t7.5, and variable level zero during state S0 from time t7.5 to time t10. During cycle 1 of the synchronization signal 302, the variable 1014 transitions from a variable level of zero to variable level V8a at time t0, from variable level V8a to variable level V2a at time t2.5, from variable level V2a to variable level V6a at time t5, and from variable level V6a to a variable level of zero at time t7.5. During cycle 2 of the synchronization signal 302, the variable 1014 also transitions from a variable level of zero to variable level V8a at time t10, from variable level V8a to variable level V2a at time t12.5, from variable level V2a to variable level V6a at time t15, and from variable level V6a to a variable level of zero at time t17.5.

[0279] 10E is a graph 1016 of one embodiment showing a variable 1018 of the RF signal 912 (FIG. 9) versus time t, where the variable 1018 is graphed on the y-axis and time t is graphed on the x-axis.

[0280] The variable 1018 periodically transitions between variable levels V8a, V6a, V2a, and V4a in a state synchronized with the synchronization signal 302. For example, the variable 1018 transitions between variable levels V8a, V6a, V2a, and V4a during cycle 1 of the synchronization signal 302, and also transitions between variable levels V8a, V6a, V2a, and V4a during cycle 2 of the synchronization signal 302. By way of example, the variable 1018 has variable level V8a during state S4a from time t0 to time t2.5, has variable level V6a during state S3a from time t2.5 to time t5, has variable level V2a during state S1a from time t5 to time t7.5, and has variable level V4a during state S2a from time t7.5 to time t10. During cycle 1 of the synchronization signal 302, the variable 1018 transitions from variable level V4a to variable level V8a at time t0, from variable level V8a to variable level V6a at time t2.5, from variable level V6a to variable level V2a at time t5, and from variable level V2a to variable level V4a at time t7.5. During cycle 2 of the synchronization signal 302, the variable 1018 also transitions from variable level V4a to variable level V8a at time t10, from variable level V8a to variable level V6a at time t12.5, from variable level V6a to variable level V2a at time t15, and from variable level V2a to variable level V4a at time t17.5.

[0281] In one embodiment, rather than achieving variable level V2a, variable 1018 has a variable level of zero. For example, variable 1018 has a variable level of zero from time t5 to time t7.5 and from time t15 to time t17.5.

[0282] 10F is a graph 1020 of one embodiment showing a variable 1022 of the RF signal 912 (FIG. 9) versus time t, where the variable 1022 is graphed on the y-axis and time t is graphed on the x-axis.

[0283] Variable 1022 periodically transitions between variable levels V6a, V8a, V4a, and V2a in a state synchronized with synchronization signal 302. For example, variable 1022 transitions between variable levels V6a, V8a, V4a, and V2a during cycle 1 of synchronization signal 302, and again transitions between variable levels V6a, V8a, V4a, and V2a during cycle 2 of synchronization signal 302. Illustratively, variable 1022 has variable level V6a during state S3a from time t0 to time t2.5, variable level V8a during state S4a from time t2.5 to time t5, variable level V4a during state S2a from time t5 to time t7.5, and variable level V2a during state S1a from time t7.5 to time t10. During cycle 1 of synchronization signal 302, variable 1022 2 transitions from variable level V2a to variable level V6a at time t0, from variable level V6a to variable level V8a at time t2.5, from variable level V8a to variable level V4a at time t5, and from variable level V4a to variable level V2a at time t7.5. During cycle 2 of the synchronization signal 302, variable 10 22 also transitions from variable level V2a to variable level V6a at time t10, from variable level V6a to variable level V8a at time t12.5, from variable level V8a to variable level V4a at time t15, and from variable level V4a to variable level V2a at time t17.5.

[0284] 10G is a graph 1024 of one embodiment showing a variable 1026 of the RF signal 912 (FIG. 9) versus time t, where the variable 1026 is graphed on the y-axis and time t is graphed on the x-axis.

[0285] Variable 1026 periodically transitions between variable levels V4a, V6a, V8a, and V2a in a state synchronized with synchronization signal 302. For example, variable 1026 transitions between variable levels V4a, V6a, V8a, and V2a during cycle 1 of synchronization signal 302, and also transitions between variable levels V4a, V6a, V8a, and V2a during cycle 2 of synchronization signal 302. By way of example, variable 1024 has variable level V4a during state S2a from time t0 to time t2.5, variable level V6a during state S3a from time t2.5 to time t5, variable level V8a during state S4a from time t5 to time t7.5, and variable level V2a during state S1a from time t7.5 to time t10. During cycle 1 of the synchronization signal 302, the variable 1026 transitions from variable level V2a to variable level V4a at time t0, from variable level V4a to variable level V6a at time t2.5, from variable level V6a to variable level V8a at time t5, and from variable level V8a to variable level V2a at time t7.5. During cycle 2 of the synchronization signal 302, the variable 1026 also transitions from variable level V2a to variable level V4a at time t10, from variable level V4a to variable level V6a at time t12.5, from variable level V6a to variable level V8a at time t15, and from variable level V8a to variable level V2a at time t17.5.

[0286] In one embodiment, rather than achieving variable level V2a, variable 1026 has a variable level of zero. For example, variable 1026 has a variable level of zero from time t7.5 to time t10 and from time t17.5 to time t20.

[0287] 10H is a graph 1028 of one embodiment showing a variable 1030 of the RF signal 912 (FIG. 9) versus time t, where the variable 1030 is graphed on the y-axis and time t is graphed on the x-axis.

[0288] The variable 1030 periodically transitions between variable levels V8a, V6a, V4a, V2a, and zero in a state synchronized with the synchronization signal 302. For example, the variable 1030 transitions between variable levels V8a, V6a, V4a, V2a, and zero during cycle 1 of the synchronization signal 302, and also transitions between variable levels V8a, V6a, V4a, V2a, and zero during cycle 2 of the synchronization signal 302. Illustratively, the variable 1030 has variable level V8a during state S4a from time t0 to time t2, variable level V6a during state S3a from time t2 to time t4, variable level V4a during state S2a from time t4 to time t6, variable level V2a during state S1a from time t6 to time t8, and variable level 0 during no state from time t8 to time t10. During cycle 1 of the synchronization signal 302, the variable 1030 transitions from a variable level of zero to variable level V8a at time t0, from variable level V8a to variable level V6a at time t2, from variable level V6a to variable level V4a at time t4, from variable level V4a to variable level V2a at time t6, and from variable level V2a to a variable level of zero at time t8. During cycle 2 of the synchronization signal 302, the variable 1030 also transitions from a variable level of zero to variable level V8a at time t10, from variable level V8a to variable level V6a at time t12, from variable level V6a to variable level V4a at time t14, from variable level V4a to variable level V2a at time t16, and from variable level V2a to a variable level of zero at time t18.

[0289] In one embodiment, a stepwise decreasing change in the variable level is shown in graph 1028, however, it should be noted that stepwise increasing changes in the variable level may occur. For example, during each cycle of the synchronization signal, the variable of the RF signal 912 may increase from zero to a variable level V2a, from variable level V2a to a variable level V4a, from variable level V4a to a variable level V6a, and from variable level V6a to a variable level V8a.

[0290] 10I is a graph 1032 of one embodiment showing a variable 1034 of the RF signal 912 (FIG. 9) versus time t, where the variable 1034 is graphed on the y-axis and time t is graphed on the x-axis.

[0291] The variable 1034 periodically transitions between variable levels V8a, V16a, V14a, V12a, V10a, V8a, V6a, V4a, V2a, and zero in synchronization with the synchronization signal 302. For example, the variable 1034 transitions between variable levels V18a, V16a, V14a, V12a, V10a, V8a, V6a, V4a, V2a, and zero during cycle 1 of the synchronization signal 302, and also transitions between variable levels V18a, V16a, V14a, V12a, V10a, V8a, V6a, V4a, V2a, and zero during cycle 2 of the synchronization signal 302. For example, variable 1034 has a variable level V18a during state S9a from time t0 to time t1, a variable level V16a during state S8a from time t1 to time t2, a variable level V14a during state S7a from time t2 to time t3, a variable level V12a during state S6a from time t3 to time t4, a variable level V10a during state S5a from time t4 to time t5, a variable level V8a during state S4a from time t5 to time t6, a variable level V6a during state S3a from time t6 to time t7, a variable level V4a during state S2a from time t7 to time t8, a variable level V2a during state S1a from time t8 to time t9, and a variable level of zero during state S0 from time t9 to time t10. During cycle 1 of the synchronization signal 302, the variable 1034 transitions from a variable level of zero to variable level V18a at time t0, from variable level V18a to variable level V16a at time t1, from variable level V16a to variable level V14a at time t2, from variable level V14a to variable level V12a at time t3, from variable level V12a to variable level V10a at time t4, from variable level V10a to variable level V8a at time t5, from variable level V8a to variable level V6a at time t6, from variable level V6a to variable level V4a at time t7, from variable level V4a to variable level V2a at time t8, and from variable level V2a to a variable level of zero at time t9. During cycle 2 of the synchronization signal 302, the variable 1034 4transitions from the zero variable level to variable level V18a at time t10, from variable level V18a to variable level V16a at time t11, from variable level V16a to variable level V14a at time t12, from variable level V14a to variable level V12a at time t13, from variable level V12a to variable level V10a at time t14, from variable level V10a to variable level V8a at time t15, from variable level V8a to variable level V6a at time t16, from variable level V6a to variable level V4a at time t17, from variable level V4a to variable level V2a at time t18, and from variable level V2a to the zero variable level at time t19.

[0292] Variable level V10a is greater than variable level V8a. Also, variable level V12a is greater than variable level V10a, and variable level V14a is greater than variable level V12a. Variable level V16a is greater than variable level V14a, and variable level V18a is greater than variable level V16a. For example, the power value of variable level V14a is less than the power value of variable level V16a. As another example, none of the power values ​​of variable level V14a exceed the power value of variable level V16a.

[0293] In one embodiment, a stepwise decreasing change in variable level is shown in graph 1032, however, it should be noted that stepwise increasing changes in variable level may occur. For example, during each cycle of the synchronization signal, the variable of the RF signal 912 may increase from zero to variable level V2a, from variable level V2a to variable level V4a, from variable level V4a to variable level V6a, from variable level V6a to variable level V8a, from variable level V8a to variable level V10a, and so on up to variable level V18a.

[0294] 10J is a diagram of an embodiment in which an RF generator 1070 is provided having multiple power controllers and multiple automatic frequency tuners (AFTs). The RF generator 1070 is an example of the source RF generator 102 or bias RF generator 104 (FIG. 1). RF generatorThe power control unit 1070 further includes a DSP 204 and an RF power supply 222. The DSP 204 is an example of a receiver. S(n-A) and another power controller PWR S(n-1) and the power controller PWR Sn AFT stands for Automatic Frequency Tuner AFT S(n-A) and another automatic frequency tuner AFT S(n-1) and the automatic frequency tuner AFT Sn and so on until an automatic frequency tuner is included. As used herein, an automatic frequency tuner is also a frequency controller.

[0295] During state S(nA), the automatic frequency tuner AFT S(n-A) tunes the frequency of the RF signal 220 generated by the RF power supply 222 or controls the power controller PWR S(n-A) modifies the power of the RF signal 220, or modifies both the frequency and power, where (nA) is an integer less than the integer n, and A is an integer. For example, if n is 4 or 5 or 10, then (nA) is 1. For example, during state S(nA), the DSP 204 sends a control signal to the automatic frequency tuner AFT S(n-A) , which indicates a logic level, such as a voltage level of state S(nA). S(n-A) Automatic Frequency Tuner AFT S(n-A) The frequency level for state S(nA) is accessed from a database in the memory device of the automatic frequency tuner AFT. S(n-A) DSP 204 provides a frequency level for state S(nA) to RF power supply 222. Upon receiving the frequency level for state S(nA), RF power supply 222 generates RF signal 220 having a frequency level during state S(nA). Similarly, during state S(nA), DSP 204 provides a control signal to power controller PWR S(n-A) to indicate the logic level of the state S(nA). S(n-A) is the power controller PWR S(n-A) The power level PL for state S (nA) is calculated from the database in the memory device.S(n-A) Access the power controller PWR S(n-A) is the power level PL for state S(nA) S(n-A) to the RF power supply 222. The power level PL for the state S(nA) S(n-A) Upon receiving this, the RF power supply 222 sets the power level PL S(n-A) The RF signal 220 has a magnitude of:

[0296] Similarly, during state S(n-1), the automatic frequency tuner AFT S(n-1) tunes the frequency of the RF signal 220 generated by the RF power supply 222 or controls the power controller PWR S(n-1) modifies the power, or both the frequency and power, of the RF signal 220. Also, during state Sn, the automatic frequency tuner AFT Sn tunes the frequency of the RF signal 220 generated by the RF power supply 222 or controls the power controller PWR Sn modifies the power of the RF signal 220, or modifies both the frequency and power.

[0297] The RF signal 220 is provided to an impedance matching circuit 216 via an output, such as an RF output port, of the RF generator 1070, which generates a modified signal based on the RF signal 220 and provides the modified RF signal to an electrode, such as a TCP electrode or a bottom electrode, of the plasma chamber 112 (FIG. 1). The bottom electrode is located within the chuck of the plasma chamber 112. The electrode or the plasma chamber 112 is an example of a load.

[0298] The RF signal 220 is generated when a digital pulse signal having states S(n-4) through Sn is received by the DSP 204 from the host controller or host computer 106 (FIG. 1), another processor in the controller, or an analog-digital voltage control interface (ADVCI). The digital pulse signal is received at an input of the DSP 204, such as an input port, shown in FIG. 10J. If the DSP 204 is located within the RF generator 1070, the digital pulse signal is received by an input port of the RF generator 1070. The digital pulse signal is an example of an input signal and is generated by another processor or ADVCI. The duty cycle, such as the duration, of each of the four states S(n-4) through Sn is identified by the digital pulse signal. The four states occur during a clock cycle of a clock signal received at another input, such as another input port of the processor, shown in FIG. 10J. The clock signal is generated by another processor or ADVCI.

[0299] In one embodiment, a level, such as a power level or frequency level, includes one or more values ​​or amounts within a predetermined range. For example, a first power level has one or more values ​​of power within a predetermined range, and a second power level has one or more values ​​within the predetermined range. The second power level is exclusive of the first power level. For example, none of the power values ​​of the second power level are the same as the power values ​​of the first power level.

[0300] FIG. 10K is a diagram of one embodiment showing an RF signal, where the RF signal has a power level PL S(n-3) , P.L. S(n-2) , P.L. S(n-1) and PL Sn The four states S(n-3), S(n-2), S(n-1), and Sn represent the power level PL of the RF signal generated by an RF generator, such as source RF generator 102 or bias RF generator 104 (FIG. 1), during state Sn. Sn is the power level PL of the RF signal during state S(n-1). S(n-1)Similarly, the power level PL of the RF signal during state S(n-1) is S(n-1) is the power level PL of the RF signal during state S(n-2). S(n-2) and the power level PL of the RF signal during state S(n-2) is lower than S(n-2) is the power level PL of the RF signal during state S(n-3). S(n-3) Lower than.

[0301] 10L is a diagram of an embodiment showing another RF signal having four states S(n-3), S(n-2), S(n-1), and Sn. The RF signal shown in FIG. 10L also shows the RF signal during state S(n-1) at a power level PL S(n-2) Higher power levels than PL S(n-1) , which is a step-decreasing signal except that

[0302] 10M is a diagram of an embodiment showing another RF signal having four states S(n-3), S(n-2), S(n-1), and Sn. The RF signal shown in FIG. 10M also shows that the RF signal during state Sn has a power level PL S(n-1) Higher power levels than PL Sn , which is a step-decreasing signal except that

[0303] FIG. 10N is a diagram of an embodiment showing yet another RF signal having four states S(n-3), S(n-2), S(n-1), and Sn. 10N The RF signal shown in FIG. 1 is a signal that is transmitted at a power level PL during state S(n-2) and at a power level PL during state S(n-3). S(n-3) Higher power levels than PL S(n-2) , which is a step-decreasing signal except that

[0304] 10O is a diagram of an embodiment showing yet another RF signal having four states S(n-3), S(n-2), S(n-1), and Sn. The RF signal maintains a power level PL S(n-3) From PL S(n-1)During state Sn, the power level PL from state S(n-1) is increased stepwise to S(n-1) The power level PL Sn Decrease gradually until

[0305] figure 10J During each clock cycle of the clock signal received by the RF generator processor, the power level PL S(n-3) From PL Sn Repeat until the power level PL reaches the specified value for multiple clock cycles. S(n-3) From PL Sn is repeated. The clock signal is received from a clock source, or a processor in a host computer, or a host controller, or an ADVCI. The clock signal is generated by a clock source, or a processor in a host computer, or a processor in a host controller, or an ADVCI. Similarly, the power level PL S(n-A) From PL Sn The power level PL is maintained for multiple clock cycles. S(n-A) From PL Sn The process is repeated until the power level PL S(n-A) From PL Sn occurs once during an instance of a clock cycle and is repeated during each subsequent instance of a clock cycle.

[0306] figure 10B ~Figure 10I Note that the RF signal shown in either of the figures is the envelope of the sinusoidal RF signal generated by the RF generator, either source RF generator 102 or bias RF generator 104 (FIG. 1).

[0307] 10P is a diagram of one embodiment of a method for illustrating that a zero power level is achieved during any of states S(nA) through Sn. As shown in FIG. 10P, rather than the RF signal having a zero power level during state Sn, the RF signal has a zero power level in another state, such as S2 or S3.

[0308] In one embodiment, the embodiments described herein in Figures 10K-10P relating to power apply equally to frequency, e.g., multiple frequency levels are achieved between states S(nA) through Sn instead of or in addition to multiple power levels.

[0309] It should be noted that in one embodiment, a zero power level is achieved when the power level is zero. In one embodiment, a zero power level is achieved when the RF power level is near or substantially zero, such as within a preset range. An example of a preset range value is a range between 0.1 watts and 1 watt. Another example of a preset range value is a range between 0.1 watts and 0.25 watts. Yet another example of a preset range value is a range between 0.1 watts and 0.5 watts.

[0310] Transition Control

[0311] FIG. 11A is a diagram of one embodiment of a plasma system 1100 illustrating gradient control of state transitions. The plasma system 1100 includes an RF generator 1102 and a host computer 106. The RF generator 1102 is an example of the source RF generator 102 (FIG. 1) or the bias RF generator 104 (FIG. 1). The RF generator 1102 includes a DSP 204, parameter controllers PRS1a through PRSna, and multiple transition parameter controllers PRST1a, PRTS2a, PRST(n-1)a, and PRSTna, where n is an integer greater than or equal to 4. For example, n is greater than or equal to 4. As an example, the RF generator 1102includes four transition parameter controllers: one transition parameter controller for a state transition ST1a between parameter states S1a and S2a during the current cycle of the synchronization signal; another transition parameter controller for a state transition ST2a between parameter states S2a and S3a during the current cycle of the synchronization signal; another transition parameter controller for a state transition ST(n-1)a between parameter states S(n-1)a and Sna during the current cycle of the synchronization signal; and another transition parameter controller for a state transition STna between parameter state Sna during the current cycle of the synchronization signal and parameter state S1a during the next cycle of the synchronization signal. The current cycle precedes the next cycle. For example, there is no cycle of the synchronization signal between the current cycle and the next cycle. As another example, RF generator 1102 includes five transition parameter controllers.

[0312] The RF generator 1102 further includes frequency controllers FCS1a to FCSna and a plurality of transition frequency controllers FCST1a, FCTS2a, FCST(n-1)a, and FCSTna, where n is an integer equal to or greater than 4. For example, n is equal to or greater than 4. As an example, the RF generator 1102 includes four transition frequency controllers, and one transition frequency controller controls a state transition ST1 between frequency states S1a and S2a during the current cycle of the synchronization signal. a and another transition frequency controller for state transition ST2 between frequency states S2a and S3a during the current cycle of the synchronization signal. a Another transition frequency controller is for a state transition ST(n-1)a between frequency states S(n-1)a and Sna during the current cycle of the synchronization signal, and another transition frequency controller is for a state transition STna between frequency state Sna during the current cycle of the synchronization signal and frequency state Sla during the next cycle of the synchronization signal. As another example, RF generator 1102 includes five transition frequency controllers. RF generator 1102 further includes a driver system 1104 and an RF power supply 222.

[0313] The DSP 204 is coupled to each of the parameter controllers PRS1a through PRSna and each of the transition parameter controllers PRST1a through PRSTna of the RF generator 1102. The parameter controllers PRS1a through PRSna and the transition parameter controllers PRST1a through PRSTna are coupled to a driver system 1104, which is coupled to an RF power source 222.

[0314] DSP 204 is also coupled to each of frequency controllers FCS1a through FCSna and each of transition frequency controllers FCST1a through FCSTna of RF generator 1102. Frequency controllers FCS1a through FCSna and transition frequency controllers FCST1a through FCSTna are coupled to driver system 1104. The functionality of system 1110 is described below with reference to FIG.

[0315] FIG. 11B is a diagram of one embodiment of a system 1100 illustrating the functionality of the system 1100. The system 1100 includes an RF generator 1102 and a host computer 106. The RF generator 1102 includes a DSP 204, a parameter controller PRS(N±M)a, a transition parameter controller PRSTa, and a parameter controller PRSNa, where N is an integer greater than or equal to 1 and N±M is an integer different from N. For example, if N is 1, N±M is 2, 3, or 4, and if N is 3, N±M is 4, 2, or 1. The integers N±M define M, which is a positive integer. Examples of the parameter controller PRSNa include the parameter controllers PRS1a, PRS2a, PRS3a, or PRSna (FIG. 11A). Examples of parameter controller PRS(N±M)a include parameter controller PRS1a, PRS2a, PRS3a, or PRSna (FIG. 11A), and parameter controller PRS(N±M) is different from parameter controller PRSNa. For example, if parameter controller PRSNa is PRS4a, parameter controller PRS(N±M)a is PRS2a or PRS1a.

[0316] Examples of transition parameter controller PRSTa include parameter controller PRST1a, PRST2a, PRST3a, PRST(n-1), or PRSTna (FIG. 11A). For example, if parameter controller PRSNa is parameter controller PRS1a and parameter controller PRS(N±M)a is parameter controller PRS2a, transition parameter controller PRSTa is PRST1a that controls the transition of the parameter between states S1a and S2a. As another example, if parameter controller PRSNa is parameter controller PRS3a and parameter controller PRS(N±M)a is parameter controller PRS5a, transition parameter controller PRSTa is PRST3a that controls the transition of the parameter between states S3a and S5a.

[0317] It should be noted that RF generator 1102 may include any number of transition parameter controllers, such as transition parameter controller PRSTa. For example, if a parameter transitions from synchronization signal 146's previous cycle state S4a to current cycle state S1a, from current cycle state S1a to current cycle state S2a, from current cycle state S2a to current cycle state S3a, and from current cycle state S3a to current cycle state S4a, RF generator 1102 may include four transition parameter controllers. The four transition parameter controllers include one transition parameter controller that controls synchronization signal 146's transition from previous cycle state S4a to current cycle state S1a, another transition parameter controller that controls synchronization signal 146's transition from current cycle state S1a to current cycle state S2a, another transition parameter controller that controls synchronization signal 146's transition from current cycle state S2a to current cycle state S3a, and another transition parameter controller that controls synchronization signal 146's transition from current cycle state S2a to current cycle state S3a, and another transition parameter controller that controls synchronization signal 146's transition from current cycle state S3a to current cycle state S4a. The previous cycle of the synchronization signal 146 precedes the current cycle of the synchronization signal 146 .

[0318] The RF generator 1102 further includes a frequency controller FCS(N±M)a, a transition frequency controller FCSTa, and a frequency controller FCSNa, where M and N are defined above. Examples of the frequency controller FCSNa include frequency controller FCS1a or FCS2a or FCS3a or FCSna (FIG. 11A). Examples of the frequency controller FCS(N±M)a include frequency controller FCS1a or FCS2a or FCS3a or FCSna (FIG. 11A), where frequency controller FCS(N±M) is different from frequency controller FCSNa.

[0319] Examples of the transition frequency controller FCSTa include frequency controller FCST1a, FCST2a, FCST3a, FCST(n-1), or FCSTna. For example, if the frequency controller FCSNa is frequency controller FCS1a and the frequency controller FCS(N±M)a is frequency controller FCS2a, the transition frequency controller FCSTa is FCST1a that controls the transition between frequency states S1a and S2a. As another example, if the frequency controller FCSNa is frequency controller FCS3a and the frequency controller FCS(N±M)a is frequency controller FCS5a, the transition frequency controller FCSTa is FCST3a that controls the transition between frequency states S3a and S5a.

[0320] It should be noted that RF generator 1102 may include any number of transition frequency controllers, such as transition frequency controller FCSTa. For example, if the frequency transitions from synchronization signal 146's previous cycle state S4a to current cycle state S1a, from current cycle state S1a to current cycle state S2a, from current cycle state S2a to current cycle state S3a, and from current cycle state S3a to current cycle state S4a, RF generator 1102 may include four transition frequency controllers: one transition frequency controller that controls synchronization signal 146's transition from previous cycle state S4a to current cycle state S1a, another transition frequency controller that controls synchronization signal 146's transition from current cycle state S1a to current cycle state S2a, another transition frequency controller that controls synchronization signal 146's transition from current cycle state S2a to current cycle state S3a, and another transition frequency controller that controls synchronization signal 146's transition from current cycle state S2a to current cycle state S3a, and another transition frequency controller that controls synchronization signal 146's transition from current cycle state S3a to current cycle state S4a.

[0321] The DSP 204 is coupled to the parameter controllers PRS(N±M) and PRSNa and the transition parameter controller PRSTa. The DSP 204 is also coupled to the frequency controllers PRS(N±M) and FCSNa and the transition frequency controller FCSTa. The parameter controllers PRS(N±M)a and PRSNa, the transition parameter controller PRSTa, the frequency controllers FCS(N±M)a and FCSNa, and the transition frequency controller FCSTa are coupled to a driver system 1104, which is coupled to an RF power supply 222.

[0322] Processor 118 provides parameter levels and synchronization signals 146 for states S(N±M) and SNa to DSP 204 via transmission cable system 214. Additionally, processor 118 provides one or more parameter values ​​for the parameter's state transition STa to DSP 204 via transmission cable system 214. For example, processor 118 provides one or more parameter values ​​to be achieved during the parameter's state transition ST1a, one or more parameter values ​​to be achieved during the parameter's state transition ST2a, one or more parameter values ​​to be achieved during the parameter's state transition ST(n-1)a, and one or more parameter values ​​to be achieved during the parameter's state transition STna.

[0323] The parameter state transition STa is a transition between the parameter state S(N±M) and SNa. For example, the parameter state transition STa is a transition from the parameter state S(N±M)a to the parameter state SNa, or a transition from the parameter state SNa to the parameter state S(N±M)a.

[0324] The processor 118 also provides frequency levels for states S(N±M) and SNa to the DSP 204 via the transmission cable system 214. The processor 118 also provides frequency values ​​for frequency state transition STa to the DSP 204 via the transmission cable system 214. For example, the processor 118 provides one or more frequency values ​​to be achieved during frequency state transition ST1a, one or more frequency values ​​to be achieved during frequency state transition ST2a, one or more frequency values ​​to be achieved during frequency state transition ST2a, one or more frequency values ​​to be achieved during frequency state transition ST(n-1)a, and one or more frequency values ​​to be achieved during frequency state transition STna.

[0325] The frequency state transition STa is a transition between the frequency states S(N±M) and SNa. For example, the frequency state transition STa is a transition from the frequency state S(N±M)a to the frequency state SNa, or a transition from the frequency state SNa to the frequency state S(N±M)a.

[0326] Upon receiving the parameter levels for states S(N±M)a and SNa, DSP 204 provides the parameter level for state S(N±M)a of RF signal 1106 to parameter controller PRS(N±M)a and stores the parameter level for state S(N±M)a in the memory device of parameter controller PRS(N±M)a. RF signal 1106 is an example of RF signal 152 or RF signal 168 (FIG. 1). Furthermore, upon receiving one or more parameter values ​​for parameter transition state STa, DSP 204 provides one or more parameter values ​​for parameter transition state STa of RF signal 1106 to transition parameter controller PRSTa and stores the parameter value for transition state STa in the memory device of transition parameter controller PRSTa. An example of a parameter value during state transition STa is the envelope, such as the zero-to-peak amplitude or peak-to-peak amplitude, of the parameter of RF signal 1106 during state transition STa. Also, in response to receiving the parameter levels for states S(N±M)a to SNa, DSP 204 provides the parameter levels for state SNa of RF signal 1106 to parameter controller PRSNa and stores the parameter levels for state SNa in the memory device of parameter controller PRSNa.

[0327] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for the parameter state S(N±M)a to the parameter controller PRS(N±M)a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for the state S(N±M)a to the parameter controller PRS(N±M)a at the end of the transition time from a state different from or other than state S(N±M)a, such as state S(N±M-1)a or state S0, to state S(N±M)a. The command signal for the state S(N±M)a transmitted to the parameter controller PRS(N±M)a includes the time period of state S(N±M)a during each cycle, and the parameter controller PRS(N±M)a supplies the parameter level for state S(N±M)a to the driver system 1104. Upon receiving the command signal for state S(N±M)a, parameter controller PRS(N±M)a accesses the parameter levels for state S(N±M)a from its memory device and transmits the parameter levels for the time period of state S(N±M)a to driver system 1104. For example, parameter controller PRS(N±M)a transmits the parameter levels for state S(N±M)a to driver system 1104 at the end of the transition time from a state different from state S(N±M)a to state S(N±M)a. After the time period of state S(N±M)a, parameter controller PRS(N±M)a does not transmit the parameter levels for state S(N±M)a to driver system 1104 for the cycle of synchronization signal 146.

[0328] Similarly, upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for the state transition STa to the transition parameter controller PRSTa during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for the state transition STa to the transition parameter controller PRSTa at the start of the transition time from state S(N±M)a to state SNa or at the start of the transition time from state S0 to state SNa. The command signal for the state transition STa transmitted to the transition parameter controller PRSTa includes the time period of the state transition STa during each cycle, and the transition parameter controller PRSTa provides one or more parameter values ​​for the state transition STa to the driver system 1104. Upon receiving the command signal for the state transition STa, the transition parameter controller PRSTa accesses one or more parameter values ​​for the state transition STa from the memory device of the transition parameter controller PRSTa and transmits the one or more parameter values ​​to the driver system 1104 during the time period of the state transition STa. For example, at the end of the state S(N±M)a time, the transition parameter controller PRSTa transmits one or more parameter values ​​of the state transition STa to the driver system 1104. After the time period of the state transition STa, during the cycle of the synchronization signal 146, the transition parameter controller PRSTa does not transmit one or more parameter levels of the state transition STa to the driver system 1104.

[0329] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state SNa to the parameter controller PRSNa during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state transition SNa to the parameter controller PRSNa at the end of the transition time from state S(N±M)a to state SNa. The command signal for state SNa transmitted to the parameter controller PRSNa includes the time period for state Sna during each cycle, and the parameter controller PRSNa provides the parameter levels for state SNa to the driver system 1104. Upon receiving the command signal for state SNa, the parameter controller PRSNa accesses the parameter levels for state SNa from the memory device of the parameter controller PRSNa and transmits the parameter levels to the driver system 1104 during the time period for state SNa. For example, the parameter controller PRSNa transmits the parameter levels for state SNa to the driver system 1104 at the end of the transition time from state S(N±M)a to state SNa. After the time period for state SNa, during the cycle of the synchronization signal 146, the parameter controller PRSNa does not send the parameter levels for state SNa to the driver system 1104.

[0330] Similarly, upon receiving the frequency levels for states S(N±M)a and SNa, the DSP 204 provides the frequency level of state S(N±M)a of the frequency of the RF signal 1106 to the frequency controller FCS(N±M)a and stores the frequency level of state S(N±M)a in the memory device of the frequency controller FCS(N±M)a. Furthermore, upon receiving one or more frequency values ​​of a state transition STa of the frequency, the DSP 204 provides one or more frequency values ​​of the state transition STa of the frequency of the RF signal 1106 to the transition frequency controller FCSTa and stores the frequency value of the state transition STa in the memory device of the transition frequency controller FCSTa. An example of a frequency value during state transition STa is the envelope, such as the zero-to-peak amplitude or peak-to-peak amplitude, of the frequency of the RF signal 1106 during state transition STa. Also, in response to receiving the frequency levels for states S(N±M)a to SNa, DSP 204 provides the frequency level of state SNa of RF signal 1106 to frequency controller FCSNa and stores the frequency level of state SNa in the memory device of frequency controller FCSNa.

[0331] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for the frequency state S(N±M)a to the frequency controller FCS(N±M)a during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for the state S(N±M)a to the frequency controller FCS(N±M)a at the end of the transition time from a state different from or other than state S(N±M)a, such as state S(N±M-1)a or state S0, to state S(N±M)a. The command signal for the state S(N±M)a transmitted to the frequency controller FCS(N±M)a includes the time period of state S(N±M)a during each cycle, and the frequency controller FCS(N±M)a supplies the frequency level of state S(N±M)a to the driver system 1104. Upon receiving the command signal for state S(N±M)a, frequency controller FCS(N±M)a accesses the frequency level for state S(N±M)a from its memory device and transmits the frequency level for the time period of state S(N±M)a to driver system 1104. For example, frequency controller FCS(N±M)a transmits the frequency level for state S(N±M)a to driver system 1104 at the end of the transition time from a state different from state S(N±M)a to state S(N±M)a. After the time period of state S(N±M)a, frequency controller FCS(N±M)a does not transmit the frequency level for state S(N±M)a to driver system 1104 during the cycle of synchronization signal 146.

[0332] Similarly, upon receiving the synchronization signal 146, the DSP 204 transmits a frequency state transition STa command signal to the transition frequency controller FCSTa during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a state transition STa command signal to the transition frequency controller FCSTa at the start of the transition time from state S(N±M)a to state SNa or at the start of the transition time from state SO to state SNa. The state transition STa command signal transmitted to the transition frequency controller FCSTa includes the time period of the state transition STa during each cycle, and the transition frequency controller FCSTa provides one or more frequency values ​​for the state transition STa to the driver system 1104. Upon receiving the state transition STa command signal, the transition frequency controller FCSTa accesses one or more parameter values ​​for the state transition STa from the memory device of the transition frequency controller FCSTa and transmits one or more frequency values ​​for the time period of the state transition STa to the driver system 1104. For example, at the end of the state S(N±M)a time, the transition frequency controller FCSTa transmits one or more frequency values ​​of the state transition STa to the driver system 1104. After the time period of the state transition STa, during the cycle of the synchronization signal 146, the transition frequency controller FCSTa does not transmit one or more frequency values ​​of the state transition STa to the driver system 1104.

[0333] Upon receiving the synchronization signal 146, the DSP 204 transmits a command signal for state SNa to the frequency controller FCSNa during each cycle of the synchronization signal 146. For example, the DSP 204 transmits a command signal for state transition SNa to the frequency controller FCSNa at the end of the transition time from state S(N±M)a to state SNa. The command signal for state SNa transmitted to the frequency controller FCSNa includes the time period for state SNa during each cycle, and the frequency controller FCSNa provides the frequency level for state SNa to the driver system 1104. Upon receiving the command signal for state SNa, the frequency controller FCSNa accesses the frequency level for state SNa from the memory device of the frequency controller FCSNa and transmits the parameter level to the driver system 1104 during the time period for state SNa. For example, the frequency controller FCSNa transmits the frequency level for state SNa to the driver system 1104 at the end of the transition time from state S(N±M)a to state SNa. After the time period of state SNa, during the cycle of the synchronization signal 146, the frequency controller FCSNa does not transmit the frequency level of state SNa to the driver system 1104.

[0334] In response to receiving the parameter level for state S(N±M)a and the frequency level for state S(N±M)a, driver system 1104 generates a drive signal for state S(N±M)a for the time period of parameter level state S(N±M)a and frequency level state S(N±M)a and transmits the drive signal to RF power supply 222. For example, upon receiving the parameter level for state S(N±M)a at the end of the transition time from parameter state S(N±M-1)a or state S0 to state S(N±M)a and receiving the frequency level for state S(N±M)a at the end of the transition time from frequency state S(N±M-1)a or state S0 to state S(N±M)a, driver system 1104 generates a drive signal for parameter level state S(N±M)a and frequency level state S(N±M)a for the time period of state S(N±M)a and transmits the drive signal to RF power supply 222. When the RF power supply 222 receives a drive signal for the state S(N±M)a from the driver system 1104, it generates a parameter state S(N±M)a and a frequency state S(N±M)a for the RF signal 1106. For example, when the RF power supply 222 receives a drive signal for the parameter state S(N±M)a and the frequency state S(N±M)a from the driver system 1104, it generates a parameter state S(N±M)a and a frequency state S(N±M)a for the RF signal 1106. The parameter state S(N±M)a of the RF signal 1106 has a parameter level of the state S(N±M)a for the time period of the parameter state S(N±M)a. Also, the frequency state S(N±M)a of the RF signal 1106 has a frequency level of the state S(N±M)a for the time period of the frequency state S(N±M)a.

[0335] Similarly, in response to receiving one or more parameter values ​​for state transition STa and one or more frequency values ​​for state transition STa, driver system 1104 generates a drive signal for state transition STa for the time period of parameter state transition STa and frequency state transition STa of RF signal 1106 and transmits the drive signal to RF power supply 222. For example, upon receiving one or more parameter values ​​for parameter state transition STa at the end of the time for parameter state S(N±M)a or state S0 and one or more frequency values ​​for frequency state transition STa at the end of the time for frequency state S(N±M)a or state S0, driver system 1104 generates a drive signal for parameter state transition STa and frequency state transition STa for the time period of frequency and parameter state transition STa and transmits the drive signal to RF power supply 222. Upon receiving the drive signal for frequency and parameter state transition STa from driver system 1104, RF power supply 222 generates parameter state transition STa and frequency state transition STa of RF signal 1106. For example, upon receiving a drive signal for parameter state transition STa and frequency state transition STa from driver system 1104, RF power supply 222 initiates a transition of RF signal 1106 from parameter state S(N±M)a or parameter state S0 to parameter state SNa, and from frequency state S(N±M)a or frequency state S0 to frequency state SNa. The parameter state STa of RF signal 1106 has one or more parameter values ​​of state transition STa during the time period of parameter state transition STa. Furthermore, the frequency state STa of RF signal 1106 has a frequency level of state transition STa during the time period of frequency state transition STa.

[0336] In response to receiving the parameter level for state SNa and the frequency level for state SNa, driver system 1104 generates a drive signal for the parameter level of state SNa and the frequency level of state SNa for the time period and transmits the drive signal to RF power supply 222. For example, upon receiving the parameter level for state SNa at the end of the transition time from parameter state S(N±M)a or state S0 to state SNa, and receiving the frequency level for state SNa at the end of the transition time from frequency state S(N±M)a or state S0 to state SNa, driver system 1104 generates a drive signal for the parameter level of state SNa and the frequency level of state SNa for the time period and transmits the drive signal to RF power supply 222. Upon receiving the drive signal for state SNa from driver system 1104, RF power supply 222 generates the parameter level of state SNa and the frequency level of state SNa for the RF signal 1106. For example, upon receiving a drive signal for parameter state SNa and frequency state SNa from driver system 1104, RF power supply 222 generates parameter state SNa and frequency state SNa of RF signal 1106. The parameter state SNa of RF signal 1106 has a parameter level of state SNa for the time period of parameter state SNa. Also, the frequency state SNa of RF signal 1106 has a frequency level of state SNa for the time period of frequency state SNa.

[0337] In one embodiment, rather than the parameter controllers PRS(N±M)a and PRSNa, the transition parameter controller PRSTa, the frequency controllers FCS(N±M)a and FCSNa, and the transition frequency controller FCSTa, one or more controllers, such as one or more processors, are used to perform the functions described herein performed by the parameter controllers PRS(N±M)a and PRSNa, the transition parameter controller PRSTa, the frequency controllers FCS(N±M)a and FCSNa, and the transition frequency controller FCSTa.

[0338] In one embodiment, rather than DSP204, parameter controllers PRS(N±M)a and PRSNa, transition parameter controller PRSTa, frequency controllers FCS(N±M)a and FCSNa, and transition frequency controller FCSTa, one or more controllers, such as one or more processors, are used to perform the functions described herein that are performed by DSP204, parameter controllers PRS(N±M)a and PRSNa, transition parameter controller PRSTa, frequency controllers FCS(N±M)a and FCSNa, and transition frequency controller FCSTa.

[0339] FIG. 12A is a graph 300 of one embodiment showing a synchronization signal 302.

[0340] 12B is an embodiment graph 1204 showing a variable 1206, such as frequency or a parameter, of the RF signal 1106 (FIGS. 11A and 11B) versus time t, where the variable 1206 is graphed on the y-axis and time t is graphed on the x-axis.

[0341] The variable 1206 periodically transitions between variable levels V8a, V6a, V4a, and V2a in synchronization with the synchronization signal 302. For example, the variable 1206 transitions between variable levels V8a, V6a, V4a, and V2a during cycle 1 of the synchronization signal 302, and also transitions between variable levels V8a, V6a, V4a, and V2a during cycle 2 of the synchronization signal 302. For example, variable 1206 may have a variable level V8a during variable state S4a of RF signal 1106 from time t0 to time t1.5, one or more variable values ​​during variable state transition ST3a from time t1.5 to time t2.5, a variable level V6a during state S3a from time t2.5 to time t4, one or more variable values ​​during variable state transition ST2a from time t4 to time t5, a variable level V4a during state S2a from time t5 to time t6.5, one or more variable values ​​during variable state transition ST1a from time t6.5 to time t7.5, a variable level V2a during state S1a from time t7.5 to time t9, and one or more variable values ​​during variable state transition ST4a from time t9 to time t10. Note that time t1.5 is between times t1 and t2, and time t6.5 is between times t6 and t7.

[0342] During cycle 1 of the synchronized signal 302, the variable 1206 begins transitioning from variable level V8a to variable level V6a at time t1.5 and completes the transition at time t2.5. Also during cycle 1 of the synchronized signal 302, the variable 1206 begins transitioning from variable level V6a to variable level V4a at time t4 and completes the transition at time t5. Also during cycle 1 of the synchronized signal 302, the variable 1206 begins transitioning from variable level V4a to variable level V2a at time t6.5 and completes the transition at time t7.5. Also during cycle 1 of the synchronized signal 302, the variable 1206 begins transitioning from variable level V2a to variable level V8a at time t9 and completes the transition at time t10.

[0343] During cycle 2 of the synchronization signal 302, the variable 1206 begins transitioning from variable level V8a to variable level V6a at time t11.5 and completes the transition at time t12.5. Also during cycle 2 of the synchronization signal 302, the variable 1206 begins transitioning from variable level V6a to variable level V4a at time t14 and completes the transition at time t15. Also during cycle 2 of the synchronization signal 302, the variable 1206 begins transitioning from variable level V4a to variable level V2a at time t16.5 and completes the transition at time t17.5. Also during cycle 2 of the synchronization signal 302, the variable 1206 begins transitioning from variable level V2a to variable level V8a at time t19 and completes the transition at time t20. Note that time t11.5 is between times t11 and t12, and time t16.5 is between times t16 and t17.

[0344] One or more variable values ​​of a state transition ST3a between variable levels V8a and V6a are smaller than the variable level V8a and larger than the variable level V6a. Similarly, one or more variable values ​​of a state transition ST2a between variable levels V6a and V4a are smaller than the variable level V6a and larger than the variable level V4a. Furthermore, one or more variable values ​​of a state transition ST1a between variable levels V4a and V2a are smaller than the variable level V4a and larger than the variable level V2a. One or more variable values ​​of a state transition ST4a between variable levels V2a and V8a are smaller than the variable level V8a and larger than the variable level V2a.

[0345] In one embodiment, rather than transitioning to variable level V2a in state S1a, the variable of RF signal 1106 transitions to a variable level of zero.

[0346] In one embodiment, in addition to the synchronization signal 302, a digital pulse signal is received by the DSP 204 from the processor 118 via the transmission cable system 214 (FIG. 11B). For example, the synchronization signal 302 is received via a first transmission cable of the transmission cable system 214, and the digital pulse signal is received via a second transmission cable of the transmission cable system 214. The digital pulse signal similarly periodically transitions between four logic levels 8, 6, 4, and 2, and the variable 1206 transitions between variable levels V8a, V6a, V4a, and V2a. For example, during cycle 1 of the synchronization signal 302, the digital pulse signal begins transitioning from logic level 8 to logic level 6 at time t1.5 and completes the transition at time t2.5. Also, during cycle 1 of the synchronization signal 302, the digital pulse signal begins transitioning from logic level 6 to logic level 4 at time t4 and completes the transition at time t5. During cycle 1 of synchronization signal 302, the digital pulse signal begins transitioning from logic level 4 to logic level 2 at time t6.5 and completes the transition at time t7.5. Also during cycle 1 of synchronization signal 302, the digital pulse signal begins transitioning from logic level 2 to logic level 8 at time t9 and completes the transition at time t10. Logic level 8 is greater than logic level 6, which is greater than logic level 4. Logic level 4 is greater than logic level 2. For example, the DC voltage of logic level 8 is greater than the DC voltage of logic level 6, which is greater than the DC voltage of logic level 4. The DC voltage of logic level 4 is greater than the DC voltage of logic level 2.

[0347] In this embodiment, during cycle 2 of the synchronization signal 302, the digital pulse signal begins transitioning from logic level 8 to logic level 6 at time t11.5 and completes the transition at time t12.5. Also during cycle 2 of the synchronization signal 302, the digital pulse signal begins transitioning from logic level 6 to logic level 4 at time t14 and completes the transition at time t15. Also during cycle 2 of the synchronization signal 302, the digital pulse signal begins transitioning from logic level 4 to logic level 2 at time t16.5 and completes the transition at time t17.5. Also during cycle 2 of the synchronization signal 302, the digital pulse signal begins transitioning from logic level 2 to logic level 8 at time t19 and completes the transition at time t20. Upon receiving the digital pulse signal, the DSP 204 identifies from the digital pulse signal the time durations of states S1a to S4a and state transitions ST1a to ST4a of the variable 1206 and generates a command signal having these time durations. For example, a The time period of the transition from logic level 4 to logic level 2 of the digital pulse signal is the same as the time period of the transition from logic level 4 to logic level 2 of the variable 1206. a The time period is the same as the transition time period from logic level 6 to logic level 4 of the digital pulse signal.

[0348] 12C is an embodiment graph 1208 showing a variable 1210, such as frequency or a parameter, of the RF signal 1106 (FIGS. 11A and 11B) versus time t, where the variable 1210 is graphed on the y-axis and time t is graphed on the x-axis.

[0349] The variable 1210 periodically transitions between variable levels V8a, V6a, V4a, and V2a in synchronization with the synchronization signal 302. For example, the variable 1210 transitions between variable levels V8a, V6a, V4a, and V2a during cycle 1 of the synchronization signal 302, and also transitions between variable levels V8a, V6a, V4a, and V2a during cycle 2 of the synchronization signal 302. For example, variable 1210 may have a variable level V8a during the variable's state S4a of RF signal 1106 from time t0 to time t1.5, one or more variable values ​​during the variable's state transition ST3a from time t1.5 to time t3.5, a variable level V6a during state S3a from time t3.5 to time t4, one or more variable values ​​during the variable's state transition ST2a from time t4 to time t5, a variable level V4a during state S2a from time t5 to time t6.5, one or more variable values ​​during the variable's state transition ST1a from time t6.5 to time t7.5, a variable level V2a during state S1a from time t7.5 to time t9, and one or more variable values ​​during the variable's state transition ST4a from time t9 to time t10. Note that time t3.5 is between times t3 and t4.

[0350] During cycle 1 of the synchronization signal 302, the variable 1210 begins transitioning from variable level V8a to variable level V6a at time t1.5 and completes the transition at time t3.5, and the remaining transitions of the variable 1210 during cycle 1 of the synchronization signal 302 are the same as the transitions of the variable 1206 (FIG. 12B).

[0351] During cycle 2 of the synchronization signal 302, variable 1210 begins transitioning from variable level V8a to variable level V6a at time t11.5 and completes the transition at time t13.5. Also, the remaining transitions of variable 1210 during cycle 2 of the synchronization signal 302 are the same as the transitions of variable 1206. Note that time t13.5 is between times t13 and t14. The slope of state transition ST3a is greater than the slope of state transition ST2a and the slope of state transition ST1a.

[0352] In one embodiment, rather than transitioning to variable level V2a in state S1a, variable 1210 transitions to a variable level of zero.

[0353] In one embodiment, the slope of state transition ST3a is less than the slope of state transition ST2a and the slope of state transition ST1a.

[0354] In one embodiment, one or more of the state transitions ST1a through STna of the variables described herein have a different slope than one or more of the remaining state transitions ST1a through STna. For example, state transition ST1a has a different slope, such as a slope greater than or less than the slope of state transition ST2a, the slope of state transition ST3a, and the slope of state transition ST4a. Illustratively, state transition ST1a has an angle greater than the angle of state transition ST2a and the angle of state transition ST3a, and an angle less than the angle of state transition ST4a.

[0355] 12D is an embodiment graph 1212 illustrating various types of transitions of a variable 1214, such as frequency or a parameter, versus time t of the RF signal 1106 (FIGS. 11A and 11B). The variable 1214 is graphed on the y-axis and time t is graphed on the x-axis.

[0356] Variable 1214 periodically transitions between variable levels VRa and VSa in synchronization with synchronization signal 302, where R and S are each real numbers and S is greater than R. For example, variable 1214 transitions between variable levels VRa and VSa during cycle 1 of synchronization signal 302, and again transitions between variable levels VRa and VSa during the remaining cycles of synchronization signal 302 (FIG. 12A), such as cycle 2. Illustratively, variable 1214 has variable level VSa during variable state 1216 of RF signal 1106 from time t1 to time t2.5, has one or more variable values ​​during variable state transition 1220 from time t2.5 to time t3.5, and has variable level VRa during state 1218 from time t3.5 to time t5.

[0357] During state transition 1220, variable 1214 has multiple values ​​1222 and 1224 that define the negative linear slope of state transition 1220 between states 1216 and 1218. Values ​​1222 and 1224 are less than the value of variable level VSa and greater than the value of variable level VRa. Note that variable 1214 may have more or less than two values ​​during state transition 1220.

[0358] In one embodiment, during state transition 1220 , variable 1214 has multiple values ​​1226 and 1228 that define a convex slope of state transition 1220 between states 1216 and 1218 .

[0359] In one embodiment, during state transition 1220, variable 1214 has multiple values ​​1230 and 1232 that define a concave slope of state transition 1220 between states 1216 and 1218. Each of the convex slope and convex slope of variable 1214 is an example of a curved slope.

[0360] 12E is an embodiment graph 1250 illustrating various types of transitions of a variable 1252, such as a frequency or parameter, of the RF signal 1106 (FIGS. 11A and 11B) versus time t. The variable 1252 is graphed on the y-axis and time t is graphed on the x-axis.

[0361] The variable 1252 periodically transitions between the variable levels VRa and VSa in synchronization with the synchronization signal 302. For example, the variable 1252 transitions between the variable levels VRa and VSa during cycle 1 of the synchronization signal 302, and again transitions between the variable levels VRa and VSa during the remaining cycles of the synchronization signal 302 (FIG. 12A), such as cycle 2. By way of example, the variable 1252 transitions between the variable levels VRa and VSa during the variable state 1218 of the RF signal 1106 from time t1 to time t2.5. R a, has one or more variable values ​​during variable state transition 1260 from time t2.5 to time t3.5, and has variable level VSa during state 1216 from time t3.5 to time t5.

[0362] During state transition 1260, variable 1252 has multiple values ​​1262 and 1264 that define the positive linear slope of state transition 1260 between states 1216 and 1218. Values ​​1262 and 1264 are less than the value of variable level VSa and greater than the value of variable level VRa. Note that variable 1252 may have more or less than two values ​​during state transition 1260.

[0363] In one embodiment, during state transition 1260 , variable 1252 has multiple values ​​1266 and 1268 that define a convex slope of state transition 1260 between states 1216 and 1218 .

[0364] In one embodiment, during state transition 1260, variable 1252 has multiple values ​​1270 and 1272 that define a concave slope of state transition 1260 between states 1216 and 1218. Each of the convex slope and convex slope of variable 1252 is an example of a curved slope.

[0365] 12F is a diagram of one embodiment of a pulse shaping method. As shown with respect to FIG. 12F, the transitions of the RF signal 1106 (FIG. 11B) generated by the RF generator 1102 (FIG. 11B) have a negative slope and are modified to reduce the pulse width of one or more pulses from state S(nA) to Sn. For example, rather than a vertical or substantially vertical transition from state S(n-1) to state Sn, a sloped transition with a negative slope is provided between states S(n-1) and Sn. Because of the negative slope, the power level PL of the RF signal 1106 S(n-1) The pulse width of decreases during state S(n-1). The power level to achieve the slope transition is supplied from the host computer or host controller to RF generator 1102 to achieve the slope transition.

[0366] In one embodiment, a sloped transition between frequency levels occurs. For example, one frequency level transitions to another frequency level via a positive sloped transition or a negative sloped transition. The frequency level between the sloped transitions is provided from the host computer to RF generator 1102, which generates RF signal 1106 having this frequency level.

[0367] 12G is a diagram of one embodiment of another pulse shaping method. As shown in FIG. 12G, the transition slope of the RF signal 1106 (FIG. 11B) generated by the RF generator 1102 (FIG. 11B) from state S(nA) to state S(n-A+1) is steeper, i.e., greater, than the transition slope of the RF signal 1106 from state S(n-1) to state Sn.

[0368] In one embodiment, the transition slope of the RF signal 1106 generated by the RF generator 1102 from state S(nA) to state S(n-A+1) is less steep, i.e., less than the transition slope of the RF signal 1106 from state S(n-1) to state Sn.

[0369] 12H is a diagram of another embodiment of a pulse shaping method. In FIG. 12H, RF generator 1102 (FIG. 11B) generates RF signal 1106 (FIG. 11B) with a curved transition slope from state S(nA) to state S(n-A+1), such as a semi-parabolic or exponential curve. Also, RF signal 1106 with a curved transition slope from state S(n-1) to state Sn.

[0370] 12I is a diagram of one embodiment of another pulse shaping method. As shown in FIG. 12I, the RF generator 1102 (FIG. 11B) generates an RF signal 1106 (FIG. 11B) with a curved transition slope from state S(nA) to state S(n-A+1), and the RF signal 1106 with a linear transition slope from state S(n-1) to state S.

[0371] 12J is a diagram of another embodiment of yet another pulse shaping method. As shown with respect to FIG. 12J, the transitions of the RF signal 1106 (FIG. 11B) generated by the RF generator 1102 (FIG. 11B) have a positive slope or a negative slope and are modified to reduce the pulse width of one or more of the RF signals 1106 from state S(nA) to Sn. For example, rather than a vertical or substantially vertical transition from state S(n-1) to state Sn, a sloped transition having a negative slope is provided between states S(nA) and S(n-A+1). Because of the negative slope, the power level PL of the RF signal 1106 S(n-A)The pulse width of the RF signal 1106 is reduced during state S(nA). As another example, rather than a vertical or substantially vertical transition from state S(n-1) to state Sn, a gradient transition having a positive slope is provided between states S(n-1) and Sn. Because of the positive slope, the power level PL Sn The pulse width of decreases during state Sn.

[0372] 12K is a diagram of an embodiment of another pulse shaping method. In FIG. 12K, the transition from state S(nA) to state S(n-A+1) of RF signal 1106 (FIG. 11B) generated by RF generator 1102 (FIG. 11B) has a linear slope, such as a negative linear slope, and the transition from state S(n-1) to state S of RF signal 1106 has a curved slope, such as a concave slope. The curved slope has a positive slope.

[0373] 12L is a diagram of an embodiment of another pulse shaping method. In FIG. 12L, the transition from state S(nA) to state S(n-A+1) of RF signal 1106 (FIG. 11B) generated by RF generator 1102 (FIG. 11B) has a linear slope, such as a negative linear slope, and the transition from state S(n-1) to state S of RF signal 1106 has a curved slope, such as a convex slope. The curved slope has a positive slope.

[0374] EtherCAT cable

[0375] FIG. 13A is a diagram of one embodiment of system 1300, illustrating the transmission of information between various components of a plasma system via one or more Ethernet for Control Automation (EtherCAT) cables. An example of an EtherCAT cable is an Ethernet cable. EtherCAT is an Ethernet-based protocol used for real-time distributed control information, making it suitable for automation technologies. EtherCAT frames or packets pass through the EtherCAT slave device, which processes the data on the fly while the EtherCAT slave device reads the data to be addressed. Similarly, input data is inserted into EtherCAT frames from the EtherCAT slave device, while the EtherCAT frames pass through the EtherCAT slave device. EtherCAT frames are not fully received by the EtherCAT slave device until they are processed; instead, they begin processing as soon as possible. The transmission of input data from the EtherCAT slave device occurs with minimal latency of a few bit times.

[0376] System 1300 includes host computer 106, source RF generator 102, bias RF generator 104, source matcher 108, and bias matcher 110, each of which is an example of a plasma tool or plasma system component. A plasma tool component that transmits one or more EtherCAT frames is referred to herein as a master EtherCAT device, and a plasma tool component that receives one or more EtherCAT frames is referred to herein as a slave EtherCAT device. For example, bias RF generator 104, source matcher 108, and bias matcher 110 are each examples of slave EtherCAT devices, and source RF generator 102 is an example of a master EtherCAT device. Source RF generator 102, bias RF generator 104, source matcher 108, and bias matcher 110 are each examples of plasma system components. One or more EtherCAT frames may be referred to herein as a pulse train.

[0377] The host computer 106 includes a processor 118 and a communications controller 1302. Examples of communications controllers as used herein include ASICs, PLDs, controllers, and processors.

[0378] The processor 118 is coupled to a communications controller 1302. The communications controller 1302 is coupled to a port 1308 of the source RF generator 102 via an EtherCAT cable 1304. Examples of Ethernet cables used herein include twisted pair cables. Illustratively, the Ethernet cable is a 100BASE-TX™ or 100BASE-T4™ cable, which can transmit data at speeds of 100 Megabits per second (Mbps) or greater. Furthermore, another port 1310 of the source RF generator 102 is coupled to a port 1312 of the bias RF generator 104 via an EtherCAT cable 1306.

[0379] The processor 118 transmits processor data 1311, such as timing information of the synchronization signal 146 (FIG. 7), source RF generator variable information, and bias RF variable information, to the communication controller 1302. Examples of the timing information of the synchronization signal 146 include the time when the synchronization signal 146 changes logic levels, such as from 1 to 0 or from 0 to 1, during each cycle of the synchronization signal 146, and the number of cycles of the synchronization signal 146. The timing information also includes the logic levels 0 and 1 of the synchronization signal 146. Examples of the source RF generator variable information include variable levels, such as parameter levels or frequency levels, for each operating state of the source RF generator 102. For example, the source RF generator variable information includes the power level and frequency level of the variable states S1a to Sna of the RF signal 152 generated by the source RF generator 102. Examples of the bias RF generator variable information include variable levels, such as parameter levels or frequency levels, for each operating state of the bias RF generator 104. Illustratively, the bias RF generator variable information includes the power and frequency levels of the variable states S1a through Sna of the RF signal 168 generated by the bias RF generator 104.

[0380] The communications controller 1302 receives the processor data 1311, applies the EtherCAT protocol, embeds the processor data 1311, generates one or more EtherCAT frames 1314 with the processor data 1311, and transmits the one or more EtherCAT frames 1314 to a port 1308 of the source RF generator 102 via the EtherCAT cable 1304. The communications controller of the source RF generator 102 receives the one or more EtherCAT frames 1314 via the port 1308, identifies source RF generator variable information and timing information of the synchronization signal 146 from the one or more EtherCAT frames 1314, and transmits the source RF generator variable information and timing information to the DSP 204 of the source RF generator 102.

[0381] Additionally, the communications controller of the source RF generator 102 sends a request for information, such as source RF generator measurement information, to the DSP 204 of the source RF generator 102. An example of source RF generator measurement information includes factors determined or identified by the DSP 204 of the source RF generator 102. An example of factors identified by the DSP 204 of the source RF generator 102 includes a reference, such as a complex voltage-current, a complex voltage, a complex power, a complex current, or a complex impedance. The reference is measured by a sensor for each state of the RF signal 152. The sensor measuring the reference is located inside or outside the source RF generator 102 and coupled to the output 154 of the source RF generator 102. The complex factor includes a magnitude and a phase. For example, a complex voltage includes a complex voltage magnitude and a complex voltage phase. A complex voltage-current includes a voltage magnitude, a current magnitude, and a phase between the voltage and the current. The sensor measures the reference and provides the reference to the DSP 204 of the source RF generator 102. The DSP 204 of the source RF generator 102 identifies a reference and / or determines a reference frequency from the measurement reference for each state of the RF signal 152. For example, the DSP 204 of the source RF generator 102 applies a Fourier transform to the reference value to determine the reference frequency. The reference frequency is an example of a factor.

[0382] Upon receiving the request for information, DSP 204 of source RF generator 102 provides the source RF generator measurement information to a communications controller of source RF generator 102. Upon receiving the source RF generator measurement information, the communications controller of source RF generator 102 embeds the source RF generator measurement information into one or more EtherCAT frames 1314 and transmits the one or more EtherCAT frames 1314 to port 1312 of bias RF generator 104 via port 1310 of source RF generator 102 and EtherCAT cable 1306.

[0383] The communication controller of the bias RF generator 104 receives one or more EtherCAT frames 1314 via port 1312, identifies bias RF generator variable information and timing information of the synchronization signal 146 from the one or more EtherCAT frames 1314, and sends the bias RF generator variable information and timing information to the DSP 204 of the bias RF generator 104.

[0384] Additionally, the communication controller of the bias RF generator 104 sends a request for information, such as bias RF generator measurement information, to the DSP 204 of the bias RF generator 104. An example of the bias RF generator measurement information includes factors determined or identified by the DSP 204 of the bias RF generator 104. An example of factors identified by the DSP 204 of the bias RF generator 104 includes a reference, such as a complex voltage-current, complex voltage, complex power, complex current, or complex impedance. The reference is measured by a sensor for each state of the RF signal 168. The sensor that measures the reference is located inside or outside the bias RF generator 104 and is coupled to the output 160 of the bias RF generator 104. The sensor measures the reference and provides the reference to the DSP 204 of the bias RF generator 104. The DSP 204 of the bias RF generator 104 identifies the reference from the measurement reference and determines a reference frequency for each state of the RF signal 168. For example, the DSP 204 of the bias RF generator 104 applies a Fourier transform to the reference value to determine the reference frequency.

[0385] Upon receiving the request for information, DSP 204 of bias RF generator 104 provides the bias RF generator measurement information to the communications controller of source RF generator 104. Upon receiving the bias RF generator measurement information, the communications controller of bias RF generator 104 embeds the bias RF generator measurement information into one or more EtherCAT frames 1314 and transmits the one or more EtherCAT frames 1314 to port 1310 of source RF generator 102 via port 1312 of bias RF generator 104 and EtherCAT cable 1306. The communications controller of source RF generator 102 receives the one or more EtherCAT frames 1314 via port 1310 and transmits the one or more EtherCAT frames 1314 to communications controller 1302 of host computer 106 via port 1308 and EtherCAT cable 1304.

[0386] The communications controller 1302 of the host computer 106 applies the EtherCAT protocol to one or more EtherCAT frames 1314 and obtains or extracts source RF generator measurement information for each state of the variable of the source RF signal 152 and bias RF generator measurement information for each state of the variable of the bias RF signal 168 from the one or more EtherCAT frames 1314. The communications controller 1302 provides the source RF generator measurement information and the bias RF generator measurement information to the processor. The processor 118 determines whether to modify the variable of the source RF generator 102 during each state of the variable of the RF signal 152, or the variable of the bias RF generator 104 during each state of the variable of the RF signal 168, or a combination thereof, based on the source RF generator measurement information or the bias RF generator measurement information or a combination thereof. The processor 118 controls the state of each variable of the RF signal 152 generated by the source RF generator 102 based on the correction variable of the source RF generator 102, and / or controls the state of each variable of the RF signal 168 generated by the bias RF generator 104 based on the correction variable of the bias RF generator 104.

[0387] Note that in one embodiment, there is no storage of one or more EtherCAT frames 1314 within the source RF generator 102, and there is no storage of one or more EtherCAT frames 1314 within the bias RF generator 104. For example, one or more EtherCAT frames 1314 are in constant motion within a memory device of a communications controller of the source RF generator 102, and one or more EtherCAT frames 1314 are in constant motion within a memory device of a communications controller of the bias RF generator 104. Illustratively, one or more EtherCAT frames 1314 move within a memory device, such as moving from one register to another in a register array of the communications controller of the source RF generator 102, while source RF generator variable information and source RF generator measurement information are transmitted between the communications controller of the source RF generator 102 and the DSP 204 of the source RF generator 102. As another example, one or more EtherCAT frames 1314 move within a memory device, such as moving from one register to another in a register string of the bias RF generator 104 communication controller, while bias RF generator variable information and bias RF generator measurement information are transmitted between the bias RF generator 104 communication controller and the bias RF generator 104 DSP 204.

[0388] 13B is a diagram of one embodiment of a system 1350 illustrating the transmission of information between various components of a plasma system via one or more EtherCAT cables. System 1350 includes host computer 106, source RF generator 102, bias RF generator 104, source matcher 108, and bias matcher 110. Communications controller 1302 is coupled to port 1312 of bias RF generator 104 via EtherCAT cable 1306.

[0389] The processor 118 sends processor data 1311 to the communication controller 1302. The communication controller 1302 receives the processor data 1311, applies the EtherCAT protocol, embeds timing information of the synchronization signal 146 and source RF generator variable information in the processor data 1311, generates one or more EtherCAT frames 1352 having the timing information of the synchronization signal 146 and the source RF generator variable information, and transmits the one or more EtherCAT frames 1352 to port 1308 of the source RF generator 102 via the EtherCAT cable 1304. The communication controller of the source RF generator 102 receives the one or more EtherCAT frames 1352 via port 1308, identifies the source RF generator variable information, and performs the same functions as described above with reference to FIG. 13A until source RF generator measurement information is received from the DSP 204 of the source RF generator 102. Upon receiving the source RF generator measurement information, the communication controller of the source RF generator 102 embeds the source RF generator measurement information into one or more EtherCAT frames 1352 and transmits the source RF generator measurement information to the port 1308 of the source RF generator 102 and the EtherCAT cable 1308. 4 13. The host computer 106 transmits one or more EtherCAT frames 1352 to the communication controller 1302 of the host computer 106 via the EtherCAT.

[0390] In a similar manner, the communications controller 1302 receives the processor data 1311, applies the EtherCAT protocol, embeds the timing information of the synchronization signal 146 and the bias RF generator variable information in the processor data 1311, generates one or more EtherCAT frames 1354 having the timing information of the synchronization signal 146 and the bias RF generator variable information, and transmits the one or more EtherCAT frames 1354 to a port 1312 of the bias RF generator 104 via the EtherCAT cable 1306. The communications controller of the bias RF generator 104 receives the one or more EtherCAT frames 1354 via the port 1312, identifies the bias RF generator variable information, and performs the same functions as described above with reference to FIG. 13A until bias RF generator measurement information is received from the DSP 204 of the bias RF generator 104. Upon receiving the bias RF generator measurement information, the communication controller of the bias RF generator 104 embeds the bias RF generator measurement information into one or more EtherCAT frames 1354 and transmits the one or more EtherCAT frames 1354 to the communication controller 1302 of the host computer 106 via the port 1312 of the bias RF generator 104 and the EtherCAT cable 1306.

[0391] The communications controller 1302 of the host computer 106 applies the EtherCAT protocol to one or more EtherCAT frames 1352 and obtains or extracts the source RF generator measurement information from the one or more EtherCAT frames 1352. The communications controller 1302 provides the source RF generator measurement information to the processor 118.

[0392] Similarly, the communications controller 1302 of the host computer 106 applies the EtherCAT protocol to one or more EtherCAT frames 1354 and obtains or extracts the bias RF generator measurement information from the one or more EtherCAT frames 1354. The communications controller 1302 provides the bias RF generator measurement information to the processor 118, which performs the same functions as described above with reference to FIG.

[0393] It should be noted that in one embodiment, there is no storage of one or more EtherCAT frames 1352 within the source RF generator 102, and there is no storage of one or more EtherCAT frames 1354 within the bias RF generator 104. For example, one or more EtherCAT frames 1352 are in constant motion within a memory device of a communications controller of the source RF generator 102, and one or more EtherCAT frames 1354 are in constant motion within a memory device of a communications controller of the bias RF generator 104. By way of example, one or more EtherCAT frames 1352 move within a memory device, such as moving from one register to another in a register string of the communications controller of the source RF generator 102, while source RF generator variable information and source RF generator measurement information are transmitted between the communications controller of the source RF generator 102 and the DSP 204 of the source RF generator 102. As another example, one or more EtherCAT frames 1352 are in constant motion within a memory device, such as moving from one register to another in a register string of the communications controller of the source RF generator 102. 4 While the bias RF generator variable information and bias RF generator measurement information are transferred between the bias RF generator 104 communication controller and the bias RF generator 104 DSP 204, the bias RF generator variable information and bias RF generator measurement information are transferred within the memory device, such as from one register to another in the bias RF generator 104 communication controller register array.

[0394] 14 is a diagram of one embodiment of an EtherCAT frame 1400. EtherCAT frame 1400 is an example of one or more of EtherCAT frames 1314 (FIG. 13A). EtherCAT frame 1400 is also an example of any one or more of EtherCAT frames 1352 (FIG. 13B) and any one or more of EtherCAT frames 1354 (FIG. 13B).

[0395] In one embodiment, the terms frame and packet are used interchangeably herein. EtherCAT frame 1400 includes fields 1401, 1403, 1402, 1404, 1406, 1408, 1410, 1412, 1414, 1416, and 1418.

[0396] Field 1401 contains a start of frame delimiter that identifies the start of the EtherCAT frame 1400. Field 1402 contains the source address of the EtherCAT frame 1400. An example of a source address is the address of the communication controller 1302 of the host computer 106 that generates the EtherCAT frame 1400. Field 1403 of the EtherCAT frame 1400 contains the order in which the EtherCAT frame 1400 is circulated to the various components of the plasma system. An example of an order is from the communication controller 1302 to the source RF generator 102, from the source RF generator 102 to the bias RF generator 104, from the bias RF generator 104 back to the source RF generator 102, and from the source RF generator 102 to the processor 106. 18 Another example of the order includes a sequence from the communications controller 1302 to the source RF generator 102 and back from the source RF generator 102 to the communications controller 1302.

[0397] Field 1404 contains the destination address of the EtherCAT frame 1400. An example of a destination address is the address of the communication controller 1302 of the host computer 106, which is the final destination of the EtherCAT frame 1400.

[0398] Field 1406 contains an address identifying the source RF generator 102 (FIG. 13A), such as a media access control (MAC) address, that distinguishes the source RF generator 102 from other RF generators in the plasma system. Field 1408 contains source RF generator variable information, and field 1410 contains source RF generator measurement information. The address identifying the source RF generator 102 is used by the communications controller of the source RF generator 102 to determine whether data in field 1408 should be provided to the DSP 204 of the source RF generator 102 and whether data received from the DSP 204 of the source RF generator 102 should be stored in field 1410.

[0399] Field 1412 contains an address, such as a MAC address, that identifies the bias RF generator 104 (FIG. 13A) to distinguish it from other RF generators in the plasma system. Field 1414 contains bias RF generator variable information, and field 1416 contains bias RF generator measurement information. The address that identifies the bias RF generator 104 is used by the communications controller of the bias RF generator 104 to determine whether data in field 1414 should be provided to the DSP 204 of the bias RF generator 104 and whether data received from the DSP 204 of the bias RF generator 104 should be stored in field 1416.

[0400] Field 1418 contains a cyclic redundancy check (CRC) for one or more of fields 1408 and 1414. For example, the CRC is performed by the communications controller 1302 (FIG. 13A) after receiving the EtherCAT frame 1400 to determine whether the source RF generator variable information in field 1408 sent by the communications controller 1302 matches the source RF generator variable information in field 1408 received by the communications controller 1302, thereby determining the validity of the EtherCAT frame 1400.

[0401] In one embodiment, any of fields 1406, 1408, and 1410, or fields 1412, 1414, and 1416 are not included in EtherCAT frame 1400. For example, if EtherCAT frame 1400 is an example of any of one or more EtherCAT frames 1452 sent to source RF generator 102 (FIG. 13B), EtherCAT frame 1400 excludes fields 1412, 1414, and 1416 of bias RF generator 104.

[0402] In one embodiment, any of fields 1406, 1408, and 1410, or fields 1412, 1414, and 1416, are included but empty in EtherCAT frame 1400. For example, if EtherCAT frame 1400 is an example of any of one or more EtherCAT frames 1452 sent to source RF generator 102 (FIG. 13B), EtherCAT frame 1400 excludes any data or information in fields 1412, 1414, and 1416 for bias RF generator 104.

[0403] 15A is a diagram of one embodiment of a system 1500 illustrating the transmission of information between various components of a plasma system via one or more EtherCAT cables. The system 1500 includes a host computer 106, a source RF generator 102, a bias RF generator 104, a source matcher 108, and a bias matcher 110.

[0404] A port 1310 of the source RF generator 102 is coupled to a port 1502 of the source matching box 108 via an EtherCAT cable 1306. Another port 1505 of the source matching box 108 is coupled to a port 1312 of the bias RF generator 104 via an EtherCAT cable 1504. Another port 1506 of the bias RF generator 104 is coupled to a port 1510 of the bias matching box 110 via an EtherCAT cable 1508.

[0405] The processor 118 transmits processor data 1501, which includes processor data 1302 (FIG. 13A) for the source RF generator 102 and the bias RF generator 104, as well as matcher data, such as bias matcher data or source matcher data, or a combination thereof. The processor data 1501 is transmitted to the communications controller 1302. An example of source matcher data includes one or more specifications for one or more components of the source matcher 108, An example of bias matcher data is: The source matching circuit 108 includes one or more specifications of one or more components of the bias matching circuit 110. Examples of the one or more specifications of one or more components of the source matching circuit 108 include a capacitance value of a capacitor of the source matching circuit 108 and an inductance value of an inductor of the source matching circuit 108. Examples of the one or more specifications of one or more components of the bias matching circuit 110 include a capacitance value of a capacitor of the bias matching circuit 110 and an inductance value of an inductor of the bias matching circuit 110.

[0406] The communications controller 1302 receives the processor data 1501, applies the EtherCAT protocol, embeds the processor data 1501, generates one or more EtherCAT frames 1512 with the processor data 1501, and transmits the one or more EtherCAT frames 1512 to the port 1308 of the source RF generator 102 via the EtherCAT cable 1304. The communications controller of the source RF generator 102 receives the one or more EtherCAT frames 1512 via the port 1308, identifies source RF generator variable information and timing information of the synchronization signal 146 from the one or more EtherCAT frames 1512, and transmits the source RF generator variable information and timing information to the DSP 204 of the source RF generator 102.

[0407] Additionally, the communications controller of the source RF generator 102 sends requests to the DSP 204 of the source RF generator 102 for information such as source RF generator measurement information and source state information of the RF signal 152. An example of the source state information of the RF signal 152 includes timing information of the states and / or timing information of state transitions of the RF signal 152. As an example, the timing information of the states of the RF signal 152 includes the times when the RF signal 152 changes variable levels and the time for which the RF signal 152 remains at that variable level. 10B, the timing information for state S4a of RF signal 152 includes time t0 when variable 1006 of RF signal 152 transitions from variable level V2a to variable level V8a, the time period between time t0 and t2.5 when variable 1006 of RF signal 152 remains at variable level V8a, time t2.5 when variable 1006 of RF signal 152 transitions from variable level V8a to a variable level of zero, time t5 when variable 1006 transitions from a variable level of zero to variable level V6a, the time period between time t5 and t7.5 when variable 1006 of RF signal 152 remains at variable level V6a, time t7.5 when variable 1006 transitions from variable level V6a to variable level V2a, and the time period between time t7.5 and t10 when variable 1006 of RF signal 152 remains at variable level V2a.

[0408] 12B, the timing information for state S4a of RF signal 152 includes the time t0 when variable 1206 of RF signal 152 transitions from variable level V2a to variable level V8a, and the time period between t0 and t1.5 when variable 1206 of RF signal 152 remains at variable level V8a. 3 The timing information of a includes the time t1.5 when the variable of RF signal 152 starts to transition from variable level V8a to variable level V6a, and the time t2.5 when the variable 1206 of RF signal 152 stops transitioning. Similarly, the state transition ST 2The timing information of a includes a time t4 when the variable 1206 of the RF signal 152 starts to transition from the variable level V6a to the variable level V4a, and a time t5 when the variable 1206 of the RF signal 152 stops transitioning, and the state transition ST of the variable 1206 of the RF signal 152 1 The timing information of ST4a includes time t6.5 when the variable 1206 of the RF signal 152 starts to transition from variable level V4a to variable level V2a, and time t7.5 when the variable 1206 of the RF signal 152 stops the transition, and the timing information of ST4a of the variable 1206 of the RF signal 152 includes time t9 when the variable 1206 of the RF signal 152 starts to transition from variable level V2a to variable level V8a, and time t10 when the variable 1206 of the RF signal 152 stops the transition.

[0409] Upon receiving the request for information, DSP 204 of source RF generator 102 provides the source RF generator measurement information and source state information to a communications controller of source RF generator 102. Upon receiving the source RF generator measurement information and source state information, the communications controller of source RF generator 102 embeds the source RF generator measurement information and source state information into one or more EtherCAT frames 1512 and transmits the one or more EtherCAT frames 1512 via port 1310 of source RF generator 102 and EtherCAT cable 1306 to port 1502 of source matcher 108.

[0410] The communication controller of the source matcher 108 receives one or more EtherCAT frames 1512 via the port 1502 of the source matcher 108, extracts source matching data and source state information from the one or more EtherCAT frames 1512, and transmits the source matching data and source state information to the processor of the source matcher 108. The processor of the source matcher 108 controls one or more components of the source matcher 108 according to the source matching data and source state information. For example, the processor of the source matcher 108 does not control the components of the source matcher 108 during one or more of states S1a to Sna, but controls the components during the remainder of states S1a to Sna. The processor of the source matcher 108 controls the components of the source matcher 108 to achieve the capacitance and inductance values ​​in the source matching data.

[0411] The communications controller of source matcher 108 also sends requests for information, such as source matcher measurement information, to the processor of source matcher 108. Examples of source matcher measurement information include standards measured by components of source matcher 108 or sensors coupled to output 158 ​​of source matcher 108. The sensors may be located inside or outside of source matcher 108. Upon receiving the request for information, the processor of source matcher 108 provides the source matcher measurement information to the communications controller of source matcher 108. The communications controller of source matcher 108 embeds the source matcher measurement information into one or more EtherCAT frames 1512 and transmits the one or more EtherCAT frames 1512 to port 1312 of bias RF generator 104 via port 1505 and EtherCAT cable 1504.

[0412] The communication controller of the bias RF generator 104 receives one or more EtherCAT frames 1512 via port 1312, identifies bias RF generator variable information and timing information of the synchronization signal 146 from the one or more EtherCAT frames 1512, and sends the bias RF generator variable information and timing information to the DSP 204 of the bias RF generator 104.

[0413] Additionally, the communications controller of the bias RF generator 104 sends requests to the DSP 204 of the bias RF generator 104 for information such as bias RF generator measurement information and bias state information of the RF signal 168. An example of the bias state information of the RF signal 168 includes timing information of the state and / or timing information of the state transition of the RF signal 168. As an example, the timing information of the state of the RF signal 168 includes the time when the RF signal 168 changes variable levels and the time for which the RF signal 168 remains at that variable level. 10B, the timing information for state S4a of RF signal 168 includes time t0 when variable 1006 of RF signal 168 transitions from variable level V2a to variable level V8a, the time period between time t0 and t2.5 when variable 1006 of RF signal 168 remains at variable level V8a, time t2.5 when variable 1006 of RF signal 168 transitions from variable level V8a to a variable level of zero, time t5 when variable 1006 transitions from a variable level of zero to variable level V6a, the time period between time t5 and t7.5 when variable 1006 of RF signal 168 remains at variable level V6a, time t7.5 when variable 1006 transitions from variable level V6a to variable level V2a, and the time period between time t7.5 and t10 when variable 1006 of RF signal 168 remains at variable level V2a.

[0414] 12B, the timing information for state S4a of RF signal 168 includes the time t0 when variable 1206 of RF signal 168 transitions from variable level V2a to variable level V8a, and the time period between t0 and t1.5 when variable 1206 of RF signal 168 remains at variable level V8a. 3 The timing information of a includes the time t1.5 when the variable of RF signal 168 starts to transition from variable level V8a to variable level V6a, and the time t2.5 when the variable 1206 of RF signal 168 stops transitioning. Similarly, the state transition ST 2The timing information of the variable 1206 of the RF signal 168 includes a time t4 when the variable 1206 of the RF signal 168 starts to transition from the variable level V6a to the variable level V4a, and a time t5 when the variable 1206 of the RF signal 168 stops transitioning. 1 The timing information of ST4a includes time t6.5 when the variable 1206 of the RF signal 168 starts to transition from variable level V4a to variable level V2a, and time t7.5 when the variable 1206 of the RF signal 168 stops the transition, and the timing information of ST4a of the variable 1206 of the RF signal 168 includes time t9 when the variable 1206 of the RF signal 168 starts to transition from variable level V2a to variable level V8a, and time t10 when the variable 1206 of the RF signal 168 stops the transition.

[0415] Upon receiving the request for information, DSP 204 of bias RF generator 104 provides the bias RF generator measurement information and bias state information to a communication controller of bias RF generator 104. Upon receiving the bias RF generator measurement information and bias state information, the communication controller of bias RF generator 104 embeds the bias RF generator measurement information and bias state information into one or more EtherCAT frames 1512 and transmits the one or more EtherCAT frames 1512 to port 1510 of bias matcher 110 via port 1506 of bias RF generator 104 and EtherCAT cable 1508.

[0416] The communication controller of the bias matcher 110 receives one or more EtherCAT frames 1512 via the port 1510 of the bias matcher 110, extracts bias matcher data and bias state information from the one or more EtherCAT frames 1512, and sends the bias matcher data and bias state information to the processor of the source matcher 110. The processor of the bias matcher 110 controls one or more components of the bias matcher 110 according to the bias matcher data and bias state information. For example, the processor of the bias matcher 110 does not control the components of the bias matcher 110 during one or more of states S1a to Sna, but controls the components during the remainder of states S1a to Sna. The processor of the bias matcher 110 controls the components of the bias matcher 110 to achieve the capacitance and inductance values ​​in the bias matcher data.

[0417] The communications controller of bias matcher 110 also sends requests for information, such as bias matcher measurement information, to the processor of bias matcher 110. Examples of bias matcher measurement information include standards measured by components of bias matcher 110 or sensors coupled to output 164 of bias matcher 110. The sensors may be located internal or external to bias matcher 110. Upon receiving the request for information, the processor of bias matcher 110 provides the bias matcher measurement information to the communications controller of bias matcher 110. The communications controller of bias matcher 110 embeds the bias matcher measurement information into one or more EtherCAT frames 1512 and transmits the one or more EtherCAT frames 1512 via port 1510 and EtherCAT cable 1508 to port 1506 of bias RF generator 104.

[0418] The communications controller of the bias RF generator 104 receives one or more EtherCAT frames 1512 from the bias matcher 110 via port 1506 and transmits one or more EtherCAT frames 1512 to port 1505 of the source matcher 108 via port 1312 and EtherCAT cable 1504. The communications controller of the source matcher 108 receives one or more EtherCAT frames 1512 from the bias RFG 104 via port 1505 and transmits one or more EtherCAT frames 1512 to port 1310 of the source RF generator 102 via port 1502 and EtherCAT cable 1306. The communications controller of the source RF generator 102 receives one or more EtherCAT frames 1512 via port 1310 and transmits one or more EtherCAT frames 1512 to the communications controller 1302 of the host computer 106 via port 1308 and EtherCAT cable 1304.

[0419] The communication controller 1302 of the host computer 106 applies the EtherCAT protocol to one or more EtherCAT frames 1512 and transmits the source RF generator measurement information and the bias RF generator measurement information to one or more EtherCAT frames 1512. 512 The communications controller 1302 provides the source RF generator measurement information and the bias RF generator measurement information to the processor 118.

[0420] 15B is a diagram of one embodiment of a system 1550 illustrating the transmission of information between various components of a plasma system via one or more EtherCAT cables. System 1550 includes a host computer 106, a source RF generator 102, a bias RF generator 104, a source matcher 108, and a bias matcher 110. A communications controller 1302 is coupled to a port 1505 of the source matcher 108 via an EtherCAT cable 1508, and the communications controller 1302 is coupled to a port 1510 of the bias matcher 110 via an EtherCAT cable 1504.

[0421] The processor 118 transmits the processor data 1501 to the communication controller 1302. The communication controller 1302 receives the processor data 1501, applies the EtherCAT protocol, and transmits the processor data 1501 to the communication controller 1302. 501 15A , the communication controller 1302 of the host computer 106 embeds the timing information and source matcher data of the synchronization signal 146 in the source matcher 108, generates one or more EtherCAT frames 1552 having the timing information and source matcher data of the synchronization signal 146, and transmits the one or more EtherCAT frames 1552 to the port 1505 of the source matcher 108 via the EtherCAT cable 1508. The communication controller of the source matcher 108 receives the one or more EtherCAT frames 1552 via the port 1505, identifies the source matcher data, and performs the same functions as described above with reference to FIG. 15A until source matcher measurement information is received from the processor of the source matcher 108. Upon receiving the source matcher measurement information, the communication controller of the source matcher 108 embeds the source matcher measurement information into one or more EtherCAT frames 1552 and transmits the one or more EtherCAT frames 1552 to the communication controller 1302 of the host computer 106 via the port 1505 of the source matcher 108 and the EtherCAT cable 1508.

[0422] Similarly, the communication controller 1302 receives the processor data 1501 and applies the EtherCAT protocol to the processor data 1501. 50115A , the bias matcher 110 transmits the bias matcher measurement information to the communication controller 1302 of the host computer 106. The bias matcher 110 then embeds the synchronization signal 146 timing information and bias matcher data into one or more EtherCAT frames 1554 having the synchronization signal 146 timing information and bias matcher data, and transmits the one or more EtherCAT frames 1554 to the port 1510 of the bias matcher 110 via the EtherCAT cable 1504. The communication controller of the bias matcher 110 receives the one or more EtherCAT frames 1554 via the port 1510, identifies the bias matcher data, and performs the same functions as described above with reference to FIG. 15A until bias matcher measurement information is received from the processor of the bias matcher 110. Upon receiving the bias matcher measurement information, the communication controller of the bias matcher 110 embeds the source matcher measurement information into one or more EtherCAT frames 1554 and transmits the one or more EtherCAT frames 1554 to the communication controller 1302 of the host computer 106 via the port 1510 of the bias matcher 110 and the EtherCAT cable 1504.

[0423] The communications controller 1302 of the host computer 106 applies the EtherCAT protocol to one or more EtherCAT frames 1552 and obtains or extracts source matcher measurement information from the one or more EtherCAT frames 1552. The communications controller 1302 provides the source matcher measurement information to the processor 1108. Upon receiving the source matcher measurement information, the processor 1108 controls one or more of the source RF generator 102, the source matcher 108, the bias RF generator 104, and the bias matcher 110 based on the source matcher measurement information.

[0424] Similarly, the communications controller 1302 of the host computer 106 applies the EtherCAT protocol to one or more EtherCAT frames 1554 and obtains or extracts bias matcher measurement information from the one or more EtherCAT frames 1554. The communications controller 1302 provides the bias matcher measurement information to the processor 1108. Upon receiving the bias matcher measurement information, the processor 1108 controls one or more of the source RF generator 102, the source matcher 108, the bias RF generator 104, and the bias matcher 110 based on the bias matcher measurement information.

[0425] Note that in one embodiment, there is no storage of one or more EtherCAT frames 1552 within the source matcher 108, and there is no storage of one or more EtherCAT frames 1554 within the bias matcher 110. For example, one or more EtherCAT frames 1552 are in a constant state of motion within the source matcher 108, and one or more EtherCAT frames 1554 are in a constant state of motion within the bias matcher 110. Illustratively, one or more EtherCAT frames 1552 move within a memory device, such as moving from one register to another in a register array of the communication controller of the source matcher 108, while source matcher data and source matcher measurement information are transferred between the communication controller of the source matcher 108 and the processor of the source matcher 108. As another example, one or more EtherCAT frames 1554 move within a memory device, such as moving from one register to another in a register array of the bias matcher's 110 communications controller, while bias matcher data and bias matcher measurement information are transmitted between the bias matcher's 110 communications controller and the bias matcher's 110 processor.

[0426] Figure 16 is a diagram of one embodiment of an EtherCAT frame 1600. EtherCAT frame 1600 is an example of one or more EtherCAT frames 1512 (Figure 15A). EtherCAT frame 1600 is an example of one or more EtherCAT frames 1552 (Figure 15B). EtherCAT frame 1600 is also an example of one or more EtherCAT frames 1554 (Figure 15B).

[0427] The EtherCAT frame 1600 includes multiple fields 1401, 1403, 1402, 1404, 1406, 1408, 1410, 1602, 1604, 1606, 1608, 1412, 1414, 1416, 1610, 1612, 1614, 1616, and 1418. Field 1401 includes a start of frame delimiter that identifies the start of the EtherCAT frame 1600. Field 1402 includes a source address of the EtherCAT frame 1600. An example of a source address is the address of the host computer 106 that generates the EtherCAT frame 1600.

[0428] Field 1403 of the EtherCAT frame 1600 contains the order in which the EtherCAT frame 1600 is circulated to the various components of the plasma system. An example of an order in which the EtherCAT frame 1600 is circulated includes the sequence from the communications controller 1302 to the source RF generator 102, from the source RF generator 102 to the source matcher 108, from the source matcher 108 to the bias RF generator 104, from the bias RF generator 104 to the bias matcher 110, from the bias matcher 110 back to the bias RF generator 104, from the bias RF generator 104 to the source matcher 108, from the source matcher 108 to the source RF generator 102, and from the source RF generator 102 to the communications controller 1302. Another example of an order for circulating the EtherCAT frame 1600 includes a sequence from the communications controller 1302 to the source RF generator 102 and back from the source RF generator 102 to the communications controller 1302 .

[0429] The field 1404 contains the destination address of the EtherCAT frame 1600. An example of a destination address is the address of the communication controller 1302 of the host computer 106, and the address of the communication controller 1302 is the final destination of the EtherCAT frame 1600.

[0430] Field 1602 contains source state information. The address identifying the source RF generator 102 is used by the communications controller of the source RF generator 102 to determine whether data received from the DSP 204 of the source RF generator 102 should be stored in field 1602.

[0431] Field 1604 contains an address of the source matcher 108, such as a MAC address, that identifies the source matcher 108 (FIG. 13A) and distinguishes it from other RF generators in the plasma system. Field 1606 contains source matcher data, and field 1608 contains source matcher measurement information. The address that identifies the source RF generator 108 is used by the communications controller of the source matcher 108 to determine whether data in field 1606 should be provided to the processor of the source matcher 108 and whether data received from the processor of the source matcher 108 should be stored in field 1608.

[0432] Field 1610 contains bias state information. The address identifying the bias RF generator 104 is used by the communications controller of the bias RF generator 104 to determine whether data received from the DSP 204 of the bias RF generator 104 should be stored in field 1610.

[0433] Field 1612 contains an address of bias matcher 110, such as a MAC address, that identifies bias matcher 110 (FIG. 13A) and distinguishes bias matcher 110 from other RF generators in the plasma system. Field 1614 contains bias matcher data, and field 1616 contains bias matcher measurement information. The address that identifies bias matcher 110 is used by the communications controller of bias matcher 110 to determine whether data in field 1614 should be provided to the processor of bias matcher 110 and whether data received from the processor of bias matcher 110 should be stored in field 1616.

[0434] Field 1418 includes a CRC for one or more of fields 1408, 1410, 1602, 1606, 1608, 1414, 1416, 1610, 1614, and 1616. For example, the CRC may be performed by the communications controller 1302 (FIG. 13A) after receiving the EtherCAT frame 1600 to determine whether the source RF generator variable information in field 1408 sent by the communications controller 1302 matches the source RF generator variable information in field 1408 received by the communications controller 1302, and to determine whether the EtherCAT frame 1600 is matched by the source RF generator variable information in field 1408 received by the communications controller 1302. 6 Determine the validity of 00.

[0435] In one embodiment, fields 1408, 1410, and 1602, or fields 1606 and 1608, or fields 1414, 1416, and 1610, or fields 1614 and 1616, or combinations thereof, are not included in EtherCAT frame 1600. For example, if EtherCAT frame 1600 is an example of any one of one or more EtherCAT frames 1552 (FIG. 15B) sent to source matcher 108 (FIG. 15B), EtherCAT frame 1600 excludes fields 1408, 1410, 1602, 1414, 1416, 1610, 1614, and 1616 of source RF generator 102, bias RF generator 104, and bias matcher 110.

[0436] In one embodiment, fields 1408, 1410, and 1602, or fields 1606 and 1608, or fields 1414, 1416, and 1610, or fields 1614 and 1616, or combinations thereof, are included but empty in EtherCAT frame 1600. For example, if EtherCAT frame 1600 is an example of any one of one or more EtherCAT frames 1552 sent to source matcher 108, EtherCAT frame 1600 excludes any data or information in fields 1408, 1410, 1602, 1414, 1416, 1610, 1614, and 1616 of source RF generator 102, bias RF generator 104, and bias matcher 110.

[0437] It should be noted that in one embodiment, the addresses of the components of the plasma system described herein are the addresses of the communication controllers of the components. For example, the MAC address of source RF generator 102 is the address of the communication controller of source RF generator 102, the MAC address of bias RF generator 104 is the address of the communication controller of bias RF generator 104, the MAC address of source matcher 108 is the address of the communication controller of source matcher 108, and the MAC address of bias matcher 110 is the address of the communication controller of bias matcher 110.

[0438] 17 is a diagram of one embodiment of a system 1700 showing an RF generator 1702 coupled to EtherCAT cables 1706 and 1708. RF generator 1702 is an example of source RF generator 102 or bias RF generator 104 (FIG. 15A). EtherCAT cable 1706 is an example of any of EtherCAT cables 1304 (FIG. 13A), 1306 (FIG. 13B), and 1504 (FIG. 15A). EtherCAT cable 1708 is an example of any of EtherCAT cables 1306 and 1508 (FIGS. 13A and 15A).

[0439] The RF generator 1702 includes a communications controller 1704, a DSP 204, an RF power supply 222, and a sensor 1710. Examples of the sensor 1710 include a complex voltage / current sensor, a complex impedance sensor, a complex power sensor, and a complex voltage sensor. The RF generator 202 (FIG. 2) is an example of the RF generator 1702, except that within the RF generator 1702, the DSP 204 is coupled to the processor 118 of the host computer 106 via the communications controller 1704. Any of the RF generators 702 (FIG. 7), 802 (FIG. 8), 902 (FIG. 9), and 1102 (FIG. 11A) is an example of the RF generator 1702, except that within the RF generator 1702, the DSP 204 is coupled to the processor 118 of the host computer 106 via the communications controller 1704.

[0440] The communications controller 1704 is coupled to an EtherCAT cable 1706 via a port 1714 on the communications controller 1704 and to an EtherCAT cable 1708 via another port 1716 on the communications controller 1704. The communications controller 1704 is also coupled to the DSP 204. The sensor 1710 is coupled to the DSP 204 and to an output 1712 of the RF generator 1702. Either of the outputs 158 and 164 (FIG. 1) is an example of an output 1712.

[0441] The communications controller 1704 receives one or more EtherCAT frames 1712 from the plasma system components via port 1714. For example, the communications controller 1704 receives one or more EtherCAT frames 1314 ( FIG. 13A ), 1352 ( FIG. 13B ), 1354 ( FIG. 13C ), or 1512 ( FIG. 15A ) from the plasma system components via port 1714. The communications controller 1704 processes the one or more EtherCAT frames 1712 and identifies the address of the RF generator 1702. For example, the communications controller 1704 compares the address of the RF generator 1702 with an address of the RF generator 1702 previously stored in the communications controller 1704's memory device and determines whether the two addresses match. If the communications controller 1704 determines that the two addresses match, the communications controller 1704 identifies the address of the RF generator 1702 from the one or more EtherCAT frames 1712.

[0442] Upon identifying the address, the communications controller 1704 identifies and extracts the data from one or more EtherCAT frames 1712 and provides the data to the DSP 204. As an example, the data provided to the DSP 204 of the RF generator 1702 is identified as the data between the address of the RF generator 1702 in one or more EtherCAT frames 1712 and the next address in the one or more EtherCAT frames 1712. Illustratively with respect to FIG. 14 , the source RF generator variable information in field 1408 is between the source RF generator address in field 1406 and the bias RF generator address in field 1412. An example of data provided to the DSP 204 includes the source RF generator variable information in field 1408 or the bias RF generator variable information in field 1414. Once the data is identified, the communications controller 1704 extracts (gets or reads or copies, etc.) the data to be provided to the DSP 204 from one or more EtherCAT frames 1712 and transmits the data to the DSP 204 .

[0443] The sensor 1710 measures a metric for one or more of the conditions described above and provides the metric to the DSP 204. The DSP 204 communicates the metric to the communications controller 1710. 0 4 or calculate the factor from the reference and send the factor to the communication controller 17 04, or a combination thereof. The communications controller 1704 also receives data from the DSP 204 and includes the data in the fields of the RF generator 1702 in one or more EtherCAT frames 1712. For example, the communications controller 1704 receives factors from the DSP 204, embeds the factors in one or more EtherCAT frames 1712, and transmits the factors via port 1714 and EtherCAT cable 1706 to a source component, such as the processor 118, source RF generator 102, or source matcher 108 of the plasma system, or transmits one or more EtherCAT frames 1712 via port 1716 to a destination component, such as the source matcher 108 or bias RF generator 104 of the plasma system. Illustratively, to transmit one or more EtherCAT frames 1712 to a component, such as a source component, a destination component, or any other component of the plasma system, the communications controller 1704 reads the sequence field 1403 of the one or more EtherCAT frames 1712 and identifies the component address from the one or more EtherCAT frames 1712. Further illustratively, to identify the component address, the communications controller 1704 compares the destination component address stored in the one or more EtherCAT frames 1712 with a component address previously stored in the communications controller 1704's memory device to determine whether the two addresses match. If the communications controller 1704 determines that the two addresses match, it identifies the component address from the one or more EtherCAT frames 1712 and transmits the one or more EtherCAT frames 1712 to the component. A source component is a component from which one or more EtherCAT frames 1712 are received by the RF generator 1702, and a destination component is a component to which one or more EtherCAT frames 1712 are transmitted by the RF generator 1702.When one or more EtherCAT frames 1712 are sent to a destination component of the plasma system via port 1716, one or more EtherCAT frames 1712 are then received from the destination component via port 1716 and sent to the destination component by the communications controller 1704 via port 1714.

[0444] In one embodiment, multiple sensors are associated with RF generator 1702. For example, another sensor may be coupled to a point on RF cable 138 or 142 (FIG. 1) and also coupled to DSP 204 to measure and provide a reference to DSP 204.

[0445] In one embodiment, the system 1700 excludes the EtherCAT cable 1708 and the communications controller 1702 excludes the port 1716 .

[0446] FIG. 18 is a diagram of one embodiment of a system 1800 showing a matcher 1802 coupled to RF generator 1702 (FIG. 17) via RF cable 1804 and coupled to EtherCAT cables 1806 and 1808. RF cable 1804 is an example of any of RF cables 138 and 142 (FIG. 1) and 218 (FIG. 2). Matcher 1802 is an example of source matcher 108 (FIG. 15A) or bias matcher 110 (FIG. 15B). EtherCAT cable 1806 is an example of any of EtherCAT cables 1306 (FIG. 15A), 1508 (FIG. 15B), and 1504 (FIGS. 15A and 15B). EtherCAT cable 1808 is an example of EtherCAT cable 1504 (FIG. 15A).

[0447] The matcher 1802 includes a communications controller 1810, a processor 1812, a driver system 1814, a sensor system 1816, a circuit component system 1818, and a motor system 1820. An example of the sensor system 1816 includes one or more sensors, such as the sensor 1710 ( FIG. 17 ). An example of the driver system 1814 includes one or more drivers, such as one or more transistors coupled to each other. An example of the circuit component system 1818 includes one or more circuit components, such as one or more inductors and capacitors coupled to each other. An example of the motor system 1820 includes one or more electric motors. Each electric motor is coupled to a respective circuit component, such as an inductor or capacitor, of the circuit component system 1818.

[0448] The source matcher 108 or the bias matcher 110 is an example of a matcher 1802, except that the matcher 1802 includes a communications controller 1810 and a processor 1812. The communications controller 1810 is coupled to the EtherCAT cable 1806 via a port 1826 of the communications controller 1810 and to the EtherCAT cable 1808 via a port 1828 of the communications controller 1810. The communications controller 1810 is also coupled to the processor 1812. The processor 1812 is coupled to a sensor system 1816 and a driver system 1814, which is coupled to a motor system 1820. The motor system 1820 is coupled to a circuitry system 1818, which is coupled to the RF cable 1804 and the plasma chamber 112 via an RF transmission line 1822. The circuitry system 1818 is coupled to the sensor system 1816. For example, a first sensor of sensor system 1816 is coupled to a first circuit component of circuit component system 1818, and a second sensor of sensor system 1816 is coupled to a second circuit component of circuit component system 1818. Either of transmission lines 140 and 144 (FIG. 1) is an example of an RF transmission line 1822.

[0449] The communications controller 1810 receives one or more EtherCAT frames 1824 from a plasma system component via port 1826. For example, the communications controller 1810 receives one or more EtherCAT frames 1512 ( FIG. 15A ), 1552 ( FIG. 15B ), or 1554 ( FIG. 15C ) from a plasma system component via port 1826. The communications controller 1810 processes the one or more EtherCAT frames 1824 and identifies the address of the matcher 1802. For example, the communications controller 1810 compares the address of the matcher 1802 with an address of the matcher 1802 previously stored in the communications controller 1810's memory device to determine whether the two addresses match. If the communications controller 1810 determines that the two addresses match, the communications controller 1810 identifies the address of the matcher 1802 from the one or more EtherCAT frames 1824.

[0450] Once the address is identified, the communications controller 1810 identifies the data, extracts the data from one or more EtherCAT frames 1824, and provides it to the processor 1812. As an example, the data provided to the processor 1812 of the matcher 1802 is identified as the data between the address of the matcher 1802 in one or more EtherCAT frames 1824 and the next address in the one or more EtherCAT frames 1824. Illustrating with respect to FIG. 16 , the source matcher data in field 1606 is between the source matcher address in field 1604 and the bias RF generator address in field 1412. An example of the data provided to the processor 1812 includes the source matcher data in field 1606 or the bias matcher data in field 1614. The communications controller 1810 extracts the data from one or more EtherCAT frames 1824. 824 The processor 1812 extracts (reads, obtains, copies, etc.) data to be provided to the processor 1812 from the

[0451] The sensor system 1816 measures a reference at one or more outputs of one or more circuit components of the circuit component system 1818 and provides the reference to the processor 1812. The processor 1812 provides the reference to the communications controller 1810. The communications controller 1810 also receives data from the processor 1812 and includes the data in the fields of the matcher 1802 in one or more EtherCAT frames 1824. For example, the communications controller 1810 receives the reference from the processor 1812, embeds the reference in one or more EtherCAT frames 1824, and transmits the reference via port 1826 and EtherCAT cable 1806 to a source component, such as the source RF generator 108 or bias RF generator 104 or host computer 106 of the plasma system, or transmits the one or more EtherCAT frames 1824 via port 1828 to a destination component, such as the bias RF generator 104 of the plasma system. For example, to transmit one or more EtherCAT frames 1824 to a component, such as a source component or a destination component or any other component of the plasma system, the communications controller 1810 reads the sequence field 1403 of the one or more EtherCAT frames 1824 and identifies the address of the destination component from the one or more EtherCAT frames 1824. Illustratively, to identify the address of the destination component, the communications controller 1810 compares the address of the destination component stored in the one or more EtherCAT frames 1824 with the address of the destination component previously stored in the memory device of the communications controller 1810 and determines whether the two addresses match. If the communications controller 1810 determines that the two addresses match, it identifies the address of the destination component from the one or more EtherCAT frames 1824 and transmits the one or more EtherCAT frames 1824 to the destination component.

[0452] A source component is a component from which one or more EtherCAT frames 1824 are received by matcher 1802. A destination component is a component to which one or more EtherCAT frames 1824 are transmitted by matcher 1802. When one or more EtherCAT frames 1824 are transmitted to a destination component of the plasma system via port 1828, the one or more EtherCAT frames 1824 are subsequently received from the destination component via port 1828 and transmitted to the destination component via port 1826 by communication controller 1810.

[0453] In one embodiment, multiple sensors are associated with matcher 1802. For example, another sensor is coupled to a point on RF transmission line 1804 and also coupled to processor 1812 to measure and provide a reference to processor 1812.

[0454] In one embodiment, the system 1800 excludes the EtherCAT cable 1808 and the communications controller 1810 excludes the port 1828.

[0455] 19A shows another embodiment of an EtherCAT synchronization system 1920, such as a plasma system, in which multiple EtherCAT cables are coupled between any two components of the EtherCAT synchronization system 1920. For example, an EtherCAT cable is coupled from an output port of the master controller to an input port of the source RF generator 102, another EtherCAT cable is coupled from another output port of the master controller to an input port of the bias RF generator 104, an EtherCAT cable is coupled from an output port of the source RF generator 102 to an input port of the source matcher 108, and an EtherCAT cable is coupled from an output port of the bias RF generator 104 to an input port of the bias matcher 110. Examples of master controllers include the host controller or host computer 106 (FIG. 1) or an ADVCI or another controller.

[0456] State information for the source RF generator 102 and the source matcher 108 is provided in pulse trains transmitted from the master controller to the source RF generator 102 and from the source RF generator 102 to the source matcher 108. For example, the duty cycle, power level, and frequency level of the states of the variables S(nA) to Sn of the RF signal 152 generated by the source RF generator 102, as well as source matcher data, are provided in pulse trains transmitted from the master controller to the source RF generator 102, and the duty cycle of the states of the variables S(nA) to Sn are provided in pulse trains transmitted from the source RF generator 102 to the source matcher 108. Similarly, the duty cycle, power level and frequency level of the RF signal 168 variables for states S(nA) through Sn, and bias matcher data are provided in another pulse train sent from the master controller to the source RF generator 104, and the duty cycle for states S(nA) through Sn is provided in another pulse train sent from the bias RF generator 104 to the bias matcher 110.

[0457] FIG. 19B is a diagram of one embodiment of an EtherCAT synchronization system 1930, such as a plasma system, in which an EtherCAT cable is coupled between an output port of the master controller and an input port of the source RF generator 102, an EtherCAT cable is coupled between an output port of the source RF generator 102 and an input port of the bias RF generator 104, an EtherCAT cable is coupled between the output port of the source RF generator 102 and an input port of the source matcher 108, and an EtherCAT cable is coupled from the output port of the source matcher 108 to the input port of the bias matcher 110.

[0458] State information for source RF generator 102, source matcher 108, bias RF generator 104, and bias matcher 110 is provided by pulse trains sent from the master controller to source RF generator 102. For example, duty cycles, power levels, and frequency levels of the states S(nA) through Sn of the variables of RF signals 152 and 168, source matcher data, and bias matcher data are provided by pulse trains sent from the master controller to source RF generator 102. The pulse trains are transmitted from source RF generator 102 to bias RF generator 104. The pulse trains sent from source RF generator 102 to source matcher 108 are also transmitted from source matcher 108 to bias matcher 110.

[0459] In one embodiment, an EtherCAT cable is coupled from the output port of bias RF generator 104 to the input of source RF generator 102, and an EtherCAT cable is coupled from the output port of bias matcher 110 to the input port of source matcher 108. In this embodiment, rather than an EtherCAT cable coupling the master controller to source RF generator 102, an EtherCAT cable is used coupling the output port of the master controller to the input port of bias RF generator 104. Also, an EtherCAT cable is coupled from the output port of bias RF generator 104 to the input port of bias matcher 110. Status information for source RF generator 102, source matcher 108, bias RF generator 104, and bias matcher 110 is provided in pulse trains sent from the master controller to bias RF generator 104. For example, a pulse train is transmitted from the master controller to the bias RF generator 104, from the bias RF generator 104 to the source RF generator 102, from the bias RF generator 104 to the bias matcher 110, and from the bias matcher 110 to the source matcher 108.

[0460] 19C is a diagram of an embodiment of an EtherCAT synchronization system 1950, such as a plasma system, in which components are coupled in a daisy chain configuration. For example, an EtherCAT cable is coupled from an output port of the master controller to an input port of the source RF generator 102, an EtherCAT cable is coupled from an output port of the source RF generator 102 to an input port of the source matcher 108, an EtherCAT cable is coupled from an output port of the source matcher 108 to an input port of the bias matcher 110, and an EtherCAT cable is coupled from an output port of the bias matcher 110 to an input port of the bias RF generator 104.

[0461] Status information for source RF generator 102, source matcher 108, bias RF generator 104, and bias matcher 110 is provided in a pulse train sent from the master controller to source RF generator 102. The pulse train is then sent from source RF generator 102 to source matcher 108, then from source matcher 108 to bias matcher 110, and from bias matcher 110 to bias RF generator 104.

[0462] 19D is a diagram of an embodiment of an EtherCAT synchronization system 1960, such as a plasma system, in which components are coupled in a daisy chain configuration. For example, an EtherCAT cable is coupled from an output port of the master controller to an input port of the bias RF generator 104, an EtherCAT cable is coupled from an output port of the bias RF generator 104 to an input port of the bias matcher 110, an EtherCAT cable is coupled from an output port of the bias matcher 110 to an input port of the source matcher 108, and an EtherCAT cable is coupled from an output port of the source matcher 108 to an input port of the source RF generator 102.

[0463] Status information for source RF generator 102, source matcher 108, bias RF generator 104, and bias matcher 110 is provided in a pulse train sent from the master controller to bias RF generator 104. The pulse train is then sent from bias RF generator 104 to bias matcher 110, then from bias matcher 110 to source matcher 108, and from source matcher 108 to source RF generator 102.

[0464] calibration

[0465] 20 is a diagram of one embodiment of a system 2000 illustrating a pulse train calibration method. As shown with respect to FIG. 20, a radio frequency generator (RFG) generator, such as a host computer 106 (FIG. 1) or a digital signal processor or ADVCI, generates PL signals to the RFG for multiple states S(nA), S(n-A+1), S(n-1), and Sn. S(n-A) , P.L. S(n-A+1) PL S(n-1) and PL Sn, etc., where A is a positive integer. As an example, several states S(nA) through Sn range from 4 to 36. Illustratively, the number of states may be four, five, six, seven, eight, nine, ten, eleven, twelve, thirteen, fourteen, fifteen, or sixteen. Each state may occur for one or more microseconds. For example, each of states S(nA) through Sn has the same duty cycle. Illustratively, state S(nA) may occur for a number of microseconds, state S(n-A+1) may occur for the same number of microseconds, and so on until state Sn occurs for the same number of microseconds. As another example, the duty cycle of one or more states may differ from the duty cycle of one or more of the remaining states. For example, state S(nA) occurs for the first microsecond, and state Sn occurs for the second microsecond. As another example, state S(nA) occurs for the first microsecond, state S(n-A+1) occurs for the second microsecond, and state Sn occurs for the third microsecond. One example of a radio frequency generator RFG is RF generator 702 (FIG. 7). Another example of a radio frequency generator RFG is RF generator 902 (FIG. 9).

[0466] The radio frequency generator RFG operates at a power level PL S(n-A) , P.L. S(n-A+1) PL S(n-1) and PL Sn and supplies the RF signal to a known load, such as a 50 ohm load. A voltage sensor coupled to the known load measures the voltage value and supplies the voltage value to the RFG controller. For example, the voltage sensor is coupled to the input of the known load. As another example, the voltage sensor is coupled to an RF cable, and the RF cable is coupled between the radio frequency generator RFG and the known load. The RFG controller calculates V for states S(nA), S(n-A+1) from the voltage value received from the voltage sensor. S(n-A) , V S(n-A+1) ···V S(n-1), VSn, etc. For each state, the RFG controller determines whether to change the power level of the state based on the voltage value of the state, and based on the decision, adjusts the power level PL S(n-A) , P.L. S(n-A+1) PL S(n-1) and PL Sn As an example, the RFG controller determines whether the voltage value of the state is outside a preset range and adjusts the power level of the state until the voltage value is within the preset range.

[0467] 21 is a diagram of one embodiment of a system 2000 illustrating a voltage pulse leveling method. As described above with respect to the system 2000 of FIG. 20, the power level PL S(n-A) , P.L. S(n-A+1) PL S(n-1) and PL Sn An RF signal having a voltage V is applied to a known load, and a voltage sensor measures the voltage value. The voltage value is provided to the RFG controller. Referring back to system 2000 of FIG. 21, the RFG controller divides each state into multiple substates or subpulses. For example, state S(nA) is divided into substates S(nA)1, S(nA)2, and substate S(nA)m, and so on, until substates S(nA)1, S(nA)2, and substate S(nA)m are determined, where m is an integer greater than or equal to 3. As another example, state S(n-1) is divided into substates S(n-1)1, S(n1-1)2, and state Sn is divided into substates Sn1, Sn2, and substate Snm, and so on, until substates Sn1, Sn2, and substate Snm are determined. For each substate, the RFG controller determines a voltage value from the measured voltage value received from the voltage sensor. As an example, the RFG controller may determine a voltage value V S(n-A)1 , V S(n-A)2 and the voltage value V of the lower states S(nA)1 to S(nA)m S(n-A)m The same calculation is repeated until the voltage value V S(n-A)1 is a statistical measurement of the voltage values, such as the mean or median, measured during the substate S(nA)1, and the voltage values ​​V S(n-A)2 is a statistical measurement of the voltage values ​​measured during the substate S(nA)2. Similarly, the RFG controller S(n-1)1 , V S(n-1)2, and the voltage values ​​V of the substates S(n-1)1 to S(n-1)m S(n-1)m The same calculation is continued until the voltage value V Sn1 , V Sn2 , and the voltage values ​​V from the lower states Sn1 to Snm Snm Based on the calculated voltage values ​​for each substate, the RFG controller calculates the power level PL S(n-A)2 , and the power level PL of the substate S(n-1)1 of state S(n-1) S(n-1)1 and so on until the voltage value is within the predetermined range. In this way, the RFG controller adjusts the power level PL S(n-A) , P.L. S(n-A+1) PL S(n-1) and PL Sn Adjust one or more of the following.

[0468] 22 is a diagram of one embodiment of a system 2000 illustrating a duty cycle calibration method. As described with respect to FIG. 20, a voltage sensor measures a voltage value and provides the voltage value to an RFG controller. Referring to system 100, the RFG controller adjusts the power level PL from states S(nA) to S(nA) based on the voltage value of the state. S(n-A) , P.L. S(n-A+1) PL S(n-1) and PL Sn For example, multiple voltage values ​​for state Sn are measured for a duration, and multiple voltage values ​​for state S(nA) are measured for the same or different durations, where the voltage values ​​for state S(nA) are different from the voltage values ​​for state Sn.

[0469] The determined duty cycle is the power level PL S(n-A) State S(nA) Duty cycle DC S(n-1) etc., power level PL S(n-1) The duty cycle of the state S(n-1) is DC S(n-1) and power level PL Sn State of Sn Duty cycle DC Snand so on until it is determined that the duty cycle of each of the corresponding states is within a preset duty cycle range. The RFG controller adjusts one or more of the duty cycles of the corresponding states until the duty cycle or duty cycles are within the corresponding one or more preset duty cycle ranges. For example, the RFG controller may adjust the duty cycle DC Sn In response to determining that the power level PL is not within the preset duty cycle range of state Sn, Sn Regarding the duty cycle of the Sn state, DC Sn Increase or decrease.

[0470] It should be noted that in one embodiment, rather than using a voltage sensor in the systems of Figures 20, 21 or 22, a power sensor that measures power, or a complex voltage-current sensor that measures complex voltage-current, may be used.

[0471] Tuning four or more states (tuning TCCT matchers to average impedance)

[0472] 23 shows a system 2300 including a controller (CTRL) and a source matcher 108, such as a source-transformer coupled capacitively tuned (TCCT) matcher. An example of a controller includes an RFG controller (FIG. 20). A further example of a controller CRTL includes a host computer 106 (FIG. 1) and a host controller. An example of a TCCT matcher is provided in U.S. Patent No. 10,056,231, which is incorporated herein by reference in its entirety.

[0473] The controller CTRL is coupled to the source RF generator 102, the bias RF generator 104, the source matcher 108, and the bias matcher 110. The source matcher 108 is coupled to the TCP coil 126 of the plasma chamber 112. The substrate support 128 or the lower electrode of the substrate support 128 may be referred to herein as the bias electrode.

[0474] The controller CTRL provides timing information for states S(nA) through Sn to the source matching device 108. For example, the controller CTRL provides a duty cycle, including a start time and an end time for each of states S(nA) through Sn, to the source matching device 108. The timing information is provided to the source matching device 108 to tune the source matching device 108 during one or more of states S(nA) through Sn, matching the impedance of a load coupled to the output of the source matching device 108 with the impedance of a source coupled to the input of the source matching device 108 and reducing reflected power toward the source RF generator 102. Examples of a load include the plasma chamber 112 and the RF transmission line 140 that couples the source matching device 108 to the TCP coil 126, and examples of a source include the source RF generator 102 and the RF cable 138 that couples the source RF generator 102 to the source matching device 108.

[0475] The controller CTRL controls the source matching circuit 108 via one or more motor drivers and corresponding one or more motors to adjust one or more capacitances or inductances, or combinations thereof, from states S(nA) to Sn to further reduce reflected power toward one or more source RF generators 102 from states S(nA) to Sn. For example, the source matching circuit 108 changes the capacitance or inductance, or combinations thereof, of a state over multiple clock cycles of the clock signal to match the impedance of a load coupled to the output 158 ​​of the source matching circuit 108 with the impedance of a source coupled to the input 156 of the source matching circuit 108. States S(nA) to Sn occur over each clock cycle of the clock signal and repeat with each clock cycle. The clock signal is received from the controller CTRL or a clock source, such as a clock oscillator. While the source RF generator 102 generates an RF signal 152 having states S(nA) to Sn, the bias RF generator 104 can generate an RF signal 168, which may be continuous or have two states or more than two states.

[0476] In one embodiment, in addition to the bias RF generator 104 , one or more additional bias RF generators are coupled to the plasma chamber 112 via a bias matcher 110 .

[0477] In one embodiment, the bias matcher 110 opera...

Claims

1. 1. A multi-state pulsing method, the method comprising: receiving a synchronization signal; identifying a plurality of cycles from the synchronization signal; generating a first plurality of plasma impedance states by controlling a first radio frequency (RF) generator to generate a first RF signal having a first plurality of states and controlling a second RF generator to generate a second RF signal having a second plurality of states during one cycle of the plurality of cycles; Including, each of the first plurality of states defines a maximum amplitude of a respective variable of the first RF signal, and each of the second plurality of states defines a maximum amplitude of a respective variable of the second RF signal, and each of the first and second plurality of states is repeated for another one of the plurality of cycles; varying the first plurality of plasma impedance states to a second plurality of plasma impedance states by varying a time at which the first RF signal transitions from a first state of the first plurality of states to a second state of the first plurality of states; method.

2. 2. The method of claim 1, wherein the receiving is performed by the first RF generator, the synchronization signal is a digital pulse signal, the digital pulse signal is periodically repeated and has the plurality of cycles, each of the plurality of cycles having a duty cycle.

3. 2. The method of claim 1, wherein identifying the plurality of cycles includes identifying a first cycle of the plurality of cycles and a second cycle of the plurality of cycles, and wherein identifying the first cycle of the plurality of cycles and the second cycle of the plurality of cycles includes identifying a start time and a stop time of the first cycle of the plurality of cycles and a start time and a stop time of the second cycle of the plurality of cycles.

4. 2. The method of claim 1, wherein the first RF signal has four or more variable levels, each of the four or more variable levels being a parameter level, each of the four or more parameter levels having a plurality of amplitudes, a maximum amplitude of each of the variables of the first RF signal being a maximum amplitude of the plurality of amplitudes at each parameter level of the four or more parameter levels, and the maximum amplitude of each of the variables of the first RF signal being one of a plurality of envelopes of the first RF signal.

5. 10. The method of claim 1, wherein each of the four or more variable levels is a distinct horizontal level, the first plurality of plasma impedance states is varied to achieve a second plurality of plasma impedance states, and the RF signal is an oscillating signal; varying the second plurality of plasma impedance states to a third plurality of plasma impedance states by varying a time at which the second RF signal transitions from a first state of the second plurality of states to a second state of the second plurality of states.

6. 2. The method of claim 1, wherein the variable is frequency or power; The method, wherein the RF signals are oscillating signals, the first RF signal is supplied to an RF coil of a plasma chamber, and the second RF signal is supplied to a lower electrode of the plasma chamber.

7. 2. The method of claim 1, wherein during the one cycle of the plurality of cycles, the first RF signal transitions from a first variable level of four or more variable levels to a second variable level of the four or more variable levels, from the second variable level of the four or more variable levels to a third variable level of the four or more variable levels, and from the third variable level of the four or more variable levels to a fourth variable level of the four or more variable levels.

8. 2. The method of claim 1, wherein the first RF signal has four or more variable levels, each of the four or more variable levels defining a minimum amplitude of the first RF signal, and the minimum amplitude of a first variable level of the four or more variable levels is greater than the maximum amplitude of a second variable level of the four or more variable levels.

9. 2. The method of claim 1, wherein during the one cycle of the plurality of cycles, the first RF signal transitions from a first variable level of the four or more variable levels to a second variable level of the four or more variable levels, from the second variable level of the four or more variable levels to a third variable level of the four or more variable levels, and from the third variable level of the four or more variable levels to a fourth variable level of the four or more variable levels, the method comprising: controlling a transition gradient from the first variable level of the four or more variable levels to the second variable level of the four or more variable levels; controlling a transition gradient from the second variable level of the four or more variable levels to the third variable level of the four or more variable levels; controlling a transition gradient from the third variable level of the four or more variable levels to the fourth variable level of the four or more variable levels; The method further comprises:

10. 1. A system for multi-state pulsing, comprising: a first processor configured to receive a synchronization signal, the first processor configured to identify a plurality of cycles from the synchronization signal; a first radio frequency (RF) power source; a second processor configured to receive the synchronization signal, the second processor configured to identify the plurality of cycles from the synchronization signal; a second RF power source; Equipped with the first processor is configured to control the first RF power source and the second processor is configured to control the second RF power source to generate a first plurality of plasma impedance states during a cycle of the plurality of cycles; the first RF power source is controlled to generate a first radio frequency (RF) signal having a first plurality of states, and the second RF power source is controlled to generate a second RF signal having a second plurality of states; each of the first plurality of states defines a maximum amplitude of a respective variable of the first RF signal, and each of the second plurality of states defines a maximum amplitude of a respective variable of the second RF signal, and each of the first and second plurality of states is repeated for another one of the plurality of cycles; the first processor is configured to vary the first plurality of plasma impedance states to a second plurality of plasma impedance states by varying a time at which the first RF signal transitions from a first state of the first plurality of states to a second state of the first plurality of states; system.

11. 11. The system of claim 10, wherein the synchronization signal is a digital pulse signal, the digital pulse signal repeating periodically and having the plurality of cycles, each of the plurality of cycles having a duty cycle.

12. 11. The system of claim 10, wherein, to identify the plurality of cycles, the first processor is configured to identify a first cycle of the plurality of cycles and a second cycle of the plurality of cycles, and, to identify the first cycle of the plurality of cycles and the second cycle of the plurality of cycles, the first processor is configured to identify a start time and a stop time of the first cycle of the plurality of cycles and a start time and a stop time of the second cycle of the plurality of cycles.

13. 11. The system of claim 10, wherein the first RF signal has four or more variable levels, each of the four or more variable levels being a parameter level, each of the four or more parameter levels having a plurality of amplitudes, a maximum amplitude of each of the variables of the first RF signal being a maximum amplitude of the plurality of amplitudes at each of the parameter levels of the four or more parameter levels, and the maximum amplitude of each of the variables of the first RF signal being one of a plurality of envelopes of the first RF signal.

14. 11. The system of claim 10, wherein each of the four or more variable levels is a distinct horizontal level and the first RF signal is an oscillator signal.

15. The system of claim 10 , wherein each of the four or more variable levels is a frequency level or a power level.

16. 11. The system of claim 10, wherein during the one cycle of the plurality of cycles, the first processor is configured to control the first RF power source to transition from a first variable level of four or more variable levels to a second variable level of the four or more variable levels, to transition from the second variable level of the four or more variable levels to a third variable level of the four or more variable levels, and to transition from the third variable level of the four or more variable levels to a fourth variable level of the four or more variable levels.

17. 11. The system of claim 10, wherein each of the four or more variable levels defines a minimum amplitude of the first RF signal, and the minimum amplitude of a first variable level of the four or more variable levels is greater than the maximum amplitude of a second variable level of the four or more variable levels.

18. 1. A controller for multi-state pulsing, said controller comprising: a processor configured to generate a synchronization signal comprising a plurality of cycles; a memory device coupled to the processor; Equipped with the processor is configured to generate a first plurality of plasma impedance states by controlling a first radio frequency (RF) generator to generate a first RF signal having a first plurality of states and a second RF generator to generate a second RF signal having a second plurality of states during one cycle of the plurality of cycles; each of the first plurality of states defines a maximum amplitude of a respective variable of the first RF signal, and each of the second plurality of states defines a maximum amplitude of a respective variable of the second RF signal, and each of the first and second plurality of states is repeated for another one of the plurality of cycles; the processor is configured to vary the first plurality of plasma impedance states to a second plurality of plasma impedance states by varying a time at which the first RF signal transitions from a first state of the first plurality of states to a second state of the first plurality of states; Controller.

19. 20. The controller of claim 18, wherein the synchronization signal is a digital pulse signal, the digital pulse signal repeating periodically and having the plurality of cycles, each of the plurality of cycles having a duty cycle.

20. 20. The controller of claim 18, wherein the plurality of cycles includes a first cycle of the plurality of cycles and a second cycle of the plurality of cycles, the first cycle of the plurality of cycles including a start time and a stop time, and the second cycle of the plurality of cycles including a start time and a stop time.

21. 20. The controller of claim 18, wherein the first RF signal has four or more variable levels, each of the four or more variable levels being a parameter level, each of the four or more parameter levels having a plurality of amplitudes, a maximum amplitude of each of the variables of the first RF signal being a maximum amplitude of the plurality of amplitudes at each of the parameter levels of the four or more parameter levels, and the maximum amplitude of each of the variables of the first RF signal being one of a plurality of envelopes of the first RF signal.

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