Query instructions for model-dependent information

Abstract

Instructions are executed to perform a query function. Executing the instructions includes obtaining information about a selected model of a processor. The information includes at least one model-dependent data attribute of the selected model of the processor. The information is placed in a selected location for use by at least one application in performing one or more functions.

Description

[Technical Field]

[0001] One or more aspects relate generally to facilitating processing within a computing environment, and more particularly, to improving such processing. [Background technology]

[0002] To improve processing in computing environments that are data-intensive, computationally intensive, or both, coprocessors, such as artificial intelligence accelerators (also called neural network processors or neural network accelerators), are utilized. Such accelerators provide a large amount of computing power that is used in performing computations involving, for example, matrix and tensor calculations.

[0003] Tensor calculus is used in complex processing, including, by way of example, deep learning, a subset of machine learning. Deep learning or machine learning, a form of artificial intelligence, is used in a variety of technologies, including but not limited to, engineering, manufacturing, medical technology, automotive technology, and computer processing.

[0004] Tensors and tensor computations enable deep learning processes to accept large amounts of data, detailed data, or both as inputs. However, accelerators used for deep learning processes are limited by the data bandwidth to and from the accelerator. Currently, data locality and data reuse on accelerators are employed to address this limitation. Advances in the use of tensors, or processes using such tensors, or both, are expected to lead to improvements in machine learning techniques involving computer processing. Summary of the Invention

[0005] Shortcomings of the prior art are overcome and further advantages are achieved through the provision of a computer program product for facilitating processing within a computing environment. The computer program product includes one or more computer-readable storage media and program instructions collectively stored on the one or more computer-readable storage media for performing a method. The method includes executing instructions to perform a query function. Executing the instructions includes obtaining information about a selected model of a processor. The information includes at least one model-dependent data attribute of the selected model of the processor. The information is placed in a selected location for use by at least one application in performing one or more functions.

[0006] The query function adapts the machine to the features present in a particular model of the machine, providing information that makes it easier to solve problems involving larger data sets, thereby improving techniques that use machine learning, including computer processing.

[0007] Executing the query function obtains model-dependent information for at least one data attribute, which can be used when executing one or more functions using data having the at least one data attribute. Knowing the at least one data attribute can save execution time by preparing an application for the at least one data attribute, which can then adapt the application to the data, data layout, and / or data size, for example, to perform neural network processing on that particular model. Preparing the application reduces errors, saves execution time, and improves system performance.

[0008] The query function provides improvements in the use of tensors and / or processing using such tensors when at least one data attribute is associated with a tensor and / or when processing uses such tensors.

[0009] In one example, the at least one model-dependent data attribute includes one or more supported data types for a selected model of the processor. By obtaining the supported data types, the application is tailored to the data types supported by the particular model of the processor. This allows the application to adapt to the data, data layout, and / or data size, for example, to perform neural network processing on that particular model. Preparing the application reduces errors, saves execution time, and improves system performance.

[0010] The selected location may, for example, include a parameter block accessible to at least one application, with one or more supported data types included in one or more fields of the parameter block. By having the parameter block accessible to at least one application, the application can learn the supported data types and use this knowledge in its processing. This allows the application to adapt to the data, data layout, and / or data size, for example, to perform neural network processing on that particular model. Preparing the application reduces errors, saves execution time, and improves system performance.

[0011] In one example, the at least one model-dependent data attribute includes one or more supported data layout formats for a selected model of the processor. By obtaining the one or more supported data layout formats, the application is tailored to one or more data layout formats supported by the particular model of the processor. This allows the application to adapt to the data, data layout, and / or data size, for example, to perform neural network processing on that particular model. Preparing the application reduces errors, saves execution time, and improves system performance.

[0012] The selected location may, for example, include a parameter block accessible to at least one application, where one or more supported data layout formats are included in one or more fields of the parameter block. By having the parameter block accessible to at least one application, the application can learn the one or more supported data layout formats and use this knowledge in its processing. This allows the application to adapt to the data, data layout, and / or data size, for example, to perform neural network processing on that particular model. Preparing the application reduces errors, saves execution time, and improves system performance.

[0013] In one example, the at least one model-dependent data attribute includes one or more supported data sizes for a selected model of processor. By obtaining the supported data sizes, the application is tailored to one or more data sizes supported by the particular model of processor. This allows the application to adapt to the data, data layout, and / or data sizes, for example, to perform neural network processing on that particular model. Preparing the application reduces errors, saves execution time, and improves system performance.

[0014] The selected location may, for example, include a parameter block accessible to at least one application, with one or more supported data sizes contained in one or more fields of the parameter block. By having the parameter block accessible to at least one application, the application can learn the supported data sizes and use this knowledge in its processing. This allows the application to adapt to the data, data layout, and / or data size, for example, to perform neural network processing on that particular model. Preparing the application reduces errors, saves execution time, and improves system performance.

[0015] By way of example, the one or more supported data sizes include a maximum dimension index size and a maximum tensor size.

[0016] As an example, the selected location includes a parameter block accessible to at least one application, the parameter block including a plurality of fields for storing a plurality of model-dependent data attributes of the selected model. The plurality of fields may include, for example, an installed data type field including one or more supported data types for the selected model of the processor, an installed data layout format field including one or more supported data layout formats for the selected model of the processor, and one or more fields including supported data sizes for the selected model of the processor. By making the parameter block accessible to at least one application, the application can learn the supported data types, data layout formats, and data sizes and use this knowledge in its processing. This allows the application to adapt to the data, data layout, and / or data size, for example, to perform neural network processing on that particular model. Preparing the application reduces errors, saves execution time, and improves system performance.

[0017] In one example, the parameter block further includes at least one of an installed function vector field and an installed parameter block format field, where the installed function vector field indicates one or more supported functions of the selected model of the processor and the installed parameter block format field indicates one or more supported formats of the parameter block.

[0018] Computer-implemented methods and systems relating to one or more aspects are also described and claimed herein. Additionally, services relating to one or more aspects may also be described and claimed herein.

[0019] Additional features and advantages are realized by the techniques described herein. Other embodiments and aspects are described in detail herein and are considered a part of the claimed aspects. [Brief explanation of the drawings]

[0020] One or more aspects are particularly pointed out and distinctly claimed as examples in the claims at the end of this specification. The foregoing, as well as objects, features, and advantages of one or more aspects, will become apparent from the following detailed description taken in conjunction with the accompanying drawings. [Figure 1A] FIG. 1 illustrates an example of a computing environment that incorporates and uses one or more aspects of the present invention. [Figure 1B] FIG. 1B illustrates further details of the processor of FIG. 1A in accordance with one or more aspects of the present invention. [Figure 2] FIG. 10 illustrates an example of processing a query function in accordance with one or more aspects of the present invention. [Figure 3A] FIG. 10 illustrates an example format of neural network processing assist instructions for performing a query function in accordance with one or more aspects of the present invention. [Figure 3B] FIG. 2 illustrates an example of a general purpose register used by neural network processing assist instructions in accordance with one or more aspects of the present invention. [Figure 3C] FIG. 10 illustrates an example of function code supported by neural network processing assist instructions in accordance with one or more aspects of the present invention. [Figure 3D] FIG. 10 illustrates an example of another general-purpose register used by neural network processing assist instructions in accordance with one or more aspects of the present invention. [Figure 3E] FIG. 2 illustrates an example of a parameter block used by a query function of a neural network processing assist instruction in accordance with one or more aspects of the present invention. [Figure 3F]FIG. 2 illustrates an example of a parameter block used by one or more non-query functions of a neural network processing assist instruction in accordance with one or more aspects of the present invention. [Figure 3G] FIG. 10 illustrates an example of a tensor descriptor used by neural network processing assist instructions in accordance with one or more aspects of the present invention. [Figure 4] FIG. 1 illustrates an example of a data type format for Neural Network Processing (NNP)-Data Type 1 in accordance with one or more embodiments of the present invention. [Figure 5] 1A-1C illustrate exemplary input data layouts used by neural network processing assist instructions in accordance with one or more aspects of the present invention. [Figure 6] 6A-6C are diagrams illustrating example outputs corresponding to the input data layouts of FIGS. 5A-5C, according to one or more aspects of the present invention. [Figure 7A] FIG. 1 illustrates an example of facilitating processing within a computing environment in accordance with one or more aspects of the present invention. [Figure 7B] FIG. 1 illustrates an example of facilitating processing within a computing environment in accordance with one or more aspects of the present invention. [Figure 8A] FIG. 1 illustrates another example of a computing environment that incorporates and uses one or more aspects of the present invention. [Figure 8B] FIG. 8B illustrates an example of further details of the memory of FIG. 8A in accordance with one or more embodiments of the present invention. [Figure 8C] FIG. 8B illustrates another example of further details of the memory of FIG. 8A in accordance with one or more embodiments of the present invention. [Figure 9A] FIG. 1 illustrates yet another example of a computing environment incorporating and using one or more aspects of the present invention. [Figure 9B] FIG. 9B illustrates further details of the memory of FIG. 9A in accordance with one or more embodiments of the present invention. [Figure 10] FIG. 1 illustrates an embodiment of a cloud computing environment in accordance with one or more aspects of the present invention. [Figure 11] FIG. 2 illustrates an example of an abstraction model layer in accordance with one or more aspects of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0021] According to one or more aspects of the present invention, capabilities are provided to facilitate processing within a computing environment. As one example, a query function is provided that conveys model-dependent detailed information regarding selected attributes of a processor (e.g., selected attributes of a particular model of a processor). The selected attributes include selected attributes of data stored and / or used by the processor, such as, for example, data layout, data type, and / or data size.

[0022] In one example, the query function is included as part of an instruction, such as a single instruction (e.g., a single architected hardware machine instruction at a hardware / software interface) configured to perform multiple functions including the query function. The query function is configured to indicate detailed information about the function / operation and one or more data attributes supported by the instruction. Because each function is configured as part of a single instruction (e.g., a single architected instruction), system resource usage and complexity can be reduced, and system performance can be improved.

[0023] The instructions may be part of a general-purpose processor instruction set architecture (ISA) that is dispatched by a program on a processor, such as a general-purpose processor. The instructions may be executed by the general-purpose processor, or one or more functions of the instructions may be executed by a special-purpose processor, such as a co-processor configured for a specific function, that is coupled to or is part of the general-purpose processor, or both. Other variations are possible.

[0024] An example of an instruction that includes and uses a query function is a Neural Network Processing Assist instruction, which is used to provide functionality related to tensor computations and / or other operations. This example instruction is described in more detail below. Note that the Neural Network Processing Assist instruction is an example of an instruction that uses a query function, but other instructions may also use such functions.

[0025] One embodiment of a computing environment incorporating and using one or more aspects of the present invention is described with reference to FIG. 1A. By way of example, the computing environment is based on the z / Architecture® instruction set architecture (manufactured by International Business Machines Corporation, Armonk, New York). One embodiment of the z / Architecture instruction set architecture is described in the publication entitled “z / Architecture Principles of Operation” (IBM Publication No. SA22-7832-12, 13th Edition, September 2019), which is incorporated herein by reference in its entirety. However, the z / Architecture instruction set architecture is merely an example, and other architectures and / or types of computing environments from International Business Machines Corporation and / or other entities may include and / or use one or more aspects of the present invention. Note that z / Architecture and IBM are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction.

[0026] 1A , a computing environment 100 includes, for example, a computer system 102. The computer system 102 is illustrated, for example, as a general-purpose computing device. The computer system 102 may include, but is not limited to, one or more general-purpose processors or processing units 104 (e.g., central processing units (CPUs)), at least one special-purpose processor, such as a neural network processor 105, memory 106 (also referred to as, for example, system memory, main memory, main storage, central storage, or storage), and one or more input / output (I / O) interfaces 108, coupled to each other via one or more buses and / or other connections. For example, the processors 104, 105 and the memory 106 are coupled to the I / O interface 108 via one or more buses 110, and the processors 104, 105 are coupled to each other via one or more buses 111.

[0027] Bus 111 may be, for example, a memory or cache coherence bus. Bus 110 may represent any one or more of several types of bus structures, including, for example, a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. For example, but not limited to, such architectures include Industry Standard Architecture (ISA), Micro Channel Architecture (MCA), Enhanced ISA (EISA), Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI).

[0028] By way of example, one or more special purpose processors (e.g., neural network processors) may be separate from and coupled to, or integrated with, one or more general purpose processors, or both. Many variations are possible.

[0029] For example, memory 106 may include a cache 112, such as a shared cache, that may be coupled to a local cache 114 of processor 104 and / or to neural network processor 105, e.g., via one or more buses 111. Additionally, memory 106 may include one or more programs or applications 116 and at least one operating system 118. One example of an operating system is the z / OS® operating system (manufactured by International Business Machines Corporation, Armonk, New York). z / OS is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Other operating systems provided by International Business Machines Corporation and / or other entities may also be used. Memory 106 may also include one or more computer-readable program instructions 120 that may be configured to perform functions of embodiments of aspects of the present invention.

[0030] Additionally, in one or more embodiments, memory 106 includes processor firmware 122. Processor firmware includes, for example, processor microcode or millicode. Processor firmware includes, for example, hardware-level instructions and / or data structures used in implementing higher-level machine code. In one embodiment, processor firmware includes, for example, microcode or millicode that includes trusted software or proprietary code that controls operating system access to system hardware, typically provided as microcode or millicode specific to the underlying hardware.

[0031] The computer system 102 may communicate with one or more external devices 130, such as a user terminal, a tape drive, a pointing device, a display, and one or more data storage devices 134, for example, via the I / O interface 108. The data storage devices 134 may store one or more programs 136, one or more computer-readable program instructions 138, or data, or a combination thereof. The computer-readable program instructions may be configured to perform the functions of embodiments of aspects of the present invention.

[0032] The computer system 102 may also communicate with a network interface 132, for example, via the I / O interface 108. This enables the computer system 102 to communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network (e.g., the Internet), or a combination thereof, to facilitate communication with other computing devices or systems.

[0033] Computer system 102 may include, be coupled to, or both removable and non-removable, volatile and non-volatile computer system-readable media. For example, computer system 102 may include, be coupled to, or both non-removable, non-volatile magnetic media (commonly referred to as a "hard drive"), a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a "floppy disk"), or an optical disk drive for reading from and writing to a removable, non-volatile optical disk (e.g., a CD-ROM, DVD-ROM, or other optical media). It should be noted that other hardware and / or software components may be used with computer system 102. Examples include, but are not limited to, microcode or millicode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data archive storage systems, etc.

[0034] Computer system 102 may operate with numerous other general-purpose or special-purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, suitable for use with computer system 102 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0035] As an example, a processor (e.g., processor 104 or 105, or both) includes multiple functional components (or a subset thereof) used to execute instructions. As shown in FIG. 1B , these functional components include, for example, an instruction fetch component 150 that fetches instructions to be executed, an instruction decode unit 152 that decodes the fetched instructions and obtains operands for the decoded instructions, one or more instruction execution components 154 that execute the decoded instructions, a memory access component 156 that accesses memory for instruction execution as needed, and a write back component 158 ​​that provides results of the executed instructions. One or more of the components may access and / or use one or more registers 160 in instruction processing. Furthermore, one or more of the components may include at least a portion of or have access to one or more other components used in performing, in accordance with one or more aspects of the present invention, for example, query functions and / or neural network processing assist processing of neural network processing assist instructions (or other processing that can use one or more aspects of the present invention) described herein. These one or more other components may include, for example, a query function component 170 or a neural network processing assist component 172 or both (and / or one or more other components).

[0036] In accordance with one or more aspects of the present invention, a query function is provided that conveys detailed information about a particular model of a selected processor (e.g., neural network processor 105). For example, the query function is implemented in processor 104 (because the processor knows the details of the particular model of the selected processor) or in the selected processor (e.g., neural network processor 105). The detailed information includes, for example, model-dependent data attributes supported by the processor, such as the particular model of the processor, and functions / operations provided by selected instructions. In one example, the processor is a neural network processor (also called a neural network accelerator), such as neural network processor 105, and the query function is used to convey at least detailed information about the data attributes supported by the particular model of the neural network processor.

[0037] An example of processing a query function is described with reference to Figure 2. This processing is performed by a general purpose processor, such as general purpose processor 104. In other embodiments, this processing may be performed by a special purpose processor, such as neural network processor 105. Other embodiments are possible.

[0038] Referring to FIG. 2 , in one embodiment, a query function is initiated via an instruction. Thus, the instruction is obtained at step 200 and executed at step 210. In one example, this execution includes determining whether a query function is specified by the instruction at step 220. This may include, for example, decoding the instruction and checking at least one operand of the instruction to determine which function is being initiated. If a query function is not specified at step 220, other instruction processing is performed at step 230. In contrast, if a query function is specified at step 220, information about a particular processor, and in particular a particular model of the processor, is obtained at step 240. A particular model of a machine or processor has particular capabilities. Another model of a machine or processor (e.g., currently implemented) may have additional, less, or different capabilities or a combination thereof, and / or may be of a different generation (e.g., current or future generation) having additional, less, or different capabilities or a combination thereof. The information obtained includes, for example, model-dependent attributes of a particular processor, particularly attributes related to data used and / or stored by a particular model of a particular processor. The query function also obtains an indication of particular functions that may be executed on the processor, such as through instructions used to execute the query function. Additional, less, or other information, or combinations thereof, may also be obtained.

[0039] In one example, the information is obtained by firmware of the processor executing the query function. The firmware has knowledge about the attributes of a particular model of a particular processor (e.g., a neural network processor). This information may be stored, for example, in a control block, a register, or a memory or a combination thereof, and / or may be accessible to the processor executing the query function.

[0040] The retrieved information is placed in step 250, for example, in a parameter block or other structure that is accessible to and / or used with one or more applications that may use the information in further processing. In one example, the parameter block and / or the parameter block information are maintained in memory. In other embodiments, the parameter block and / or the information may be maintained in one or more hardware registers. As another example, the query function may be a privileged operation performed by an operating system that makes available an application programming interface to make this information available to applications or other non-privileged programs. In yet another example, the query function is performed by a dedicated processor, such as neural network processor 105. Other examples are possible.

[0041] In one example, the query function is executed to determine information about a neural network processor, such as neural network processor 105. This information includes, for example, the data types, data sizes, and / or data layout formats supported by a selected model of the neural network processor. This information is model-dependent in that other models (e.g., earlier models and / or future models) may not support the same data attributes, such as the same data types, data sizes, and / or data layout formats.

[0042] In other embodiments, other information may be acquired. The acquired information (e.g., model-dependent data attributes and / or other information) is used, for example, by an application in further processing. For example, the application executes neural network processing assist instructions on a processor, such as general-purpose processor 104, to acquire model-dependent information (e.g., model-dependent data attributes) and / or other information (e.g., functions supported by the instructions and / or neural network processor, parameter block format, etc.) about the neural network processor. The acquired information (at least selected information) is then used in other executions of the neural network processing assist instructions to perform other functions specified by the instructions (referred to herein as “non-query functions”). These non-query functions are used to perform operations related to, for example, tensor calculations. In one embodiment, other executions of the neural network processing assist instructions are initiated by the general-purpose processor, while the non-query functions specified by the instructions are executed by a dedicated processor (e.g., neural network processor 105) using at least a portion of the acquired information. Further details related to query functions and neural network processing assist instructions are described below.

[0043] An example of a neural network processing assist instruction is described with reference to FIG. 3A. In one example, the instruction is initiated on a general-purpose processor (e.g., processor 104), and the function specified by the instruction is executed on the general-purpose processor or the special-purpose processor (e.g., special-purpose processor 105), or both, depending on the function. The instruction is then completed on the general-purpose processor. In another example, the instruction is initiated, executed, and completed on one or more general-purpose processors or one or more special-purpose processors. Other variations are possible. Note that the description herein refers to a particular location, a particular field, or a particular size of a field, or a combination thereof (e.g., a particular byte or bit, or both). However, other locations, fields, or sizes, or combinations thereof, may be provided. Furthermore, while it may be specified that a bit is set to a particular value, e.g., 1 or 0, this is by way of example only. In other examples, when a bit is set, it may be set to a different value, such as the opposite value or a different value. Many variations are possible.

[0044] In one example, referring to Figure 3A, a neural network processing assist instruction 300 has an RRE format that indicates registers and register operations through an extended operation code (opcode). As shown in Figure 3A, in one example, the neural network processing assist instruction 300 includes an operation code (opcode) field 302 (e.g., bits 0-15) that indicates a neural network processing assist operation. In one example, bits 16-31 of the instruction are reserved and contain zeros.

[0045] In one example, an instruction uses multiple general purpose registers implicitly specified by the instruction. For example, neural network processing assist instruction 300 uses implicit registers general purpose register 0 and general purpose register 1. Examples of these are described with reference to Figures 3B and 3D, respectively.

[0046] Referring to FIG. 3B, in one example, general register 0 includes a function code field and a status field that may be updated upon completion of an instruction. In one example, general register 0 includes a response code field 310 (e.g., bits 0-15), an exception flags field 312 (e.g., bits 24-31), and a function code field 314 (e.g., bits 56-63). Additionally, in one example, bits 16-23 and bits 32-55 of general register 0 are reserved and contain zeros. One or more fields are used by a particular function performed by the instruction. In one example, not all fields are used by all functions. Each field is described below.

[0047] Response Code (RC) 310: This field (e.g., bit positions 0-15) contains a response code. When execution of a neural network processing assist instruction completes with a condition code of, for example, "1," the response code is stored. When an invalid input condition is encountered, a non-zero value indicating the cause of the invalid input condition recognized during execution is stored in the response code field, and a selected condition code, for example, "1," is set. The codes stored in the response code field are defined as follows, by way of example:

[0048] Response Code Meaning

[0049] 0001 The parameter block format specified by the parameter block version number is not supported by the model.

[0050] 0002 The specified function is not defined or is not installed on your machine.

[0051] 0010 The specified tensor data layout format is not supported.

[0052] 0011 The specified tensor data type is not supported.

[0053] 0012 The specified single tensor dimension is larger than the maximum dimension index size.

[0054] 0013 The specified tensor size is larger than the maximum tensor size.

[0055] 0014 The specified tensor address is not aligned on a 4 K-byte boundary.

[0056] 0015 The function-specific-save-area-address is not aligned to a 4K-byte boundary.

[0057] F000-FFFF Function-specific response codes. These responses are defined for specific functions.

[0058] Exception Flags (EF) 312: This field (e.g., bit positions 24-31) contains exception flags. If an exception condition is detected during execution of an instruction, the corresponding exception flag control (e.g., bit) is set, e.g., to 1; otherwise, the control is not changed. The exception flags field is initialized to 0 before the first call of the instruction. The reserved flags are not changed during execution of the instruction. The flags stored in the exception flags field are defined as follows, by way of example:

[0059] EF (bit) meaning

[0060] 0 Range violation. This flag is set when a non-numeric value is detected in an input tensor or stored in an output tensor. This flag is only valid when the instruction completes with a condition code of, for example, '0'.

[0061] 1~7 spare

[0062] Function Code (FC) 314: This field (e.g., bit positions 56-63) contains the function code. Examples of function codes assigned to neural network processing assist instructions are shown in FIG. 3C. All other function codes are unassigned. When an unassigned or uninstalled function code is specified, a response code of, for example, hexadecimal "0002" and a selection condition code of, for example, "1" are set. This field does not change during execution.

[0063] As shown here, the neural network processing assist instructions use general-purpose register 1 in addition to general-purpose register 0. An example of general-purpose register 1 is shown in FIG. 3D. As an example, bits 40 through 63 in 24-bit addressing mode, bits 33 through 63 in 31-bit addressing mode, or bits 0 through 63 in 64-bit addressing mode contain the address of parameter block 320. The contents of general-purpose register 1 specify, for example, the logical address of the leftmost byte of the parameter block in storage. The parameter block is specified on a doubleword boundary; otherwise, a specification exception is recognized. For all functions, the contents of general-purpose register 1 are unchanged.

[0064] In access register mode, access register 1 specifies an address space that includes, by way of example, the parameter block, input tensors, output tensors, and function-specific save areas.

[0065] In one example, the parameter block can have different formats depending on the function specified by the instruction being executed. For example, a query function has a parameter block in one format, while other functions of the instruction have a parameter block in another format. In another example, all functions use the same parameter block format. Other variations are possible.

[0066] An example of a parameter block used by a query function such as an NNPA-QAF (Query Available Functions) operation is described with reference to Figure 3E. As shown, in one example, the NNPA-QAF parameter block 330 includes, for example:

[0067] Installed Functions Vector 332: This field (e.g., bytes 0-31) of the parameter block contains a vector of installed functions. In one example, bits 0-255 of the installed functions vector correspond to function codes 0-255, respectively, of the neural network processing assist instructions. If a bit is, for example, 1, the corresponding function is installed; otherwise, the function is not installed.

[0068] Installed parameter block formats vector 334: This field (e.g., bytes 32-47) of the parameter block contains a vector of installed parameter block formats. In one example, bits 0-127 of the installed parameter block formats vector correspond to parameter block formats 0-127 of the non-query functions of the neural network processing assist instruction. If a bit is, for example, 1, the corresponding parameter block format is installed; otherwise, the parameter block format is not installed.

[0069] Installed Data Types 336: This field of the parameter block (e.g., bytes 48-49) contains a vector of installed data types. In one example, bits 0-15 of the installed data types vector correspond to the data types to be installed. If a bit is, for example, 1, the corresponding data type is installed; otherwise, the data type is not installed. Examples of data types include the following (although additional, fewer, or other data types, or combinations thereof, are possible):

[0070] Bit Data Type

[0071] 0 NNP-Data Type 1

[0072] 1~15 Reserve

[0073] Installed Data Layout Formats 338: This field (e.g., bytes 52-55) of the parameter block contains a vector of installed data layout formats. In one example, bits 0-31 of the installed data layout formats vector correspond to the data layout formats to be installed. If a bit is, for example, 1, the corresponding data layout format is installed; otherwise, the data layout format is not installed. Examples of data layout formats include the following (note that additional, fewer, or other data layout formats, or combinations thereof, are possible):

[0074] Bit Data Layout Format

[0075] 0 4D-feature tensor

[0076] 1 4D-kernel tensor

[0077] 2~31 Reserve

[0078] Maximum Dimension Index Size 340: This field (e.g., bytes 60-63) of the parameter block contains, for example, a 32-bit unsigned binary integer that specifies the maximum number of elements in the specified dimension index size for any specified tensor. In another example, the maximum dimension index size specifies the maximum number of bytes in the specified dimension index size for any specified tensor. Other examples are possible.

[0079] Maximum Tensor Size 342: This field (e.g., bytes 64-71) of the parameter block contains a 32-bit unsigned binary integer that specifies the maximum number of bytes in any specified tensor, including, for example, any pad bytes required by the tensor format. In another example, the maximum tensor size specifies the maximum total number of elements in any specified tensor, including any padding required by the tensor format. Other examples are possible.

[0080] Installed NNP-Data Type 1 Transformation Vector 344: This field (e.g., bytes 72-73) of the parameter block contains a vector of installed NNP-Data Type 1 transformations. In one example, bits 0-15 of the Installed NNP-Data Type 1 Transformation Vector correspond to the transformations of installed data types from / to the NNP-Data Type 1 format. If a bit is 1, the corresponding transformation is installed; otherwise, the transformation is not installed. Additional, fewer, or other transformations, or a combination thereof, may be specified.

[0081] Bit Data Type

[0082] 0 Reserve

[0083] 1 BFP tiny format

[0084] 2. BFP short format

[0085] 3~15 Reserve

[0086] Although an example of a query function parameter block is described with reference to Figure 3E, other formats of a query function parameter block including an NNPA-QAF operation may be used. The format may, in one example, depend on the type of query function being performed. Furthermore, the parameter block and / or each field of the parameter block may include additional information, less information, other information, or a combination thereof.

[0087] In addition to parameter blocks for query functions, in one example there is a parameter block format for non-query functions, such as non-query functions of neural network processing assist instructions. An example of a parameter block used by a non-query function, such as a non-query function of a neural network processing assist instruction, is described with reference to FIG. 3F.

[0088] As shown, in one example, a parameter block 350 employed by, for example, a non-query function of a neural network processing assist instruction includes, for example:

[0089] Parameter Block Version Number 352: This field of the parameter block (e.g., bytes 0-1) specifies the version and size of the parameter block. In one example, bits 0-8 of the parameter block version number are reserved and contain zeros, and bits 9-15 of the parameter block version number contain an unsigned binary integer that specifies the format of the parameter block. The query function provides a mechanism to indicate available parameter block formats. If the specified parameter block size or format is not supported by the model, a response code, e.g., hexadecimal "0001", is stored in general register 0 and the instruction is completed by setting a condition code (e.g., condition code "1"). The parameter block version number is specified by the program and does not change during instruction execution.

[0090] Model Version Number 354: This field (e.g., byte 2) of the parameter block is an unsigned binary integer that identifies the model that executed the instruction (e.g., a particular non-query function). If the Continue Flag (described below) is 1, the Model Version Number can be input to the operation for the purpose of interpreting the contents of the Continuation State Buffer field (described below) of the parameter block and resuming the operation.

[0091] Continuation flag 356: This field (e.g., bit 63) of the parameter block, when set to 1, indicates that the operation is partially complete and can be resumed using the contents of the continuation state buffer. Programs initialize the continuation flag to 0 and do not change it if an instruction is re-executed with the intent of resuming the operation; otherwise, results are unpredictable.

[0092] If the continue flag is set at the beginning of the operation and the contents of the parameter block are changed since the initial call, the results are unpredictable.

[0093] Function-specific save area address 358: This field (e.g., bytes 56-63) of the parameter block contains the logical address of the function-specific save area. In one example, the function-specific save area address is aligned to a 4K byte boundary. If not, a response code of, for example, hexadecimal "0015" is set in general register 0, and the instruction completes with a condition code of, for example, "1". The address depends on the current addressing mode. The size of the function-specific save area depends on the function code.

[0094] If the entire function-specific save area overlaps with a program event recording (PER) storage area specification, a PER storage modification event is recognized for the function-specific save area, if applicable. If only part of the function-specific save area overlaps with a PER storage area specification, one of the following occurs, depending on the model:

[0095] * PER storage modification events are recognized, if applicable, for the entire function-specific save area.

[0096] * PER storage modification events are recognized, if applicable, for stored portions of function-specific save areas.

[0097] If the entire parameter block overlaps with the PER storage region specification, a PER storage change event is recognized, if applicable, for the parameter block. If only part of the parameter block overlaps with the PER storage region specification, it is model-dependent which of the following occurs:

[0098] * PER storage change events are recognized, if applicable, for the entire parameter block.

[0099] * For stored portions of the parameter block, PER storage change events are recognized, if applicable.

[0100] For parameter blocks, a PER zero-address detection event is recognized, if applicable. Zero address detection does not apply to tensor addresses or function-specific save area addresses, in one example.

[0101] Output tensor descriptors (e.g., 1-2) 360 / input tensor descriptors (e.g., 1-3) 365: An example of a tensor descriptor is described with reference to Figure 3G. In one example, the tensor descriptors 360, 365 include:

[0102] Data layout format 382: This field (e.g., byte 0) of the tensor descriptor specifies the data layout format. Valid data layout formats include, for example, the following (note that additional, fewer, or other data layout formats, or combinations thereof, are possible):

[0103] Format Description Alignment (bytes)

[0104] 0 4D feature tensor 4096

[0105] 1 4D kernel tensor 4096

[0106] 2~255 Reserve -

[0107] If an unsupported or reserved data layout format is specified, a response code of, for example, hex "0010" is stored in general register 0, and the instruction is completed by setting a condition code of, for example, "1".

[0108] Data Type 384: This field (e.g., byte 1) specifies the data type of the tensor. Examples of supported data types are listed below (note that additional, fewer, or other data types, or combinations thereof, are possible):

[0109] Value Data Type Data Size (bits)

[0110] 0 NNP Data Type-1 16

[0111] 1~255 Reserved -

[0112] If an unsupported or reserved data type is specified, a response code of, for example, hex "0011" is stored in general register 0, and the instruction is completed by setting a condition code of, for example, "1".

[0113] Dimension 1-4 Index Size 386: Collectively, dimension index sizes 1-4 specify the shape of a four-dimensional tensor. Each dimension index size is greater than 0 and less than or equal to the maximum dimension index size (340, Figure 3E). If not, a response code, e.g., hex "0012", is stored in general register 0, and the instruction is completed by setting a condition code, e.g., "1". The total tensor size is less than or equal to the maximum tensor size (342, Figure 3E). If not, a response code, e.g., hex "0013", is stored in general register 0, and the instruction is completed by setting a condition code, e.g., "1".

[0114] In one example, to determine the number of bytes (i.e., total tensor size) of a 4D feature tensor with elements of NNPA-data type 1, the following is used: dimension index 4 * dimension index 3 * ceil(dimension index 2 / 32) * 32 * ceil(dimension index 1 / 64) * 64 * 2.

[0115] Tensor Address 388: This field of the tensor descriptor (e.g., bytes 24-31) contains the logical address of the leftmost byte of the tensor. The address is subject to the current addressing mode.

[0116] If the address is not aligned to a boundary in the relevant data layout format, a response code, e.g., hex "0014", is stored in general register 0 and the instruction is completed by setting a condition code, e.g., "1".

[0117] In access register mode, access register 1 specifies the address space containing all active input and output tensors in storage.

[0118] Returning to FIG. 3F, parameter block 350, in one example, further includes function-specific parameters 1-5 (370) that can be used by particular functions, as described herein.

[0119] Additionally, parameter block 350, in one example, includes a continuation state buffer field 375. This field contains data (or the location of data) to be used if operation of this instruction is resumed.

[0120] As input to the operation, the reserved field of the parameter block must contain 0. Once the operation is complete, the reserved field may be stored as 0 or may remain unchanged.

[0121] Although an example of a non-query function parameter block was described with reference to FIG. 3F, other formats of non-query function parameter blocks may be used, including non-query functions of neural network processing assist instructions. The format may, in one example, depend on the type of function being performed. Furthermore, although an example of a tensor descriptor was described with reference to FIG. 3G, other formats may be used. Furthermore, different formats may be used for input and output tensors. Other variations are possible.

[0122] Further details regarding the various functions supported by one embodiment of the neural network processing assist instructions are provided below.

[0123] Function code 0: NNPA-QAF (Query available functions)

[0124] The Neural Network Processing Assist (NNPA) query function provides a mechanism to display selected information, such as the availability of installed functions, installed parameter block formats, installed data types, installed data layout formats, maximum dimension index size, maximum tensor size, etc. Once the information is obtained, it is placed in a selected location, such as a parameter block (e.g., parameter block 330). Once the operation is complete, the reserved fields of the parameter block may be stored as zero or may remain unchanged.

[0125] In executing one embodiment of a query function, a processor, such as general-purpose processor 104, obtains information about a particular model of a selected processor, such as a particular model of a neural network processor, such as neural network processor 105. The obtained information is placed in a parameter block (e.g., parameter block 330) or other structure that is accessible to and / or used in conjunction with one or more applications that may use this information in further processing.

[0126] The obtained information includes model-dependent detailed information about at least one or more data attributes of a particular processor, including, for example, one or more installed or supported data types, one or more installed or supported data layout formats, or one or more installed or supported data sizes, or a combination thereof, of a selected model of the particular processor. This information is model-dependent in that other models (e.g., earlier models or future models, or both) may not support the same data attributes, such as the same data types, data sizes, or data layout formats, or a combination thereof. When execution of a query function (e.g., an NNPA-QAF function) is completed, in one example, a condition code of 0 is set. Condition codes 1, 2, and 3, in one example, do not apply to query functions. Further details regarding the obtained information are described below.

[0127] As shown here, in one example, the obtained information includes, for example, model-dependent information regarding one or more data attributes of a particular model of a neural network processor. One example of a data attribute is the installed data type of the neural network processor. For example, a particular model of a neural network processor (or other processor) may support one or more data types, such as, for example, the NNP-Data Type 1 data type (also referred to as the Neural Network Processing-Data Type 1 data type) and / or other data. The NNP-Data Type 1 data type is a 16-bit floating-point format that offers many advantages, for example, for deep learning training and inference operations. Advantages include, for example, maintaining the precision of deep learning networks, eliminating subnormal formats to simplify rounding modes and corner case handling, automatic rounding to nearest in arithmetic operations, and combining the special entities infinity and not-a-number (NaN) into a single value (NINF) that can be accepted and handled in arithmetic operations. NINF provides better defaults for exponent overflow and invalid operations (such as division by zero), allowing many programs to continue running without hiding such errors and without using dedicated exception handlers. Other model-dependent data types are also possible.

[0128] An example of the format of the NNP-Data Type 1 data type is shown in Figure 4. As shown, in one example, data of NNP-Data Type 1 can be represented, for example, in format 400. Format 400 includes, for example, a sign 402 (e.g., bit 0), an exponent +31 (404) (e.g., bits 1-6), and a decimal 406 (e.g., bits 7-15).

[0129] An example of the format characteristics of NNP-Data Type 1 is shown below.

[0130] Characteristics NNP-Data Type 1

[0131] Format length (bits) 16 bits

[0132] Biased exponent length (bits) 6 bits

[0133] Decimal length (bits) 9 bits

[0134] Precision (p) 10 bits

[0135] Maximum left-units-view index (Emax) 32

[0136] Minimum left unit display exponent (Emin) -31

[0137] Left Unit Display (LUV) Bias 31

[0138] TIFF0007828703000001.tif8161

[0139] TIFF0007828703000002.tif8161

[0140] TIFF0007828703000003.tif19167

[0141] Further details regarding the NNP-Data Type 1 data type are provided below.

[0142] Biased exponent: The bias used to allow the exponent to be expressed as an unsigned number is shown above. Biased exponents are similar to the properties of binary floating-point formats, except that no special meaning is attached to all-zero and all-one biased exponents, as described below with reference to the NNP-DataType1 data type class.

[0143] Significand: The binary point of a number of NNP-data type 1 is considered to be to the left of the leftmost fraction bit. To the left of the binary point there is an implied unit bit, which is considered to be 1 for normal numbers and 0 for zero. The fraction with the implied unit bit attached to its left is the significand of the number.

[0144] A typical NNP-data type 1 value is the mantissa multiplied by base 2 and raised to the power of the unbiased exponent.

[0145] Values ​​of non-zero numbers: The values ​​of non-zero numbers are as follows:

[0146] Numeric Class Value

[0147] Normal number ±2 e-31 x (1.f)

[0148] where e is the biased exponent in decimal and f is the fraction in binary.

[0149] In one embodiment, NNP-Data Type 1 data has three classes containing numeric entities and associated non-numeric entities. Each data item contains a sign, an exponent, and a mantissa. The exponent is biased so that all biased exponents are non-negative unsigned numbers, and the smallest biased exponent is 0. The mantissa contains an explicit fraction and an implicit unit bit to the left of the binary point. The sign bit is 0 for positive and 1 for negative.

[0150] All allowable non-zero finite numbers have a unique NNP-Data Type 1 representation. There are no subnormal numbers that allow multiple representations of the same value, and there are no subnormal arithmetic operations. The three classes include, for example:

[0151] Data Class Sign Biased Exponent Unit Bits* Fraction

[0152] Zero ± 0 0 0

[0153] Normal number ± 0 1 non-0

[0154] Normal numbers ± 1 Any value that is not 0, not all 1s

[0155] normal number ± all ones - not all ones

[0156] NINF ± all 1 - all 1 where "-" indicates not applicable, "*" indicates an implicit unit bit, and NINF indicates not a number or infinity.

[0157] Further details regarding each class are provided below.

[0158] Zero: Zero has a biased exponent of zero and a fraction of zero. The implicit unit bit is zero.

[0159] Normal Numbers: Normal numbers can have biased exponents of any value. If the biased exponent is zero, the fraction is non-zero. If the biased exponent is all ones, the fraction is not all ones. Other biased exponent values ​​can be any fractional value. The implicit unit bit is 1 for all normal numbers.

[0160] NINF: NINF is represented by a biased exponent of all ones and a fraction of all ones. NINF represents values ​​that are not in the range of representable values ​​of NNP - data type 1 (i.e., a 16-bit floating point designed for deep learning with 6 exponent bits and 9 fraction bits). Typically, NINF is only propagated during an operation, so it remains displayed even after the operation is complete.

[0161] In one example, NNP-data type 1 is supported, but other model-dependent (e.g., proprietary or non-standard) data types and one or more standard data types (e.g., IEEE 754 short precision, binary floating point 16-bit, IEEE half precision floating point, 8-bit floating point, 4-bit integer format, 8-bit integer format, or a combination thereof) may be supported. These data formats have different properties for neural network processing. As an example, smaller data types (e.g., fewer bits) can be processed faster and require less cache / memory. Larger data types provide more accurate results in neural networks. Supported data types may have one or more allocated bits in the query parameter block (e.g., in the installed data types field 336 of the parameter block 330). For example, model-dependent, proprietary, or non-standard data types supported by a particular processor are indicated in the installed data types field, while standard data types are not. In other embodiments, one or more standard data types are also indicated. Other variations are possible.

[0162] In one example, bit 0 of installed data types field 336 is reserved for the NNP-Data Type 1 data type, and when set to 1, indicates that the processor supports NNP-Data Type 1. In one example, the installed data types bit vector is configured to represent up to 16 data types, with a bit assigned to each data type. However, in other embodiments, the bit vector may support more or fewer data types. Furthermore, the vector may be configured such that one or more bits are assigned to a data type. Many examples are possible, and / or additional, fewer, or other data types, or combinations thereof, may be supported and / or represented in the vector.

[0163] In one example, the query function obtains an indication of the data types installed in the model-dependent processor and places the indication in the parameter block, e.g., by setting one or more bits in the installed data type field 336 of the parameter block 330. Additionally, in one example, the query function obtains an indication of the installed data layout format (another data attribute) and places the information in the parameter block, e.g., by setting one or more bits in the installed data layout format field 338. Examples of data layout formats include, for example, a 4D-feature tensor layout and a 4D-kernel tensor layout. In one example, the 4D feature tensor layout is used by the functions described herein, and in one example, a convolution function uses a 4D kernel tensor layout. These data layout formats arrange data in storage for tensors in a manner that improves processing efficiency when executing the functions of the neural network processing assist instructions. For example, the neural network processing assist instructions use input tensors provided in a particular data layout format to operate efficiently. It should be noted that although example layouts have been provided, additional, fewer, or other layouts, or combinations thereof, may be provided for the functions described herein and / or other functions.

[0164] The use or availability of a layout for a particular processor model is provided by a vector of installed data layout formats (e.g., field 338 of parameter block 330). This vector, for example, a bit vector of installed data layout formats, allows the CPU to communicate to applications which layouts are supported. For example, bit 0 is reserved for the 4D feature tensor layout and, when set to, for example, 1, indicates that the processor supports the 4D feature tensor layout. Bit 1 is reserved for the 4D kernel tensor layout and, when set to, for example, 1, indicates that the processor supports the 4D kernel tensor layout. In one example, the bit vector of installed data layout formats is configured to represent up to 16 data layouts, with a bit assigned to each data layout. However, in other embodiments, the bit vector may support more or fewer data layouts. Furthermore, the vector may be configured such that one or more bits are assigned to a data layout. Many examples are possible. Details of the 4D feature tensor layout and the 4D kernel tensor layout are described below. Again, other layouts may be used now or in the future to optimize performance.

[0165] In one example, the neural network processing assist instructions operate on four-dimensional tensors, i.e., tensors having four dimensions. These four-dimensional tensors are obtained from the general input tensors described herein, e.g., in a row-major manner. That is, when enumerating the tensor elements in increasing memory address order, the inner dimension, called E1, first steps up by the value of E1 index size, starting from 0 to E1 index size 1, then the index of the E2 dimension is incremented, and the stepping of the E1 dimension is repeated. Finally, the index of the outer dimension, called E4 dimension, is incremented.

[0166] A tensor with a lower dimensionality (e.g., a 3D or 1D tensor) is represented as a 4D tensor, with one or more dimensions of the 4D tensor beyond the dimensions of the original tensor set to 1.

[0167] We describe the conversion of a row-major generalized 4-dimensional tensor with dimensions E4, E3, E2, E1 to a 4-dimensional feature tensor layout (also referred to herein as NNPA data layout format 0 - 4-dimensional feature tensor).

[0168] The resulting tensor can be represented as, for example, a 4-dimensional tensor of a 64-element vector, or a 5-dimensional tensor with the following dimensions:

[0169] TIFF0007828703000004.tif12167

[0170] The elements [e4][e3][e2][e1] of the generic tensor are mapped to the following elements of the resulting 5-dimensional tensor:

[0171] TIFF0007828703000005.tif24169

[0172] The resulting tensor may be larger than the generic tensor. Elements of the resulting tensor that do not have a corresponding element in the generic tensor are called pad elements.

[0173] NNPA Data Layout Format for 64-Element Vectors - Consider elements [fe4][fe1][fe3][fe2][fe0] of a 4-dimensional feature tensor, or equivalent representation, as a 5-dimensional tensor of elements, which are either padded elements or corresponding elements of a generalized 4-dimensional tensor with dimensions E4, E3, E2, E1, which can be determined by the following formula:

[0174] If fe2 ≧ E2, then E2 (or page) is a pad element.

[0175] Otherwise, if fe1 * 64 + fe0 ≥ E1, then E1 (or row) is a pad element.

[0176] Otherwise, the corresponding elements of the generic 4-dimensional tensor are:

[0177] [fe4][fe3][fe2][fe1 * 64 + fe0]

[0178] For convolutional neural network-based artificial intelligence models, the meaning of the four dimensions of the feature tensor can generally be mapped as follows:

[0179] E4: N-mini-batch size

[0180] E3:H - 3D tensor / image height

[0181] E2:W - Width of 3D tensor / image

[0182] E1:C - Channel or class of 3D tensors

[0183] For machine learning or recurrent neural network based artificial intelligence models, the meaning of the four dimensions of a four-dimensional feature tensor can generally be mapped as follows:

[0184] E4:T - Number of time steps or models

[0185] E3: Reserved. Normally set to 1.

[0186] E2:N mb -Minibatch size

[0187] E1:L-Features

[0188] NNPA Data Layout Format 0, for example, provides two-dimensional data locality of 4k-byte data blocks (pages) and 4k-byte block data alignment for the outer dimension of the generated tensor.

[0189] Pad element bytes are ignored in input tensors and are unpredictable in output tensors. Changes to PER storage on pad bytes are unpredictable.

[0190] An example of an input data layout for a four-dimensional feature tensor layout having dimensions E1, E2, E3, and E4 is shown in FIGS. 5A-5C, and an example of an output four-dimensional feature tensor layout is shown in FIGS. 6A-6C. Referring to FIG. 5A, a three-dimensional tensor 500 having dimensions E1, E2, and E3 is shown. In one example, each three-dimensional tensor contains multiple two-dimensional tensors 502. The numerical values ​​in each two-dimensional tensor 502 describe the memory offset where each of its elements is located in memory. The input is used to layout the data of the original tensor (e.g., the original four-dimensional tensor of FIGS. 5A-5C) in memory as shown in FIGS. 6A-6C, which correspond to FIGS. 5A-5C.

[0191] In FIG. 6A, as an example, a unit (e.g., a memory page) of memory 600 includes a preselected number (e.g., 32) of rows 602, each identified by, e2_page_idx, for example. Each row has a preselected number (e.g., 64) of elements 604, each identified by, e1_page_idx, for example. If a row does not include the preselected number of elements, padding 606, referred to as row padding or E1 padding, is performed. If the memory unit does not have the preselected number of rows, padding 608, referred to as page padding or E2 padding, is performed. By way of example, the row padding may be, for example, 0 or another value, and the page padding may be, for example, the existing value, 0, or another value.

[0192] In one example, output elements of a row are provided in memory (e.g., in a page) based on the element position in the E1 direction of its corresponding input. For example, referring to FIG. 5A, element positions 0, 1, and 2 (e.g., element positions at the same position in each matrix) of the three illustrated matrices are shown in row 0 of page 0 of FIG. 6A, and so on. In this example, the four-dimensional tensor is small, and all of the elements of each two-dimensional tensor representing the four-dimensional tensor fit on one page. However, this is merely an example. A two-dimensional tensor may include one or more pages. If a two-dimensional tensor is created based on reformatting a four-dimensional tensor, the number of pages for the two-dimensional tensor is based on the size of the four-dimensional tensor. In one example, one or more ceil functions are used to determine the number of rows of the two-dimensional tensor and the number of elements in each row, indicating how many pages will be used. Other variations are possible.

[0193] In one example, in addition to the 4-dimensional feature tensor layout, the neural network processor may support 4-dimensional kernel tensors, which rearrange the elements of a 4-dimensional tensor to reduce the number of memory accesses and data collection steps when performing certain artificial intelligence (e.g., neural network processing assist) operations such as convolution. In one example, a row-major generic 4D tensor with dimensions E4, E3, E2, E1 is converted to the NNPA data layout format 1 - 4-dimensional kernel tensor (4-dimensional kernel tensor) as described herein.

[0194] The resulting tensor can be represented as a 4-dimensional tensor, for example a 64-element vector, or as a 5-dimensional tensor with the following dimensions:

[0195] TIFF0007828703000006.tif12167

[0196] The elements [e4][e3][e2][e1] of the generic tensor are mapped to the following elements of the resulting 5-dimensional tensor:

[0197] TIFF0007828703000007.tif24167

[0198] The resulting tensor may be larger than the generic tensor. Elements of the resulting tensor that do not have a corresponding element in the generic tensor are called pad elements.

[0199] NNPA Data Layout Format for 64-Element Vectors 1 - Consider the elements [fe4][fe1][fe3][fe2][fe0] of a 4-dimensional feature tensor, or equivalent representation, as a 5-dimensional tensor of elements, which are either padded elements or corresponding elements of a generalized 4-dimensional tensor with dimensions E4, E3, E2, E1, which can be determined by the following formula:

[0200] If fe2 ≧ E2, then E2 (or page) is a pad element.

[0201] Otherwise, if fe1 * 64 + fe0 ≥ E1, then E1 (or row) is a pad element.

[0202] Otherwise, the corresponding elements of the generic 4-dimensional tensor are:

[0203] [fe4][fe3][fe2][fe1 * 64 + fe0]

[0204] For convolutional neural network-based artificial intelligence models, the meaning of the 4th dimension of the kernel tensor can generally be mapped as follows:

[0205] E4:H - 3D tensor / image height

[0206] E3:W - Width of a 3D tensor / image

[0207] E2:C - Number of channels in a 3D tensor

[0208] E1: K-kernel number

[0209] NNPA Data Layout Format 1 provides, for example, two-dimensional kernel parallelism within 4k-byte data blocks (pages) and 4k-byte block data alignment for the outer dimension of the generated tensor for efficient processing.

[0210] Pad bytes are ignored in input tensors; changes to PER storage on pad bytes are unpredictable.

[0211] Again, exemplary data layout formats include a 4-dimensional feature tensor layout and a 4-dimensional kernel tensor layout, although other data layout formats may be supported by a processor (e.g., neural network processor 105). An indication of the supported data layouts may be obtained, for example, by setting one or more bits in field 338 and placed in the query parameter block.

[0212] The query parameter block also includes other data attribute information in accordance with one or more aspects of the present invention. The other data attribute information includes, for example, supported size information for the data. Processors, such as neural network processors, typically have limitations based on internal buffer size, processing unit, data bus structure, firmware limitations, etc., which can limit the maximum size of a tensor dimension and / or the overall size of a tensor. Therefore, the query function provides fields for communicating these limitations to the application. For example, the processor obtains various data sizes, such as the maximum dimension index size (e.g., 65,536 elements) and the maximum tensor size (e.g., 8 GB), based on the execution of the query function and includes this information in fields 340 and 342, respectively, of the parameter block (e.g., parameter block 330). Note that additional, lesser, or other size information, or combinations thereof, may be supported by the processor (e.g., neural network processor 105) and therefore may be obtained and placed in the parameter block (e.g., fields 340, 342, and / or other fields). In other embodiments, the limit may be smaller or larger, or the size may be in other units, such as bytes instead of elements, or elements instead of bytes, or both. Furthermore, in other embodiments, rather than having the same maximum size for all dimensions, the maximum size for each dimension may be different. Many variations are possible.

[0213] In accordance with one or more aspects of the present invention, a query function is provided that conveys detailed information related to a particular model of a selected processor (e.g., neural network processor 105). The detailed information may include, for example, model-dependent information related to the particular processor. (The processor may also support standard data attributes, such as standard data types, standard data layouts, etc., which are implied, not necessarily presented, by the query function. However, in other embodiments, the query function may display all or various selected subsets of the data attributes, etc.) While exemplary information is provided, other information may be provided in other embodiments. The obtained information (which may be different for different models of a processor, or different models of different processors, or both) is used to perform artificial intelligence processing and / or other processing. The artificial intelligence processing and / or other processing may employ, for example, one or more non-query functions of neural network processing assist instructions. The particular non-query functions employed by a process are implemented by executing the neural network processing assist instructions one or more times and specifying the particular non-query functions.

[0214] Examples of non-query functions supported by neural network processing assist instructions are described below (although in other embodiments additional, fewer, or other functions, or combinations thereof, may be supported).

[0215] Function code 16: NNPA-ADD (addition)

[0216] When the NNPA-ADD function is specified, each element of input tensor 1, described by tensor descriptor 1, is added to the corresponding element of input tensor 2, described by tensor descriptor 2, and the resulting sum is placed in the corresponding element of the output tensor, described by output tensor descriptor.

[0217] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0218] In one example, the shapes, data layouts, and data types of input tensor1, input tensor2, and output tensor are the same; otherwise, a general operand data exception is recognized.

[0219] In one example, the output tensor descriptor 2, input tensor descriptor 3, function-specific parameters 1-5, and function-specific save area address fields are ignored.

[0220] Function code 17: NNPA-SUB (subtraction)

[0221] When the NNPA-SUB function is specified, each element of input tensor 2, described by tensor descriptor 2, is subtracted from the corresponding element of input tensor 1, described by tensor descriptor 1, and the resulting difference is placed in the corresponding element of the output tensor.

[0222] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0223] In one example, the shapes, data layouts, and data types of Input Tensor1, Input Tensor2, and Output Tensor are the same; if not, a general operand data exception is recognized.

[0224] In one example, the output tensor descriptor 2, input tensor descriptor 3, function-specific parameters 1-5, and function-specific save area address fields are ignored.

[0225] Function code 18: NNPA-MUL (multiplication)

[0226] When the NNPA-MUL function is specified, the product of each element (multiplier) of input tensor 1 described by tensor descriptor 1 and the corresponding element (multiplicand) of input tensor 2 described by tensor descriptor 2 is placed in the corresponding element of the output tensor.

[0227] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0228] In one example, the shapes, data layouts, and data types of Input Tensor1, Input Tensor2, and Output Tensor are the same; if not, a general operand data exception is recognized.

[0229] In one example, the output tensor descriptor 2, input tensor descriptor 3, function-specific parameters 1-5, and function-specific save area address fields are ignored.

[0230] Function code 19: NNPA-DIV (division)

[0231] When the NNPA-DIV function is specified, each element (dividend) of input tensor 1, described by tensor descriptor 1, is divided by the corresponding element (divisor) of input tensor 2, described by tensor descriptor 2, and the quotient is placed in the corresponding element of the output tensor.

[0232] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0233] In one example, the shapes, data layouts, and data types of Input Tensor1, Input Tensor2, and Output Tensor are the same; if not, a general operand data exception is recognized.

[0234] In one example, the output tensor descriptor 2, input tensor descriptor 3, function-specific parameters 1-5, and function-specific save area address fields are ignored.

[0235] Function code 20: NNPA-MIN (minimum)

[0236] When the NNPA-MIN function is specified, each element of input tensor 1, described by tensor descriptor 1, is compared to the corresponding element of input tensor 2, described by tensor descriptor 2. The smaller of the two values ​​is placed in the corresponding element of the output tensor descriptor. If both values ​​are equal, that value is placed in the corresponding element of the output tensor.

[0237] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0238] In one example, the shapes, data layouts, and data types of Input Tensor1, Input Tensor2, and Output Tensor are the same; if not, a general operand data exception is recognized.

[0239] In one example, the output tensor descriptor 2, input tensor descriptor 3, function-specific parameters 1-5, and function-specific save area address fields are ignored.

[0240] Function code 21: NNPA-MAX (maximum)

[0241] When the NNPA-MAX function is specified, each element of input tensor 1, described by tensor descriptor 1, is compared to the corresponding element of input tensor 2, described by tensor descriptor 2. The larger of the two values ​​is placed in the corresponding element of the output tensor descriptor. If both values ​​are equal, that value is placed in the corresponding element of the output tensor.

[0242] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0243] In one example, the shapes, data layouts, and data types of Input Tensor1, Input Tensor2, and Output Tensor are the same; if not, a general operand data exception is recognized.

[0244] In one example, the output tensor descriptor 2, input tensor descriptor 3, function-specific parameters 1-5, and function-specific save area address fields are ignored.

[0245] Function code 32: NNPA-LOG (natural logarithm)

[0246] When the NNPA-LOG function is specified, for each element of the input tensor described by tensor descriptor 1, if that element is greater than 0, the corresponding element of the output tensor described by the output tensor descriptor is the natural logarithm of that element. Otherwise, the corresponding element of the output tensor cannot be represented numerically, and the value associated with negative infinity for the target data type is stored.

[0247] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0248] In one example, the shape, data layout, and data type of the input tensor 1 and the output tensor are the same; if they are not, a general operand data exception is recognized.

[0249] In one example, the output tensor descriptor 2, input tensor descriptor 2, input tensor descriptor 3, function-specific parameters 1-5, and function-specific save area address fields are ignored.

[0250] Function code 33: NNPA-EXP (exponent)

[0251] When the NNPA-EXP function is specified, for each element of the input tensor described by tensor descriptor 1, the corresponding element of the output tensor described by output tensor descriptor 1 is the exponent of that element.

[0252] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0253] In one example, the shape, data layout, and data type of the input tensor 1 and the output tensor are the same; if they are not, a general operand data exception is recognized.

[0254] In one example, the output tensor descriptor 2, input tensor descriptor 2, input tensor descriptor 3, function-specific parameters 1-5, and function-specific save area address fields are ignored.

[0255] Function code 49: NNPA-RELU (Rectified Linear Unit)

[0256] When an NNPA-RELU function is specified, for each element of the input tensor described by tensor descriptor 1, if the element is less than or equal to 0, the corresponding element of the output tensor described by output tensor descriptor is 0. Otherwise, the corresponding element of the output tensor is the minimum of the element of the input tensor and the clipping value specified in function-specific parameter 1.

[0257] As an example, Function Specific Parameter 1 defines the clipping value for the RELU operation. For example, the clipping value is in bits 16-31 of Function Specific Parameter 1. The clipping value is specified, for example, in NNPA-Data Type 1 format. A clipping value of 0 indicates that the maximum positive value is to be used, in other words, no clipping is performed. If a negative value is specified, a general operand data exception is recognized.

[0258] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0259] In one example, the shape, data layout, and data type of the input tensor 1 and the output tensor are the same; if they are not, a general operand data exception is recognized.

[0260] In one example, the output tensor descriptor 2, input tensor descriptor 2, input tensor descriptor 3, and function-specific save area address fields are ignored. In one example, function-specific parameters 2-5 contain zeros.

[0261] Function code 50:NNPA-TANH

[0262] When the NNPA-TANH function is specified, for each element of the input tensor described by tensor descriptor 1, the value of the corresponding element of the output tensor described by output tensor descriptor 1 is the hyperbolic tangent of that element.

[0263] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0264] In one example, the shape, data layout, and data type of the input tensor 1 and the output tensor are the same; if they are not, a general operand data exception is recognized.

[0265] In one example, the output tensor descriptor 2, input tensor descriptor 2, input tensor descriptor 3, function-specific parameters 1-5, and function-specific save area address fields are ignored.

[0266] Function code 51: NNPA-SIGMOID

[0267] When the NNPA-SIGMOID function is specified, for each element of the input tensor described by tensor descriptor 1, the corresponding element of the output tensor described by output tensor descriptor 1 is the sigmoidal version of that element.

[0268] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0269] In one example, the shape, data layout, and data type of the input tensor 1 and the output tensor are the same; if they are not, a general operand data exception is recognized.

[0270] In one example, the output tensor descriptor 2, input tensor descriptor 2, input tensor descriptor 3, function-specific parameters 1-5, and function-specific save area address fields are ignored.

[0271] Function code 52:NNPA-SOFTMAX

[0272] When the NNPA-SOFTMAX function is specified, for each vector of dimension 1 in the input tensor 1, the corresponding vector in the output tensor is calculated as described below.

[0273] * The maximum value of the vector is calculated.

[0274] * The sum of the exponents of the difference between each element of dimension 1 of the vector and the maximum calculated above is calculated. If both an element of dimension 1 of the input vector and the maximum calculated above are numeric and the difference is non-numeric, the result of the exponent for that element is forced to zero.

[0275] * For each element of the vector, an intermediate quotient is formed by dividing the exponential of the difference between that element and the maximum value calculated above by the sum calculated above. An optional activation function is applied to this intermediate quotient to form the corresponding element of the output vector.

[0276] This process is repeated for all dimension 4 index size by dimension 3 index size by dimension 2 index size vectors in dimension 1, for example.

[0277] In one example, NNPA-SOFTMAX function-specific parameter 1 controls the activation function. In one example, the ACT field (e.g., bits 28-31) of function-specific parameter 1 specifies the activation function. Examples of activation functions include:

[0278] ACT activation function

[0279] 0 No activation function is performed

[0280] 1 LOG

[0281] 2~15 spare

[0282] If a reserved value is specified in the ACT field, a response code of, for example, hexadecimal "F001" is reported, and the operation completes with a condition code of, for example, "1".

[0283] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0284] In one example, if the dimension 3 index size of the input tensor is not equal to 1, a response code of, for example, hexadecimal "F000" is stored and the instruction completes with a condition code of, for example, "1".

[0285] In one example, the shape, data layout, and data type of the input tensor 1 and the output tensor are the same; if they are not, a general operand data exception is recognized.

[0286] In one example, output tensor descriptor 2, input tensor descriptor 2, and input tensor descriptor 3 are ignored. In one example, function specific parameters 2 through 5 include zero.

[0287] An 8K byte function-specific save area may be used by this function.

[0288] In one embodiment, when retrieving a vector of dimension 1, the elements may not be contiguous in memory depending on the specified data layout format. If all elements of the input tensor1 dimension 1 vector contain negative numbers of the maximum magnitude representable in the specified data type, the results may be less accurate.

[0289] Function code 64: NNPA-BATCHNORM (batch normalization)

[0290] When the NNPA-BATCHNORM function is specified, for each vector in dimension 1 of the input 1 tensor, the corresponding vector in dimension 1 of the output tensor is calculated by multiplying each element of that vector by the corresponding element of the dimension 1 vectors that make up the input 2 tensor. The full precision product is then added to the corresponding element of the dimension 1 vectors that make up the input 3 tensor, rounded to the precision of the specified data type of the output tensor. This process is repeated for all dimension 4 index size × dimension 3 index size × dimension 2 index size vectors in dimension 1, for example.

[0291] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0292] In one example, the following conditions are true; if not, a general operand data exception is recognized:

[0293] * The input tensor1 and output tensor have the same shape and data layout.

[0294] * The data types of the input and output tensors are the same.

[0295] * The dimension 1 index size of input tensors 1, 2, 3 and the output tensor is the same.

[0296] * Dimensions 2, 3, and 4 of input tensors 2 and 3 have index size 1.

[0297] In one example, the output tensor descriptor 2 and function-specific save area address fields are ignored. In one example, function-specific parameters 2 through 5 contain zero.

[0298] Function code 80:NNPA-MAXPOOL2D Function code 81: NNPA-AVGPOOL2D

[0299] When either the NNPA-MAXPOOL2D or NNPA-AVGPOOL2D function is specified, the input tensor 1 described by the input tensor 1 descriptor is reduced by the specified operation to summarize windows of the input. The input window is selected by moving a 2D sliding window on dimension indices 2 and 3. The window summaries become elements of the output tensor. The dimension of the sliding window is described, for example, by function-specific parameters 4 and 5. The amount by which the sliding window moves over the input 1 tensor when computing adjacent output tensor elements is called the stride. The stride of the sliding window is specified, for example, by function-specific parameters 2 and 3. When the NNPA-MAXPOOL2D operation is specified, the Max operation defined below is performed on the window. When the NNPA-AVGPOOL2D operation is specified, the AVG operation defined below is performed on the window. If the specified padding type is "Valid", all elements in the window are added to the collection used to compute the output elements. If the specified padding type is "Same", depending on the position of the window, only a subset of elements from the window may be added to the collection used to compute the output elements.

[0300] In one example, the CollectElements operation adds an element to a collection of elements, incrementing the number of elements in the collection. Each time the start of the window is moved, the collection becomes empty. It is unpredictable whether elements not needed to perform the operation are accessed.

[0301] Max Operation: In one example, the maximum value of a set of elements within a window is calculated by comparing all elements in the set with each other and returning the maximum value.

[0302] Avg (average) operation: In one example, the average value of a set of elements within a window is calculated as the sum of all elements in the set divided by the number of elements in the set.

[0303] In one example, the fields are assigned as follows:

[0304] * Pooling function specific parameter 1 controls the padding type. For example, bits 29-31 of function specific parameter 1 contain a PAD field that specifies the padding type. Examples of types include, for example:

[0305] PAD padding type

[0306] 0 Valid

[0307] 1 Same

[0308] 2~7 spare

[0309] If a reserved value is specified in the PAD field, a response code of, for example, hexadecimal "F000" is reported, and the operation completes with a condition code of, for example, "1".

[0310] In one example, bit positions 0-28 of Function Specific Parameter 1 are reserved and contain zeros.

[0311] * Function-specific parameter 2 contains, for example, a 32-bit unsigned binary integer specifying the dimension-2-stride (D2S), which specifies the number of elements in dimension 2 that the sliding window moves.

[0312] * Function-specific parameter 3 contains, for example, a 32-bit unsigned binary integer that specifies the dimension 3 stride (D3S), which specifies the number of elements in dimension 3 that the sliding window moves.

[0313] * Function-specific parameter 4 includes, for example, a 32-bit unsigned binary integer specifying the dimension-2-window-size (D2WS), which specifies the number of elements in dimension 2 that the sliding window will include.

[0314] * Function specific parameters 5 includes, for example, a 32-bit unsigned binary integer that specifies the dimension 3 window size (D3WS), which specifies the number of elements in dimension 3 that the sliding window will contain.

[0315] In one example, the specified values ​​of function-specific parameters 2-5 are less than or equal to the maximum dimension index size, and the specified values ​​of function-specific parameters 4-5 are greater than zero. Otherwise, a response code of, for example, hexadecimal "0012" is reported, and the operation completes with a condition code of, for example, "1."

[0316] If the dimension 2 stride and dimension 3 stride are both 0 and either the dimension 2 window size or the dimension 3 window size is greater than, for example, 1024, a response code of, for example, hexadecimal "F001" is stored. If the dimension 2 stride and dimension 3 stride are both greater than, for example, 0 and either the dimension 2 window size or the dimension 3 window size is greater than, for example, 64, a response code of, for example, hexadecimal "F002" is stored. If the dimension 2 stride and dimension 3 stride are both greater than, for example, 0 and either the dimension 2 stride or the dimension 3 stride is greater than, for example, 30, a response code of, for example, hexadecimal "F003" is stored. If the dimension 2 stride and dimension 3 stride are both greater than, for example, 0 and either the input tensor dimension 2 index size or the input tensor dimension 3 index size is greater than, for example, 1024, a response code of, for example, hexadecimal "F004" is stored. For all of the above conditions, the instruction completes with a condition code of, for example, "1".

[0317] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0318] In one example, the following conditions are true; if not, a general operand data exception is recognized:

[0319] * The dimension 4 index size and dimension 1 index size of the input and output tensors are the same.

[0320] * The data layout and data type of the input and output tensors are the same.

[0321] * If both dimension 2 stride and dimension 3 stride are 0, then in one example the following additional condition is true:

[0322] * The input tensor dimension 2 index size is equal to the dimension 2 window size.

[0323] * The input tensor dimension 3 index size of the input tensor is equal to the dimension 3 window size.

[0324] * The dimension 2 index size and dimension 3 index size of the output tensor are 1.

[0325] * The specified padding is valid.

[0326] * If either dimension 2 stride or dimension 3 stride is non-zero, then in one example both strides are non-zero.

[0327] * If both dimension 2 stride and dimension 3 stride are greater than 0, then in one example the following additional condition is true:

[0328] * If the specified padding is valid, the dimension 2 window size is less than or equal to the dimension 2 index size of the input tensor.

[0329] * If the specified padding is valid, the dimension 3 window size is less than or equal to the dimension 3 index size of the input tensor.

[0330] * If the specified padding is Same, the following relationship is satisfied between the dimension 2 index size and dimension 3 index size of the input and output tensors (Pooling Same padding):

[0331] TIFF0007828703000008.tif10153

[0332] TIFF0007828703000009.tif10153

[0333] Here, the following is true:

[0334] IxDyIS Dimension y index size of input tensor x defined by tensor descriptor x

[0335] OxDyIS Dimension y index size of output tensor x defined by tensor descriptor x

[0336] D2S Dimension 2 Stride

[0337] D3S Dimension 3 Stride

[0338] * If the specified padding is valid, the following relationship is satisfied between the dimension 2 index size and dimension 3 index size of the input tensor and output tensor (pooling valid padding):

[0339] TIFF0007828703000010.tif10129

[0340] TIFF0007828703000011.tif12129

[0341] where D2WS is the dimension 2 window size and D3WS is the dimension 3 window size.

[0342] The output tensor descriptor 2, input tensor descriptors 2 and 3, and function-specific save area address fields are ignored.

[0343] Function Code 96: NNPA-LSTMACT (Long Short-Term Memory Activation)

[0344] When the NNPA-LSTMACT function is specified, input tensor 1, described by the Input Tensor 1 descriptor and split into four subtensors for each dimension 4 index value, becomes the input to the LSTMACT operation, along with input tensor 2, described by the Input Tensor 2 descriptor and split into four subtensors for each dimension 4 index value, and input tensor 3, described by the Input Tensor 3 descriptor. At the end of the LSTMACT operation, the results are written to output tensor 1, described by the Output Tensor 1 descriptor, and output tensor 2, described by the Output Tensor 2 descriptor.

[0345] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code of hexadecimal "0010" or hexadecimal "0011", respectively, is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0346] In one embodiment, the following conditions are true; if not, a general operand data exception is recognized:

[0347] * Dimension 4 index size of input tensor 3 and output tensors 1, 2 is equal to 1 for example.

[0348] * Dimension 4 index size of input tensor1 and input tensor2 is equal to 4 for example.

[0349] * For example, all input tensors and two output tensors have dimension 3 index size equal to, say, 1.

[0350] * For example, all input tensors and the two output tensors have the same data layout and data type.

[0351] * For example, all input tensors and the two output tensors have the same dimension 1 index size.

[0352] * For example, all input tensors and the two output tensors have the same dimension 2 index size.

[0353] In one example, the function specific save area address field is ignored. Function specific parameters 1-5 include 0 in one example.

[0354] Function Code 97: NNPA-GRUACT (Gated Recurrent Unit Activation)

[0355] When the NNPA-GRUACT function is specified, input tensor 1, described by the input tensor 1 descriptor and split into three subtensors for each dimension 4 index value, becomes the input to the GRUACT operation, along with input tensor 2, described by the input tensor 2 descriptor and split into three subtensors for each dimension 4 index value, and input tensor 3, described by the input tensor 3 descriptor. At the end of the GRUACT operation, the output tensor, described by the output tensor descriptor, is recorded.

[0356] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0357] In one embodiment, the following conditions are true; if not, a general operand data exception is recognized:

[0358] * Dimension 4 index size of output tensor and input tensor 3 equals to 1 for example.

[0359] * For example, input tensor 1 and input tensor 2 have dimension 4 index size equal to say 3.

[0360] * For example, dimension 3 index size of all input tensors and output tensors is equal to, say, 1.

[0361] * For example, all input and output tensors have the same dimension 1 index size.

[0362] * For example, all input and output tensors have the same dimension 2 index size.

[0363] * For example, all input and output tensors have the same data layout and data type.

[0364] In one example, the output tensor descriptor 2 and function specific save area address fields are ignored. Function specific parameters 2-5 contain 0 in one example.

[0365] Function code 112:NNPA-CONVOLUTION

[0366] When the NNPA-CONVOLUTION function is specified, for each output element of the output tensor described by the output tensor1 descriptor, a 3-dimensional input 1 window consisting of dimension indices 3, 2, and 1 is selected from input tensor 1 described by the input tensor1 descriptor. An equally sized 3-dimensional input 2 window consisting of dimension indices 4, 3, and 2 is selected from tensor 2 described by the input tensor2 descriptor. Elements of the input 1 window are multiplied with the corresponding elements of the input 2 window, and all products are added together to create an initial sum. This initial sum is added to the corresponding element of input tensor 3 to compute the value of the intermediate sum. The elements of the output tensor are the result of running the specified activation function on the intermediate sum. If no activation function is specified, the output elements are equal to the intermediate sum.

[0367] If the specified padding type is Valid, all elements of the window are used to calculate the initial sum. If the specified padding type is Same, depending on the position of the window, some elements of the input 1 window may be implicitly 0 when calculating the initial sum.

[0368] It is unpredictable whether elements not necessary to perform the operation will be accessed.

[0369] In one example, the fields of the function-specific parameters used by the convolution function are assigned as follows:

[0370] * NNPA-CONVOLUTION function-specific parameter 1 controls the padding type and activation function. In one example, bits 29-31 of function-specific parameter 1 contain a PAD field that specifies the padding type. Example types are shown below:

[0371] PAD padding type

[0372] 0 Valid

[0373] 1 Same

[0374] 2~7 spare

[0375] If a reserved value is specified in the PAD field, a response code of, for example, hex "F000" is reported, and the operation completes with a condition code of, for example, "1".

[0376] Additionally, in one example, bits 24-27 of NNPA-CONVOLUTION function specific parameter 1 include an activation field that specifies an activation function. An example function is shown below:

[0377] ACT activation function

[0378] 0 No activation function is performed

[0379] 1 RELU

[0380] 2~15 spare

[0381] When a RELU activation function is specified, the output element value is determined as follows: If the value of the intermediate sum is less than or equal to 0, the corresponding element of the output tensor is set to 0. Otherwise, the corresponding element of the output tensor is set to the minimum of the intermediate sum value and the clipping value specified by function-specific parameter 4.

[0382] If a reserved value is specified in the ACT field, a response code of, for example, hex "F001" is reported, and the operation completes with a condition code of, for example, "1".

[0383] * Function specific parameters 2 includes, for example, a 32-bit unsigned binary integer that specifies the dimension 2 stride (D2S), which specifies the number of elements in dimension 2 that the sliding window moves.

[0384] * Function-specific parameter 3 contains, for example, a 32-bit unsigned binary integer that specifies the dimension 3 stride (D3S), which specifies the number of elements in dimension 3 that the sliding window moves.

[0385] The specified values ​​of function-specific parameters 2-3 are less than the maximum dimension index size. If not, a response code, e.g., hex "0012", is reported and the operation completes with a condition code, e.g., "1".

[0386] * Function specific parameter 4 defines the clipping value for any RELU operation. In one example, the clipping value is in bits 16-31 of function specific parameter 4.

[0387] In one example, if the ACT field is 0, the clipping value field is ignored. If the ACT field specifies RELU, the clipping value is specified in NNP-Data Type 1 format. A clipping value of 0 indicates that the maximum positive value is to be used, in other words, no clipping is performed. If a non-zero value is specified, a general operand data exception is recognized.

[0388] In one example, if the specified data layout of any of the specified tensor descriptors except input tensor 2 does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the specified data layout of input tensor 2 does not specify a 4-dimensional kernel tensor (e.g., data layout = 1), a response code of, for example, hexadecimal "0010" is set in general register 0 and the instruction completes with, for example, a condition code of "1". In one example, if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code of, for example, hexadecimal "0011" is set in general register 0 and the instruction completes with, for example, a condition code of "1".

[0389] If the dimension 2 stride and dimension 3 stride are both 0 and the dimension 3 index size or dimension 4 index size of input tensor 2 is greater than, for example, 448, a response code of, for example, hexadecimal "F002" is stored. If the dimension 2 stride and dimension 3 stride are both greater than 0 and either the dimension 3 index size or dimension 4 index size of input tensor 2 is greater than, for example, 64, a response code of, for example, hexadecimal "F003" is stored and the operation completes with, for example, a condition code of "1". If either the dimension 2 stride or dimension 3 stride is greater than, for example, 13, a response code of, for example, hexadecimal "F004" is stored and the operation completes with, for example, a condition code of "1".

[0390] In one example, the following conditions are true; if not, a general operand data exception is recognized:

[0391] * The data layout of input tensor 1, input tensor 3, and output tensor is the same.

[0392] * All input and output tensors have the same data type.

[0393] * The index size of dimension 2, dimension 3, and dimension 4 of the input 3 tensor is 1.

[0394] * The dimension 4 index size of the output tensor is equal to the dimension 4 index size of the input 1 tensor.

[0395] * The dimension 1 index size of the output tensor is equal to the dimension 1 index size of the input 2 tensor and the dimension 1 index size of the input 3 tensor.

[0396] * The dimension 1 index size of the input 1 tensor is equal to the dimension 2 index size of the input 2 tensor.

[0397] * If both dimension 2 stride and dimension 3 stride are 0, then in one example the following additional condition is true:

[0398] * The dimension 2 index size of the input 1 tensor is equal to the dimension 3 index size of the input 2 tensor.

[0399] * The dimension 3 index size of the input 1 tensor is equal to the dimension 4 index size of the input 2 tensor.

[0400] * The dimension 2 index size and dimension 3 index size of the output tensor is 1.

[0401] * The specified padding is valid.

[0402] * If either dimension 2 stride or dimension 3 stride is non-zero, then both strides are non-zero.

[0403] * If both dimension 2 stride and dimension 3 stride are greater than 0, then in one example the following additional condition is true:

[0404] * If the specified padding is valid, the dimension 2 index size of input tensor 1 is greater than or equal to the dimension 3 index size of input tensor 2.

[0405] * If the specified padding is valid, the dimension 3 index size of the input 1 tensor is greater than or equal to the dimension 4 index size of the input 2 tensor.

[0406] * If the specified padding is Same, in one example, the following relationship is satisfied between the dimension 2 index size and dimension 3 index size of the input 1 tensor and output tensor (Convolution Same padding):

[0407] TIFF0007828703000012.tif12128

[0408] TIFF0007828703000013.tif12128

[0409] Here, the following is true:

[0410] O1D2IS Dimension 2 index size of the output tensor

[0411] O1D3IS Dimension 3 index size of the output tensor

[0412] I1D2IS Dimension 2 index size of input 1 tensor

[0413] I1D3IS Dimension 3 index size of input 1 tensor

[0414] D2S Dimension 2 Stride

[0415] D3S Dimension 3 Stride

[0416] * If the specified padding is valid, in one example, the following relationship is satisfied between the dimension 2 index size and dimension 3 index size of the input 1 tensor, the dimension 3 index size and dimension 4 index size of the input 2 tensor, and the output tensor (convolution valid padding):

[0417] TIFF0007828703000014.tif12128

[0418] TIFF0007828703000015.tif12128

[0419] Here, the following is true:

[0420] O1D2IS Dimension 2 index size of the output tensor

[0421] O1D3IS Dimension 3 index size of the output tensor

[0422] I1D2IS Dimension 2 index size of input 1 tensor

[0423] I1D3IS Dimension 3 index size of input 1 tensor

[0424] I2D3IS Dimension 3 index size of input 2 tensor

[0425] I2D4IS Input 2 tensor dimension 4 index size

[0426] D2S Dimension 2 Stride

[0427] D3S Dimension 3 Stride

[0428] In one example, the output tensor descriptor 2 and function specific save area address fields are ignored. Function specific parameters 5 contains 0 in one example.

[0429] Function code 113: NNPA-MATMUL-OP (Matrix Multiplication Operation)

[0430] When the NNPA-MATMUL function is specified, each element of the output tensor described by the output tensor descriptor is calculated as described below in one example.

[0431] * A dimension-1 vector is selected from input tensor 1 described by the input tensor 1 descriptor using the get-dimension-1-vector operation described below.

[0432] * A dimension-2 vector is selected from the input tensor 2 described by the input tensor 2 descriptor using the get-dimension-2-vector operation described below.

[0433] * The intermediate dot product of a dimension 1 vector and a dimension 2 vector is calculated using the dot product operation described below.

[0434] * An operation is performed on the intermediate dot product and elements of input tensor 3 that have the same values ​​of dimension index 4 and dimension index 1 as the output tensor elements, as described by the input tensor 3 descriptor. The resulting elements are stored in the output tensor. The fused operation is determined by function-specific parameter 1 and is described below.

[0435] Get Dimension 1 Vector Operation: For a specified output element, a dimension 1 vector is selected from the input 1 tensor, where the input dimension 4 index is the output dimension 4 index, the input dimension 3 index is the output dimension 3 index, and the input dimension 2 index is the output dimension 2 index.

[0436] Get dimension 2 vector operation: For a specified output element, a dimension 2 vector is selected from an input 2 tensor, where the input dimension 4 index is the output dimension 4 index, the input dimension 3 index is the output dimension 3 index, and the input dimension 1 index is the output dimension 1 index.

[0437] Dot Product Operation: The intermediate dot product of two vectors of the same size and data type is calculated as the sum of the products of each element of Input Vector 1 with the corresponding element of Input Vector 2.

[0438] Fusion Operation: Function-specific parameters 1 control the operation performed on the intermediate dot products and the corresponding elements from input tensor 3. In one example, NNPA-MATMUL-OP function-specific parameters 1 includes an operation field, e.g., in bits 24-31. The operation field specifies the operation to be performed. Example operations are shown below:

[0439] Operation Operation Type

[0440] Add 0

[0441] 1 Compare the dot product to see if it is higher

[0442] 2 Compare whether the dot product is low

[0443] 3 Dot product and element equality comparison

[0444] 4 Dot product and element inequality comparison

[0445] 5. Compare whether the dot product is high or not

[0446] 6. Compare the dot product to see if it is lower

[0447] In one example, for an addition operation type, the input tensor triplet is added to the intermediate dot product. For a comparison operation type, the intermediate dot product is compared to the input tensor triplet, and if the comparison is true, the result is set to a value, e.g., +1; otherwise, the result is set to a value, e.g., +0, in the data type specified for the output tensor.

[0448] In one example, all other values ​​in the OPERATION field are reserved. If a reserved value is specified in the OPERATION field, a response code of, for example, hex "F000" is reported, and the operation completes with a condition code of, for example, "1."

[0449] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0450] In one embodiment, the following conditions are true; if not, a general operand data exception is recognized:

[0451] * All input and output tensors have the same dimension 4 index size.

[0452] * All input and output tensors have dimension 3 index size equal to 1.

[0453] * The dimension 2 index size of input tensor 3 is equal to 1.

[0454] * The dimension 2 index size of input tensor 1 and output tensor is the same.

[0455] * The dimension 1 index size of input tensor 1 and the dimension 2 index size of input tensor 2 are the same.

[0456] * The dimension 1 index size of input tensor 2, input tensor 3, and output tensor is the same.

[0457] * All input and output tensors have the same data layout and data type.

[0458] In one embodiment, the output tensor descriptor 2 and function-specific save area address fields are ignored. Function-specific parameters 2-5 include 0 in one example.

[0459] Function code 114: NNPA-MATMUL-OP-BCAST23 (Matrix multiplication operation - broadcast 23)

[0460] When the NNPA-MATMUL-OP-BCAST23 function is specified, each element of the output tensor described by the output tensor descriptor is calculated as described below, by way of example.

[0461] * A dimension 1 vector is selected from the input tensor 1 described by the input tensor 1 descriptor using the get dimension 1 vector operation described below.

[0462] * A dimension 2 vector is selected from the input tensor 2 described by the input tensor 2 descriptor using the get dimension 2 vector operation described below.

[0463] * The dot product of a dimension 1 vector and a dimension 2 vector is calculated using the dot product operation described below.

[0464] * Elements of input tensor 3 that have the same value of dimension index 1 as the output tensor element described by the input tensor 3 descriptor are added to the previously computed dot product and stored in the output tensor.

[0465] Get Dimension 1 Vector Operation: For a specified output element, a dimension 1 vector is selected from the input 1 tensor, where the input dimension 4 index is the output dimension 4 index, the input dimension 3 index is the output dimension 3 index, and the input dimension 2 index is the output dimension 2 index.

[0466] Get dimension 2 vector operation: For a specified output element, a dimension 2 vector is selected from an input 2 tensor, where the input dimension 4 index is 1, the input dimension 3 index is the output dimension 3 index, and the input dimension 1 index is the output dimension 1 index.

[0467] Dot Product Operation: The intermediate product of two vectors of the same size and data type is calculated as the sum of the products of each element of Input Vector 1 with the corresponding element of Input Vector 2.

[0468] In one example, if the specified data layout of any of the specified tensor descriptors does not specify a 4-dimensional feature tensor (e.g., data layout = 0), or if the data type of the specified tensor descriptor does not specify NNP-data type 1 (e.g., data type = 0), a response code (e.g., hex "0010" or hex "0011", respectively) is set in general register 0, and the instruction completes with a condition code of, for example, "1".

[0469] In one embodiment, the following conditions are true; if not, a general operand data exception is recognized:

[0470] * The dimension 4 index size of input tensor 1 and output tensor is the same.

[0471] * Dimension 4 index size of input tensor 2 and input tensor 3 is equal to 1.

[0472] * All input and output tensors have dimension 3 index size equal to 1.

[0473] * The dimension 2 index size of input tensor 3 is equal to 1.

[0474] * The dimension 2 index size of input tensor 1 and output tensor is the same.

[0475] * The dimension 1 index size of input tensor 1 and the dimension 2 index size of input tensor 2 are the same.

[0476] * The dimension 1 index size of input tensor 2, input tensor 3, and output tensor is the same.

[0477] * All input and output tensors have the same data layout and data type.

[0478] In one embodiment, the output tensor descriptor 2 and function specific save area address fields are ignored. Function specific parameters 1-5 include 0 in one example.

[0479] For neural network processing assist instructions, in one embodiment, if the output tensor overlaps with any of the input tensors or parameter blocks, the results are unpredictable.

[0480] As an example, a specification exception is recognized when an attempt is made to execute a neural network processing assist instruction and the parameter block is not specified, for example, on a double word boundary.

[0481] A general operand data exception is recognized when a neural network processing assist instruction is attempted to be executed and there is, for example, a tensor descriptor mismatch.

[0482] Condition code results for neural network processing assist instructions include, for example: 0: successful completion, 1: response code is set, 2: -, 3: CPU determined amount of data processed.

[0483] In one embodiment, the execution priority for neural network processing assist instructions includes, for example:

[0484] 1. to 7. Exceptions with the same priority as the general case program interrupt condition

[0485] 8.A Condition code 1 due to an unassigned or uninstalled function code being specified

[0486] 8.B Parameter Block Not Aligned on Doubleword Boundary Exception

[0487] 9. Access exception for parameter block access

[0488] 10. Condition code 1 due to the specified format of the parameter block not being supported by the model

[0489] 11.A Condition code 1 due to the specified tensor data layout being unsupported

[0490] 11.B General operand data exception due to different data layout between tensor descriptors.

[0491] 12.A Condition Code 1 for conditions other than those included in 8.A, 10, 11.A above and 12.B.1 below

[0492] 12.B.1 Condition Code 1 due to invalid data type of output tensor of NNPA-RELU and NNPA-CONVOLUTION

[0493] 12.B.2 General Operand Data Exception for Invalid Values ​​of NNPA-RELU Function Specific Parameter 1 and NNPA-CONVOLUTION Function Specific Parameter 4

[0494] 13.A Access Exception for Accessing Output Tensors

[0495] 13.B Access Exception for Accessing Input Tensors

[0496] 13.C Access exception when accessing function-specific save area

[0497] 14. Condition Code 0

[0498] As described herein, a single instruction (e.g., a neural network processing assist instruction) is configured to perform multiple functions, including a query function. The query function provides information useful to an application in executing one or more functions (e.g., functions related to tensor computation) in accordance with one or more aspects of the present invention. This information conveys not only the functions supported by the instruction and / or processor, but also additional information about how the instruction and / or processor operates, such as information related to the data used by the instruction and / or processor. By way of example, this information includes model-dependent data attributes, such as data types installed on the processor and available data layout formats supported by the processor, as well as data size information, such as maximum tensor size and maximum dimension index size. The query function allows an application to determine whether it is designed to operate with the attributes of the particular model on which the non-query function is being executed. Alternatively, an application can be written to dynamically change its behavior to operate on different models depending on the exact attributes of the model determined by the query instruction. If an application does not know how to handle a particular model, it may be able to perform neural network computations in software instead of using an accelerator function.

[0499] Query functions are useful for a variety of tasks, including, for example, live migration of virtual machines, which allows applications to optimize their behavior for the model they run in. Query functions can also be used for many other tasks.

[0500] While the query function is provided as part of the neural network processing assist instructions as an example, the query function may be used with other instructions to provide detailed information about the capabilities, operations, and / or attributes of the processor, or operations associated with the processor, or a combination thereof. The neural network processing assist instructions are only an example.

[0501] One or more aspects of the present invention are closely tied to computer technology and facilitate processing within a computer and improve its performance. The use of a single architected machine instruction configured to perform various functions, including query functions, improves performance within a computing environment by reducing complexity, reducing resource usage, and increasing processing speed. Processing is improved by using query functions to obtain detailed information describing model-dependent attributes of a processor, including data attributes. As an example, performance is improved by determining what a processor supports before non-query functions are executed. Because applications know in advance what will happen, not only execution time but also the complexity of application processing is reduced. Data and / or instructions can be used in many technical fields, such as computer processing, medical processing, engineering, automotive technology, and manufacturing. Achieving optimizations in obtaining model-dependent processor-related data improves these technical fields by reducing execution time.

[0502] Further details of one embodiment that facilitates processing within a computing environment in accordance with one or more aspects of the present invention are described with reference to FIGS. 7A-7B.

[0503] 7A, in one embodiment, instructions for performing a query function are executed 700. Execution may include, for example, obtaining information related to a selected model of a processor 702. As an example, the information may include at least one model-dependent data attribute of the selected model of the processor 704. The information may be placed 706 in a selected location for use by at least one application in performing one or more functions.

[0504] The query function adapts the machine to the features present in a particular model of the machine, providing information that makes it easier to solve problems involving larger data sets, thereby improving techniques using machine learning that involve computation.

[0505] Executing the query function obtains model-dependent information for at least one data attribute, which can be used when executing one or more functions using data having the at least one data attribute. Knowing the at least one data attribute can save execution time by preparing an application for the at least one data attribute, which can then adapt the application to the data, data layout, and / or data size, for example, to perform neural network processing on that particular model. Preparing the application reduces errors, saves execution time, and improves system performance.

[0506] The query function provides improvements in the use of tensors and / or processing using such tensors when at least one data attribute is associated with a tensor and / or when processing uses such tensors.

[0507] As an example, the at least one model-dependent data attribute includes one or more supported data types (710) for the selected model of processor, one or more supported data layout formats (712) for the selected model of processor, or one or more supported data sizes (714) for the selected model of processor, or a combination thereof. By obtaining the supported data types, data layout formats, or data sizes, or a combination thereof, the application is tailored to the data types, data layout formats, or data sizes supported by the particular model of processor. This allows the application to adapt to the data, data layout, or data sizes, or a combination thereof, for example, to perform neural network processing on that particular model. Preparing the application reduces errors, saves execution time, and improves system performance.

[0508] In one example, the selected location includes a parameter block accessible to at least one application (720). For example, one or more supported data types are included in one or more fields of the parameter block (722), or one or more supported data layout formats are included in one or more fields of the parameter block (724), or one or more supported data sizes are included in one or more fields of the parameter block (726), or any combination thereof. By having the parameter block accessible to at least one application, the application can learn one or more supported data types, one or more supported data layout formats, or one or more data sizes, or any combination thereof, and use this knowledge in its processing. This allows the application to adapt to the data, data layout, or data size, or any combination thereof, for example, to perform neural network processing on that particular model. Preparing the application reduces errors, saves execution time, and improves system performance.

[0509] Referring to FIG. 7B, in one example, one or more supported data sizes for the selected model of the processor include a maximum dimension index size and a maximum tensor size (730).

[0510] In one example, the parameter block includes a plurality of fields for storing a plurality of model-dependent data attributes of the selected model (740), including, for example, an installed data type field for containing one or more supported data types of the selected model of the processor, an installed data layout format field for containing one or more supported data layout formats of the selected model of the processor, and one or more fields for containing one or more supported data sizes of the selected model of the processor (742).

[0511] The parameter block further includes, for example, at least one of an installed function vector field and an installed parameter block format field (750). The installed function vector field, for example, indicates one or more supported functions of the selected model of the processor (752). Further, in one example, the installed parameter block format field indicates one or more supported formats of the parameter block (754).

[0512] By using the query function to determine model-dependent attributes of the processor on which a selected function will run, the complexity of the application can be reduced by having the appropriate information and / or the application can be tuned to use the correct attributes (e.g., data type, data layout format, and / or data size). The function will run faster, reducing execution time and improving the performance of the processor and / or the overall system.

[0513] Other variations and embodiments are possible.

[0514] Aspects of the present invention can be used in many types of computing environments. Another example of a computing environment incorporating and using one or more aspects of the present invention is described with reference to FIG. 8A. By way of example, the computing environment of FIG. 8A is based on the z / Architecture® instruction set architecture manufactured by International Business Machines Corporation (Armonk, New York). However, the z / Architecture instruction set architecture is only one example of an architecture. Again, the computing environment may be based on other architectures, including, but not limited to, the Intel® x86 architecture, other International Business Machines Corporation architectures, or architectures of other companies, or combinations thereof. Intel is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0515] As an example, computing environment 10 includes a central electronics complex (CEC) 11. Central electronics complex 11 includes multiple components, including, for example, one or more processors, such as one or more general-purpose processors (also known as central processing units (CPUs) 13) and one or more special-purpose processors (e.g., neural network processor 31), and memory 12 (also known as system memory, main memory, main storage, central storage, storage) coupled to an input / output (I / O) subsystem 14.

[0516] By way of example, one or more special purpose processors may be separate from one or more general purpose processors, at least one special purpose processor may be integrated within at least one general purpose processor, or both. Other variations are possible.

[0517] I / O subsystem 14 may be part of or separate from the central electronic processing unit. I / O subsystem 14 directs the flow of information between main storage 12 and input / output control unit 15 and input / output (I / O) devices 16 coupled to the central electronic processing unit.

[0518] Many types of I / O devices can be used. One particular type is a data storage device 17. The data storage device 17 can store one or more programs 18, one or more computer readable program instructions 19, or data, or a combination thereof. The computer readable program instructions can be configured to perform the functions of embodiments according to aspects of the present invention.

[0519] Central electronic processing unit 11 may include and / or be coupled to removable / non-removable, volatile / non-volatile computer system storage media. For example, central electronic processing unit 11 may include and / or be coupled to non-removable, non-volatile magnetic media (commonly referred to as "hard disks"), magnetic disk drives for reading from and writing to removable, non-volatile magnetic disks (e.g., "floppy disks"), and / or optical disk drives for reading from and writing to removable, non-volatile optical disks, such as CD-ROMs, DVD-ROMs, and other optical media. Note that other hardware and / or software components may be used in combination with central electronic processing unit 11. Examples of these components include, but are not limited to, microcode or millicode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0520] Additionally, central electronic processing unit 11 is operational with numerous other general purpose or special purpose computing system environments or configurations. Examples of well-known computing systems, environments, or configurations, or combinations thereof, suitable for use with central electronic processing unit 11 include, but are not limited to, personal computer (PC) systems, server computer systems, thin clients, thick clients, handheld or laptop devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments that include any of these systems or devices.

[0521] In one or more embodiments, central electronic processing unit 11 provides logical partitioning and / or virtualization support. In one embodiment, as shown in FIG. 8B, memory 12 includes, for example, one or more logical partitions 20, a hypervisor 21 that manages the logical partitions, and processor firmware 22. One example of a hypervisor 21 is the Processor Resource / System Manager (PR / SM) manufactured by International Business Machines Corporation (Armonk, NY). TM ) and PR / SM are trademarks or registered trademarks of International Business Machines Corporation in at least one jurisdiction.

[0522] Each logical partition 20 can function as a separate system. That is, each logical partition can be reset independently, run a guest operating system 23 (such as the z / OS® operating system manufactured by International Business Machines Corporation, Armonk, New York), or other control code 24 (such as coupling facility control code (CFCC)), and operate with different programs 25. An operating system or application program running within a logical partition appears to have access to the entire, complete system, but in fact only a portion of it is available. Note that while the z / OS operating system is illustrated, other operating systems provided by International Business Machines Corporation and / or other companies may also be used in accordance with one or more aspects of the present invention.

[0523] Memory 12 is coupled to, for example, CPU 13 (FIG. 8A). CPU 13 is a physical processor resource that can be assigned to a logical partition. For example, logical partition 20 may include one or more logical processors, each of which represents all or a portion of physical processor resource 13 that can be dynamically assigned to a logical partition.

[0524] In a further embodiment, the central electronic processing unit provides virtual machine support (either with or without logical partitioning support). As shown in FIG. 8C, memory 12 of central electronic processing unit 11 includes, for example, one or more virtual machines 26, a virtual machine manager, such as hypervisor 27, that manages the virtual machines, and processor firmware 28. An example of hypervisor 27 is the z / VM® hypervisor manufactured by International Business Machines Corporation (Armonk, New York). A hypervisor is sometimes referred to as a host. Note that z / VM is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction.

[0525] The central electronic processing unit's virtual machine support provides the ability to operate multiple virtual machines 26, each capable of running a different program 29 and a guest operating system 30, such as the Linux operating system. Each virtual machine 26 can function as a separate system; that is, each virtual machine can be reset independently, run a guest operating system, and operate with different programs. An operating system or application program running within a virtual machine appears to have access to the entire, complete system, but in fact only a portion of it is available. While z / VM and Linux are illustrated, other virtual machine managers and / or operating systems may be used in accordance with one or more aspects of the present invention. The registered trademark Linux is used pursuant to a sublicense from the Linux Foundation, the exclusive licensee of Linus Torvalds, the owner of such trademarks worldwide.

[0526] Another embodiment of a computing environment incorporating and using one or more aspects of the present invention is described with reference to FIG. 9A. In this example, computing environment 36 includes, for example, a native central processing unit (CPU) 37, memory 38, and one or more input / output devices 39 and / or input / output interfaces 39 coupled to one another, for example, via one or more buses 40 and / or other connections. By way of example, computing environment 36 may include a PowerPC® processor manufactured by International Business Machines Corporation (Armonk, New York), an HP Superdome with an Intel® Itanium® II processor manufactured by Hewlett-Packard Company (Palo Alto, California), or other machines based on architectures offered by International Business Machines Corporation, Hewlett-Packard, Intel Corporation, Oracle, or other companies, or combinations thereof. Note that PowerPC is a trademark or registered trademark of International Business Machines Corporation in at least one jurisdiction. Itanium is a trademark or registered trademark of Intel Corporation or its subsidiaries in the United States and other countries.

[0527] The native central processing unit 37 includes one or more native registers 41, such as one or more general purpose registers and / or one or more special purpose registers that are used during processing within the environment. These registers contain information that represents the state of the environment at any particular time.

[0528] Additionally, native central processing unit 37 executes instructions and code stored in memory 38. In one specific example, central processing unit executes emulator code 42 stored in memory 38. This code allows a computing environment configured with one architecture to emulate another architecture. For example, emulator code 42 allows machines based on architectures other than the z / Architecture instruction set architecture (e.g., PowerPC processors, HP Superdome servers, etc.) to emulate the z / Architecture instruction set architecture and execute software and instructions developed based on the z / Architecture instruction set architecture.

[0529] Further details related to emulator code 42 are described with reference to FIG. 9B . Guest instructions 43 stored in memory 38 include software instructions (e.g., correlated with machine instructions) developed to execute on an architecture other than that of native CPU 37. For example, guest instructions 43 may have been designed to execute on a processor based on the z / Architecture instruction set architecture, but instead are emulated on native CPU 37 (which may be, for example, an Intel Itanium II processor). As an example, emulator code 42 includes an instruction fetching routine 44 for retrieving one or more guest instructions 43 from memory 38 and providing a local buffer for the retrieved instructions, if necessary. Emulator code 42 also includes an instruction translation routine 45 for determining the type of the retrieved guest instruction and converting the guest instruction into one or more corresponding native instructions 46. This conversion may include, for example, identifying a function performed by the guest instruction and selecting a native instruction to perform the function.

[0530] Additionally, emulator code 42 includes an emulation control routine 47 for causing the execution of native instructions. Emulation control routine 47 may cause native CPU 37 to execute a routine of native instructions that emulates one or more previously fetched guest instructions, and upon completion of such execution, return control to an instruction fetch routine to emulate the fetch of the next guest instruction or group of guest instructions. Execution of native instructions 46 may include loading data from memory 38 into registers, storing data from registers back to memory, or performing some type of arithmetic or logical operation as determined by a translation routine.

[0531] Each routine is implemented, for example, in software stored in memory and executed by native central processing unit 37. In other examples, one or more of the routines or operations are implemented in firmware, hardware, software, or a combination thereof. The emulated processor's registers may be emulated using the native CPU's registers 41 or may be emulated using locations in memory 38. In an embodiment, guest instructions 43, native instructions 46, and emulator code 42 may reside in the same memory or may be distributed among different memory devices.

[0532] The emulatable instructions include the neural network assisted processing instructions described herein, in accordance with one or more aspects of the present invention. Additionally, other instructions and / or the query function itself may be emulated, in accordance with one or more aspects of the present invention.

[0533] The computing environments described above are merely examples of computing environments that may be used. Other environments (including, but not limited to, non-partitioned, partitioned, cloud, or emulated environments, or combinations thereof) may also be used, and embodiments are not limited to any one environment. Although various examples of computing environments are described herein, one or more aspects of the present invention may be used with many types of environments. The computing environments provided herein are merely examples.

[0534] Each computing environment can be configured to include one or more aspects of the present invention.

[0535] One or more aspects may relate to cloud computing.

[0536] Although this disclosure includes detailed descriptions of cloud computing, it should be understood that implementation of the teachings described herein is not limited to cloud computing environments. Rather, embodiments of the present invention may be practiced in conjunction with any other type of computing environment now known or later developed.

[0537] Cloud computing is a service delivery model for enabling convenient, on-demand network access to a shared pool of configurable computing resources (e.g., networks, network bandwidth, servers, processing, memory, storage, applications, virtual machines, and services) that can be rapidly provisioned and released with minimal management effort or interaction with a service provider. This cloud model includes at least five characteristics, at least three service models, and at least four deployment models.

[0538] The characteristics are as follows:

[0539] On-Demand Self-Service: Cloud consumers can unilaterally provision computing capacity, such as server time or network storage, automatically as needed, without the need for human interaction with the service provider.

[0540] Broad network access: Computing power is available over the network and can be accessed through standard mechanisms, facilitating use by heterogeneous thin or thick client platforms (e.g., cell phones, laptops, PDAs).

[0541] Resource Pooling: Computing resources from a provider are pooled and offered to multiple consumers using a multi-tenant model. Various physical and virtual resources are dynamically allocated and reallocated based on demand. Consumers generally have no control or knowledge of the exact location of the resources they are provided with, resulting in a sense of location independence. However, consumers may be able to determine location at a higher level of abstraction (e.g., country, state, data center).

[0542] Rapid Elasticity: Computing capacity can be provisioned quickly and elastically, sometimes automatically, to instantly scale out and quickly release to instantly scale in. To the consumer, the computing power available for provisioning often appears unlimited, and can be purchased at any time and in any quantity.

[0543] Service Metering: Cloud systems leverage metering capabilities at a level of abstraction appropriate to the type of service (e.g., storage, processing, bandwidth, active user accounts) to automatically control and optimize resource usage. Resource usage can be monitored, controlled, and reported to provide transparency to both providers and consumers of utilized services.

[0544] The service model is as follows:

[0545] Software as a Service (SaaS): The functionality offered to the consumer is the availability of a provider's applications running on a cloud infrastructure that can be accessed from a variety of client devices through a thin client interface such as a web browser (e.g., webmail). The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, storage, or even individual application functionality, except for limited user-specific application configuration settings.

[0546] Platform as a Service (PaaS): The capability offered to consumers is to deploy applications they create or acquire using programming languages ​​and tools supported by the provider onto a cloud infrastructure. The consumer does not manage or control the underlying cloud infrastructure, including the network, servers, operating systems, or storage, but does have control over the deployed applications and, in some cases, the configuration of their hosting environment.

[0547] Infrastructure as a Service (IaaS): The functionality offered to consumers is the provisioning of processors, storage, networking, and other basic computing resources on which they can deploy and run any software, including operating systems and applications. The consumer does not manage or control the underlying cloud infrastructure, but has control over the operating system, storage, and deployed applications, and in some cases partial control over some network components (e.g., host firewalls).

[0548] The deployment model is as follows:

[0549] Private Cloud: This cloud infrastructure is dedicated to a specific organization and can be managed by that organization or a third party, and can exist on-premise or off-premise.

[0550] Community Cloud: This cloud infrastructure is shared by multiple organizations to support a specific community with common concerns (e.g., mission, security requirements, policies, and compliance). This cloud infrastructure can be managed by those organizations or a third party and can exist on-premises or off-premises.

[0551] Public cloud: This cloud infrastructure is available to the general public or large industry organizations and is owned by an organization that sells cloud services.

[0552] Hybrid cloud: This cloud infrastructure combines two or more cloud models (private, community, or public), each of which retains its inherent nuances but is bound by standards or specific technologies that enable data and application portability (e.g., cloud bursting for load balancing between clouds).

[0553] A cloud computing environment is a service-oriented environment that emphasizes statelessness, low coupling, modularity, and semantic interoperability. At the core of cloud computing is an infrastructure that includes a network of interconnected nodes.

[0554] FIG. 10 illustrates an exemplary cloud computing environment 50. As illustrated, the cloud computing environment 50 includes one or more cloud computing nodes 52, with which local computing devices used by cloud consumers (e.g., PDAs or cell phones 54A, desktop computers 54B, laptop computers 54C, or automobile computer systems 54N, or combinations thereof) can communicate. The nodes 52 can communicate with each other. The nodes 52 can be physically or virtually grouped (not shown) in one or more networks, such as the private, community, public, or hybrid clouds described above, or combinations thereof. This enables the cloud computing environment 50 to provide infrastructure, platform, or software as a service, or combinations thereof, for which cloud consumers are not required to maintain resources on their local computing devices. It should be understood that the types of computing devices 54A-N illustrated in FIG. 10 are merely exemplary, and that the computing nodes 52 and the cloud computing environment 50 can communicate with any type of electronic device via any type of network or network-addressable connection (e.g., using a web browser), or both.

[0555] A set of functional abstraction layers provided by the cloud computing environment 50 (FIG. 10) is shown in FIG. 11. It should be understood in advance that the components, layers, and functions shown in FIG. 11 are merely exemplary, and embodiments of the present invention are not limited thereto. As shown, the following layers and corresponding functions are provided:

[0556] Hardware and software layer 60 includes hardware and software components. Examples of hardware components include mainframe 61, reduced instruction set computer (RISC) architecture-based server 62, server 63, blade server 64, storage device 65, and network and network components 66. In some embodiments, software components include network application server software 67 and database software 68.

[0557] The virtualization layer 70 provides an abstraction layer from which virtual entities such as virtual servers 71, virtual storage 72, virtual networks including virtual private networks 73, virtual applications and operating systems 74, and virtual clients 75 can be provided.

[0558] By way of example, the management layer 80 may provide the following functionality: Resource provisioning 81 enables dynamic procurement of computing and other resources utilized to execute tasks within the cloud computing environment. Metering and pricing 82 enables cost tracking as resources are utilized within the cloud computing environment and billing or invoicing for the consumption of these resources. By way of example, these resources may include application software licenses. Security enables identification and verification of cloud consumers and tasks, as well as protection for data and other resources. User portal 83 provides consumers and system administrators with access to the cloud computing environment. Service level management 84 enables allocation and management of cloud computing resources so that requested service levels are met. Service level agreement (SLA) planning and fulfillment 85 enables advance arrangement and procurement of anticipated future cloud computing resources required in accordance with SLAs.

[0559] The workload layer 90 provides examples of functionality available in a cloud computing environment. Examples of workloads and functionality that can be provided from this layer include mapping and navigation 91, software development and lifecycle management 92, virtual classroom instruction delivery 93, data analytics processing 94, transaction processing 95, and query and / or neural network processing assisted processing 96.

[0560] Aspects of the invention may be a system, method, or computer program product, or combination thereof, integrated at any possible level of technical detail. The computer program product may include a computer-readable storage medium having stored thereon computer-readable program instructions for causing a processor to perform aspects of the invention.

[0561] A computer-readable storage medium may be a tangible device that can hold and store instructions used by an instruction execution device. The computer-readable storage medium may be, for example, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or a suitable combination thereof. More specific examples of computer-readable storage media include portable computer diskettes, hard disks, RAM, ROM, erasable programmable ROM (EPROM or flash memory), static random access memory (SRAM), CD-ROMs, DVDs, memory sticks, floppy disks, punch cards, or mechanically encoded devices that have instructions recorded on ridge-in-groove structures, and the like, and suitable combinations thereof. As used herein, a computer-readable storage medium should not be construed as a transitory signal per se, such as an electric wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., light pulses passing through a fiber optic cable), or an electrical signal transmitted over a wire.

[0562] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing device / processing device. Alternatively, they can be downloaded to an external computer or external storage device via a network (e.g., the Internet, a LAN, a WAN, or a wireless network, or a combination thereof). The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, or edge servers, or a combination thereof. A network adapter card or network interface within each computing device / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions to a computer-readable storage medium in the respective computing device / processing device for storage.

[0563] The computer-readable program instructions for carrying out the operations of the present invention can be either assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state setting data, configuration data for integrated circuits, or source or object code written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Smalltalk and C++, and procedural programming languages ​​such as the "C" programming language and similar programming languages. The computer-readable program instructions can execute entirely on the user's computer as a stand-alone software package, partially on the user's computer, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In the latter case, the remote computer may be connected to the user's computer via any type of network, including a LAN or WAN, or may be connected to an external computer (e.g., via the Internet using an Internet Service Provider). In some embodiments, electronic circuitry, including, for example, programmable logic circuits, field programmable gate arrays (FPGAs), programmable logic arrays (PLAs), can execute computer-readable program instructions by utilizing state information of the computer-readable program instructions to customize the electronic circuitry for carrying out aspects of the present invention.

[0564] Aspects of the present invention are described herein with reference to flowchart and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. Each block of the flowchart and / or block diagrams, and combinations of blocks in the flowchart and / or block diagrams, can be implemented by computer-readable program instructions.

[0565] These computer-readable program instructions can be provided to a processor of a computer or other programmable data processing apparatus to produce a machine, whereby the instructions, executed by the processor of such computer or other programmable data processing apparatus, create means for performing the functions / acts identified in one or more blocks of the flowcharts and / or block diagrams. These computer-readable program instructions can also be stored on a computer-readable storage medium that can instruct a computer, programmable data processing apparatus, or other device, or combination thereof, to function in a particular manner. The computer-readable storage medium having instructions stored thereon thereby constitutes an article of manufacture including instructions for performing aspects of the functions / acts identified in one or more blocks of the flowcharts and / or block diagrams.

[0566] Computer-readable program instructions may also be loaded into a computer, other programmable apparatus, or other device and a series of operational steps executed on the computer, other programmable apparatus, or other device to create a computer-implemented process, whereby the instructions executing on the computer, other programmable apparatus, or other device perform the functions / operations identified in one or more blocks in the flowcharts and / or block diagrams.

[0567] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of instructions, including one or more executable instructions for performing specific logical functions. In some implementations, the functions shown in the blocks may be performed in an order different from that shown in the figures. For example, depending on the functionality involved, two blocks shown in succession may actually be accomplished as a single step, may be executed simultaneously or substantially simultaneously, may be executed in a partially or fully overlapping manner, or the blocks may even be executed in reverse order. Note that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs specific functions or operations or executes a combination of dedicated hardware and computer instructions.

[0568] In addition to the above, one or more aspects may be provided, offered, deployed, managed, serviced, etc. by a service provider that offers management of a customer environment. For example, the service provider may create, maintain, support, etc., computer code and / or computer infrastructure that implements one or more aspects for one or more customers. In return, the service provider may receive payments from the customer, for example, based on a subscription and / or fee agreement. Additionally or alternatively, the service provider may receive payments from the sale of advertising content to one or more third parties.

[0569] In one aspect, an application may be deployed to implement one or more embodiments. By way of example, deploying an application includes providing a computer infrastructure operable to implement one or more embodiments.

[0570] As a further aspect, a computing infrastructure may be deployed that includes integrating computer-readable code into a computing system, where the code in combination with the computing system is capable of implementing one or more embodiments.

[0571] In yet another aspect, a process for integrating a computing infrastructure may be provided, the process comprising integrating computer-readable code into a computer system. The computer system includes a computer-readable medium. The computer medium includes one or more embodiments. The code in combination with the computer system may implement one or more embodiments.

[0572] Although various embodiments have been described above, these are by way of example only. For example, computing environments of other architectures may be used to incorporate and / or use one or more aspects. Furthermore, different instructions or operations may be used. Furthermore, different types of registers and / or different registers may be used. Furthermore, other data formats, data layouts, and / or data sizes may be supported. In one or more embodiments, one or more general-purpose processors, one or more special-purpose processors, or a combination of general-purpose and special-purpose processors may be used. Many variations are possible.

[0573] Various aspects are described herein. Furthermore, many variations are possible without departing from the spirit of the aspects of the present invention. Unless otherwise contradictory, each aspect or feature described herein, and variations thereof, may be combined with any other aspect or feature.

[0574] Additionally, other types of computing environments can also benefit from and be used with the present invention. As an example, a data processing system suitable for storing and / or executing program code can be used that includes at least two processors coupled directly or indirectly via a system bus to memory elements, such as local memory used during the actual execution of the program code, bulk storage, and cache memory that provides temporary storage of at least some program code to reduce the number of times the code must be retrieved from bulk storage during execution.

[0575] Input / output or I / O devices (including but not limited to keyboards, displays, pointing devices, DASDs, tapes, CDs, DVDs, thumb drives, and other memory media) may be coupled to the system either directly or through intervening I / O controllers. Network adapters may also be coupled to the system to enable the data processing system to be coupled to other data processing systems, remote printers, or storage devices through intervening private or public networks. Available network adapters include modems, cable modems, and Ethernet cards, to name a few.

[0576] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit various embodiments. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly dictates otherwise. Furthermore, as used herein, the terms "comprises" and / or "comprising" specify the presence of stated features, integers, steps, operations, elements, or components, or combinations thereof, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, or groups or combinations thereof.

[0577] Where present in the following claims, the corresponding structure, material, acts, and equivalents of all means-plus-function or step-plus-function elements are intended to include any structure, material, or acts for performing the function in combination with other specifically claimed claim elements. The description of one or more embodiments has been presented for purposes of illustration and description and is not intended to be exhaustive or limited to the precise form disclosed. Many modifications and variations will be apparent to those skilled in the art. The present embodiments were chosen and described to best explain various aspects and practical applications and to enable others skilled in the art to recognize various embodiments with various modifications suited to the particular use contemplated.

Claims

1. 1. A computer program product for performing a method for facilitating processing in a computing environment, the method comprising: executing instructions to perform a query function, the executing instructions comprising: obtaining information about a selected model of a processor, the information including at least one model-dependent data attribute of the selected model of the processor; placing said information in a selected location for use by at least one application in performing one or more functions; Including, The at least one model-dependent data attribute includes one or more supported data types of the selected model of the processor.

2. 2. The computer program product of claim 1, wherein the selected location includes a parameter block accessible to the at least one application, and the one or more supported data types are included in one or more fields of the parameter block.

3. 3. The computer program product of claim 1, wherein the at least one model-dependent data attribute includes one or more supported data layout formats of the selected model of the processor.

4. A computer program product for executing a method for facilitating processing in a computing environment, the method comprising: executing instructions to perform a query function, the executing instructions comprising: obtaining information about a selected model of a processor, the information including at least one model-dependent data attribute of the selected model of the processor; placing said information in a selected location for use by at least one application in performing one or more functions; Including, The at least one model-dependent data attribute includes one or more supported data layout formats of the selected model of the processor.

5. 4. The computer program product of claim 3, wherein the selected location includes a parameter block accessible to the at least one application, and the one or more supported data layout formats are included in one or more fields of the parameter block.

6. The computer program product of claim 1 , wherein the at least one model-dependent data attribute includes one or more supported data sizes of the selected model of the processor.

7. 7. The computer program product of claim 6, wherein the selected location comprises a parameter block accessible to the at least one application, and the one or more supported data sizes are contained in one or more fields of the parameter block.

8. 8. The computer program product of claim 6 or 7, wherein the one or more supported data sizes of the selected model of the processor include a maximum dimension index size and a maximum tensor size.

9. A computer program product for executing a method for facilitating processing in a computing environment, the method comprising: executing instructions to perform a query function, the executing instructions comprising: obtaining information about a selected model of a processor, the information including at least one model-dependent data attribute of the selected model of the processor; placing said information in a selected location for use by at least one application in performing one or more functions; Including, the selected location includes a parameter block accessible to the at least one application, the parameter block including a plurality of fields for storing a plurality of model-dependent data attributes of the selected model, the plurality of fields including an installed data type field for containing one or more supported data types of the selected model of the processor, an installed data layout format field for containing one or more supported data layout formats of the selected model of the processor, and one or more fields for containing one or more supported data sizes of the selected model of the processor.

10. 10. The computer program product of claim 9, wherein the parameter block further includes at least one of an installed function vector field and an installed parameter block format field, the installed function vector field indicating one or more supported functions of the selected model of the processor, and the installed parameter block format field indicating one or more supported formats of the parameter block.

11. 1. A computer system for facilitating processing within a computing environment, comprising: Memory and and at least one processor in communication with the memory, the computer system configured to execute a method, the method comprising: executing instructions to perform a query function, the executing instructions comprising: obtaining information about a selected model of a processor, the information including at least one model-dependent data attribute of the selected model of the processor; placing said information in a selected location for use by at least one application in performing one or more functions; Including, The at least one model-dependent data attribute includes one or more supported data types of the selected model of the processor.

12. 12. The computer system of claim 11, wherein the at least one model-dependent data attribute includes one or more supported data layout formats of the selected model of the processor.

13. A computer system for facilitating processing within a computing environment, comprising: Memory and and at least one processor in communication with the memory, the computer system configured to execute a method, the method comprising: executing instructions to perform a query function, the executing instructions comprising: obtaining information about a selected model of a processor, the information including at least one model-dependent data attribute of the selected model of the processor; placing said information in a selected location for use by at least one application in performing one or more functions; Including, The at least one model-dependent data attribute includes one or more supported data layout formats of the selected model of the processor.

14. 12. The computer system of claim 11, wherein the at least one model-dependent data attribute includes one or more supported data sizes of the selected model of the processor.

15. A computer system for facilitating processing within a computing environment, comprising: Memory and and at least one processor in communication with the memory, the computer system configured to execute a method, the method comprising: executing instructions to perform a query function, the executing instructions comprising: obtaining information about a selected model of a processor, the information including at least one model-dependent data attribute of the selected model of the processor; placing said information in a selected location for use by at least one application in performing one or more functions; Including, the selected location includes a parameter block accessible to the at least one application, the parameter block including a plurality of fields for storing a plurality of model-dependent data attributes of the selected model, the plurality of fields including an installed data type field for containing one or more supported data types of the selected model of the processor, an installed data layout format field for containing one or more supported data layout formats of the selected model of the processor, and one or more fields for containing one or more supported data sizes of the selected model of the processor.

16. 1. A computer-implemented method for facilitating processing within a computing environment, comprising: executing instructions to perform a query function, the executing instructions comprising: obtaining information about a selected model of a processor, the information including at least one model-dependent data attribute of the selected model of the processor; placing said information in a selected location for use by at least one application in performing one or more functions; Including, the at least one model-dependent data attribute includes one or more supported data types of the selected model of the processor; Computer-implemented methods.

17. 17. The computer-implemented method of claim 16, wherein the at least one model-dependent data attribute includes one or more supported data layout formats of the selected model of the processor.

18. A computer-implemented method for facilitating processing within a computing environment, comprising: executing instructions to perform a query function, the executing instructions comprising: obtaining information about a selected model of a processor, the information including at least one model-dependent data attribute of the selected model of the processor; placing said information in a selected location for use by at least one application in performing one or more functions; Including, The computer-implemented method, wherein the at least one model-dependent data attribute includes one or more supported data layout formats of the selected model of the processor.

19. 17. The computer-implemented method of claim 16, wherein the at least one model-dependent data attribute includes one or more supported data sizes of the selected model of the processor.

20. A computer-implemented method for facilitating processing within a computing environment, comprising: executing instructions to perform a query function, the executing instructions comprising: obtaining information about a selected model of a processor, the information including at least one model-dependent data attribute of the selected model of the processor; placing said information in a selected location for use by at least one application in performing one or more functions; Including, 11. The computer-implemented method of claim 10, wherein the selected location includes a parameter block accessible to the at least one application, the parameter block including a plurality of fields for storing a plurality of model-dependent data attributes of the selected model, the plurality of fields including an installed data type field for containing one or more supported data types of the selected model of the processor, an installed data layout format field for containing one or more supported data layout formats of the selected model of the processor, and one or more fields for containing one or more supported data sizes of the selected model of the processor.

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