Memory chip, logic chip, chip stacking structure, and memory

Abstract

The present invention provides a memory chip, a logic chip, a chip stacking structure, and a memory, wherein the memory chip includes m channels, the m channels are sequentially arranged along a first direction and symmetrical with respect to the chip axis, each channel having a channel signal region, each channel signal region being divided into 2 × 2 via regions distributed in an array, the m channel signal regions having the same area, and the conductive via groups in the m channel signal regions all having the same distribution positions. The chip stacking structure formed based on the memory chip of the present invention achieves a signal rotational transmission effect through a via direct connection configuration, thereby reducing parasitic capacitance and parasitic resistance on the signal transmission path.

Description

[Technical Field]

[0001] (CROSS-REFERENCE TO RELATED APPLICATIONS) This application claims priority to a Chinese patent application filed with the China Patent Office on October 17, 2023, bearing application number 202311349143.9 and entitled "Memory chip, logic chip, chip stacking structure, and memory," the entire contents of which are incorporated herein by reference.

[0002] The present invention relates to the field of semiconductors, and more particularly to memory chips, logic chips, chip stacks, and memories. [Background technology]

[0003] With the development of integrated circuit technology, semiconductor device manufacturing processes have made great strides. However, in recent years, the development of 2D semiconductor technology has faced various challenges, including physical limitations, limitations of existing lithography technology, and limitations in electron storage density. To address these challenges and further reduce the manufacturing cost per unit memory cell, 3D semiconductor devices can be formed by stacking multiple chips using bonding processes (e.g., hybrid bonding, bumping, and lead bonding). However, the interconnection structures between different chips in 3D semiconductor devices still have problems, such as large parasitic capacitance and resistance, which affect the quality of signal transmission. Summary of the Invention

[0004] The present invention provides a memory chip, a logic chip, a chip stacking structure, and a memory.

[0005] The technical solution of the present invention is realized as follows:

[0006] In a first aspect, an embodiment of the present invention provides a memory chip, the memory chip including m channels sequentially arranged along a first direction, the memory chip having a chip axis extending along a second direction and passing through a center of the memory chip, the m channels being symmetrical with respect to the chip axis, each of the channels including a first bank array region, a channel signal region, and a second bank array region sequentially distributed along the second direction, the center of each of the channel signal regions overlaps with the center of a corresponding channel, m is a positive integer, the first direction is perpendicular to the second direction, each of the channel signal regions has a first axis and a second axis, the first axis extends along the first direction or the second direction, the second axis and the first axis are perpendicular to each other and intersect at the center of the corresponding channel signal region, each of the channel signal regions is divided into 2×2 via regions distributed in an array, the first via region and the second via region are symmetrical with respect to the first axis of the corresponding channel signal region, and a third via region and the fourth via region are symmetrical along a first axis of the channel signal region to which they belong, and the first via region and the fourth via region are symmetrical along a second axis of the channel signal region to which they belong, and each of the via regions includes n conductive via groups, and the n conductive via groups penetrate the substrate of the memory chip along a direction perpendicular to the active surface of the memory chip, where n is a natural number, the m channel signal regions have the same area, and the conductive via groups in the m channel signal regions are all distributed at the same positions, and in the same channel signal region, the n conductive via groups in the first via region and the n conductive via groups in the second via region are symmetrical along the first axis of the channel signal region to which they belong, the n conductive via groups in the third via region and the n conductive via groups in the fourth via region are symmetrical along the first axis of the channel signal region to which they belong, and the n conductive via groups in the first via region and the n conductive via groups in the fourth via region are symmetrical along the second axis of the channel signal region to which they belong.

[0007] In some embodiments, each of the conductive via groups has a third axis and a fourth axis, the third axis is parallel to the first axis, the fourth axis and the third axis are perpendicular to each other and intersect at the center of the conductive via group to which it belongs, and when each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via distributed in a 2×2 array, the first conductive via and the second conductive via are symmetrical with respect to the third axis of the conductive via group to which it belongs, and the third conductive via and the fourth conductive via are symmetrical with respect to the third axis of the conductive via group to which it belongs. the first conductive vias and the fourth conductive vias are symmetrical with respect to the fourth axis of the conductive via group to which they belong, and in each of the channel signal regions, the n first conductive vias in the first via region and the n second conductive vias in the second via region are symmetrical with respect to the first axis of the channel signal region to which they belong, the n third conductive vias in the third via region and the n fourth conductive vias in the fourth via region are symmetrical with respect to the first axis of the channel signal region to which they belong, and the n first conductive vias in the first via region and the n a conductive via and the n fourth conductive vias in the fourth via region are symmetrical with respect to the second axis of the channel signal region to which they belong; a conductive via in the first via region and the n first conductive vias in the second via region are symmetrical with respect to the first axis of the channel signal region to which they belong; a conductive via in the third via region and the n third conductive vias in the fourth via region are symmetrical with respect to the first axis of the channel signal region to which they belong; a conductive via in the first via region and the n third conductive vias in the fourth via region are symmetrical with respect to the second axis of the channel signal region to which they belong; a conductive via in the first via region and the n fourth conductive vias in the second via region are symmetrical with respect to the first axis of the channel signal region to which they belong; a conductive via in the third via region and the n second conductive vias in the fourth via region are symmetrical with respect to the first axis of the channel signal region to which they belong;The n fourth conductive vias in the first via region and the n third conductive vias in the second via region are symmetrical about the first axis of the channel signal region to which they belong, the n second conductive vias in the third via region and the n first conductive vias in the fourth via region are symmetrical about the first axis of the channel signal region to which they belong, and the n fourth conductive vias in the first via region and the n first conductive vias in the fourth via region are symmetrical about the second axis of the channel signal region to which they belong.

[0008] In some embodiments, the memory chip further includes (4×m×n) first drive circuits, each of which is coupled to one of the (4×m×n) first conductive vias in a one-to-one correspondence, and each of which is coupled to a portion of the first conductive via located on the active surface, and each of which is used to transmit signals transmitted by the correspondingly connected first conductive vias to an internal circuit of the memory chip, or to transmit signals generated in the internal circuit of the memory chip to the correspondingly connected first conductive vias.

[0009] In some embodiments, the coordinate position of each conductive via is determined based on the center of the via signal area to which it belongs, and the type of signal transmitted by the four conductive vias having the same coordinate position is the same.

[0010] In some embodiments, the conductive vias are fabricated by one or more of a via-first process, a via-middle process, a via-last process, and a backside via-last process, and different conductive vias in the same memory chip are electrically isolated.

[0011] In a second aspect, an embodiment of the present invention provides a logic chip, the logic chip including m channel signal regions sequentially arranged along a first direction, the logic chip having a chip axis extending along a second direction and passing through a center of the logic chip, the m channel signal regions being symmetrical with respect to the chip axis, m being a positive integer, each of the channel signal regions having a first axis and a second axis, the first axis extending along the first direction or the second direction, the second axis and the first axis being perpendicular to each other and intersecting at a center of the channel signal region to which it belongs, each of the channel signal regions being divided into 2×2 via regions distributed in an array, the first via region and the second via region being symmetrical with respect to the first axis of the channel signal region to which it belongs, the third via region and the fourth via region being symmetrical with respect to the first axis of the channel signal region to which it belongs, the n conductive via groups in the first via region and the n conductive via groups in the second via region are symmetrical with respect to the first axis of the channel signal region, the second direction being perpendicular to the first direction, each of the via regions includes n conductive via groups, the n conductive via groups penetrate the substrate of the logic chip along a direction perpendicular to the active surface of the logic chip, n is a natural number, the m channel signal regions have the same area, the distribution positions of the conductive via groups in the m channel signal regions are all the same, in the same channel signal region, the n conductive via groups in the first via region and the n conductive via groups in the second via region are symmetrical with respect to the first axis of the channel signal region to which they belong, the n conductive via groups in the third via region and the n conductive via groups in the fourth via region are symmetrical with respect to the first axis of the channel signal region to which they belong, and the n conductive via groups in the first via region and the n conductive via groups in the fourth via region are symmetrical with respect to the second axis of the channel signal region to which they belong.

[0012] In some embodiments, each of the conductive via groups has a third axis and a fourth axis, the third axis being parallel to the first axis, the fourth axis and the third axis being perpendicular to each other and intersecting at the center of the conductive via group to which it belongs, and when each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via distributed in a 2×2 array, the first conductive via and the second conductive via are symmetrical with respect to the third axis of the conductive via group to which it belongs, and the third conductive via and the fourth conductive via are symmetrical with respect to the third axis of the conductive via group to which it belongs. the first conductive vias and the fourth conductive vias are symmetrical with respect to a fourth axis of the conductive via group to which they belong; in each of the channel signal regions, the n first conductive vias in the first via region and the n second conductive vias in the second via region are symmetrical with respect to the first axis of the channel signal region to which they belong; the n third conductive vias in the third via region and the n fourth conductive vias in the fourth via region are symmetrical with respect to the first axis of the channel signal region to which they belong; and the n fourth conductive vias in the fourth via region are symmetrical with respect to the second axis of the channel signal region to which they belong, the n second conductive vias in the first via region and the n first conductive vias in the second via region are symmetrical with respect to the first axis of the channel signal region to which they belong, the n fourth conductive vias in the third via region and the n third conductive vias in the fourth via region are symmetrical with respect to the first axis of the channel signal region to which they belong, the n second conductive vias in the first via region and the n third conductive vias in the fourth via region are symmetrical with respect to the second axis of the channel signal region to which they belong, the n third conductive vias in the first via region and the n fourth conductive vias in the second via region are symmetrical with respect to the first axis of the channel signal region to which they belong, the n first conductive vias in the third via region and the n second conductive vias in the fourth via region are symmetrical with respect to the first axis of the channel signal region to which they belong, and the n third conductive vias in the first via region and the n second conductive vias in the fourth via region areThe n fourth conductive vias in the first via region and the n third conductive vias in the second via region are symmetrical about the first axis of the channel signal region to which they belong, the n second conductive vias in the third via region and the n first conductive vias in the fourth via region are symmetrical about the first axis of the channel signal region to which they belong, and the n fourth conductive vias in the first via region and the n first conductive vias in the fourth via region are symmetrical about the second axis of the channel signal region to which they belong.

[0013] In some embodiments, the logic chip further includes (16×m×n) second drive circuits, each coupled to one of the (16×m×n) conductive vias in one-to-one correspondence, and each coupled to a portion of the conductive via located on the active surface, and each second drive circuit is used to transmit a signal transmitted by the corresponding conductive via to an internal circuit of the logic chip or to transmit a signal generated in the internal circuit of the logic chip to the corresponding conductive via.

[0014] In some embodiments, the coordinate position of each conductive via is determined based on the center of the via signal area to which it belongs, the type of signal transmitted by four conductive vias having the same coordinate position is the same, the conductive vias are manufactured by one or more processes including a via-first process, a via-middle process, a via-last process, and a backside via-last process, and all different conductive vias in the same logic chip are electrically isolated from each other.

[0015] In a third aspect, an embodiment of the present invention provides a chip stacking structure, the chip stacking structure including: a logic chip according to the second aspect; and at least one stacking unit; the logic chip and the at least one stacking unit are sequentially stacked along a third direction; each stacking unit includes a first memory chip, a second memory chip, a third memory chip, and a fourth memory chip sequentially stacked along the third direction; the third direction is perpendicular to an active surface of each of the memory chips; and the first memory chip, the second memory chip, the third memory chip, and the fourth memory chip are all the memory chips according to the first aspect; the logic chip and the first memory chip are stacked in a face-to-back or back-to-back manner; the first memory chip and the second memory chip are stacked face-to-face; the second memory chip and the third memory chip are stacked in a back-to-back manner; The third memory chip and the fourth memory chip are stacked face-to-face.

[0016] In some embodiments, the logic chip includes m channel signal regions arranged along a first direction, each of the memory chips has m channels arranged along the first direction, each of the channels includes a first bank array region, a channel signal region, and a second bank array region sequentially distributed along a second direction, when the logic chip and the first memory chip are stacked back-to-back, and first axes of the logic chip and each of the memory chips all extend along the first direction, the m channel signal regions in the logic chip, the channel signal region of the i+1-th channel in the first memory chip, the channel signal region of the i+1-th channel in the second memory chip, the channel signal region of the m channel in the third memory chip, and the channel signal region of the m channel in the fourth memory chip are aligned along a third direction, where i is a natural number less than m.

[0017] In some embodiments, the logic chip includes m channel signal areas arranged along a first direction, each of the memory chips has m channels arranged along the first direction, each of the channels includes a first bank array area, a channel signal area, and a second bank array area sequentially distributed along a second direction, when the logic chip and the first memory chip are stacked back-to-back and the second axis of the logic chip and each of the memory chips extends along the first direction, the i+1th channel signal areas in the logic chip, the channel signal area of ​​the i+1th channel in the first memory chip, the channel signal area of ​​the m-th channel in the second memory chip, the channel signal area of ​​the m-th channel in the third memory chip, and the channel signal area of ​​the i+1th channel in the fourth memory chip are aligned along a third direction, where i is a natural number smaller than m.

[0018] In some embodiments, each of the channel signal regions of each of the channels is divided into 2×2 via regions distributed in an array, and only for the plurality of channel signal regions aligned along the third direction, the fourth via region belonging to the logic chip, the first via region belonging to the first memory chip, the second via region belonging to the second memory chip, the third via region belonging to the third memory chip, and the fourth via region belonging to the fourth memory chip are aligned along the third direction, and the third via region belonging to the logic chip, the second via region belonging to the first memory chip, the first via region belonging to the second memory chip, and the fourth via region belonging to the third memory chip are aligned along the third direction. The fourth via region and the third via region belonging to the fourth memory chip are aligned along a third direction, the second via region belonging to the logic chip, the third via region belonging to the first memory chip, the fourth via region belonging to the second memory chip, the first via region belonging to the third memory chip, and the second via region belonging to the fourth memory chip are aligned along the third direction, and the first via region belonging to the logic chip, the fourth via region belonging to the first memory chip, the third via region belonging to the second memory chip, the second via region belonging to the third memory chip, and the first via region belonging to the fourth memory chip are aligned along the third direction.

[0019] In some embodiments, each of the via regions includes n conductive via groups having the same distribution positions, each conductive via group has a third axis and a fourth axis, the third axis is parallel to the first axis, and the fourth axis and the third axis are perpendicular to each other and intersect at the center of the conductive via group to which it belongs, and when each of the conductive via groups includes 2×2 first conductive vias, second conductive vias, third conductive vias, and fourth conductive vias distributed in a 2×2 array, the first conductive vias and the second conductive vias are symmetrical with respect to the third axis of the conductive via group to which it belongs, the third conductive vias and the fourth conductive vias are symmetrical with respect to the third axis of the conductive via group to which it belongs, and the first conductive vias and the fourth conductive vias are symmetrical with respect to the fourth axis of the conductive via group to which it belongs, and for only the plurality of via regions aligned along the third direction, the fourth conductive via belonging to the logic chip, the first conductive via belonging to the first memory chip, the second conductive via belonging to the second memory chip, and the third conductive via belonging to the third memory chip and the fourth conductive via belonging to the fourth memory chip are aligned along a third direction; the third conductive via belonging to the logic chip, the second conductive via belonging to the first memory chip, the first conductive via belonging to the second memory chip, the fourth conductive via belonging to the third memory chip, and the third conductive via belonging to the fourth memory chip are aligned along the third direction; the second conductive via belonging to the logic chip, the third conductive via belonging to the first memory chip, the fourth conductive via belonging to the second memory chip, the first conductive via belonging to the third memory chip, and the second conductive via belonging to the fourth memory chip are aligned along the third direction; and the first conductive via belonging to the logic chip, the fourth conductive via belonging to the first memory chip, the third conductive via belonging to the second memory chip, the second conductive via belonging to the third memory chip, and the first conductive via belonging to the fourth memory chip are aligned along the third direction, wherein a plurality of conductive vias aligned along the third direction are combined to form one conductive channel.

[0020] In some embodiments, the logic chip includes m channel signal regions arranged along a first direction, each of the memory chips has m channels arranged along the first direction, each of the channels includes a first bank array region, a channel signal region, and a second bank array region sequentially distributed along a second direction, when the logic chip and the first memory chip are stacked back-to-back and the first axis of each of the logic chip and each of the memory chips extends along the first direction, the i+1th channel signal regions in the logic chip, the channel signal region of the i+1th channel in the first memory chip, the channel signal region of the i+1th channel in the second memory chip, the channel signal region of the m-th channel in the third memory chip, and the channel signal region of the m-th channel in the fourth memory chip are aligned along a third direction, where i is a natural number less than m.

[0021] In some embodiments, the logic chip includes m channel signal regions arranged along a first direction, each of the memory chips has m channels arranged along the first direction, each of the channels includes a first bank array region, a channel signal region, and a second bank array region sequentially distributed along a second direction, when the logic chip and the first memory chip are stacked back-to-back and the second axis of each of the logic chip and each of the memory chips extends along the first direction, the m channel signal regions in the logic chip, the channel signal region of the i+1-th channel in the first memory chip, the channel signal region of the m channel in the second memory chip, the channel signal region of the m channel in the third memory chip, and the channel signal region of the i+1-th channel in the fourth memory chip are aligned along the third direction, where i is a natural number smaller than m.

[0022] In some embodiments, for only the plurality of channel signal regions aligned along the third direction, the second via region belonging to the logic chip, the first via region belonging to the first memory chip, the second via region belonging to the second memory chip, the third via region belonging to the third memory chip, and the fourth via region belonging to the fourth memory chip are aligned along the third direction; the first via region belonging to the logic chip, the second via region belonging to the first memory chip, the first via region belonging to the second memory chip, the fourth via region belonging to the third memory chip, and the third via region belonging to the fourth memory chip are aligned along the third direction; the fourth via region belonging to the logic chip, the third via region belonging to the first memory chip, the fourth via region belonging to the second memory chip, the first via region belonging to the third memory chip, and the second via region belonging to the fourth memory chip are aligned along the third direction; and the third via region belonging to the logic chip, the fourth via region belonging to the first memory chip, the third via region belonging to the second memory chip, the second via region belonging to the third memory chip, and the first via region belonging to the fourth memory chip are aligned along the third direction.

[0023] In some embodiments, each of the via regions includes n conductive via groups having the same distribution positions, each conductive via group has a third axis and a fourth axis, the third axis is parallel to the first axis, and the fourth axis and the third axis are perpendicular to each other and intersect at the center of the conductive via group to which it belongs, and when each of the conductive via groups includes 2×2 first conductive vias, second conductive vias, third conductive vias, and fourth conductive vias distributed in a 2×2 array, the first conductive vias and the second conductive vias are symmetrical with respect to the third axis of the conductive via group to which it belongs, the third conductive vias and the fourth conductive vias are symmetrical with respect to the third axis of the conductive via group to which it belongs, and the first conductive vias and the fourth conductive vias are symmetrical with respect to the fourth axis of the conductive via group to which it belongs, and for the plurality of via regions aligned along the third direction, the fourth conductive via belonging to the fourth memory chip are aligned along a third direction; the first conductive via belonging to the logic chip, the second conductive via belonging to the first memory chip, the first conductive via belonging to the second memory chip, the fourth conductive via belonging to the third memory chip, and the third conductive via belonging to the fourth memory chip are aligned along the third direction; the fourth conductive via belonging to the logic chip, the third conductive via belonging to the first memory chip, the fourth conductive via belonging to the second memory chip, the first conductive via belonging to the third memory chip, and the second conductive via belonging to the fourth memory chip are aligned along the third direction; and the third conductive via belonging to the logic chip, the fourth conductive via belonging to the first memory chip, the third conductive via belonging to the second memory chip, the second conductive via belonging to the third memory chip, and the first conductive via belonging to the fourth memory chip are aligned along the third direction, wherein a plurality of conductive vias aligned along the third direction are combined to form one conductive channel.

[0024] In some embodiments, in the case of two chips connected face-to-face, the positions of the conductive vias of both chips aligned along the third direction are electrically connected by a hybrid bonding process; in the case of two chips connected back-to-back or two chips connected front-to-back, the positions of the conductive vias of both chips aligned along the third direction are electrically connected by a conductive bump bonding process; or in the case of two chips connected face-to-face or two chips connected back-to-back or two chips connected front-to-back, the vias of both chips aligned along the third direction are electrically connected by a hybrid bonding process; or in the case of two chips connected face-to-face or two chips connected back-to-back or two chips connected front-to-back, the vias of both chips aligned along the third direction are electrically connected by a conductive bump bonding process.

[0025] In a fourth aspect, an embodiment of the present invention provides a memory including the chip stack structure of the third aspect. [Effects of the Invention]

[0026] Embodiments of the present invention provide memory chips, logic chips, chip stacking structures, and memories that reduce the number of drive circuits and data selectors, thereby reducing parasitic capacitance; and the chip stacking structure consisting of memory chips also reduces parasitic resistance by realizing a signal rotation transmission effect through a direct via connection configuration. [Brief explanation of the drawings]

[0027] [Figure 1] 1 is a schematic diagram of the structure of a chip. [Figure 2A] FIG. 1 is a schematic diagram of signal transmission in a chip stack structure. [Figure 2B] FIG. 1 is a schematic diagram of signal transmission in a chip stack structure. [Figure 3] 1 is a schematic diagram of a structure of a memory chip according to an embodiment of the present invention; [Figure 4]1 is a schematic diagram of the local structure of a memory chip according to an embodiment of the present invention; [Figure 5] 2 is a schematic diagram of the local structure of a memory chip according to an embodiment of the present invention; [Figure 6] 1 is a schematic diagram of a structure of a logic chip according to an embodiment of the present invention; [Figure 7A] 1 is a schematic diagram 1 of a local structure of a logic chip according to an embodiment of the present invention; [Figure 7B] 2 is a schematic diagram of the local structure of a logic chip according to an embodiment of the present invention; [Figure 8] 1 is a schematic diagram of a chip stack structure according to an embodiment of the present invention. [Figure 9A] 1 is a specific schematic diagram 1 of a chip stacking structure according to an embodiment of the present invention; [Figure 9B] FIG. 2 is a specific schematic diagram 2 of a chip stacking structure according to an embodiment of the present invention. [Figure 10A] 1 is a specific schematic diagram 1 of another chip stacking structure according to an embodiment of the present invention. [Figure 10B] FIG. 2 is a specific schematic diagram 2 of another chip stack structure according to an embodiment of the present invention. [Figure 11A] 1 is a specific schematic diagram 1 of another chip stacking structure according to an embodiment of the present invention. [Figure 11B] FIG. 2 is a specific schematic diagram 2 of yet another chip stacking structure according to an embodiment of the present invention. [Figure 12A] 1 is a specific schematic diagram 1 of yet another chip stacking structure according to an embodiment of the present invention. [Figure 12B] FIG. 2 is a specific schematic diagram 2 of yet another chip stacking structure according to an embodiment of the present invention. [Figure 13] FIG. 1 is a schematic diagram of signal transmission in a chip stacking structure according to an embodiment of the present invention. [Figure 14] FIG. 2 is a schematic diagram 2 of signal transmission in a chip stacking structure according to an embodiment of the present invention. [Figure 15] 1 is a schematic diagram of a memory structure according to an embodiment of the present invention; DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the drawings in the embodiments of the present invention. It should be understood that the specific embodiments described in this specification are merely for the purpose of illustrating the relevant application and are not intended to limit the application. Furthermore, for convenience of description, only parts relevant to this application are shown in the drawings. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art. The terms used in this specification are merely for the purpose of describing the embodiments of the present invention and are not intended to limit the present invention. In the following description, the term "some embodiments" refers to a subset of all possible embodiments. It should be understood that the term "some embodiments" may refer to the same or different subsets of all possible embodiments, which may be combined with each other to the extent not contradictory. The terms "first / second / third" used in the embodiments of the present invention are merely for the purpose of distinguishing similar objects and do not represent a specific order of the objects. It should be understood that "first / second / third" may, in some cases, be interchangeable with a specific order or precedence order, and therefore the embodiments of the present invention described herein may be performed in an order other than that shown or described.

[0029] Dynamic Random Access Memory (DRAM); Synchronous Dynamic Random Access Memory (SDRAM); Double Data Rate Memory (DDR: Double Data Rate SDRAM); Low Power DDR (LPDDR).

[0030] Before introducing examples of the present invention, we first define three directions for describing a three-dimensional structure that may be used in the planes referred to in the following examples. Taking the Cartesian coordinate system as an example, the three directions may include a first direction, a second direction, and a third direction.

[0031] 1, a semiconductor chip (which may be a memory chip or a logic chip) includes a top surface that is the front surface and a bottom surface that is the back surface opposite the front surface, and if the flatness of the top and bottom surfaces is ignored, a direction that intersects (e.g., is perpendicular to) the top and bottom surfaces of the semiconductor chip is defined as a third direction. Two directions that are perpendicular to each other, i.e., a first direction and a second direction, are defined on the top surface of the semiconductor chip, where the first direction is perpendicular to one side of the semiconductor chip and the second direction is perpendicular to the other side of the semiconductor chip.

[0032] Referring to Figure 1, a semiconductor chip includes a substrate, one side of which is formed with an active surface for manufacturing devices (e.g., transistors, capacitors, etc.) (the surface of the substrate opposite the active surface, i.e., the bottom surface in Figure 1, is the inactive surface), and multiple metal layers (e.g., M1, M2, M3, etc.) are distributed between the substrate and the top surface. Figure 1 also shows two types of conductive vias (e.g., silicon vias), both of which are used to realize signal connections between different stacked chips.

[0033] As shown in FIG. 1, the type 1 conductive via penetrates the bottom and top surfaces along the third direction, and the conductive via is connected to the internal circuitry of the chip through the metal layer.

[0034] As shown in FIG. 1, Type 2 conductive vias penetrate only the substrate along the third direction (through the active surface and bottom surface) and must be combined with contact structures that penetrate the top surface along the third direction to achieve signal transmission. The contact structures and conductive vias are not directly electrically connected, but are indirectly electrically connected through metal layers. For example, the contact structure in FIG. 1 is connected to M4, which is sequentially connected to M1 via M3 and M2, and M1 is connected to the conductive via. Alternatively, the conductive vias in FIG. 1 are connected to input terminals of the chip internal circuit (the device in the substrate in FIG. 1) through M1-M4, and output signals processed by the chip internal circuit are output to the corresponding contact structures again through metal layers M1-M4. Similarly, the contact structures in FIG. 1 are also connected to input terminals of the chip internal circuit (the device in the substrate in FIG. 1) through M1-M4, and output signals processed by the chip internal circuit are output to the corresponding conductive vias again through M1-M4. Of course, in other embodiments, the contact structures and conductive vias may be designed to be directly electrically connected.

[0035] Furthermore, the types of conductive vias are not limited to the above two types, and the above are merely examples. In particular, the illustrations shown in the present invention do not represent actual views of specific microelectronic devices or their components, but are merely idealized representations for illustrating illustrative embodiments. Therefore, the illustrations are not necessarily drawn to scale.

[0036] Hereinafter, each embodiment of the present invention will be described in detail with reference to the drawings.

[0037] In one embodiment, a memory chip and a logic chip are provided, and both the memory chip and the logic chip include a plurality of conductive vias penetrating the chip along a third direction, the conductive vias are for realizing signal transmission between different chips, and all the conductive vias can be arranged at any position. In particular, four conductive vias can be functionally treated as one conductive via group, but the positions of these four conductive vias are not particularly limited.

[0038] In one specific embodiment, eight of the above memory chips and one logic chip are stacked to form a 3D memory device, where the conductive vias of each of the eight memory chips are aligned along a third direction, and the nine conductive vias aligned along the third direction are connected to form one electrical path. Referring to FIG. 2A, a schematic diagram of signal transmission in a chip stacking structure is shown. As shown in FIG. 2A, the chip stacking structure includes memory chips 0-7 and a logic chip. For each memory chip, only four conductive vias D0-D3 are shown in FIG. 2A, and these four conductive vias D0-D3 belong to the same conductive via group. In this case, the conductive vias D0 in the eight memory chips and one logic chip are all aligned to form one electrical path, the conductive vias D1 in the eight memory chips and one logic chip are all aligned to form one electrical path, and so on for the other conductive vias.

[0039] Each memory chip and logic chip is further provided with a plurality of driving circuits (only one of the driving circuits is shown in a dotted line frame in FIG. 2A, and the remaining driving circuits are not surrounded by frames), and each conductive via is connected to one driving circuit. Each memory chip is further provided with a plurality of data selectors (e.g., mux0 to mux7 in FIG. 2A), and each conductive via group corresponds to one data selector, i.e., all conductive vias in one conductive via group are connected to data terminals of the data selector via their respective driving circuits. In other words, the data selector can select which conductive via transmits a signal to be output to the inside of the memory chip, or which conductive via a signal output by the memory chip is to be output to.

[0040] For the entire memory device, different areas in different memory chips are divided into different channels (e.g., CH0, CH1, CH4, CH5) and managed, and the signal Signal_CH0 of channel CH0 is transmitted via an electrical path consisting of "conductive via D0 in the logic chip, conductive via D0 in memory chip 0--conductive via D0 in memory chip 1--conductive via D0 in memory chip 2--conductive via D0 in memory chip 3--conductive via D0 in memory chip 4--conductive via D0 in memory chip 5--conductive via D0 in memory chip 6--conductive via D0 in memory chip 7," and the selection signals of the data selector mux0 in memory chip 0 and the data selector mux4 in memory chip 4 are both SEL_C0, i.e., the signal Signal_CH0 can be input to memory chip 0 and memory chip 4 via the aforementioned electrical path, and the signal output process can be understood in a similar manner.

[0041] As can be seen from the above, memory chip 0 only needs to obtain signals from conductive via D0, memory chip 1 only needs to obtain signals from conductive via D1, etc. That is, each memory chip only needs to obtain signals from one conductive via in one conductive via group. It should be noted that different memory chips need to obtain signals from different conductive vias. However, because all memory chips must be designed with the same exact structure during the manufacturing process (which can maximize cost and labor savings), to achieve structural consistency, every conductive via in a memory chip must be designed with a corresponding driving structure and data selector. Furthermore, when adopting the chip stacking structure shown in FIG. 2A, each conductive via corresponds to one driving circuit. During the operation of this chip stacking structure, all driving circuits in all memory chips in the same channel must be driven. This heavy load and large parasitic capacitance severely impact chip performance, limit transmission efficiency, increase power consumption, and further limit the number of chips stacked in a 3D device.

[0042] In another embodiment, referring to FIG. 2B, a schematic diagram of signal transmission in another chip stacking structure is shown. In particular, in FIG. 2B, only partial conductive vias (D0-D3) are shown, and the rest are omitted. However, the labels of the conductive vias aligned along the third direction are the same in FIG. 2B. As shown in FIG. 2B, the chip stacking structure also includes eight memory chips and one logic chip aligned along the third direction. However, all conductive vias in each memory chip are connected to other conductive vias at different positions in other memory chips in a rotating manner, realizing a spiral-like upward connection as a whole. That is, the signal Signal_CH0 of channel CH0 is transmitted through "conductive via D0 in the logic chip - conductive via D1 in memory chip 0 - conductive via D2 in memory chip 1 - conductive via D3 in memory chip 2 - conductive via D0 in memory chip 3 - conductive via D1 in memory chip 4 - conductive via D2 in memory chip 5 - conductive via D3 in memory chip 6 - conductive via D0 in memory chip 7," and other signals are processed similarly.

[0043] This allows memory chip 0 to obtain signal Signal_CH0 through the output terminal of conductive via D0 of the logic chip, memory chip 1 to obtain signal Signal_CH1 through the input terminal of conductive via D0 of memory chip 0, memory chip 2 to obtain signal Signal_CH4 through the input terminal of conductive via D0 of memory chip 1, memory chip 3 to obtain signal Signal_CH5 through the input terminal of conductive via D0 of memory chip 2...In each memory chip, only one conductive via in each conductive via group is connected to the driving circuit, and there is no need to place a data selector, so the number of devices can be reduced, thereby reducing parasitic capacitance. However, compared with the direct connection of the conductive vias in FIG. 2A , the process of rotationally connecting the conductive vias in FIG. 2B is more complicated. Specifically, a horizontal interconnect structure (only one of which is marked with a five-pointed star in FIG. 2B ) needs to be arranged between adjacent conductive vias in each memory chip in FIG. 2B . The signal interconnect structure may be a metal interconnect line, a conductive via, or the like. To achieve the rotational connection of the conductive vias, the input signal signal_CH0 must first be transmitted upward from the conductive via D0 of the logic chip to the interconnect structure below the conductive via D0 of memory chip 0 (it is not input to the conductive via D0 of memory chip 0), and then transmitted horizontally from the interconnect structure below the conductive via D0 of memory chip 0 to the conductive via D1 of memory chip 0. That is, in the structure shown in FIG. 2B , the signal transmission must additionally pass through the interconnect structure of each memory chip, as does the output signal, which inevitably increases parasitic resistance and process complexity.

[0044] In particular, in the chip stacking structure of Figures 2A and 2B, all chips are arranged with their active surfaces facing upward, i.e., different memory chips are stacked back-to-front, and memory chips and logic chips are also stacked back-to-front, i.e., the bottom surface of the upper chip contacts the top surface of the lower chip.

[0045] To summarize, on the one hand, the chip stacking structure of FIG. 2A requires more conductive vias to transmit corresponding signals, and the addition of corresponding driver circuits and data selectors increases the load and parasitic capacitance. On the other hand, the chip stacking structure of FIG. 2B increases the parasitic resistance due to the spiral structure. On the other hand, both the stacking structures of FIG. 2A and FIG. 2B have several problems that make them inapplicable to face-to-face stacking structures. Specifically, to achieve a face-to-face chip stacking structure, one method is to use two sets of masks to fabricate two different types of chips, one with the active side facing up and the other with the active side facing down, respectively. This method requires high process complexity and prohibits cost constraints. Another method is to fabricate an additional group of conductive vias and connect both groups of conductive vias to the same driver circuit within the memory chip. However, this method complicates the wiring within the memory chip, increasing not only process complexity but also power consumption.

[0046] In another embodiment of the present invention, referring to Fig. 3, there is shown a schematic diagram of the structure of a memory chip 10 according to an embodiment of the present invention. As shown in Fig. 3, the memory chip 10 includes m channels (m = 4 is shown as an example in Fig. 3) arranged sequentially along a first direction, the memory chip 10 has a chip axis YY' extending along a second direction and passing through the center of the memory chip, the m channels are symmetrical with respect to the chip axis YY', and each channel includes a first bank array region, a channel signal region, and a second bank array region distributed sequentially along the second direction, and the center of each channel signal region overlaps with the center of the channel to which it belongs.

[0047] It should be noted that during the chip manufacturing process, a positioning structure can be provided in the reference channel (e.g., the first channel) of the memory chip 10 to distinguish different channels of the chip, so that during subsequent packaging, the position of the reference channel can be identified through the positioning structure while other channels can be identified based on the orientation of the active surface of the chip.

[0048] 3 shows an example where m=4, and the following description will also use m=4 as an example, but m may be any positive integer. Specifically, when m is an even number, m / 2 channels are provided on one side of the global signal area 15 in the first direction, and the remaining m / 2 channels are provided on the other side of the global signal area 15 in the first direction. When m is an odd number, the (m+1) / 2 channels need to be divided into two parts located on both sides of the global signal area 15 in the first direction, and at the same time, the other (m-1) / 2 channels are provided on one side of the global signal area 15 in the first direction, and the remaining (m-1) / 2 channels are provided on the other side of the global signal area 15 in the first direction.

[0049] 3 may be viewed as a cross-sectional view of the active surface of a memory chip. As shown in FIG. 3, the center of the active surface of the memory chip and its neighboring area are defined as global signal region 15. In this case, the first channel, the second channel, global signal region 15, the third channel, and the fourth channel are sequentially distributed along the first direction. The signal transmitted by global signal region 15 is shared by the m channels of the memory chip, and the signal transmitted by each channel signal region is used only by the channel to which it belongs.

[0050] 4, there is specifically shown a schematic diagram of a first channel signal area 11, a second channel signal area 12, a third channel signal area 13, and a fourth channel signal area 14. In FIG. 4, the global signal area 15 is omitted.

[0051] As shown in Fig. 4, each channel signal area has a first axis AA' and a second axis BB', where the first axis AA' extends along the first direction or the second direction, and the second axis BB' and the first axis AA' are perpendicular to each other and intersect at the center of the associated channel signal area. In Fig. 4, the first axis AA' is shown extending along the first direction as an example, and other cases should be understood as appropriate.

[0052] Each channel signal area is divided into 2x2 via areas distributed in an array, with the first via area 21 and the second via area 22 being symmetrical along the first axis AA' of the channel signal area to which they belong, the third via area 23 and the fourth via area 24 being symmetrical along the first axis AA' of the channel signal area to which they belong, and the first via area 21 and the fourth via area 24 being symmetrical along the second axis BB' of the channel signal area to which they belong.

[0053] Each via region includes n conductive via groups (only some of the conductive via groups are shown in Figure 4), which penetrate the substrate of the memory chip 10 along a direction perpendicular to the active surface of the memory chip 10, where n is a natural number.

[0054] Furthermore, the m channel signal regions have the same area, and the conductive via groups are distributed at the same positions in the m channel signal regions. As a result, when manufacturing the memory chip 10, the layouts of the channel signal regions of different channels are completely identical, allowing the use of the same mask and reducing manufacturing costs.

[0055] Specifically, in the same channel signal region, the n conductive via groups in the first via region 21 and the n conductive via groups in the second via region 22 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, the n conductive via groups in the third via region 23 and the n conductive via groups in the fourth via region 24 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, and the n conductive via groups in the first via region 21 and the n conductive via groups in the fourth via region 24 are symmetrical with respect to the second axis BB' of the channel signal region to which they belong.

[0056] As shown in FIG. 4, the distance between the center of a certain conductive via group in the first via region 21 and the first axis AA′ is V AThe distance between the center of the conductive via group symmetrical to the conductive via group in the second via region 22 and the first axis AA′ is recorded as V C The distance between the center of the conductive via group symmetrical to the conductive via group in the third via region 23 and the first axis AA′ is recorded as V D The distance between the center of the conductive via group symmetrical to the conductive via group in the fourth via region 24 and the first axis AA′ is recorded as V B When recorded as V A =V C =V D =V B Similarly, the distance between the center of a certain conductive via group in the first via region 21 and the side of the channel signal region extending along the second direction is defined as H A The distance between the center of a conductive via group in the second via region 22 and the side of the channel signal region extending along the second direction is recorded as H C The distance between the center of a certain conductive via group in the third via region 23 and the side of the channel signal region extending along the second direction is recorded as H D The distance between the center of a conductive via group in the fourth via region 24 and the side of the channel signal region extending along the second direction is recorded as H B When recorded as H A =H C =H D =H B is.

[0057] The number and specific positions of the conductive vias in a conductive via group can be flexibly selected. For example, as long as it is guaranteed that the conductive via groups in different via regions follow the above symmetrical relationship, each conductive via group may include only one conductive via, 1x2 vias, 2x2 vias, or 2x3 vias.

[0058] In the following, a specific example will be described in which each conductive via group includes 2x2 conductive vias (D0, D1, D2, D3) distributed in an array, and other cases should be understood appropriately.

[0059] Referring to Figure 5, each conductive via group has a third axis CC' and a fourth axis DD', the third axis CC' is parallel to the first axis AA', the fourth axis DD' and the third axis CC' are perpendicular to each other and intersect at the center of the conductive via group to which it belongs, the first conductive via D0 and the second conductive via D1 are symmetrical with respect to the third axis CC' of the conductive via group to which it belongs, the third conductive via D2 and the fourth conductive via D3 are symmetrical with respect to the third axis CC' of the conductive via group to which it belongs, and the first conductive via D0 and the fourth conductive via D3 are symmetrical with respect to the fourth axis DD' of the conductive via group to which it belongs.

[0060] In this way, the entire structure consisting of one conductive via group in the first via region 21, one corresponding conductive via group in the second via region 22, one corresponding conductive via group in the third via region 23, and one corresponding conductive via group in the fourth via region 24 is symmetrical about the first axis AA' and symmetrical about the second axis BB'. For each conductive via group, the first via, the second via, the third via, and the fourth via therein are symmetrical about the third axis CC' and symmetrical about the fourth axis DD', thereby forming point-to-point direct connection conductive paths during subsequent formation of a chip stack structure, which can reduce parasitic capacitance and parasitic resistance, as described in detail below.

[0061] In some embodiments, and with reference to FIG. 4, in each channel signal domain, the following symmetrical relationship exists:

[0062] (1) The n first conductive vias D0 in the first via region 21 and the n second conductive vias D1 in the second via region 22 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, the n third conductive vias D2 in the third via region 23 and the n fourth conductive vias D3 in the fourth via region 24 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, and the n first conductive vias D0 in the first via region 21 and the n fourth conductive vias D3 in the fourth via region 24 are symmetrical with respect to the second axis BB' of the channel signal region to which they belong.

[0063] (2) The n second conductive vias D1 in the first via region 21 and the n first conductive vias D0 in the second via region 22 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, the n fourth conductive vias D3 in the third via region 23 and the n third conductive vias D2 in the fourth via region 24 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, and the n second conductive vias D1 in the first via region 21 and the n third conductive vias D2 in the fourth via region 24 are symmetrical with respect to the second axis BB' of the channel signal region to which they belong.

[0064] (3) The n third conductive vias D2 in the first via region 21 and the n fourth conductive vias D3 in the second via region 22 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, the n first conductive vias D0 in the third via region 23 and the n second conductive vias D1 in the fourth via region 24 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, and the n third conductive vias D2 in the first via region 21 and the n second conductive vias D1 in the fourth via region 24 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong. 2 axis line BB' is symmetric with respect to

[0065] (4) The n fourth conductive vias D3 in the first via region 21 and the n third conductive vias D2 in the second via region 22 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, the n second conductive vias D1 in the third via region 23 and the n first conductive vias D0 in the fourth via region 24 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, and the n fourth conductive vias D3 in the first via region 21 and the n first conductive vias D0 in the fourth via region 24 are symmetrical with respect to the second axis BB' of the channel signal region to which they belong.

[0066] In some embodiments, referring to Figure 4 or Figure 5, the memory chip 10 further includes (4 x m x n) first drive circuits 30, which are coupled to the (4 x m x n) first conductive vias D0 in one-to-one correspondence; specifically, the first drive circuits 30 are coupled to portions located on the active surfaces of the first conductive vias D0, and the first drive circuits 30 are used to transmit signals transmitted by the correspondingly connected first conductive vias D0 to the internal circuit of the memory chip 10, or to transmit signals generated in the internal circuit of the memory chip 10 to the correspondingly connected first conductive vias D0.

[0067] In this way, for each conductive via group, only the first conductive via D0 therein is connected to the internal circuit of the memory chip via the first drive circuit 30, eliminating the need to provide a data selector to select a via, and reducing the number of devices can reduce parasitic capacitance.

[0068] In some embodiments, the coordinate position of each conductive via is determined based on the center of the via signal area to which it belongs, and the type of signal transmitted by four conductive vias having the same coordinate position is the same.

[0069] For example, in a chip stack structure of a plurality of memory chips and logic chips, there are a plurality of chip select signals CS_0, CS_1, CS_2, . . . which indicate whether or not a bank array region of a different channel is selected. In this case, the first conductive via D0 provided in the first via region 21 of channel signal region 11 shown in FIG. 4, the first conductive via D0 provided at the same position in the first via region 21 of channel signal region 12, the first conductive via D0 provided at the same position in the first via region 21 of channel signal region 13, and the first conductive via D0 provided at the same position in the first via region 21 of channel signal region 14 all transmit the chip select signal CS, but the values ​​of the chip select signal CS transmitted by the first conductive vias D0 in different channel signal regions may be different. For example, the first conductive via D0 in the first via region 21 of channel signal region 11 is used to transmit CS_0 (corresponding to the first channel in the first memory chip), the first conductive via D0 in the first via region 21 of channel signal region 12 is used to transmit CS_1 (corresponding to the first channel of the second memory chip), and the first conductive via D0 in the first via region 21 of channel signal region 13 is used to transmit CS_2 (corresponding to the fourth channel of the third memory chip)...

[0070] In addition, in the same channel signal region, the types of signals transmitted by the four conductive vias symmetrical along the first and second axes are the same, but the specific signal values ​​may be different.

[0071] In some embodiments, the conductive vias can be expressed as at least through silicon vias (TSVs), specifically, vertical wiring structures that penetrate a silicon wafer / memory chip, such as Type 1 in FIG. 1 , and of course, the conductive vias can also adopt Type 2 in FIG. 1 , which realizes signal transmission in cooperation with contact structures. In other embodiments, other electrical connection structures may be used as conductive vias.

[0072] The conductive vias are fabricated by one or more of the following processes: via-first process, via-middle process, via-last process, and backside via-last process, and different conductive vias in the same memory chip 10 are electrically isolated.

[0073] The via-first process refers to a via processing method in which a via structure is fabricated before fabricating a device, such as a metal oxide semiconductor field effect transistor (MOSFET or MOS transistor) device structure. The via-middle process is a method of forming a via structure during the manufacturing process, and typically refers to a via processing method in which a via is fabricated after a device is formed and before fabricating a stack. The via-last process is a manufacturing method in which a via is formed from the front side of a wafer after the completion of back-end-of-line (BEOL) processing. The backside via-last process is a manufacturing method in which a via structure is formed from the back side of a wafer after the completion of BEOL processing. In other words, the via-first process may refer to fabricating a via before fabricating a circuit, the via-middle process may refer to fabricating a circuit and partial metal layers, then fabricating a via, and finally fabricating the remaining via, and the via-last process and backside via-last process may refer to fabricating a circuit and metal layers, then fabricating a via last.

[0074] As described above, the present invention provides a memory chip 10 including a plurality of channels symmetrical about a chip axis, and the conductive vias of each channel are symmetrical about a first axis and symmetrical about a second axis, which can be directly applied to a face-to-face stack structure without requiring two sets of masks or two sets of vias. Furthermore, since only one conductive via in each conductive via group is connected to a driving circuit, there is no need to arrange a data selector for via selection, and the number of devices can be reduced, thereby reducing parasitic capacitance and circuit area as well as chip manufacturing costs compared to the memory chip of FIG. 2A. Furthermore, when a stack structure is subsequently formed in the memory chip 10, a point-to-point direct connection conductive path can be formed, which reduces parasitic resistance as compared to the memory chip of FIG. 2B (for specific reasons, see the description below).

[0075] In yet another embodiment of the present invention, referring to Figure 6, a schematic diagram of the structure of a logic chip 40 according to an embodiment of the present invention is shown. As shown in Figure 6, the logic chip 40 includes m channel signal regions (m = 4 is shown as an example in Figure 6) arranged sequentially along a first direction, the logic chip 40 has a chip axis YY' extending along the second direction and passing through the center of the logic chip 40, and the m channel signal regions are symmetrical with respect to the chip axis YY'. Here, the area of ​​the channel signal regions of the logic chip 40 is the same as the area of ​​the channel signal regions of the memory chip.

[0076] Similarly, as shown in FIG. 6 , the center and adjacent areas of the active surface of logic chip 40 are also defined as global signal area 45. In this case, first channel signal area 41, second channel signal area 42, global signal area 45, third channel signal area 43, and fourth channel signal area 44 are sequentially distributed along the first direction, but the logic chip does not have a bank array area. That is, there are no memory cell arrays on either side of the channel signal area of ​​logic chip 40; instead, there are several logic control circuits of stacked memory. The signals transmitted by global signal area 45 are shared by m channels of the memory chip, while the signals transmitted by each channel signal area are used only by the channel to which they belong. In particular, the area of ​​the active surface of logic chip 40 may be the same as or larger than the area of ​​the active surface of memory chip 10.

[0077] As shown in Figure 7A, each channel signal area has a first axis AA' and a second axis BB', where the first axis AA' extends along the first direction or the second direction (Figure 7A shows the first axis AA' along the first direction as an example), the second axis BB' and the first axis AA' are perpendicular to each other and intersect at the center of the channel signal area to which it belongs, and each channel signal area is divided into 2 x 2 via areas distributed in an array, where the first via area 51 and the second via area 52 are symmetrical along the first axis AA' of the channel signal area to which it belongs, the third via area 53 and the fourth via area 54 are symmetrical along the first axis AA' of the channel signal area to which it belongs, and the first via area 51 and the fourth via area 54 are symmetrical along the second axis BB' of the channel signal area to which it belongs, and the second direction is perpendicular to the first direction.

[0078] Each via region includes n conductive via groups, which penetrate the substrate of the logic chip 40 in a direction perpendicular to the active surface of the logic chip 40, where n is a natural number, the m channel signal regions have the same area, and the distribution positions of the conductive via groups in the m channel signal regions are all the same. In the same channel signal region, the n conductive via groups in the first via region 51 and the n conductive via groups in the second via region 52 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, the n conductive via groups in the third via region 53 and the n conductive via groups in the fourth via region 54 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, and the n conductive via groups in the first via region 51 and the n conductive via groups in the fourth via region 54 are symmetrical with respect to the second axis BB' of the channel signal region to which they belong.

[0079] Similarly, in logic chip 40, the number and positions of conductive vias included in a conductive via group can be flexibly determined, and the following describes an example in which each conductive via group includes 2 x 2 conductive vias (D0, D1, D2, and D3) distributed in an array.

[0080] As shown in FIG. 7B, each conductive via group has a third axis CC' and a fourth axis DD', the third axis CC' is parallel to the first axis AA', the fourth axis DD' and the third axis CC' are perpendicular to each other and intersect at the center of the conductive via group to which it belongs, the first conductive via D0 and the second conductive via D1 are symmetrical with respect to the third axis CC' of the conductive via group to which it belongs, the third conductive via D2 and the fourth conductive via D3 are symmetrical with respect to the third axis CC' of the conductive via group to which it belongs, and the first conductive via D0 and the fourth conductive via D3 are symmetrical with respect to the fourth axis DD' of the conductive via group to which it belongs.

[0081] Similarly, the areas of the m channel signal regions are the same, and the distribution positions of the conductive via groups in the m channel signal regions are all the same in the logic chip 40. As a result, when manufacturing the logic chip 40, the layouts of the channel signal regions of different channels are completely consistent, so that the same mask can be used, thereby reducing manufacturing costs.

[0082] In some embodiments, referring to FIG. 7A, in each channel signal domain, the following symmetrical relationship exists:

[0083] (1) The n first conductive vias D0 in the first via region 51 and the n second conductive vias D1 in the second via region 52 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, the n third conductive vias D2 in the third via region 53 and the n fourth conductive vias D3 in the fourth via region 54 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, and the n first conductive vias D0 in the first via region 51 and the n fourth conductive vias D3 in the fourth via region 54 are symmetrical with respect to the second axis BB' of the channel signal region to which they belong.

[0084] (2) The n second conductive vias D1 in the first via region 51 and the n first conductive vias D0 in the second via region 52 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, the n fourth conductive vias D3 in the third via region 53 and the n third conductive vias D2 in the fourth via region 54 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, and the n second conductive vias D1 in the first via region 51 and the n third conductive vias D2 in the fourth via region 54 are symmetrical with respect to the second axis BB' of the channel signal region to which they belong.

[0085] (3) The n third conductive vias D2 in the first via region 51 and the n fourth conductive vias D3 in the second via region 52 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, the n first conductive vias D0 in the third via region 53 and the n second conductive vias D1 in the fourth via region 54 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, and the n third conductive vias D2 in the first via region 51 and the n second conductive vias D1 in the fourth via region 54 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong. 2 axis line BB' is symmetric with respect to

[0086] (4) The n fourth conductive vias D3 in the first via region 51 and the n third conductive vias D2 in the second via region 52 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, the n second conductive vias D1 in the third via region 53 and the n first conductive vias D0 in the fourth via region 54 are symmetrical with respect to the first axis AA' of the channel signal region to which they belong, and the n fourth conductive vias D3 in the first via region 51 and the n first conductive vias D0 in the fourth via region 54 are symmetrical with respect to the second axis BB' of the channel signal region to which they belong.

[0087] In some embodiments, referring to FIG. 7A or 7B , the logic chip 40 further includes (16×m×n) second drive circuits 50, which are coupled to the (16×m×n) conductive vias in one-to-one correspondence, and the second drive circuits 50 are coupled to portions located on the active surfaces of the conductive vias, and the second drive circuits 50 are used to transmit signals transmitted by the corresponding conductive vias to the internal circuitry of the logic chip 40, or to transmit signals generated in the internal circuitry of the logic chip 40 to the corresponding conductive vias.

[0088] In logic chip 40, all of the conductive vias in the conductive via group are connected to the internal circuitry of logic chip 40, thereby transmitting signals corresponding to different bank array portions (different channels) in the chip stack structure.

[0089] In some embodiments, the coordinate position of each conductive via is determined based on the center of the via signal area to which it belongs, and the type of signal transmitted by four conductive vias having the same coordinate position is the same. The conductive vias are manufactured by one or more processes including a via-first process, a via-middle process, a via-last process, and a backside via-last process, and different conductive vias in the same logic chip are all electrically isolated from each other.

[0090] Thus, an embodiment of the present invention provides a logic chip 40 including multiple channels, and the conductive vias of each channel have special symmetry, which can be directly applied to a face-to-face stacking structure without requiring two sets of masks or two sets of vias. Compared with the memory chip of Figure 2A, the chip stacking structure formed by the memory chip 10 and the logic chip 40 not only reduces parasitic capacitance and saves circuit area, but also reduces chip manufacturing costs. Furthermore, when forming the chip stacking structure, a point-to-point direct connection conductive path can be formed, and parasitic resistance is also reduced compared to the memory chip of Figure 2B (for specific reasons, see the explanation below).

[0091] In yet another embodiment of the present invention, referring to Figure 8, an exemplary structural diagram of a chip stack structure 70 according to an embodiment of the present invention is shown. As shown in Figure 8, chip stack structure 70 includes the above-mentioned logic chip 40 and at least one stack unit, where logic chip 40 and the at least one stack unit are stacked sequentially along a third direction, and each stack unit includes first memory chip 10A, second memory chip 10B, third memory chip 10C, and fourth memory chip 10D stacked sequentially along the third direction, where the third direction is perpendicular to the active surface of each memory chip, and The logic chip 40 and the first memory chip 10A are stacked in a face-to-back or back-to-back manner, the first memory chip 10A and the second memory chip 10B are stacked in a face-to-face manner, the second memory chip 10B and the third memory chip 10C are stacked in a back-to-back manner, and the third memory chip 10C and the fourth memory chip 10D are stacked in a face-to-face manner.

[0092] In embodiments of the present invention, face-to-face stacking refers to the top surfaces of two chips being substantially aligned along the third direction, and the center points, first axis lines, and second axis lines of the two chips being aligned along the third direction. Back-to-back stacking refers to the bottom surfaces of two chips being substantially aligned along the third direction. Front-to-back stacking refers to the top surface of one chip being substantially aligned with the bottom surface of the other chip being substantially aligned along the third direction. Unless a logic chip or a memory chip is defined, "chip" may refer to either a logic chip or a memory chip.

[0093] One possibility is that in the case of two chips connected face-to-face, their bonding surfaces (positions aligned along the third direction of the intermediate conductive vias) are electrically connected via a hybrid bonding structure (Hyperbonding) (also called bonding pillars), and in the case of two chips connected back-to-back or two chips connected front-to-back, their bonding surfaces (positions aligned along the third direction of the intermediate conductive vias) are electrically connected via conductive bumps (UBumps) (also called microbumps).

[0094] As another possibility, in the case of two chips connected face-to-face, two chips connected back-to-back, or two chips connected front-to-back, the bonding surfaces of both chips (positions aligned along the third direction of the intermediate conductive vias) are all connected via a hybrid bonding structure, i.e., the bonding surfaces between two chips connected face-to-face (positions aligned along the third direction of the intermediate conductive vias) are electrically connected via a hybrid bonding structure, and the bonding surfaces between two chips connected back-to-back (positions aligned along the third direction of the intermediate conductive vias) and the bonding surfaces between two chips connected front-to-back (positions aligned along the third direction of the intermediate conductive vias) are also electrically connected via a hybrid bonding structure.

[0095] As yet another possibility, in the case of two chips connected face-to-face, two chips connected back-to-back, or two chips connected front-to-back, their joint surfaces (positions aligned along the third direction of the intermediate conductive vias) are all connected via conductive bumps. That is, the joint surfaces (positions aligned along the third direction of the intermediate conductive vias) between the two chips connected face-to-face are connected via conductive bumps, and the joint surfaces (positions aligned along the third direction of the intermediate conductive vias) between the two chips connected back-to-back and the joint surfaces (positions aligned along the third direction of the intermediate conductive vias) between the two chips connected front-to-back are also connected via conductive bumps.

[0096] Here, the above chip may refer to the logic chip 40 or the memory chip 10.

[0097] Compared with the conductive bump process, the hybrid bonding process allows for face-to-face connection, which allows for the chips to be closely attached with almost no gaps, significantly reducing the height of the chip stacking structure, which is one of the advantages of face-to-face stacking. Of course, two chips connected back-to-back can also be connected via the hybrid bonding structure, but the connection performance is inferior to that of the conductive bump process.

[0098] The logic chip 40 or memory chip can be divided into a high-level transmission area and a low-level transmission area. The arrows in the following Figures 9A to 12B are all located in the high-level transmission area of ​​the chip. In particular, the high-level transmission area and the low-level transmission area in the embodiment of the present invention are merely two areas for distinguishing between two areas of the memory chip, and are not otherwise limited and have nothing to do with the high-level data and low-level data commonly referred to in data transmission.

[0099] Also, referring to FIG. 9A, logic chip 40 includes m channel signal areas arranged along a first direction, and each memory chip includes m channels (m=4 is shown as an example) arranged along the first direction, and each channel includes a first bank array area, a channel signal area, and a second bank array area distributed sequentially along a second direction.

[0100] When the logic chip 40 and the first memory chip 10A are stacked back-to-back, and the first axis AA' of the logic chip 40 and each memory chip all extend along the first direction (i.e., the first axis AA' divides the corresponding chip into a high-level transmission region and a low-level transmission region), the high-level transmission region of the logic chip 40, the high-level transmission region of the first memory chip 10A, the low-level transmission region of the second memory chip 10B, the low-level transmission region of the third memory chip 10C, and the high-level transmission region of the fourth memory chip 10D are aligned along the third direction, and the low-level transmission region of the logic chip 40, the low-level transmission region of the first memory chip 10A, the high-level transmission region of the second memory chip 10B, the high-level transmission region of the third memory chip 10C, and the low-level transmission region of the fourth memory chip 10D are aligned along the third direction.

[0101] Specifically, the channel signal areas of each chip have the following symmetrical relationship: the m channel signal areas in logic chip 40, the channel signal area of ​​the (i+1)th channel in first memory chip 10A, the channel signal area of ​​the (i+1)th channel in second memory chip 10B, the channel signal area of ​​the m channel in third memory chip 10C, and the channel signal area of ​​the m channel in fourth memory chip 10D are aligned along the third direction, where i is a natural number less than m.

[0102] In FIG. 9A, m=4 is shown as an example. In this case, (1) The fourth channel signal region 44 in the logic chip 40, the channel signal region 11 of the first channel in the first memory chip 10A, the channel signal region 11 of the first channel in the second memory chip 10B, the channel signal region 14 of the fourth channel in the third memory chip 10C, and the channel signal region 14 of the fourth channel in the fourth memory chip 10D are aligned along the third direction.

[0103] (2) The third channel signal region 43 in the logic chip 40, the channel signal region 12 of the second channel in the first memory chip 10A, the channel signal region 12 of the second channel in the second memory chip 10B, the channel signal region 13 of the third channel in the third memory chip 10C, and the channel signal region 13 of the third channel in the fourth memory chip 10D are aligned along the third direction.

[0104] (3) The second channel signal region 42 in the logic chip 40, the channel signal region 13 of the third channel in the first memory chip 10A, the channel signal region 13 of the third channel in the second memory chip 10B, the channel signal region 12 of the second channel in the third memory chip 10C, and the channel signal region 12 of the second channel in the fourth memory chip 10D are aligned along the third direction.

[0105] (4) The first channel signal region 41 in the logic chip 40, the channel signal region 14 of the fourth channel in the first memory chip 10A, the channel signal region 14 of the fourth channel in the second memory chip 10B, the channel signal region 11 of the first channel in the third memory chip 10C, and the channel signal region 11 of the first channel in the fourth memory chip 10D are aligned along the third direction.

[0106] In some other embodiments, referring to FIG. 10A (m=4 is shown as an example), when the logic chip 40 and the first memory chip 10A are stacked back-to-back, and the second axis BB′ of each of the logic chip 40 and each memory chip extends along the first direction (i.e., the second axis BB′ divides the corresponding chip into a high-level transmission region and a low-level transmission region), the low-level transmission region of the logic chip 40, the high-level transmission region of the first memory chip 10A, the high-level transmission region of the second memory chip 10B, the low-level transmission region of the third memory chip 10C, and the low-level transmission region of the fourth memory chip 10D are aligned along the third direction, and the high-level transmission region of the logic chip 40, the low-level transmission region of the first memory chip 10A, the low-level transmission region of the second memory chip 10B, the high-level transmission region of the third memory chip 10C, and the high-level transmission region of the fourth memory chip 10D are aligned along the third direction.

[0107] Specifically, the channel signal areas of each chip have the following symmetrical relationship: the (i+1)th channel signal areas in logic chip 40, the channel signal area of ​​the (i+1)th channel in first memory chip 10A, the channel signal area of ​​the (m)th channel in second memory chip 10B, the channel signal area of ​​the (m)th channel in third memory chip 10C, and the channel signal area of ​​the (i+1)th channel in fourth memory chip 10D are aligned along the third direction, where i is a natural number less than m.

[0108] In FIG. 10A, m=4 is shown as an example. In this case, (1) The first channel signal region 41 in the logic chip 40, the channel signal region 11 of the first channel in the first memory chip 10A, the channel signal region 14 of the fourth channel in the second memory chip 10B, the channel signal region 14 of the fourth channel in the third memory chip 10C, and the channel signal region 11 of the first channel in the fourth memory chip 10D are aligned along the third direction.

[0109] (2) The second channel signal region 42 in the logic chip 40, the channel signal region 12 of the second channel in the first memory chip 10A, the channel signal region 13 of the third channel in the second memory chip 10B, the channel signal region 13 of the third channel in the third memory chip 10C, and the channel signal region 12 of the second channel in the fourth memory chip 10D are aligned along the third direction.

[0110] (3) The third channel signal region 43 in the logic chip 40, the channel signal region 13 of the third channel in the first memory chip 10A, the channel signal region 12 of the second channel in the second memory chip 10B, the channel signal region 12 of the second channel in the third memory chip 10C, and the channel signal region 13 of the third channel in the fourth memory chip 10D are aligned along the third direction.

[0111] (4) The fourth channel signal region 44 in the logic chip 40, the channel signal region 14 of the fourth channel in the first memory chip 10A, the channel signal region 11 of the first channel in the second memory chip 10B, the channel signal region 11 of the first channel in the third memory chip 10C, and the channel signal region 14 of the fourth channel in the fourth memory chip 10D are aligned along the third direction.

[0112] To put it simply, the layout of logic chip 40 and fourth memory chip 10D is the same in FIGS. 9A to 10B.

[0113] 9B and 10B, the channel signal areas of each channel of the memory chip and the logic chip are both divided into 2x2 via areas distributed in an array. Referring to FIG. 9A or 9B, the multiple channel signal areas aligned along the third direction have the following characteristics:

[0114] (1) The fourth via region 54 belonging to the logic chip 40, the first via region 21 belonging to the first memory chip 10A, the second via region 22 belonging to the second memory chip 10B, the third via region 23 belonging to the third memory chip 10C, and the fourth via region 24 belonging to the fourth memory chip 10D are aligned along the third direction.

[0115] (2) The third via region 53 belonging to the logic chip 40, the second via region 22 belonging to the first memory chip 10A, the first via region 21 belonging to the second memory chip 10B, the fourth via region 24 belonging to the third memory chip 10C, and the third via region 23 belonging to the fourth memory chip 10D are aligned along the third direction.

[0116] (3) The second via region 52 belonging to the logic chip 40, the third via region 23 belonging to the first memory chip 10A, the fourth via region 24 belonging to the second memory chip 10B, the first via region 21 belonging to the third memory chip 10C, and the second via region 22 belonging to the fourth memory chip 10D are aligned along the third direction.

[0117] (4) The first via region 51 belonging to the logic chip 40, the fourth via region 24 belonging to the first memory chip 10A, the third via region 23 belonging to the second memory chip 10B, the second via region 22 belonging to the third memory chip 10C, and the first via region 21 belonging to the fourth memory chip 10D are aligned along the third direction.

[0118] In some embodiments, when each conductive via group includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via distributed in a 2x2 array, referring to Figure 9B or Figure 10B, each via area of ​​the memory chip and the logic chip 40 includes n conductive via groups having the same distribution positions, each conductive via group has a third axis CC' and a fourth axis DD', the third axis CC' is parallel to the first axis AA', the fourth axis DD' and the third axis CC' are perpendicular to each other and intersect at the center of the conductive via group to which it belongs, the first conductive via D0 and the second conductive via D1 are symmetrical with respect to the third axis CC' of the conductive via group to which it belongs, the third conductive via D2 and the fourth conductive via D3 are symmetrical with respect to the third axis CC' of the conductive via group to which it belongs, and the first conductive via D0 and the fourth conductive via D3 are symmetrical with respect to the fourth axis DD' of the conductive via group to which it belongs.

[0119] For multiple via fields aligned along the third direction: (1) The fourth conductive via D3 belonging to the logic chip 40, the first conductive via D0 belonging to the first memory chip 10A, the second conductive via D1 belonging to the second memory chip 10B, the third conductive via D2 belonging to the third memory chip 10C, and the fourth conductive via D3 belonging to the fourth memory chip 10D are aligned along the third direction.

[0120] (2) The third conductive via D2 belonging to the logic chip 40, the second conductive via D1 belonging to the first memory chip 10A, the first conductive via D0 belonging to the second memory chip 10B, the fourth conductive via D3 belonging to the third memory chip 10C, and the third conductive via D2 belonging to the fourth memory chip 10D are aligned along the third direction.

[0121] (3) The second conductive via D1 belonging to the logic chip 40, the third conductive via D2 belonging to the first memory chip 10A, the fourth conductive via D3 belonging to the second memory chip 10B, the first conductive via D0 belonging to the third memory chip 10C, and the second conductive via D1 belonging to the fourth memory chip 10D are aligned along the third direction.

[0122] (4) The first conductive via D0 belonging to the logic chip 40, the fourth conductive via D3 belonging to the first memory chip 10A, the third conductive via D2 belonging to the second memory chip 10B, the second conductive via D1 belonging to the third memory chip 10C, and the first conductive via D0 belonging to the fourth memory chip 10D are aligned along a third direction, where multiple conductive vias aligned along the third direction are combined to form one conductive channel.

[0123] In some other embodiments, referring to FIG. 11A (m=4 is shown as an example), when the logic chip 40 and the first memory chip 10A are stacked back-to-back, and the first axis AA′ of each of the logic chip 40 and each memory chip extends along the first direction (i.e., the first axis AA′ divides the corresponding chip into a high-level transmission region and a low-level transmission region), the low-level transmission region of the logic chip 40, the high-level transmission region of the first memory chip 10A, the low-level transmission region of the second memory chip 10B, the low-level transmission region of the third memory chip 10C, and the high-level transmission region of the fourth memory chip 10D are aligned along the third direction, and the high-level transmission region of the logic chip 40, the low-level transmission region of the first memory chip 10A, the high-level transmission region of the second memory chip 10B, the high-level transmission region of the third memory chip 10C, and the low-level transmission region of the fourth memory chip 10D are aligned along the third direction.

[0124] Specifically, the channel signal areas of each chip have the following symmetrical relationship: the (i+1)th channel signal areas in logic chip 40, the channel signal area of ​​the (i+1)th channel in first memory chip 10A, the channel signal area of ​​the (i+1)th channel in second memory chip 10B, the channel signal area of ​​the (m+1)th channel in third memory chip 10C, and the channel signal area of ​​the (m)th channel in fourth memory chip 10D are aligned along the third direction, where i is a natural number less than m.

[0125] In FIG. 11A, m=4 is shown as an example. In this case, (1) The first channel signal region 41 in the logic chip 40, the channel signal region 11 of the first channel in the first memory chip 10A, the channel signal region 11 of the first channel in the second memory chip 10B, the channel signal region 14 of the fourth channel in the third memory chip 10C, and the channel signal region 14 of the fourth channel in the fourth memory chip 10D are aligned along the third direction.

[0126] (2) The second channel signal region 42 in the logic chip 40, the channel signal region 12 of the second channel in the first memory chip 10A, the channel signal region 12 of the second channel in the second memory chip 10B, the channel signal region 13 of the third channel in the third memory chip 10C, and the channel signal region 13 of the third channel in the fourth memory chip 10D are aligned along the third direction.

[0127] (3) The third channel signal region 43 in the logic chip 40, the channel signal region 13 of the third channel in the first memory chip 10A, the channel signal region 13 of the third channel in the second memory chip 10B, the channel signal region 12 of the second channel in the third memory chip 10C, and the channel signal region 12 of the second channel in the fourth memory chip 10D are aligned along the third direction.

[0128] (4) The fourth channel signal region 44 in the logic chip 40, the channel signal region 14 of the fourth channel in the first memory chip 10A, the channel signal region 14 of the fourth channel in the second memory chip 10B, the channel signal region 11 of the first channel in the third memory chip 10C, and the channel signal region 11 of the first channel in the fourth memory chip 10D are aligned along the third direction.

[0129] In some other embodiments, referring to FIG. 12A (where m=4 is shown as an example), when m=4, the logic chip 40 and the first memory chip 10A are stacked back-to-back, and the second axis BB′ of each of the logic chip 40 and each memory chip extends along the first direction (i.e., the second axis BB′ divides the corresponding chip into a high-level transmission region and a low-level transmission region), the high-level transmission region of the logic chip 40, the high-level transmission region of the first memory chip 10A, the high-level transmission region of the second memory chip 10B, the low-level transmission region of the third memory chip 10C, and the low-level transmission region of the fourth memory chip 10D are aligned along the third direction, and the low-level transmission region of the logic chip 40, the low-level transmission region of the first memory chip 10A, the low-level transmission region of the second memory chip 10B, the high-level transmission region of the third memory chip 10C, and the high-level transmission region of the fourth memory chip 10D are aligned along the third direction.

[0130] Specifically, the channel signal areas of each chip have the following symmetrical relationship: the m channel signal areas in logic chip 40, the channel signal area of ​​the (i+1)th channel in first memory chip 10A, the channel signal area of ​​the m channel in second memory chip 10B, the channel signal area of ​​the m channel in third memory chip 10C, and the channel signal area of ​​the (i+1)th channel in fourth memory chip 10D are aligned along the third direction, where i is a natural number less than m.

[0131] (1) The fourth channel signal region 44 in the logic chip 40, the channel signal region 11 of the first channel in the first memory chip 10A, the channel signal region 14 of the fourth channel in the second memory chip 10B, the channel signal region 14 of the fourth channel in the third memory chip 10C, and the channel signal region 11 of the first channel in the fourth memory chip 10D are aligned along the third direction.

[0132] (2) The third channel signal region 43 in the logic chip 40, the channel signal region 12 of the second channel in the first memory chip 10A, the channel signal region 13 of the third channel in the second memory chip 10B, the channel signal region 13 of the third channel in the third memory chip 10C, and the channel signal region 12 of the second channel in the fourth memory chip 10D are aligned along the third direction.

[0133] (3) The second channel signal region 42 in the logic chip 40, the channel signal region 13 of the third channel in the first memory chip 10A, the channel signal region 12 of the second channel in the second memory chip 10B, the channel signal region 12 of the second channel in the third memory chip 10C, and the channel signal region 13 of the third channel in the fourth memory chip 10D are aligned along the third direction.

[0134] (4) The first channel signal region 41 in the logic chip 40, the channel signal region 14 of the fourth channel in the first memory chip 10A, the channel signal region 11 of the first channel in the second memory chip 10B, the channel signal region 11 of the first channel in the third memory chip 10C, and the channel signal region 14 of the fourth channel in the fourth memory chip 10D are aligned along the third direction.

[0135] 11A to 12B, the logic chip 40 and the second memory chip 10B are arranged in the same manner.

[0136] 11B and 12B, in some embodiments, the channel signal areas of each channel of the memory chip and the logic chip 40 are both divided into 2x2 via areas distributed in an array. Referring to FIGS. 11B and 12B, for multiple channel signal areas aligned along the third direction: (1) The second via region 52 belonging to the logic chip 40, the first via region 21 belonging to the first memory chip 10A, the second via region 22 belonging to the second memory chip 10B, the third via region 23 belonging to the third memory chip 10C, and the fourth via region 24 belonging to the fourth memory chip 10D are aligned along the third direction.

[0137] (2) The first via region 51 belonging to the logic chip 40, the second via region 22 belonging to the first memory chip 10A, the first via region 21 belonging to the second memory chip 10B, the fourth via region 24 belonging to the third memory chip 10C, and the third via region 23 belonging to the fourth memory chip 10D are aligned along the third direction.

[0138] (3) The fourth via region 54 belonging to the logic chip 40, the third via region 23 belonging to the first memory chip 10A, the fourth via region 24 belonging to the second memory chip 10B, the first via region 21 belonging to the third memory chip 10C, and the second via region 22 belonging to the fourth memory chip 10D are aligned along the third direction.

[0139] (4) The third via region 53 belonging to the logic chip 40, the fourth via region 24 belonging to the first memory chip 10A, the third via region 23 belonging to the second memory chip 10B, the second via region 22 belonging to the third memory chip 10C, and the first via region 21 belonging to the fourth memory chip 10D are aligned along the third direction.

[0140] 11B or 12B, when each conductive via group includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via distributed in a 2x2 array, referring to FIG. 11B or 12B, each via area of ​​the memory chip and the logic chip 40 includes n conductive via groups having the same distribution positions, each conductive via group has a third axis CC' and a fourth axis DD', the third axis CC' is parallel to the first axis AA', the fourth axis DD' and the third axis CC' are perpendicular to each other and intersect at the center of the conductive via group to which it belongs, the first conductive via D0 and the second conductive via D1 are symmetrical with respect to the third axis CC' of the conductive via group to which it belongs, the third conductive via D2 and the fourth conductive via D3 are symmetrical with respect to the third axis CC' of the conductive via group to which it belongs, and the first conductive via D0 and the fourth conductive via D3 are symmetrical with respect to the fourth axis DD' of the conductive via group to which it belongs.

[0141] For multiple via fields aligned along the third direction: (1) The second conductive via D1 belonging to the logic chip 40, the first conductive via D0 belonging to the first memory chip 10A, the second conductive via D1 belonging to the second memory chip 10B, the third conductive via D2 belonging to the third memory chip 10C, and the fourth conductive via D3 belonging to the fourth memory chip 10D are aligned along the third direction.

[0142] (2) The first conductive via D0 belonging to the logic chip 40, the second conductive via D1 belonging to the first memory chip 10A, the first conductive via D0 belonging to the second memory chip 10B, the fourth conductive via D3 belonging to the third memory chip 10C, and the third conductive via D2 belonging to the fourth memory chip 10D are aligned along the third direction.

[0143] (3) The fourth conductive via D3 belonging to the logic chip 40, the third conductive via D2 belonging to the first memory chip 10A, the fourth conductive via D3 belonging to the second memory chip 10B, the first conductive via D0 belonging to the third memory chip 10C, and the second conductive via D1 belonging to the fourth memory chip 10D are aligned along the third direction.

[0144] (4) The third conductive via D2 belonging to the logic chip 40, the fourth conductive via D3 belonging to the first memory chip 10A, the third conductive via D2 belonging to the second memory chip 10B, the second conductive via D1 belonging to the third memory chip 10C, and the first conductive via D0 belonging to the fourth memory chip 10D are aligned along the third direction.

[0145] Here, a plurality of conductive vias aligned along the third direction are connected to form one conductive channel.

[0146] As can be seen from the above, in each embodiment shown in Figures 9 to 12, the multiple conductive vias aligned in the third direction are the first conductive via D0, the second conductive via D1, the third conductive via D2, and the fourth conductive via D3, respectively, thereby realizing the rotational connection of Figure 2B using the direct connection configuration as shown in Figure 2A, and the chip stacking structure formed thereby not only has relatively low parasitic resistance but also low parasitic capacitance, and can also realize face-to-face stacking.

[0147] The signal transmission principle will be explained using the stacking method shown in FIGS. 9A and 9B as an example, but other cases should be understood appropriately.

[0148] 9A and 9B, taking m=4 as an example, each memory chip includes four channels, and each stacking unit includes 16 channels, corresponding to 16 channel signal areas. Referring to FIG. 13, a schematic diagram of signal transmission for each chip in the chip stacking structure is shown, particularly, FIG. 13 shows the top surface of each chip. As shown in FIG. 13, the fourth to first channel signal areas of logic chip 40 are sequentially designated S0, S1, S2, and S3. The four channel signal areas corresponding sequentially to the first through fourth channels in first memory chip 10A are designated CH0, CH1, CH2, and CH3. The four channel signal areas corresponding sequentially to the first through fourth channels in second memory chip 10B are designated CH4, CH5, CH6, and CH7. The four channel signal areas corresponding sequentially to the first through fourth channels in third memory chip 10C are designated CH8, CH9, CH10, and CH11. The four channel signal areas corresponding sequentially to the first through fourth channels in fourth memory chip 10D are designated CH12, CH13, CH14, and CH15. Each of these 16 channels has its own control signal. Figure 13 shows a schematic diagram of the transmission of the four types of control signals. There are chip select signals (CS_0 to CS_15), virtual channel signals (PC_0 to PC_15), write enable signals (WE_0 to WE_15), and memory bank address signals (BA_0 to BA_15), and of course there are many other control signals, such as a command address signal CA, a memory bank group signal BG, a read enable signal, etc. In the following, only CS_0 to CS_15 will be specifically described as an example.

[0149] Referring to Figures 14 and 15, in each channel of logic chip 40, four conductive vias symmetrical with respect to the first and second axes are used to transmit chip select signals; taking channel S0 in logic chip 40 as an example, the fourth via D3 (in the fourth via region) is used to transmit CS_0, the third via D2 (in the third via region) is used to transmit CS_4, the second via D1 (in the second via region) is used to transmit CS_8, and the first via D0 (in the first via region) is used to transmit CS_12. CS_0 is transmitted upwards sequentially via the fourth via D3 (fourth via region of channel S0) of logic chip 40, the first via D0 (first via region 21 of channel CH0) of first memory chip 10A, the second via D1 (second via region 22 of channel CH4) of second memory chip 10B, the third via D2 (third via region 23 of channel CH8) of third memory chip 10C, the fourth via D3 (fourth via region 24 of channel CH12) of fourth memory chip 10D, etc. In this transmission path, CS_0 is input to channel CH0 of first memory chip 10A in each stacked unit via the first via D0, thereby exerting a control effect on the corresponding part. However, since no driving circuit is arranged in the second via D1, the third via D2, and the fourth via D3 and they are electrically isolated from the internal circuits of the chips to which they belong, CS_0 is not input to the second memory chip 10B, the third memory chip 10C, and the fourth memory chip 10D.

[0150] Similarly, CS_4 is transmitted upward sequentially via the third via D2 of the logic chip 40 (third via region of channel S0), the second via D1 of the first memory chip 10A (second via region of channel CH0), the first via D0 of the second memory chip 10B (first via region of channel CH4), the fourth via D3 of the third memory chip 10C (fourth via region of channel CH8), the third via D2 of the fourth memory chip 10D (third via region of channel CH12), etc. In this transmission path, CS_4 is input to channel CH4 of the second memory chip 10B in each stacked unit via the corresponding first via D0, thereby exerting a control effect on the corresponding part. However, since no driving circuit is arranged in the second via D1, the third via D2, and the fourth via D3 and they are electrically isolated from the internal circuits of the chips to which they belong, CS_0 is not input to the first memory chip 10A, the third memory chip 10C, and the fourth memory chip 10D.

[0151] ...The rest should be understood in the same way.

[0152] In this way, from a physical perspective, the conductive vias of chip stack structure 40 still have a direct connection configuration, but from the perspective of the absolute positions of the conductive vias on the active surface, the conductive vias can be functionally regarded as a rotated configuration, that is, the physical direct connection configuration achieves the same signal transmission effect as in Figure 2B (i.e., a rotated transmission effect such as via D0-via D1-via D2-via D3...). In short, chip stack structure 40 of Figure 2B requires a physical spiral structure, which necessarily includes a lateral interconnection structure, while chip stack structure 40 of Figure 14 has a physical direct connection structure and does not require a lateral interconnection structure, which greatly reduces parasitic resistance and greatly improves transmission speed and performance.

[0153] In another embodiment of the present invention, referring to Figure 15, an exemplary structural diagram of a configuration of a memory 80 according to an embodiment of the present invention is shown. As shown in Figure 15, the memory 80 includes at least the above-described chip stack structure 70. The memory 80 may be a static random access memory (SRAM), a dynamic random access memory (DRAM), a synchronous dynamic random access memory (SDRAM), a double data rate synchronous dynamic random access memory (DDR SDRAM), or the like, and is not particularly limited here.

[0154] The above are merely preferred embodiments of the present invention and do not limit the scope of protection of the present invention. In the present invention, the terms "comprise," "include," or any other variant thereof are intended to be non-exclusive inclusive, meaning that a process, method, article, or apparatus comprising a set of elements not only includes those elements but also other elements not explicitly listed, as well as inherent elements of the process, method, article, or apparatus. Unless otherwise specified, an element defined by the expression "comprises" does not exclude the presence of other similar elements in the process, method, component, or apparatus comprising that element. The numbering of the above embodiments of the present invention does not indicate the relative merits of the embodiments, but is for convenience of description. The methods disclosed in the various method embodiments provided by the present invention can be arbitrarily combined to obtain new method embodiments, unless inconsistent. The features disclosed in the various product embodiments provided by the present invention can be arbitrarily combined to obtain new product embodiments, unless inconsistent. The features disclosed in the various method or apparatus embodiments provided by the present invention can be arbitrarily combined to obtain new method or apparatus embodiments, unless inconsistent. The above content is merely a specific embodiment of the present invention, and the protection scope of the present invention is not limited thereto. Any modifications or replacements that can be easily thought of by those skilled in the art within the technical scope disclosed in the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present application shall be governed by the appended claims.

Claims

1. A memory chip (10), comprising: The memory chip (10) includes m channels sequentially arranged along a first direction, and the memory chip (10) has a chip axis that extends along a second direction and passes through the center of the memory chip (10), the m channels are symmetrical with respect to the chip axis, each channel includes a first bank array region, channel signal regions (11, 12, 13, 14), and a second bank array region sequentially distributed along the second direction, the center of each channel signal region (11, 12, 13, 14) coincides with the center of the channel to which it belongs, m is a positive integer, and the first direction is perpendicular to the second direction. Each of the channel signal regions (11, 12, 13, 14) has a first axis and a second axis, the first axis extends along the first or second direction, the second axis and the first axis are perpendicular to each other and intersect at the center of the channel signal region (11, 12, 13, 14) to which they belong, and each of the channel signal regions (11, 12, 13, 14) is divided into 2 × 2 via regions distributed in an array, and the first via Region (21) and the second via region (22) are symmetrical along the first axis of the channel signal regions (11, 12, 13, 14) to which they belong, the third via region (23) and the fourth via region (24) are symmetrical along the first axis of the channel signal regions (11, 12, 13, 14) to which they belong, and the first via region (21) and the fourth via region (24) are symmetrical along the second axis of the channel signal regions (11, 12, 13, 14) to which they belong. Each of the via regions includes n conductive via groups, the n conductive via groups penetrate the substrate of the memory chip (10) along a direction perpendicular to the active surface of the memory chip (10), where n is a natural number, the areas of the m channel signal regions (11, 12, 13, 14) are the same, and the distribution positions of the conductive via groups in the m channel signal regions (11, 12, 13, 14) are all the same. In the same channel signal region (11, 12, 13, 14), the n conductive via groups in the first via region (21) and the n conductive via groups in the second via region (22) are symmetrical with respect to a first axis of the channel signal region (11, 12, 13, 14) to which they belong, the n conductive via groups in the third via region (23) and the n conductive via groups in the fourth via region (24) are symmetrical with respect to the first axis of the channel signal region (11, 12, 13, 14) to which they belong, and the n conductive via groups in the first via region (21) and the n conductive via groups in the fourth via region (24) are symmetrical with respect to a second axis of the channel signal region (11, 12, 13, 14) to which they belong.

2. Each of the conductive via groups has a third axis and a fourth axis, the third axis and the first axis are parallel, and the fourth axis and the third axis are perpendicular to each other and intersect at the center of the conductive via group to which the conductive via group belongs; When each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via distributed in a 2×2 array, the first conductive via and the second conductive via are symmetrical with respect to a third axis of the conductive via group to which they belong, the third conductive via and the fourth conductive via are symmetrical with respect to the third axis of the conductive via group to which they belong, and the first conductive via and the fourth conductive via are symmetrical with respect to the fourth axis of the conductive via group to which they belong; In each of the channel signal regions (11, 12, 13, 14), the n first conductive vias in the first via region (21) and the n second conductive vias in the second via region (22) are symmetrical with respect to a first axis of the channel signal region (11, 12, 13, 14) to which they belong, the n third conductive vias in the third via region (23) and the n fourth conductive vias in the fourth via region (24) are symmetrical with respect to the first axis of the channel signal region (11, 12, 13, 14) to which they belong, and the n first conductive vias in the first via region (21) and the n fourth conductive vias in the fourth via region (24) are symmetrical with respect to the second axis of the channel signal region (11, 12, 13, 14) to which they belong, the n second conductive vias in the first via region (21) and the n first conductive vias in the second via region (22) are symmetrical with respect to a first axis of the channel signal region (11, 12, 13, 14) to which they belong, the n fourth conductive vias in the third via region (23) and the n third conductive vias in the fourth via region (24) are symmetrical with respect to the first axis of the channel signal region (11, 12, 13, 14) to which they belong, and the n second conductive vias in the first via region (21) and the n third conductive vias in the fourth via region (24) are symmetrical with respect to a second axis of the channel signal region (11, 12, 13, 14) to which they belong, the n third conductive vias in the first via region (21) and the n fourth conductive vias in the second via region (22) are symmetrical with respect to a first axis of the channel signal region (11, 12, 13, 14) to which they belong, the n first conductive vias in the third via region (23) and the n second conductive vias in the fourth via region (24) are symmetrical with respect to the first axis of the channel signal region (11, 12, 13, 14) to which they belong, and the n third conductive vias in the first via region (21) and the n second conductive vias in the fourth via region (24) are symmetrical with respect to the first axis of the channel signal region (11, 12, 13, 14) to which they belong, The n fourth conductive vias in the first via region (21) and the n third conductive vias in the second via region (22) are symmetrical with respect to a first axis of the channel signal region (11, 12, 13, 14) to which they belong, the n second conductive vias in the third via region (23) and the n first conductive vias in the fourth via region (24) are symmetrical with respect to the first axis of the channel signal region (11, 12, 13, 14) to which they belong, and the n fourth conductive vias in the first via region (21) and the n first conductive vias in the fourth via region (24) are symmetrical with respect to a second axis of the channel signal region (11, 12, 13, 14) to which they belong. The memory chip (10) of claim 1.

3. The memory chip (10) further includes (4 × m × n) first drive circuits (30), the (4 × m × n) first drive circuits (30) are coupled in one-to-one correspondence with (4 × m × n) first conductive vias, and the first drive circuits (30) are coupled to the portion of the first conductive via located on the active surface. The first drive circuit (30) is used to transmit signals transmitted by the correspondingly connected first conductive vias to the internal circuit of the memory chip (10), or to transmit signals generated by the internal circuit of the memory chip (10) to the correspondingly connected first conductive vias. The memory chip (10) according to claim 2.

4. The coordinate position of each conductive via is determined based on the center of the via signal region to which it belongs, and the type of signal transmitted by four of the same conductive vias having the same coordinate position is the same. The conductive vias are manufactured by one or more of the following processes: via-first, via-middle, via-last, and back-side via-last, and different conductive vias in the same memory chip (10) are electrically isolated. A memory chip (10) according to any one of claims 1 to 3.

5. A logic chip (40), The logic chip (40) includes m channel signal regions (41, 42, 43, 44) sequentially arranged along a first direction, and the logic chip (40) has a chip axis that extends along a second direction and passes through the center of the logic chip (40), the m channel signal regions (41, 42, 43, 44) are symmetric with respect to the chip axis, and m is a positive integer. Each of the channel signal areas (41, 42, 43, 44) has a first axis and a second axis, the first axis extending along the first direction or the second direction, the second axis and the first axis being perpendicular to each other and intersecting at the center of the corresponding channel signal area (41, 42, 43, 44), and each of the channel signal areas (41, 42, 43, 44) is divided into 2 x 2 via areas distributed in an array, and a first via area (51) and a second via area (52) are arranged in a row. the region (52) is symmetrical along a first axis of the channel signal region (41, 42, 43, 44) to which it belongs, the third via region (53) and the fourth via region (54) are symmetrical along the first axis of the channel signal region (41, 42, 43, 44) to which it belongs, the first via region (51) and the fourth via region (54) are symmetrical along a second axis of the channel signal region (41, 42, 43, 44) to which it belongs, and the second direction is perpendicular to the first direction; Each of the via regions includes n conductive via groups, the n conductive via groups penetrate the substrate of the logic chip (40) in a direction perpendicular to the active surface of the logic chip (40), where n is a natural number, the m channel signal regions (41, 42, 43, 44) have the same area, and the conductive via groups are all distributed at the same positions in the m channel signal regions (41, 42, 43, 44); In the same channel signal region (41, 42, 43, 44), the n conductive via groups in the first via region (51) and the n conductive via groups in the second via region (52) are symmetrical with respect to a first axis of the channel signal region (41, 42, 43, 44) to which they belong, the n conductive via groups in the third via region (53) and the n conductive via groups in the fourth via region (54) are symmetrical with respect to the first axis of the channel signal region (41, 42, 43, 44) to which they belong, and the n conductive via groups in the first via region (51) and the n conductive via groups in the fourth via region (54) are symmetrical with respect to a second axis of the channel signal region (41, 42, 43, 44) to which they belong.

6. Each of the conductive via groups has a third axis and a fourth axis, the third axis and the first axis are parallel, and the fourth axis and the third axis are perpendicular to each other and intersect at the center of the conductive via group to which the conductive via group belongs; When each of the conductive via groups includes a first conductive via, a second conductive via, a third conductive via, and a fourth conductive via distributed in a 2×2 array, the first conductive via and the second conductive via are symmetrical with respect to a third axis of the conductive via group to which they belong, the third conductive via and the fourth conductive via are symmetrical with respect to the third axis of the conductive via group to which they belong, and the first conductive via and the fourth conductive via are symmetrical with respect to a fourth axis of the conductive via group to which they belong, and in each of the channel signal regions (41, 42, 43, 44), n first conductive vias and n second via regions in the first via region (51) are the n second conductive vias in (52) are symmetrical with respect to a first axis of the channel signal region (41, 42, 43, 44) to which they belong, the n third conductive vias in the third via region (53) and the n fourth conductive vias in the fourth via region (54) are symmetrical with respect to the first axis of the channel signal region (41, 42, 43, 44) to which they belong, and the n first conductive vias in the first via region (51) and the n fourth conductive vias in the fourth via region (54) are symmetrical with respect to the second axis of the channel signal region (41, 42, 43, 44) to which they belong, the n second conductive vias in the first via region (51) and the n first conductive vias in the second via region (52) are symmetrical with respect to a first axis of the channel signal region (41, 42, 43, 44) to which they belong, the n fourth conductive vias in the third via region (53) and the n third conductive vias in the fourth via region (54) are symmetrical with respect to the first axis of the channel signal region (41, 42, 43, 44) to which they belong, and the n second conductive vias in the first via region (51) and the n third conductive vias in the fourth via region (54) are symmetrical with respect to a second axis of the channel signal region (41, 42, 43, 44) to which they belong, the n third conductive vias in the first via region (51) and the n fourth conductive vias in the second via region (52) are symmetrical with respect to a first axis of the channel signal region (41, 42, 43, 44) to which they belong, the n first conductive vias in the third via region (53) and the n second conductive vias in the fourth via region (54) are symmetrical with respect to the first axis of the channel signal region (41, 42, 43, 44) to which they belong, and the n third conductive vias in the first via region (51) and the n second conductive vias in the fourth via region (54) are symmetrical with respect to the first axis of the channel signal region (41, 42, 43, 44) to which they belong, The n fourth conductive vias in the first via region (51) and the n third conductive vias in the second via region (52) are symmetrical with respect to a first axis of the channel signal region (41, 42, 43, 44) to which they belong, the n second conductive vias in the third via region (53) and the n first conductive vias in the fourth via region (54) are symmetrical with respect to the first axis of the channel signal region (41, 42, 43, 44) to which they belong, and the n fourth conductive vias in the first via region (51) and the n first conductive vias in the fourth via region (54) are symmetrical with respect to a second axis of the channel signal region (41, 42, 43, 44) to which they belong. The logic chip (40) according to claim 5.

7. The logic chip (40) further includes (16×m×n) second drive circuits (50), the (16×m×n) second drive circuits (50) being coupled to the (16×m×n) conductive vias in one-to-one correspondence, and the second drive circuits (50) being coupled to portions of the conductive vias located on the active surfaces; The second driving circuit (50) is used to transmit a signal transmitted by the corresponding conductive via to an internal circuit of the logic chip (40), or to transmit a signal generated in the internal circuit of the logic chip (40) to the corresponding conductive via. The logic chip (40) according to claim 6.

8. The coordinate position of each conductive via is determined based on the center of the via signal region to which it belongs, and the type of signal transmitted by four of the same conductive vias having the same coordinate position is the same. The conductive vias are fabricated by one or more processes of a via-first process, a via-middle process, a via-last process, and a backside via-last process, and different conductive vias in the same logic chip (40) are all electrically isolated from each other. The logic chip (40) according to any one of claims 5 to 7.

9. A chip stack structure (70), comprising: A logic chip (40) according to any one of claims 5 to 7, and at least one stacked unit (71), The logic chip (40) and at least one of the stacked units (71) are stacked sequentially along a third direction, and each of the stacked units (71) includes a first memory chip (10A), a second memory chip (10B), a third memory chip (10C), and a fourth memory chip (10D) stacked sequentially along the third direction, the third direction being perpendicular to an active surface of each of the memory chips, and the first memory chip (10A), the second memory chip (10B), the third memory chip (10C), and the fourth memory chip (10D) are all memory chips (10) according to any one of claims 1 to 3; The logic chip (40) and the first memory chip (10A) are stacked in a face-to-back or back-to-back manner, The first memory chip (10A) and the second memory chip (10B) are stacked in a face-to-face configuration. The second memory chip (10B) and the third memory chip (10C) are stacked back-to-back. The third memory chip (10C) and the fourth memory chip (10D) are stacked in a face-to-face configuration, forming a chip stacking structure (70).

10. The logic chip (40) includes m channel signal regions arranged along a first direction, and each of the memory chips (10A, 10B, 10C, 10D) has m channels arranged along the first direction, and each of the channels includes a first bank array region, a channel signal region, and a second bank array region sequentially distributed along a second direction; When the logic chip (40) and the first memory chip (10A) are stacked back to back, and first axes of the logic chip (40) and each of the memory chips (10A, 10B, 10C, 10D) all extend along a first direction, the m-ith channel signal area in the logic chip (40), the channel signal area of ​​the i+1th channel in the first memory chip (10A), the channel signal area of ​​the i+1th channel in the second memory chip (10B), the channel signal area of ​​the m-ith channel in the third memory chip (10C), and the channel signal area of ​​the m-ith channel in the fourth memory chip (10D) are aligned along a third direction, where i is a natural number less than m, or When the logic chip (40) and the first memory chip (10A) are stacked back to back, and the second axes of the logic chip (40) and each of the memory chips (10A, 10B, 10C, 10D) extend along a first direction, the (i+1)th channel signal area in the logic chip (40), the channel signal area of ​​the (i+1)th channel in the first memory chip (10A), the channel signal area of ​​the (m-i)th channel in the second memory chip (10B), the channel signal area of ​​the (m-i)th channel in the third memory chip (10C), and the channel signal area of ​​the (i+1)th channel in the fourth memory chip (10D) are aligned along a third direction, where i is a natural number smaller than m. The chip stacking structure (70) according to claim 9.

11. Each of the channel signal regions is divided into 2x2 via regions distributed in an array. With respect only to the multiple channel signal regions aligned along the third direction, the fourth via region belonging to the logic chip (40), the first via region belonging to the first memory chip (10A), the second via region belonging to the second memory chip (10B), the third via region belonging to the third memory chip (10C), and the fourth via region belonging to the fourth memory chip (10D) are aligned along a third direction; the third via region belonging to the logic chip (40), the second via region belonging to the first memory chip (10A), the first via region belonging to the second memory chip (10B), the fourth via region belonging to the third memory chip (10C), and the third via region belonging to the fourth memory chip (10D) are aligned along a third direction; the second via region belonging to the logic chip (40), the third via region belonging to the first memory chip (10A), the fourth via region belonging to the second memory chip (10B), the first via region belonging to the third memory chip (10C), and the second via region belonging to the fourth memory chip (10D) are aligned along a third direction; the first via region belonging to the logic chip (40), the fourth via region belonging to the first memory chip (10A), the third via region belonging to the second memory chip (10B), the second via region belonging to the third memory chip (10C), and the first via region belonging to the fourth memory chip (10D) are aligned along a third direction; each of the via regions includes n conductive via groups having the same distribution positions, each conductive via group has a third axis and a fourth axis, the third axis is parallel to the first axis, the fourth axis and the third axis are perpendicular to each other and intersect at the center of the conductive via group to which it belongs, and each of the conductive via groups includes 2x2 first conductive vias, second conductive vias, third conductive vias, and fourth conductive vias distributed in a 2x2 array, the first conductive vias and the second conductive vias are symmetrical with respect to the third axis of the conductive via group to which it belongs, the third conductive vias and the fourth conductive vias are symmetrical with respect to the third axis of the conductive via group to which it belongs, and the first conductive vias and the fourth conductive vias are symmetrical with respect to the fourth axis of the conductive via group to which it belongs; For only the via regions aligned along a third direction, the fourth conductive via belonging to the logic chip (40), the first conductive via belonging to the first memory chip (10A), the second conductive via belonging to the second memory chip (10B), the third conductive via belonging to the third memory chip (10C), and the fourth conductive via belonging to the fourth memory chip (10D) are aligned along a third direction; the third conductive via belonging to the logic chip (40), the second conductive via belonging to the first memory chip (10A), the first conductive via belonging to the second memory chip (10B), the fourth conductive via belonging to the third memory chip (10C), and the third conductive via belonging to the fourth memory chip (10D) are aligned along a third direction; the second conductive via belonging to the logic chip (40), the third conductive via belonging to the first memory chip (10A), the fourth conductive via belonging to the second memory chip (10B), the first conductive via belonging to the third memory chip (10C), and the second conductive via belonging to the fourth memory chip (10D) are aligned along a third direction; the first conductive via belonging to the logic chip (40), the fourth conductive via belonging to the first memory chip (10A), the third conductive via belonging to the second memory chip (10B), the second conductive via belonging to the third memory chip (10C), and the first conductive via belonging to the fourth memory chip (10D) are aligned along a third direction; a plurality of conductive vias aligned along the third direction are coupled to form one conductive channel; The chip stack (70) of claim 10.

12. The logic chip (40) includes m channel signal regions arranged along a first direction, each of the memory chips has m channels arranged along the first direction, and each of the channels includes a first bank array region, a channel signal region, and a second bank array region sequentially distributed along a second direction; When the logic chip (40) and the first memory chip (10A) are stacked back to back, and the first axes of the logic chip (40) and each of the memory chips extend along a first direction, the (i+1)th channel signal area in the logic chip (40), the channel signal area of ​​the (i+1)th channel in the first memory chip (10A), the channel signal area of ​​the (i+1)th channel in the second memory chip (10B), the channel signal area of ​​the (m-i)th channel in the third memory chip (10C), and the channel signal area of ​​the (m-i)th channel in the fourth memory chip (10D) are aligned along a third direction, where i is a natural number less than m; or When the logic chip (40) and the first memory chip (10A) are stacked back-to-back, and the second axes of the logic chip (40) and each of the memory chips extend along a first direction, the m-ith channel signal area in the logic chip (40), the channel signal area of ​​the i+1th channel in the first memory chip (10A), the channel signal area of ​​the m-ith channel in the second memory chip (10B), the channel signal area of ​​the m-ith channel in the third memory chip (10C), and the channel signal area of ​​the i+1th channel in the fourth memory chip (10D) are aligned along a third direction, where i is a natural number smaller than m. The chip stacking structure (70) according to claim 9.

13. With respect only to the multiple channel signal regions aligned along the third direction, the second via region belonging to the logic chip (40), the first via region belonging to the first memory chip (10A), the second via region belonging to the second memory chip (10B), the third via region belonging to the third memory chip (10C), and the fourth via region belonging to the fourth memory chip (10D) are aligned along a third direction; the first via region belonging to the logic chip (40), the second via region belonging to the first memory chip (10A), the first via region belonging to the second memory chip (10B), the fourth via region belonging to the third memory chip (10C), and the third via region belonging to the fourth memory chip (10D) are aligned along a third direction; the fourth via region belonging to the logic chip (40), the third via region belonging to the first memory chip (10A), the fourth via region belonging to the second memory chip (10B), the first via region belonging to the third memory chip (10C), and the second via region belonging to the fourth memory chip (10D) are aligned along a third direction; the third via region belonging to the logic chip (40), the fourth via region belonging to the first memory chip (10A), the third via region belonging to the second memory chip (10B), the second via region belonging to the third memory chip (10C), and the first via region belonging to the fourth memory chip (10D) are aligned along a third direction; Each of the via regions includes n conductive via groups having the same distribution positions, and each conductive via group has a third axis and a fourth axis, the third axis is parallel to the first axis, and the fourth axis and the third axis are perpendicular to each other and intersect at the center of the conductive via group to which it belongs; When each of the conductive via groups includes 2×2 first conductive vias, second conductive vias, third conductive vias, and fourth conductive vias distributed in a 2×2 array, the first conductive vias and the second conductive vias are symmetrical with respect to a third axis of the conductive via group to which they belong, the third conductive vias and the fourth conductive vias are symmetrical with respect to the third axis of the conductive via group to which they belong, and the first conductive vias and the fourth conductive vias are symmetrical with respect to a fourth axis of the conductive via group to which they belong, For a plurality of the via areas aligned along a third direction: the second conductive vias belonging to the logic chip (40), the first conductive vias belonging to the first memory chip (10A), the second conductive vias belonging to the second memory chip (10B), the third conductive vias belonging to the third memory chip (10C), and the fourth conductive vias belonging to the fourth memory chip (10D) are aligned along a third direction; the first conductive via belonging to the logic chip (40), the second conductive via belonging to the first memory chip (10A), the first conductive via belonging to the second memory chip (10B), the fourth conductive via belonging to the third memory chip (10C), and the third conductive via belonging to the fourth memory chip (10D) are aligned along a third direction; the fourth conductive via belonging to the logic chip (40), the third conductive via belonging to the first memory chip (10A), the fourth conductive via belonging to the second memory chip (10B), the first conductive via belonging to the third memory chip (10C), and the second conductive via belonging to the fourth memory chip (10D) are aligned along a third direction; the third conductive via belonging to the logic chip (40), the fourth conductive via belonging to the first memory chip (10A), the third conductive via belonging to the second memory chip (10B), the second conductive via belonging to the third memory chip (10C), and the first conductive via belonging to the fourth memory chip (10D) are aligned along a third direction; a plurality of conductive vias aligned along the third direction are coupled to form one conductive channel; The chip stack (70) of claim 12.

14. In the case of two chips connected face-to-face, the positions of the conductive vias of both chips aligned along the third direction are electrically connected by a hybrid bonding process; in the case of two chips connected back-to-back or two chips connected face-to-back, the positions of the conductive vias of both chips aligned along the third direction are electrically connected by a conductive bump bonding process; or In the case of two chips connected face-to-face, or back-to-back, or front-to-back, the vias aligned along the third direction of the conductive vias of both chips are electrically connected by a hybrid bonding process, or In the case of two chips connected face-to-face, or back-to-back, or front-to-back, the vias aligned along the third direction of the conductive vias of both chips are electrically connected by a conductive bump bonding process. The chip stacking structure (70) according to claim 9.

15. A memory (80) comprising the chip stack (70) of claim 9.

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