Display device and manufacturing method thereof

Abstract

A TFT layer (20a) is provided with a plurality of TFTs (9ab) that follow a gate line (14), and at least one lightning rod element (9da) provided near the plurality of TFTs (9ab). Each of the TFTs (9ab) is provided with an island-form first semiconductor layer (12ab) overlapping at least part of the gate line (14) in plan view. Each lightning rod element (9da) is provided with an island-form second semiconductor layer (12da) overlapping at least part of the gate line (14) in plan view. The angle (θd) of the end surface of the second semiconductor layer (12da) with respect to the upper surface of a resin substrate (10) is greater than the angle (θab) of the end surface of the first semiconductor layer (12ab) with respect to the upper surface of the resin substrate (10).

Description

[Technical Field]

[0001] The present invention relates to a display device and a manufacturing method thereof. [Background technology]

[0002] In recent years, self-luminous organic electroluminescence (EL) display devices using organic electroluminescence (EL) elements have been attracting attention as display devices to replace liquid crystal display devices. For example, a flexible organic EL display device has been proposed, which includes a TFT layer on a flexible resin substrate, in which a plurality of thin film transistors (TFTs) for driving organic EL elements are formed for each sub-pixel constituting a display area.

[0003] Incidentally, in organic EL display devices, ESD damage to TFTs may occur due to electrostatic discharge (hereinafter also referred to as "ESD") that occurs during the manufacturing process.

[0004] In order to suppress the effects of ESD damage, for example, Patent Document 1 proposes a semiconductor device (organic EL display device) that includes a protection circuit having two elements: a protection diode made up of a transistor, and a capacitance component added using one of the gates of the transistor. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-77816 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the protection circuit described in Patent Document 1 functions mainly after the organic EL display device is completed (manufactured), and is not effective enough in suppressing ESD damage that occurs during the manufacturing process. Furthermore, if the transistors that make up the protection circuit are themselves damaged by ESD that occurs during the manufacturing process of the organic EL display device, there is a risk of leakage between unnecessary electrodes and the wiring that should be protected. Furthermore, when a protection circuit is provided for each scan line (signal wiring), a protection circuit composed of simpler elements is required for organic EL display devices with narrow frames that occupy a small area in the frame area surrounding the display area.

[0007] The present invention has been made in consideration of these points, and its purpose is to suppress ESD damage to TFTs caused by ESD that occurs during the manufacturing process of a display device, by using a lightning rod element that can be introduced into a display device with a narrow frame. [Means for solving the problem]

[0008] In order to achieve the above object, a display device according to the present invention comprises a base substrate, and a thin film transistor layer provided on the base substrate, in which a semiconductor film, an inorganic insulating film, and a metal film are laminated in this order; the thin film transistor layer comprises a plurality of signal wirings formed by the metal film and arranged so as to extend parallel to one another in one direction; a plurality of thin film transistors arranged along each of the signal wirings corresponding to a plurality of sub-pixels that constitute a display area; and at least one lightning rod element provided along each of the signal wirings in the vicinity of the plurality of thin film transistors; each of the thin film transistors comprises a first semiconductor layer formed by the semiconductor film and arranged in an island shape so as to overlap at least a portion of each of the signal wirings in a planar view; and each of the lightning rod elements comprises a second semiconductor layer formed by the semiconductor film and arranged in an island shape so as to overlap at least a portion of each of the signal wirings in a planar view; and the display device is characterized in that, in a cross-sectional view, an angle of an end face of the second semiconductor layer with respect to an upper surface of the base substrate is larger than an angle of the end face of the first semiconductor layer with respect to the upper surface of the base substrate.

[0009] A method for manufacturing a display device according to the present invention includes a base substrate, and a thin film transistor layer provided on the base substrate and including a semiconductor film, an inorganic insulating film, and a metal film laminated in this order, the thin film transistor layer including a plurality of signal wirings formed by the metal film and extending parallel to one another in one direction, a plurality of thin film transistors provided along each of the signal wirings corresponding to a plurality of sub-pixels that form a display area, and at least one lightning rod element provided along each of the signal wirings in the vicinity of the plurality of thin film transistors, each of the thin film transistors including a first semiconductor layer formed by the semiconductor film and provided in an island shape so as to overlap at least a portion of each of the signal wirings in a planar view, and each of the lightning rod elements including a second semiconductor layer formed by the semiconductor film and provided in an island shape so as to overlap at least a portion of each of the signal wirings in a planar view, The thin film transistor layer formation process for forming a thin film transistor layer includes a semiconductor layer formation process of forming a semiconductor film on a substrate surface on which a lower layer of the semiconductor film has been formed, and then patterning the semiconductor film to form the first semiconductor layer and the second semiconductor layer; an inorganic insulating film formation process of forming the inorganic insulating film on the substrate surface on which the first semiconductor layer and the second semiconductor layer have been formed, so as to cover the first semiconductor layer and the second semiconductor layer; and a wiring layer formation process of forming the metal film on the substrate surface on which the inorganic insulating film has been formed, and then patterning the metal film to form the plurality of signal wirings, wherein in the semiconductor layer formation process, by controlling a photoresist contact angle of the semiconductor film and / or etching conditions, an angle of the end face of the second semiconductor layer with respect to the upper surface of the base substrate is made larger in a cross-sectional view than an angle of the end face of the first semiconductor layer with respect to the upper surface of the base substrate. [Effects of the Invention]

[0010] According to the present invention, it is possible to suppress ESD damage to TFTs caused by ESD that occurs during the manufacturing process of a display device, by using a lightning rod element that can be introduced into a display device with a narrow frame. [Brief explanation of the drawings]

[0011] [Figure 1] FIG. 1 is a plan view showing a schematic configuration of an organic EL display device according to a first embodiment of the present invention. [Figure 2] FIG. 2 is a plan view of a display region of the organic EL display device according to the first embodiment of the present invention. [Figure 3] FIG. 3 is a cross-sectional view of a display region of the organic EL display device according to the first embodiment of the present invention. [Figure 4] FIG. 4 is an equivalent circuit diagram showing a pixel circuit of the organic EL display device according to the first embodiment of the present invention. [Figure 5] FIG. 5 is a schematic plan view showing the arrangement of pixel circuits in the organic EL display device according to the first embodiment of the present invention. [Figure 6] FIG. 6 is a schematic plan view showing an arrangement of pixel circuits and lightning rod elements of the organic EL display device according to the first embodiment of the present invention. [Figure 7] FIG. 7 is an enlarged plan view of the area surrounded by the two-dot chain line in FIG. 6, showing the TFTs and lightning rod elements that constitute the pixel circuits of the organic EL display device according to the first embodiment of the present invention. [Figure 8] FIG. 8 is an enlarged cross-sectional view taken along line VIII-VIII in FIG. 7, showing the TFTs and lightning rod elements that constitute the pixel circuit of the organic EL display device according to the first embodiment of the present invention. [Figure 9] FIG. 9 is a cross-sectional view showing an organic EL layer that constitutes the organic EL display device according to the first embodiment of the present invention. [Figure 10] FIG. 10 is a schematic plan view showing the arrangement of pixel circuits and first and second lightning rod elements of an organic EL display device according to a second embodiment of the present invention, and corresponds to FIG. [Figure 11] FIG. 11 is an enlarged plan view of the area within the two-dot chain line in FIG. 10 (a), showing the TFT and first lightning rod element that constitute the pixel circuit of the organic EL display device according to the second embodiment of the present invention, and corresponds to FIG. 7. [Figure 12]FIG. 12 is an enlarged plan view of the area within the two-dot chain line in (b) of FIG. 10, showing the TFT and second lightning rod element that constitute the pixel circuit of the organic EL display device according to the second embodiment of the present invention, and corresponds to FIG. 7. DETAILED DESCRIPTION OF THE INVENTION

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0013] First Embodiment 1 to 9 show a first embodiment of a display device according to the present invention. In the following embodiments, an organic EL display device including organic EL elements will be exemplified as a display device including light-emitting elements. Here, FIG. 1 is a plan view showing a schematic configuration of an organic EL display device 50a of this embodiment. FIG. 2 is a plan view of a display region D of the organic EL display device 50a. FIG. 3 is a cross-sectional view of the display region D of the organic EL display device 50a. FIG. 4 is a cross-sectional view of the organic EL display device 50a. 1 is an equivalent circuit diagram showing a pixel circuit C. FIG. 5 is a schematic plan view showing the arrangement of pixel circuits C of the organic EL display device 50a. FIG. 6 is a schematic plan view showing the arrangement of pixel circuits C and lightning rod elements 9da of the organic EL display device 50a. FIG. 7 is an enlarged plan view of the area within the two-dot chain line in FIG. 6, showing TFTs 9ab (first TFT 9a, second TFT 9b) and lightning rod elements 9da that constitute the pixel circuits C of the organic EL display device 50a. FIG. 8 is an enlarged cross-sectional view taken along line VIII-VIII in FIG. 7, showing the TFTs 9ab and lightning rod elements 9da that constitute the pixel circuits C of the organic EL display device 50a. FIG. 9 is a cross-sectional view showing an organic EL layer 23 that constitutes the organic EL display device 50a. Note that the upper layer of the first wiring layer, which will be described later, is omitted in FIGS. 7 and 8.

[0014] 1, the organic EL display device 50a includes, for example, a rectangular display area D for displaying an image, and a frame area F provided in a frame shape around the display area D. Note that, although the present embodiment illustrates a rectangular display area D, this rectangular shape also includes, for example, a substantially rectangular shape with arc-shaped sides, arc-shaped corners, or a shape with a notch in one of the sides.

[0015] In the display region D, a plurality of sub-pixels P are arranged in a matrix, as shown in Fig. 2. In the display region D, for example, a sub-pixel P having a red light-emitting region Lr for displaying red, a sub-pixel P having a green light-emitting region Lg for displaying green, and a sub-pixel P having a blue light-emitting region Lb for displaying blue are arranged adjacent to one another, as shown in Fig. 2. In the display region D, one pixel is formed by, for example, three adjacent sub-pixels P each having a red light-emitting region Lr, a green light-emitting region Lg, and a blue light-emitting region Lb. The arrangement of the sub-pixels P is not particularly limited, and examples thereof include a pentatile arrangement and a stripe arrangement.

[0016] A terminal portion T is provided to extend in one direction (the vertical direction in FIG. 1) at one end (the right end in FIG. 1) of the frame region F. Also, as shown in FIG. 1, a folding portion B that can be folded, for example, 180 degrees (in a U-shape) with the vertical direction in FIG. 1 as the folding axis is provided in the frame region F between the terminal portion T and the display region D and that extends in one direction (the vertical direction in FIG. 1).

[0017] As shown in FIG. 3, the organic EL display device 50a includes a resin substrate 10 provided as a base substrate, and a TFT layer 20a provided on the resin substrate 10.

[0018] The resin substrate 10 is made of an organic resin material such as polyimide resin.

[0019] As shown in FIG. 3, the TFT layer 20a includes a base coat film 11 provided on a resin substrate 10, a plurality of first TFTs 9a, a plurality of second TFTs 9b, and a plurality of capacitors 9c provided on the base coat film 11 for each sub-pixel P, and a planarization film 19 provided on each of the first TFTs 9a, each of the second TFTs 9b, and each of the capacitors 9c. Here, in the TFT layer 20a, as shown in FIG. 3, a base coat film 11, a semiconductor film that becomes the semiconductor layer 12a and the semiconductor layer 12b, a gate insulating film 13 (inorganic insulating film), a first metal film (metal film) that becomes a first wiring layer such as the gate line 14 (see FIGS. 2, 4 to 8), the gate electrodes 14a and 14b, and the lower conductive layer 14c, a first interlayer insulating film 15, a second metal film that becomes a second wiring layer such as the upper conductive layer 16, a second interlayer insulating film 17, a third metal film that becomes a third wiring layer such as the source line 18f (see FIGS. 2, 4, and 5), the source electrodes 18a and 18c, the drain electrodes 18b and 18d, and the power line 18g, and a planarization film 19 are laminated in this order on the resin substrate 10.

[0020] The base coat film 11, the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17 are each composed of a single layer or a multilayer film of an inorganic insulating film such as silicon nitride (SiNx (x is a positive number)), silicon oxide (SiO2), or silicon oxynitride (SiON).

[0021] The semiconductor film is composed of, for example, a low-temperature polysilicon film such as LTPS (low temperature polysilicon), an In-Ga-Zn-O based oxide semiconductor film, etc. In the following, the first TFT 9a and the second TFT 9b will be described as p-type TFTs in which semiconductor layers 12a and 12b (polysilicon semiconductor layers) formed of polysilicon films as semiconductor films are doped with impurities such as boron.

[0022] The first metal film, the second metal film, and the third metal film are composed of, for example, a metal single layer film of molybdenum (Mo), titanium (Ti), aluminum (Al), copper (Cu), tungsten (W), etc., or a metal laminate film such as Mo (upper layer) / Al (middle layer) / Mo (lower layer), Ti / Al / Ti, Al (upper layer) / Ti (lower layer), Cu / Mo, Cu / Ti, etc.

[0023] The planarization film 19 has a flat surface in the display region D, and is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG (spin on glass) material.

[0024] As shown in Figures 2, 4 to 8, the TFT layer 20a is provided with a plurality of gate lines 14 as signal wirings, extending parallel to one another in the horizontal direction in the drawings. Furthermore, as shown in Figures 2, 4 and 5, the TFT layer 20a is provided with a plurality of source lines 18f as signal wirings, extending in a direction intersecting (orthogonal to) the plurality of gate lines 14, i.e., extending parallel to one another in the vertical direction in the drawings. Furthermore, as shown in Figures 2 to 5, the TFT layer 20a is provided with a plurality of power supply lines 18g, extending parallel to one another in the vertical direction in the drawings. Each power supply line 18g is provided adjacent to each source line 18f, as shown in Figure 2.

[0025] As shown in FIG. 4, the first TFT 9a is electrically connected to the corresponding gate line 14 and source line 18f (signal wiring) in each subpixel P. As shown in FIG. 3, the first TFT 9a includes a semiconductor layer 12a, a gate insulating film 13, a gate electrode 14a, a first interlayer insulating film 15, a second interlayer insulating film 17, a source electrode 18a, and a drain electrode 18b, which are sequentially provided on a base coat film 11. As shown in FIG. 3, the semiconductor layer 12a is provided on the base coat film 11 in an island shape, and includes, for example, a channel region, a source region, and a drain region. As shown in FIGS. 7 and 8, the semiconductor layer 12a intersects with each gate line 14 and overlaps with each gate line 14 at the intersecting portions (hereinafter also referred to as "intersections," i.e., at least a portion of the gate line 14) in a plan view. As shown in FIG. 3, the gate insulating film 13 is provided to cover the semiconductor layer 12a. As shown in FIG. 3, the gate electrode 14a is provided on the gate insulating film 13 so as to overlap with the channel region of the semiconductor layer 12a. As shown in FIG. 3, the first interlayer insulating film 15 and the second interlayer insulating film 17 are provided in this order so as to cover the gate electrode 14a. As shown in FIG. 3, the source electrode 18a and the drain electrode 18b are provided on the second interlayer insulating film 17 so as to be spaced apart from each other. As shown in FIG. 3, the source electrode 18a and the drain electrode 18b are electrically connected to the source region and the drain region of the semiconductor layer 12a, respectively, through contact holes formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17. In addition, the source region and the drain region are electrically connected to a plurality of first TFTs 9a through corresponding gate lines 14 and source lines 18f.

[0026] As shown in FIG. 4, the second TFT 9b is electrically connected to the corresponding first TFT 9a and power line 18g in each subpixel P. As shown in FIG. 3, the second TFT 9b includes a semiconductor layer 12b, a gate insulating film 13, a gate electrode 14b, a first interlayer insulating film 15, a second interlayer insulating film 17, a source electrode 18c, and a drain electrode 18d, which are sequentially disposed on a base coat film 11. As shown in FIG. 3, the semiconductor layer 12b is disposed on the base coat film 11 in an island shape and includes, for example, a channel region, a source region, and a drain region. As shown in FIG. 3, the gate insulating film 13 is disposed so as to cover the semiconductor layer 12b. As shown in FIG. 3, the gate electrode 14b is disposed on the gate insulating film 13 so as to overlap the channel region of the semiconductor layer 12b. As shown in FIG. 3, the first interlayer insulating film 15 and the second interlayer insulating film 17 are sequentially disposed so as to cover the gate electrode 14b. 3, the source electrode 18c and the drain electrode 18d are provided spaced apart from each other on the second interlayer insulating film 17. In addition, the source electrode 18c and the drain electrode 18d are electrically connected to the source region and the drain region of the semiconductor layer 12b, respectively, through contact holes formed in the stacked film of the gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 17, as shown in FIG.

[0027] In this embodiment, the first TFT 9a and the second TFT 9b are top-gate type TFTs, but the first TFT 9a and the second TFT 9b may be bottom-gate type TFTs.

[0028] As shown in Fig. 4, the capacitor 9c is electrically connected to the corresponding first TFT 9a and power supply line 18g in each subpixel P. Here, as shown in Fig. 3, the capacitor 9c includes a lower conductive layer 14c formed in the same layer and made of the same material as the gate electrodes 14a and 14b, a first interlayer insulating film 15 provided so as to cover the lower conductive layer 14c, and an upper conductive layer 16 provided on the first interlayer insulating film 15 so as to overlap the lower conductive layer 14c. Note that the upper conductive layer 16 is electrically connected to the power supply line 18g via a contact hole formed in a second interlayer insulating film 17, as shown in Fig. 3.

[0029] In the TFT layer 20a, as shown in FIG. 4, a first TFT 9a, a second TFT 9b, and a capacitor 9c are provided as a pixel circuit C in each subpixel P. As shown in FIG. 5, a plurality of pixel circuits C are arranged in a matrix corresponding to each subpixel P. As a result, the plurality of pixel circuits C are arranged in the direction in which the gate line 14 extends as a signal wiring (the horizontal direction in FIGS. 5 and 6). The plurality of pixel circuits C are also arranged in the direction in which the source line 18f extends as a signal wiring (the vertical direction in FIG. 5). Note that black circles (●) in FIGS. 4 to 6 indicate nodes. In the following description, the first TFT 9a and the second TFT 9b are also collectively referred to as "TFT 9ab." In the following description, the semiconductor layer 12a and the semiconductor layer 12b are also collectively referred to as "first semiconductor layer 12ab."

[0030] As shown in FIGS. 6 to 8, the organic EL display device 50a includes a plurality of lightning rod elements 9da (two for each gate line 14 in FIG. 6). The lightning rod elements 9da are formed in the TFT layer 20a. The lightning rod elements 9da have the same layer structure as the TFT 9ab, except that they include a second semiconductor layer 12da instead of the first semiconductor layer 12ab constituting the TFT 9ab. Specifically, like the first semiconductor layer 12ab, the second semiconductor layer 12da is provided on the base coat film 11 in an island shape and has, for example, a channel region, a source region, and a drain region. As shown in FIGS. 7 and 8, the second semiconductor layer 12da intersects with each gate line 14 and overlaps with each gate line 14 at the intersections (at least a portion of the gate lines 14) in a planar view. The gate insulating film 13 is provided to cover the second semiconductor layer 12da, as shown in FIG. 8. The second semiconductor layer 12da is formed in the same layer as the first semiconductor layer 12ab using the same material. That is, the second semiconductor layer 12da may be formed of the above-mentioned polysilicon film or oxide semiconductor film. In the following, the second semiconductor layer 12da will be described as a polysilicon semiconductor layer formed of a polysilicon film as a semiconductor film, similar to the first semiconductor layer 12ab constituting the TFT 9ab.

[0031] 6, the lightning rod element 9da is provided near a plurality of TFTs 9ab along each gate line 14. Specifically, the lightning rod element 9da is arranged outward in the direction in which the gate line 14 extends relative to the TFTs 9ab arranged at at least one end of each gate line 14. In other words, the lightning rod element 9da is arranged along each gate line 14, closer to the frame region F than the terminal pixel circuits C (terminal TFTs 9ab constituting them) arranged at the ends of the gate line 14 in the display region D (both ends in FIG. 6). The lightning rod element 9da may be arranged either within the display region D (at its end on the frame region F side) or within the frame region F.

[0032] In the organic EL display device 50a, as shown in FIG. 7, at the intersection of the first semiconductor layer 12ab or the second semiconductor layer 12da and the gate line 14, the second width Wd, which is the width of the second semiconductor layer 12da at the intersection with the gate line 14 (the portion intersecting the signal wiring), is smaller than the first width Wab, which is the width of the first semiconductor layer 12ab at the intersection with the gate line 14 (the portion intersecting the signal wiring) (Wd < Wab). As a result, as shown in FIG. 8, in a cross-sectional view, the angle θd of the end face of the second semiconductor layer 12da with respect to the upper surface of the resin substrate 10 is larger than the angle θab of the end face of the first semiconductor layer 12ab with respect to the upper surface of the resin substrate 10 (θd > θab). Here, the end faces of the first semiconductor layer 12ab and the second semiconductor layer 12da refer to the etched end faces after patterning in the semiconductor layer forming process described later, and are tapered (in the following description, the portion indicating the above end face is also referred to as a "taper portion"). In the organic EL display device 50a, the taper portion refers to the end portion in the extending direction of the gate line 14. Also, the angle θab of the end face of the first semiconductor layer 12ab and the angle θd of the end face of the second semiconductor layer 12da correspond to the photo resist contact angle of the semiconductor film in the semiconductor layer forming process (in the following description, the above angles are also referred to as "taper angles"). Thus, the taper angle θd of the second semiconductor layer 12da constituting the lightning rod element 9da is steeper than the taper angle θab of the first semiconductor layer 12ab constituting the TFT 9ab. As a result, as shown in FIG. 8, the second distance Ld, which is the distance between the end face of the second semiconductor layer 12da and the lower surface of the corresponding gate line 14 (signal wiring), is shorter than the first distance Lab, which is the distance between the end face of the first semiconductor layer 12ab and the lower surface of the corresponding gate line 14 (signal wiring) (Ld < Lab). That is, the gate insulating film 13 in the taper portion of the lightning rod element 9da is thinner than the gate insulating film 13 in the taper portion of the TFT 9ab. Thereby, the lightning rod element 9da becomes a low breakdown voltage portion with a lower breakdown voltage than the TFT 9ab.

[0033] In conventional organic EL display devices, ESD damage to TFTs arranged near the ends of gate lines has been a cause of reduced production yields, particularly during the manufacturing of organic EL elements (the organic EL element layer formation process described below). This is thought to be due to the charge stored in the gate lines during the manufacturing process having nowhere to go at the ends of the gate lines, affecting the TFTs that make up the pixel circuits nearby. It has been found that, in particular, when a TFT is composed of a polysilicon semiconductor layer formed from a polysilicon film, an inorganic insulating film, and a gate line, ESD damage is likely to occur in the thin portions of the inorganic insulating film that correspond to the tapered portions of the polysilicon semiconductor layer.

[0034] In contrast, in the organic EL display device 50a of this embodiment, lightning rod elements 9da with a lower withstand voltage than the TFTs 9ab are provided outside (toward the frame region F) the TFTs 9ab that constitute the pixel circuits C arranged at both ends of the gate line 14, so that ESD that occurs during the manufacturing process is guided to the lightning rod elements 9da. In this way, the lightning rod elements 9da are expected to function as protective elements (dummy elements) for the TFTs 9ab (particularly the first TFT 9a) arranged at the ends of the gate lines 14, which are susceptible to the effects of ESD. The lightning rod elements 9da make it difficult for the TFTs 9ab to be affected, even if ESD occurs during the manufacturing process.

[0035] As shown in FIG. 3, the organic EL display device 50a includes, as an upper layer of the TFT layer 20a, an organic EL element layer 31 provided as a light-emitting element layer constituting the display region D, and a sealing film 35 provided on the organic EL element layer 31.

[0036] As shown in FIG. 3, the organic EL element layer 31 includes a plurality of organic EL elements 25 as a plurality of light-emitting elements arranged in a matrix corresponding to a plurality of sub-pixels P.

[0037] 3, the organic EL element 25 includes a plurality of first electrodes 21 provided in order on the planarization film 19, a plurality of organic EL layers 23 provided on the first electrodes 21 in respective sub-pixels P, and a second electrode 24 provided on the organic EL layer 23 in common to the plurality of sub-pixels P. In addition, the organic EL element 25 is covered with a sealing film 35 as shown in FIG.

[0038] As shown in FIG. 3, the first electrodes 21 are provided in a matrix on the planarization film 19 so as to correspond to the plurality of sub-pixels P. As shown in FIG. 3, each first electrode 21 is electrically connected to the drain electrode 18d (or source electrode 18c) of each second TFT 9b via a contact hole formed in the planarization film 19. The first electrodes 21 have a function of injecting holes (positive holes) into the organic EL layer 23. In order to improve the efficiency of hole injection into the organic EL layer 23, it is more preferable that the first electrodes 21 be made of a material with a large work function. Examples of materials constituting the first electrode 21 include metal materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). The material constituting the first electrode 21 may also be an alloy such as astatine (At) / astatine oxide (AtO). Furthermore, the material constituting the first electrode 21 may also be a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). The first electrode 21 may be formed by stacking a plurality of layers made of the above materials. Examples of compound materials with a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).

[0039] The peripheral edge of the first electrode 21 is covered with an edge cover 22 provided in a lattice pattern and shared by multiple sub-pixels P. Examples of materials that form the edge cover 22 include positive photosensitive resin materials such as polyimide resin, acrylic resin, polysiloxane resin, and novolac resin, as well as polysiloxane-based SOG materials. As shown in FIG. 3, a portion of the surface of the edge cover 22 protrudes upward in the drawing and serves as an island-shaped pixel photospacer.

[0040] 3, the organic EL layers 23 are disposed on each first electrode 21 and are provided in a matrix so as to correspond to the plurality of sub-pixels P. Here, each organic EL layer 23 includes a hole injection layer 1, a hole transport layer 2, a light-emitting layer 3, an electron transport layer 4, and an electron injection layer 5, which are provided in this order on the first electrode 21, as shown in FIG.

[0041] The hole injection layer 1, also called an anode buffer layer, has the function of bringing the energy levels of the first electrode 21 and the organic EL layer 23 closer to each other and improving the efficiency of hole injection from the first electrode 21 to the organic EL layer 23. Examples of materials that form the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0042] The hole transport layer 2 has a function of improving the efficiency of transporting holes from the first electrode 21 to the organic EL layer 23. Examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylenevinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, and zinc selenide.

[0043] The light-emitting layer 3 is a region into which holes and electrons are injected from the first electrode 21 and the second electrode 24, respectively, and where the holes and electrons recombine when a voltage is applied between the first electrode 21 and the second electrode 24. The light-emitting layer 3 is made of a material with high luminous efficiency. Examples of materials that can be used for the light-emitting layer 3 include metal oxinoid compounds (8-hydroxyquinoline metal complexes), naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinylacetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzthiazole derivatives, styryl derivatives, styrylamine derivatives, bisstyrylbenzene derivatives, trisstyrylbenzene derivatives, perylene derivatives, perinone derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, aquidin derivatives, phenoxazone, quinacridone derivatives, rubrene, poly-p-phenylenevinylene, and polysilane.

[0044] The electron transport layer 4 has a function of efficiently transferring electrons to the light-emitting layer 3. Examples of materials constituting the electron transport layer 4 include organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, fluorenone derivatives, silole derivatives, and metal oxinoid compounds.

[0045] The electron injection layer 5 has the function of bringing the energy levels of the second electrode 24 and the organic EL layer 23 closer to each other and improving the efficiency of electron injection from the second electrode 24 to the organic EL layer 23, thereby making it possible to reduce the driving voltage of the organic EL element 25. The electron injection layer 5 is also called a cathode buffer layer. Examples of materials that can be used to form the electron injection layer 5 include inorganic alkali compounds such as lithium fluoride (LiF), magnesium fluoride (MgF2), calcium fluoride (CaF2), strontium fluoride (SrF2), and barium fluoride (BaF2), aluminum oxide (Al2O3), and strontium oxide (SrO).

[0046] 3, the second electrode 24 is provided so as to cover each organic EL layer 23 and the edge cover 22. The second electrode 24 has a function of injecting electrons into the organic EL layer 23. The second electrode 24 is preferably made of a material with a small work function to improve the efficiency of electron injection into the organic EL layer 23. Examples of materials that can be used for the second electrode 24 include silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), ruthenium (Ru), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). The second electrode 24 may be formed of an alloy such as magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), astatine (At) / astatine oxide (AtO), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), or lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). The second electrode 24 may be formed of a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). The second electrode 24 may be formed by stacking multiple layers made of the above materials. Examples of materials with a small work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al).

[0047] As shown in FIG. 3, the sealing film 35 includes a first sealing inorganic insulating film 32 provided to cover the second electrode 24, a sealing organic film 33 provided on the first sealing inorganic insulating film 32, and a second sealing inorganic insulating film 34 provided to cover the sealing organic film 33, and has a function of protecting the organic EL layer 23 from moisture, oxygen, etc. Here, the first sealing inorganic insulating film 32 and the second sealing inorganic insulating film 34 are made of inorganic materials such as silicon oxide (SiO2), aluminum oxide (Al2O3), silicon nitride (SiNx (x is a positive number)) such as trisilicon tetranitride (Si3N4), and silicon carbonitride (SiCN). Further, the sealing organic film 33 is made of an organic material such as an acrylic resin, a polyurea resin, a parylene resin, a polyimide resin, or a polyamide resin.

[0048] In the above-described organic EL display device 50a, in each sub-pixel P, by inputting a gate signal to the first TFT 9a via the gate line 14, the first TFT 9a is turned on, and a data signal is written to the gate electrode 14b of the second TFT 9b and the capacitor 9c via the source line 18f. Then, by supplying a current from the power supply line 18g according to the gate voltage of the second TFT 9b to the organic EL layer 23, the light-emitting layer 3 of the organic EL layer 23 emits light to perform image display. In the organic EL display device 50a, even when the first TFT 9a is turned off, the gate voltage of the second TFT 9b is held by the capacitor 9c, so that the light emission by the light-emitting layer 3 is maintained until the gate signal of the next frame is input.

[0049] Next, a method for manufacturing the organic EL display device 50a of the present embodiment will be described. The method for manufacturing the organic EL display device 50a of the present embodiment includes a TFT layer formation step.

[0050] <TFT Layer Formation Step> The TFT layer formation process is a process of forming a TFT layer 20a on a resin substrate 10. For example, a base coat film 11, a first TFT 9a, a second TFT 9b, a capacitor 9c, a planarization film 19, etc. are formed on the surface of the resin substrate 10 formed on a glass substrate using a well-known method. Here, the TFT layer formation process of this embodiment includes a semiconductor layer formation process, an insulating film formation process, and a wiring layer formation process.

[0051] (Semiconductor layer formation process) An amorphous silicon film (approximately 50 nm thick) is formed on the substrate surface, on which a base coat film 11 is formed as a layer below the semiconductor layer, by, for example, plasma CVD (Chemical Vapor Deposition). The amorphous silicon film is crystallized by laser annealing or the like to form a polysilicon film, which is then patterned to form island-shaped first semiconductor layers 12ab and island-shaped second semiconductor layers 12da. A plurality of first semiconductor layers 12ab are arranged in the display region D so as to follow the gate lines 14 formed in a subsequent wiring layer formation process. The second semiconductor layers 12da are arranged along the gate lines 14, outside (toward the frame region F) of the first semiconductor layers 12ab arranged at both ends of the gate lines 14.

[0052] In the manufacturing method of the organic EL display device 50a, the photoresist contact angle of the semiconductor film and / or the etching conditions are controlled in the semiconductor layer formation process to form the second semiconductor layer 12da with a larger taper angle θd than the first semiconductor layer 12ab with a larger taper angle θab in a cross-sectional view. Examples of methods include intentionally steepening the photoresist contact angle so that θd > θab, or intentionally creating a difference in the angle of the etched end face of the semiconductor film using a gray-tone mask for exposure of the semiconductor film. In this way, by performing subsequent processes without adding additional steps or masks, a lightning rod element 9da with a lower breakdown voltage than the first TFT 9a and the second TFT 9b can be formed as a protection element for the first TFT 9a and the second TFT 9b.

[0053] (Insulating film formation process) A silicon oxide film (with a thickness of approximately 100 nm) is formed on the substrate surface on which the first semiconductor layer 12ab and the second semiconductor layer 12da are formed, for example, by plasma CVD, and then the silicon oxide film is patterned to cover the first semiconductor layer 12ab and the second semiconductor layer 12da, thereby forming a gate insulating film 13 (inorganic insulating film).

[0054] (Wiring layer formation process) A first metal film (metal film) such as a molybdenum film (thickness: about 200 nm) is formed on the substrate surface on which the gate insulating film 13 is formed, for example, by sputtering, and then the first metal film is patterned to form a first wiring layer such as a gate electrode 14a and a gate line 14.

[0055] The method for manufacturing the organic EL display device 50a also includes an organic EL element layer forming step and a sealing film forming step.

[0056] <Organic EL element layer formation process> On the planarization film 19 of the TFT layer 20a formed in the TFT layer formation process, a first electrode 21, an edge cover 22, an organic EL layer 23 (hole injection layer 1, hole transport layer 2, light-emitting layer 3, electron transport layer 4, electron injection layer 5) and a second electrode 24 are formed using a well-known method to form an organic EL element 25, thereby forming an organic EL element layer 31.

[0057] <Sealing film formation process> First, on the substrate surface on which the organic EL element layer 31 formed in the organic EL element layer forming process has been formed, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using a CMM as a deposition mask so as to cover each organic EL element 25, thereby forming a first sealing inorganic insulating film 32. Next, an organic resin material such as an acrylic resin is formed on the first sealing inorganic insulating film 32 by, for example, an inkjet method, thereby forming a sealing organic film 33. Thereafter, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using a CMM as a deposition mask so as to cover the sealing organic film 33, thereby forming a second sealing inorganic insulating film 34, thereby forming a sealing film 35. Through the above steps, a sealing film 35 can be formed in the display region D, in which the first sealing inorganic insulating film 32, the sealing organic film 33, and the second sealing inorganic insulating film 34 are stacked in this order.

[0058] Finally, a protective sheet (not shown) is attached to the surface of the substrate, and then laser light is applied from the glass substrate side of the resin substrate 10 to peel the glass substrate from the lower surface of the resin substrate 10, and a protective sheet (not shown) is attached to the lower surface of the resin substrate 10 from which the glass substrate has been peeled. In this manner, the organic EL display device 50a can be manufactured.

[0059] <Effects> As described above, the organic EL display device 50a of this embodiment and the manufacturing method thereof can provide the following effects.

[0060] The organic EL display device 50a includes a lightning protection element 9da having a layer structure similar to that of the TFTs 9ab, except that in the TFT layer 20a, instead of the first semiconductor layer 12ab constituting the TFTs 9ab, a second semiconductor layer 12da is provided outside (on the frame region F side) of the TFTs 9ab arranged at both ends of the gate line 14 along the extending direction of the gate line 14 within the display region D. The taper angle θd of the second semiconductor layer 12da is larger than the taper angle θab of the first semiconductor layer 12ab (θd > θab). As a result, as shown in FIG. 8, in the tapered portion, the second distance Ld, which is the distance between the end face of the second semiconductor layer 12da and the lower surface of the corresponding gate line 14 (signal wiring) (i.e., the film thickness of the gate insulating film 13), is smaller than the first distance Lab, which is the distance between the end face of the first semiconductor layer 12ab and the lower surface of the corresponding gate line 14 (signal wiring) (Ld < Lab). The lightning protection element 9da becomes a low breakdown voltage portion with a lower breakdown voltage than the TFTs 9ab. As a result, during the manufacturing process of the display device, the charges charged on the gate line 14 are induced to the lightning protection element 9da, and the ESD breakdown of the TFTs 9ab (especially the first TFT 9a) caused by ESD generated during the manufacturing process can be suppressed.

[0061] Also, as shown in FIG. 7, the lightning protection element 9da, which is a protection element of the TFT 9ab, is provided along the same gate line 14. At the intersection with the gate line 14, the second width Wd, which is the width of the second semiconductor layer 12da at the intersection with the gate line 14 (the portion intersecting with the signal wiring), is smaller than the first width Wab, which is the width of the first semiconductor layer 12ab at the intersection with the gate line 14 (the portion intersecting with the signal wiring) (Wd < Wab). Therefore, it can be said that it is a simple element that does not pose a major obstacle when narrowing the frame, and it can also be introduced into the narrow-frame organic EL display device 50a.

[0062] In the manufacturing method of the organic EL display device 50a, in the same TFT layer forming step (semiconductor layer forming step) as in the conventional method, it is sufficient to intentionally create a difference in the taper angle so that θd > θab by controlling the photoresist contact angle of the semiconductor film and / or etching conditions, and no additional steps or masks are required. Therefore, the manufacturing method of the organic EL display device 50a employs conventionally known steps and is also excellent in workability.

[0063] Second Embodiment Next, a second embodiment of the present invention will be described with reference to FIGS. 10 to 12. FIG. 10 is a schematic plan view showing the arrangement of the pixel circuit C, the first lightning rod element 9dba, and the second lightning rod element 9dbb of an organic EL display device 50b of this embodiment, and corresponds to FIG. 6. FIG. 11 is an enlarged plan view of the area enclosed by the two-dot chain line in FIG. 10(a) showing the TFT 9ab and the first lightning rod element 9dba that constitute the pixel circuit C of the organic EL display device 50b, and corresponds to FIG. 7. FIG. 12 is an enlarged plan view of the area enclosed by the two-dot chain line in FIG. 10(b) showing the TFT 9ab and the second lightning rod element 9dbb that constitute the pixel circuit C of the organic EL display device 50b, and corresponds to FIG. 7. The overall configuration of the organic EL display device 50b is the same as that of the first embodiment described above, except for the configuration of the TFT layer 20b, and therefore a detailed description thereof will be omitted here. Furthermore, components similar to those of the first embodiment will be denoted by the same reference numerals, and their description will be omitted. 11 and 12, the layer above the first wiring layer is omitted.

[0064] In the organic EL display device 50b, as shown in FIGS. 10 to 12, the TFT layer 20b includes a plurality of first lightning rod elements 9dba (two for each gate line 14 in FIG. 10) and a plurality of second lightning rod elements 9dbb.

[0065] The first lightning protection element 9dba corresponds to the lightning protection element 9da provided in the organic EL display device 50a (its TFT layer 20a). As shown in FIG. 10, similar to the lightning protection element 9da, the first lightning protection element 9dba is arranged on the frame region F side of each terminal pixel circuit C (the terminal TFT 9ab constituting it) arranged at the ends (both ends in FIG. 10) of the gate line 14 in the display region D along each gate line 14. Incidentally, the first lightning protection element 9dba may be arranged within the display region D (the frame region F side end thereof), or may be arranged within the frame region F.

[0066] On the other hand, as shown in FIG. 11, the planar shape and size of the island-shaped second semiconductor layer 12dba constituting the first lightning protection element 9dba are different from those of the island-shaped second semiconductor layer 12da constituting the lightning protection element 9da. Specifically, the second semiconductor layer 12dba is provided in a circular shape. Note that the planar shape of the second semiconductor layer 12dba is not limited to a circular shape, and may be, for example, a trapezoid, a rectangle, or the like. The size of the circular second semiconductor layer 12dba (diameter φdba in FIG. 11) is smaller than the first width Wab which is the width of the first semiconductor layer 12ab at the intersection (the portion intersecting the signal wiring) with the gate line 14 constituting the TFT 9ab and the width L14 of the gate line 14 (φdba < Wab and φdba < L14). That is, the second semiconductor layer 12dba is provided so that its entirety overlaps the gate line 14 in a plan view.

[0067] The second lightning protection element 9dbb is configured to have the same structure and shape as the first lightning protection element 9dba. That is, as shown in FIG. 12, the second semiconductor layer 12dbb constituting the second lightning protection element 9dbb is provided in a circular shape, similar to the second semiconductor layer 12dba constituting the first lightning protection element 9dba. Also, similar to the second semiconductor layer 12dba, the size of the circular second semiconductor layer 12dbb (diameter φdbb in FIG. 12) is smaller than the first width Wab which is the width of the first semiconductor layer 12ab at the intersection (the portion intersecting the signal wiring) with the gate line 14 and the width L14 of the gate line 14 (φdbb < Wab and φdbb < L14).

[0068] 10 and 12, the second lightning rod element 9dbb is arranged between adjacent TFTs 9ab, unlike the lightning rod element 9da and the first lightning rod element 9dba. That is, the second lightning rod element 9dbb is provided between adjacent pixel circuits C in the display area D.

[0069] The taper angle θd of the second semiconductor layer 12dba constituting the first lightning rod element 9dba and the second semiconductor layer 12dbb constituting the second lightning rod element 9dbb is larger than the taper angle θab of the first semiconductor layer 12ab constituting the TFT 9ab (θd>θab), as with the second semiconductor layer 12da constituting the lightning rod element 9da. Also, in the tapered portion, the second distance Ld, which is the distance between the end face of the second semiconductor layer 12dba or the second semiconductor layer 12dbb and the lower surface of the corresponding gate line 14 (signal wiring) (i.e., the film thickness of the gate insulating film 13), is smaller than the first distance Lab, which is the distance between the end face of the first semiconductor layer 12ab and the corresponding gate line 14 (signal wiring) (Ld <Lab)。

[0070] In the present embodiment, the organic EL display device 50b is illustrated as including the first lightning rod element 9dba and the second lightning rod element 9dbb, but the present invention is not limited to this and may be an organic EL display device including only the second lightning rod element 9dbb. However, from the viewpoint of further suppressing ESD damage to the TFT 9ab (particularly the first TFT 9a) due to ESD occurring during the manufacturing process, it is preferable to include both the first lightning rod element 9dba and the second lightning rod element 9dbb.

[0071] Furthermore, an organic EL display device may be a combination of the first and second embodiments. For example, the organic EL display device may include the lightning rod element 9da exemplified in the first embodiment and the second lightning rod element 9dbb exemplified in the second embodiment.

[0072] In the organic EL display device 50b, the second semiconductor layers 12dba and 12dbb may be formed by changing the pattern shape of the semiconductor film in the semiconductor layer forming step of the TFT layer forming step of the organic EL display device 50a described above.

[0073] <Effect> According to the organic EL display device 50b described above, in addition to the effects of the organic EL display device 50a described above, the following effects can be obtained.

[0074] In the organic EL display device 50b, in the TFT layer 20a, in addition to the first lightning protection element 9dba corresponding to the lightning protection element 9da provided in the organic EL display device 50a, a second lightning protection element 9dbb arranged between a plurality of TFTs 9ab provided in the display area D along the extending direction of the gate line 14 is provided. That is, in the organic EL display device 50b, the protection elements of the TFT 9ab are arranged on the outer side (frame edge region F side) in the extending direction of the gate line 14 rather than the TFTs 9ab arranged at both ends of both sides of each gate line 14 and between two adjacent TFTs 9ab. Thereby, the charges charged on the gate line 14 during the manufacturing process of the display device are induced to these two first lightning protection elements 9dba and the second lightning protection element 9dbb, and the ESD breakdown of the TFT 9ab (especially the first TFT 9a) caused by ESD generated during the manufacturing process can be further suppressed.

[0075] Also, as shown in FIGS. 11 and 12, the two first lightning protection elements 9dba and the second lightning protection element 9dbb have a size (diameter φdba, φdbb ) that is smaller than the first width Wab which is the width of the first semiconductor layer 12ab at the intersection (the part intersecting with the signal wiring) of the gate line 14 that constitutes the TFT 9ab and the width L14 of the gate line 14 (φdba < Wab and φdba < L14, φdbb < Wab and φdbb < L14). Therefore, not only is the first lightning protection element 9dba provided outside the TFT 9ab at the end of the gate line 14, but even when the second lightning protection element 9dbb is provided between each TFT 9ab, the pattern density of the semiconductor layer (the second semiconductor layers 12dba, 12dbb) does not increase significantly. Therefore, the two first lightning protection elements 9dba and the second lightning protection element 9dbb can be said to be simple elements that do not pose a major obstacle when narrowing the frame, and can also be introduced into the narrow-frame organic EL display device 50b.

[0076] <<Other Embodiments>> In each of the above embodiments, a TFT layer having a plurality of lightning rod elements along each gate line has been exemplified, but this is not limited to this, and a TFT layer having at least one lightning rod element along each gate line may also be used.

[0077] In each of the above embodiments, a TFT layer in which lightning rod elements are arranged at both ends of each gate line has been exemplified, but this is not limited to this, and a TFT layer in which lightning rod elements are arranged at one end (at least one end) of each gate line may also be used.

[0078] In each of the above embodiments, gate lines (first wiring layer) are exemplified as signal lines, but the present invention is not limited to this, and the signal lines may be source lines (second wiring layer), power supply lines (third wiring layer), etc.

[0079] In each of the above embodiments, the inorganic laminated film is composed of four layers, namely, a gate insulating film, a first interlayer insulating film, and a second interlayer insulating film, stacked in this order on a base coat film, but it may also be composed of a single layer of the base coat film, or two layers, namely, the base coat film and the gate insulating film.

[0080] In each of the above embodiments, an organic EL layer having a five-layer stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer has been exemplified. However, the organic EL layer may have a three-layer stacked structure of, for example, a hole injection layer / hole transport layer, a light-emitting layer, and an electron transport layer / electron injection layer.

[0081] Furthermore, in each of the above embodiments, an organic EL display device in which the first electrode is an anode and the second electrode is a cathode is exemplified, but the present invention can also be applied to an organic EL display device in which the stacked structure of the organic EL layer is reversed, and the first electrode is a cathode and the second electrode is an anode.

[0082] In each of the above embodiments, an organic EL display device is exemplified in which the electrode of the TFT connected to the first electrode is the drain electrode, but the present invention can also be applied to an organic EL display device in which the electrode of the TFT connected to the first electrode is called the source electrode.

[0083] In each of the above embodiments, the display device is an organic EL display device. For example: However, the present invention can also be applied to display devices such as active matrix drive liquid crystal display devices.

[0084] In the above embodiments, an organic EL display device has been described as an example of a display device, but the present invention is not limited to organic EL display devices and can be applied to any flexible display device. For example, the present invention can be applied to a flexible display device including a quantum-dot light emitting diode (QLED), which is a light emitting element using a quantum dot-containing layer. [Industrial Applicability]

[0085] As described above, the present invention is useful for flexible display devices. [Explanation of symbols]

[0086] D Display area F Frame area θab Angle of the end face of the first semiconductor layer θd Angle of the end face of the second semiconductor layer Lab first distance (the distance between the end face of the first semiconductor layer and the bottom face of the corresponding signal wiring) Ld: Second distance (the distance between the end face of the second semiconductor layer and the bottom face of the corresponding signal wiring) Wab First width (width of the first semiconductor layer at the intersection with the signal wiring) Wd Second width (width of the second semiconductor layer at the intersection with the signal wiring) φdba, φdbb Diameter of the second semiconductor layer 9a First TFT (thin film transistor) 9b Second TFT (thin film transistor) 9ab First TFT, second TFT (thin film transistor) 9da lightning rod element 9dba First lightning rod element 9dbb Second lightning rod element 10 Resin substrate (base substrate) 12a, 12b Semiconductor layers 12ab First semiconductor layer 12da, 12dba, 12dbb Second semiconductor layer 13 Gate insulating film (inorganic insulating film) 14 Gate line (signal wiring) 20a, 20b TFT layer (thin film transistor layer) 25 Organic EL element (light-emitting element) 31 Organic EL element layer (light emitting element layer) 35 Sealing film 50a,50b Organic EL display device

Claims

1. A base substrate; a thin film transistor layer provided on the base substrate, in which a semiconductor film, an inorganic insulating film, and a metal film are stacked in this order; The thin film transistor layer is a plurality of signal wirings formed from the metal film and extending parallel to one another in one direction; a plurality of thin film transistors provided along the signal lines and corresponding to a plurality of sub-pixels constituting the display area; at least one lightning rod element provided along each of the signal wirings and in the vicinity of the plurality of thin film transistors; each of the thin film transistors includes a first semiconductor layer formed of the semiconductor film and provided in an island shape so as to overlap at least a portion of each of the signal lines in a plan view; The lightning rod elements are formed of the semiconductor film, and each of the lightning rod elements includes a second semiconductor layer provided in an island shape so as to overlap at least a part of each of the signal wirings in a plan view. A display device, wherein, in a cross-sectional view, an angle of an end face of the second semiconductor layer relative to an upper surface of the base substrate is larger than an angle of an end face of the first semiconductor layer relative to the upper surface of the base substrate.

2. 2. The display device according to claim 1, A display device characterized in that the distance between the end surface of the second semiconductor layer and the corresponding lower surface of the signal wiring is shorter than the distance between the end surface of the first semiconductor layer and the corresponding lower surface of the signal wiring.

3. 2. The display device according to claim 1, the first semiconductor layer and the second semiconductor layer intersect with each of the signal lines, The display device, wherein the width of the second semiconductor layer at the portions intersecting with the signal wirings is smaller than the width of the first semiconductor layer at the portions intersecting with the signal wirings.

4. 2. The display device according to claim 1, the first semiconductor layer intersects with each of the signal lines, The display device according to the present invention, wherein the second semiconductor layer has a width smaller than the width of each of the signal lines and at the portions where the second semiconductor layer intersects with the signal lines of the first semiconductor layer.

5. The display device according to any one of claims 1 to 4, a lightning rod element arranged on the outer side of the thin film transistor arranged at least at one end of each of the signal wirings in a direction in which the signal wirings extend;

6. The display device according to any one of claims 1 to 4, The display device is characterized in that the at least one lightning rod element is arranged between the plurality of thin film transistors adjacent to each other.

7. The display device according to any one of claims 1 to 4, The lightning rod element is provided in plurality, a display device characterized in that the plurality of lightning rod elements are arranged both outside the thin film transistors arranged at at least one end of each of the signal wirings in the direction in which the signal wirings extend and between the plurality of thin film transistors adjacent to each other.

8. The display device according to any one of claims 1 to 4, The display device is characterized in that the first semiconductor layer and the second semiconductor layer are formed of a polysilicon film.

9. The display device according to any one of claims 1 to 4, The display device is characterized in that the signal wiring is a gate line.

10. The display device according to any one of claims 1 to 4, a light-emitting element layer provided on the thin film transistor layer; a sealing film provided so as to cover the light-emitting element layer.

11. 11. The display device according to claim 10, The display device is characterized in that the light emitting element layer is an organic electroluminescence element layer.

12. A base substrate; a thin film transistor layer provided on the base substrate, in which a semiconductor film, an inorganic insulating film, and a metal film are stacked in this order; The thin film transistor layer is a plurality of signal wirings formed from the metal film and extending parallel to one another in one direction; a plurality of thin film transistors provided along the signal lines and corresponding to a plurality of sub-pixels constituting the display area; at least one lightning rod element provided along each of the signal wirings and in the vicinity of the plurality of thin film transistors; each of the thin film transistors includes a first semiconductor layer formed of the semiconductor film and provided in an island shape so as to overlap at least a portion of each of the signal lines in a plan view; a manufacturing method of a display device including a second semiconductor layer formed by the semiconductor film and provided in an island shape so as to overlap at least a part of each of the signal wirings in a plan view, The thin film transistor layer forming step of forming the thin film transistor layer on the base substrate includes: a semiconductor layer forming step of forming a semiconductor film on a surface of a substrate on which a lower layer of the semiconductor film has been formed, and then patterning the semiconductor film to form the first semiconductor layer and the second semiconductor layer; an inorganic insulating film forming step of forming the inorganic insulating film on the surface of the substrate on which the first semiconductor layer and the second semiconductor layer are formed, so as to cover the first semiconductor layer and the second semiconductor layer; a wiring layer forming step of forming the metal film on the surface of the substrate on which the inorganic insulating film has been formed, and then patterning the metal film to form the plurality of signal wirings; A method for manufacturing a display device, characterized in that in the semiconductor layer formation process, the angle of the end face of the second semiconductor layer relative to the top surface of the base substrate is made larger than the angle of the end face of the first semiconductor layer relative to the top surface of the base substrate by controlling the photoresist contact angle and / or etching conditions of the semiconductor film.

Images