Power semiconductor device drive control circuit and power circuit

Abstract

In a drive control circuit (100), a mirror period determining circuit (190) determines whether it is a mirror period on the basis of a detection value of the voltage at a control electrode of a power semiconductor element (50), and stores a determination result in a flag register (145). A variable gate driver (170) applies a voltage to the control electrode of the power semiconductor element (50) with a current drive power in accordance with a current command value stored in an output port register (144). A controller (101) sequentially executes, in response to a gate signal (GS) supplied externally to the power semiconductor element (50), a plurality of instructions stored in at least one program memory (130, 131). The plurality of instructions include a conditional instruction for changing a current command value that is to be stored in the output port register (144) in accordance with the determination result, stored in the flag register (145), as to whether it is a mirror period.

Description

Technical Field

[0001] The present disclosure relates to a drive control circuit and a power circuit for driving and controlling a power semiconductor device.

Background Art

[0002] The gate drive circuit described in Patent Document 1 (International Publication No. 2015 / 122483) includes a gate resistor connected to the gate of a switching device and a gate diode connected in parallel with the gate resistor. Many conventional gate drive circuits adjust the gate current during switching using such a gate resistor and diode.

[0003] Patent Document 2 (Japanese Unexamined Patent Application Publication No. 2017-229151) aims to provide a drive device that drives a power semiconductor device while reflecting variations in the manufacturing process and external environment. Specifically, the drive device of this document includes a trigger detection circuit and a current switching circuit. The trigger detection circuit monitors the voltage or current between the terminals of the power semiconductor device during the switching period and detects that the voltage or current between the terminals has reached a predetermined reference value. The current switching circuit switches the register to be selected from a plurality of registers that store current values by using the detection result of the trigger detection circuit as a trigger during the switching period, thereby transitioning the drive current of the variable current driver circuit. Specifically, the current switching circuit is constituted by a state machine.

[0004] The power semiconductor element drive control circuit described in Patent Document 3 (Japanese Patent Application Publication No. 2018-093684) also takes into account the characteristic variations of the power semiconductor element, similar to the case of Patent Document 2. Specifically, the drive control circuit in this document comprises a state machine control circuit and a current drive circuit that drives the IGBT based on drive current information stored in the base data memory. The state machine control circuit drives the current drive circuit by reading the rise-up drive current information stored in the base data memory multiple times within a fixed period when the PWM signal is rising, and drives the current drive circuit by reading the fall-down drive current information stored in the base data memory multiple times within a predetermined period when the PWM signal is falling. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] International Publication No. 2015 / 122483 [Patent Document 2] Japanese Patent Publication No. 2017-229151 [Patent Document 3] Japanese Patent Publication No. 2018-093684 [Overview of the Initiative] [Problems that the invention aims to solve]

[0006] In well-known gate drive circuit configurations such as those in Patent Document 1, a gate resistor with a fixed resistance value is used, making it impossible to control the drive current of the drive circuit in accordance with variations in the characteristics of the power semiconductor element.

[0007] In the drive control circuit configurations of Patent Documents 2 and 3, the drive current of the gate drive circuit can be controlled according to the current value or drive current information stored in a register or memory. Therefore, while it can handle variations in the characteristics of power semiconductor elements to some extent, it cannot control the drive current value or drive current information that deviates from the predetermined value. 。

[0008] This disclosure has been made in consideration of the above-mentioned problems. One of the purposes of this disclosure is to provide a drive control circuit for a power semiconductor device that can control the power semiconductor device more appropriately than conventional methods in response to variations in the characteristics of the power semiconductor device and changes in its characteristics over time. [Means for solving the problem]

[0009] In one embodiment, a drive control circuit for driving and controlling a power semiconductor element comprises a Miller period determination circuit, a variable gate driver, and a controller. The Miller period determination circuit determines whether or not it is a Miller period based on the detected voltage of the control electrode of the power semiconductor element and stores the determination result in a flag register. The variable gate driver applies a voltage to the control electrode of the power semiconductor element with a current driving force corresponding to the current command value stored in the output port register. The controller sequentially executes a plurality of instructions stored in at least one program memory in response to a gate signal supplied from an external source to turn on and turn off the power semiconductor element. The plurality of instructions include a conditional instruction that changes the current command value to be stored in the output port register according to the determination result of whether or not it is a Miller period, which is stored in the flag register. [Effects of the Invention]

[0010] According to the above embodiment, the current driving force of the variable gate driver can be changed according to a set of instructions stored in program memory and the result of determining whether or not it is a mirror period. Therefore, the power semiconductor elements can be controlled more appropriately than in the conventional method in response to variations in the characteristics of the power semiconductor elements and changes in their characteristics over time. [Brief explanation of the drawing]

[0011] [Figure 1] This is a block diagram showing the configuration of the drive control circuit 100 according to Embodiment 1. [Figure 2] This diagram shows examples of commands in a table format. [Figure 3] Figure 1 is a circuit diagram showing an example of the Miller period determination circuit 190. [Figure 4] It is a block diagram showing a configuration example of buffers 180 to 182 in FIG. 1. [Figure 5] It is a diagram conceptually showing the voltage waveform or current waveform of each part of the drive control circuit 100 in FIG. 1. [Figure 6] It is a flowchart showing an example of a control algorithm at turn-on. [Figure 7] It is a diagram showing an example in which the control algorithm described with reference to FIG. 6 is described in a program. [Figure 8] It is a flowchart showing an example of a control algorithm at turn-off. [Figure 9] It is a diagram showing an example in which the control algorithm described in FIG. 8 is described in a program. [Figure 10] It is a diagram showing the simulation result of the double-pulse test of an IGBT by the drive control circuit of the comparative example. [Figure 11] It is a diagram showing the simulation result of the double-pulse test of an IGBT by the drive control circuit of the present embodiment. [Figure 12] It is a block diagram showing the configuration of a drive control circuit 300 as a modification of the drive control circuit 100 in FIG. 1. [Figure 13] It is a circuit diagram showing the configuration of a half-bridge 400. [Figure 14] It is a block diagram showing the detailed configuration of the drive control circuits 500A and 500B in FIG. 13. [Figure 15] It is a block diagram showing the configuration of a drive control circuit 600 according to Embodiment 3. [Figure 16] It is a diagram showing the configuration of drive control circuits 700A and 700B according to Embodiment 4. [Figure 17] It is a block diagram showing the configuration of a drive control circuit 800 according to Embodiment 5.

Mode for Carrying Out the Invention

[0012] Hereinafter, each embodiment will be described in detail with reference to the drawings. In the following description, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

[0013] Embodiment 1. [Configuration of Drive Control Circuit] FIG. 1 is a block diagram showing the configuration of a drive control circuit 100 according to Embodiment 1. Referring to FIG. 1, the drive control circuit 100 drives and controls a power semiconductor device 50. In the case of FIG. 1, an IGBT (Insulated Gate Bipolar Transistor) is shown as the power semiconductor device 50, but it is not limited thereto. For example, the power semiconductor device 50 may be a bipolar transistor or a FET (Field-Effect Transistor).

[0014] As shown in FIG. 1, a freewheeling diode 51 is connected in the reverse bias direction between the main electrode E on the low potential side and the main electrode C on the high potential side of the power semiconductor device 50. Further, in order to prevent the control electrode G from becoming a negative potential, a diode 53 is connected between the main electrode C on the low potential side and the control electrode G so that the direction from the main electrode C to the control electrode G is in the forward direction. The main electrode E on the low potential side is connected to a ground 52 that provides a reference potential.

[0015] In the following description, the main electrode C on the high potential side may be referred to as a collector, the main electrode E on the low potential side may be referred to as an emitter, and the control electrode G may be referred to as a gate. Also, the main current flowing between the main electrode C and the main electrode E may be referred to as a collector current ICE, and the voltage between the main electrode C and the main electrode E may be referred to as a collector voltage VCE. The current flowing into or out of the control electrode G may be referred to as a gate current, and the voltage between the control electrode G and the main electrode E on the low potential side may be referred to as a gate voltage VGE.

[0016] The drive control circuit 100 comprises a controller 101, a variable gate driver 170, a Miller period determination circuit 190, and a current estimation circuit 191. Furthermore, the controller 101 comprises a counter 150, program memories 130 and 131, an edge trigger circuit 160, a register file 140, an instruction decoder 120, and an ALU (Arithmetic Logic Unit) 110.

[0017] The edge trigger circuit 160 detects the rising and falling edges of the gate signal GS input from an external source and outputs an edge detection pulse (also called a trigger pulse). In this embodiment, the gate signal GS is assumed to be positive logic. Therefore, when the gate signal GS is at a high level (H level), the gate signal GS is in an active state and the power semiconductor element 50 is in an ON state. When the gate signal GS is at a low level (L level), the gate signal GS is in an inactive state and the power semiconductor element 50 is in an OFF state.

[0018] The edge trigger circuit 160 is composed of, for example, two D-FFs (flip-flops), an inverter, and a logical AND circuit. Specifically, the gate signal GS is input to the clock input of the first D-FF. The inverted gate signal GS is input to the clock input of the second D-FF via the inverter. By calculating the logical AND of the output signal of the first D-FF and the inverted output signal of the second D-FF, an edge detection pulse corresponding to the rising edge of the gate signal GS can be generated. Also, by calculating the logical AND of the inverted output signal of the first D-FF and the output signal of the second D-FF, an edge detection pulse corresponding to the falling edge of the gate signal GS can be generated. In the above, the power supply voltage is input to the D terminals of the first and second D-FFs.

[0019] The program memory 130 stores a number of instructions (also referred to as first instructions) that should be executed when the power semiconductor element 50 is turned on. The program memory 131 stores a number of instructions (also referred to as second instructions) that should be executed when the power semiconductor element 50 is turned off.

[0020] Figure 2 is a table illustrating an example of an instruction. As shown in Figure 2, an instruction includes an instruction code and operands. The operands include the name of the register to be read from or written to, and an immediate value. For example, in "LOAD_IM(register, immediate value)", "LOAD_IM" is the instruction code, and "register" and "immediate value" are the operands. Details of the function of each instruction in Figure 2 will be described later.

[0021] Returning to Figure 1, when the edge trigger circuit 160 detects the rising edge of the gate signal GS, the counter 150 increments its count value by 1 based on the external clock. The counter 150 outputs address ADDR corresponding to the count value to the turn-on program memory 130 and reads the instruction (ROM_DATA in Figure 1) stored at address ADDR from the program memory 130. The counter 150 outputs the instruction code and immediate value included in the instruction read from the program memory 130 as data B to the instruction decoder 120. Furthermore, the counter 150 outputs the name of the register to be read or written included in the instruction read from the program memory 130 as data A to the register file 140. The value read from the specified register is output as data C from the register file 140 to the instruction decoder 120. Data D includes the value of register (CUR) 146 and the value of flag register (MRR) 145, and is output from the register file 140 to the instruction decoder 120.

[0022] The operation of the counter 150 when the falling edge of the gate signal GS is detected by the edge trigger circuit 160 is almost the same as described above. However, in this case, the program memory 131 for turn-off is accessed by the counter 150.

[0023] The instruction decoder 120 interprets the instruction code (data B) together with the value of the flag register (MRR) 145 (data D), and outputs the ENABLE signal for the arithmetic circuit to be executed as data E to the ALU 110. Furthermore, the instruction decoder 120 outputs the register values ​​and immediate values ​​necessary for the calculation as data F to the ALU 110.

[0024] Based on the ENABLE signal received from the instruction decoder 120 as data E, the ALU 110 performs an operation using the register values ​​and / or immediate values ​​received as data F. Supported operations include, for example, addition, subtraction, and logical operations. The ALU 110 may also be configured to perform other operations such as multiplication and division. The ALU 110 outputs the operation result as data G to the register file 140.

[0025] The register file 140 includes multiple registers for storing various values. Specifically, the register file 140 includes a program counter (PC) 141, a general-purpose register (R0) 142, a general-purpose register (R1) 143, a register (CUR) 146, a flag register (MRR) 145, and an output port register (PORTOUT) 144.

[0026] The program counter (PC) 141 is essentially the same as the counter 150 mentioned above. The register (CUR) 146 (also called the first register) stores the current value estimated by the current estimation circuit 191. The flag register (MRR) 145 stores the flag value representing the determination result of the Miller period determination circuit 190. The output port register (PORTOUT) 144 stores the current command value to be output to the variable gate driver 170.

[0027] As already explained, the register file 140 receives the register names required for instruction execution as data A, and the calculation result of the ALU 110 as data G. The register file 140 stores data G in a general-purpose register 142 or general-purpose register 143, etc. The register file 140 also outputs the values ​​of the registers required for instruction execution as data C to the instruction decoder 120, and outputs the values ​​of register (CUR) 146 and flag register (MRR) 145, etc., as data D to the instruction decoder 120.

[0028] The Miller period determination circuit 190 monitors the voltage value of the control electrode G of the power semiconductor element 50 and determines whether or not it is a Miller period based on the voltage value of the control electrode G. If the Miller period determination circuit 190 determines that it is a Miller period, it outputs a high-level signal to the flag register (MRR) 145 and the current estimation circuit 191.

[0029] Figure 3 is a circuit diagram showing an example of the Miller period determination circuit 190 of Figure 1. Referring to Figure 3, the Miller period determination circuit 190 comprises a differentiating circuit 210, an integrating circuit 220, comparators 230 and 231, threshold voltage generation circuits 250 and 251, and an edge detection circuit 240.

[0030] The differentiating circuit 210 includes a capacitor 211 and a resistor 212 connected in series, with a gate voltage VGE input to one end. The integrating circuit 220 is located after the differentiating circuit 210 and includes a capacitor 221 and a resistor 222. The capacitor 221 is connected between the input node 223 of the integrating circuit 220 and ground 52. The resistor 222 is connected between the input node 223 of the integrating circuit 220 and the output node 224. The integrating circuit 220 is provided to blunt the differentiated signal output from the differentiating circuit 210.

[0031] The threshold voltage generation circuit 250 generates a negative threshold voltage Vng. The threshold voltage generation circuit 251 generates a positive threshold voltage Vps. The comparator 231 detects the Miller period at turn-on by comparing the output signal of the integrating circuit 220 with the positive threshold voltage Vps. The comparator 230 detects the Miller period at turn-off by comparing the output signal of the integrating circuit 220 with the negative threshold voltage Vng.

[0032] The edge detection circuit 240 detects the edges of the output signals of comparators 230 and 231. Specifically, when the circuit is turned on, the output signal of comparator 231 changes in the order of L level, H level, L level, H level, L level. Therefore, the edge detection circuit 240 switches its output to H level on the first falling edge and switches its output to L level on the next rising edge. Also, when the circuit is turned off, the output signal of comparator 230 changes in the order of H level, L level, H level, L level, H level. Therefore, the edge detection circuit 240 switches its output to H level on the first rising edge and switches its output to L level on the next falling edge. Thus, the period during which the Miller period determination circuit 190 outputs an H level signal corresponds to the Miller period.

[0033] Returning to Figure 1, while the Mirror Period Determination Circuit 190 determines that a Mirror Period is occurring, the flag stored in the Flag Register (MRR) 145 is set to "1". Therefore, if the instruction decoded by the Instruction Decoder 120 is a conditional instruction that is in a Mirror Period, the load, store, jump instruction, etc., will be executed if the flag stored in the Flag Register (MRR) 145 is set to "1". This function ensures that the current driving force from the gate driver to the power semiconductor element 50 can be reliably changed during the Mirror Period, even if the start and end timings of the Mirror Period change. As a result, the power semiconductor element 50 can be operated in a way that suppresses switching losses and surges. In the following description, the current driving force will also be simply referred to as the driving force.

[0034] The current estimation circuit 191 receives a flag value representing the Miller period from the Miller period determination circuit 190, as well as the voltage of the control electrode G at that time (i.e., the gate voltage). Based on these, the current estimation circuit 191 estimates the main current (i.e., the collector current) flowing between the main electrodes and stores the estimation result in the register (CUR) 146. Since the gate voltage during the Miller period is proportional to the collector current, the collector current can be estimated based on the gate voltage. To estimate the collector current, a table showing the relationship between the gate voltage and the collector current may be created in advance and this table may be referenced, or the collector current may be calculated from the gate current using a linear approximation formula. Note that a different method may be used as the collector current estimation method in the current estimation circuit 191.

[0035] The variable gate driver 170 is connected to the output port register (PORTOUT) 144 of the register file 140 and applies a voltage to the control electrode G of the power semiconductor element 50 with a current driving force corresponding to the current command value stored in the output port register 144. As shown in Figure 1, the variable gate driver 170 includes a level shifter 171 and buffers 180, 181, and 182.

[0036] The level shifter 171 receives a current command value, for example, a 3-bit digital signal, from the output port register 144. The level shifter 171 level-shifts this digital signal, which represents a voltage value such as 5V / 0V or 3.3V / 0V, to a digital signal representing a voltage value of 15V / 0V, and outputs it to buffers 180, 181, and 182.

[0037] Buffers 180, 181, and 182 receive a level-shifted 3-bit digital signal and generate an analog voltage corresponding to this digital signal, which is then applied to the control electrode G of the power semiconductor element 50. Here, buffers 180, 181, and 182 are configured such that the current driven by buffer 181 is twice the reference value, and the current driven by buffer 182 is four times the reference value, with the current driven by buffer 180 being used as a reference. By increasing the number of buffer stages, the amount of drive current can be controlled more precisely.

[0038] Figure 4 is a block diagram showing an example configuration of buffers 180 to 182 in Figure 1. Referring to Figures 1 and 4, buffer 180 includes a PMOS (P-channel Metal Oxide Semiconductor) transistor 180A connected between the power node 57 for the drive control circuit 100 and the control electrode G of the power semiconductor element 50, and an NMOS (N-channel Metal Oxide Semiconductor) transistor 180B connected between the control electrode G and ground 52. Similarly, buffer 181 includes a PMOS transistor 181A connected between the power node 57 and the control electrode G, and an NMOS transistor 181B connected between the control electrode G and ground 52. Buffer 182 includes a PMOS transistor 182A connected between the power node 57 and the control electrode G, and an NMOS transistor 182B connected between the control electrode G and ground 52. According to the above connection relationships, the PMOS transistors 180A, 181A, and 182A are connected in parallel to each other between the power node 57 and the control electrode G. NMOS transistors 180B, 181B, and 182B are connected in parallel to each other between the control electrode G and ground 52.

[0039] To differentiate the buffer's current-driving power (i.e., the amount of driving current), for example, the gate width of each PMOS transistor 181A and NMOS transistor 181B is twice the gate width of each PMOS transistor 180A and NMOS transistor 180B. Also, the gate width of each PMOS transistor 182A and NMOS transistor 182B is four times the gate width of each PMOS transistor 180A and NMOS transistor 180B.

[0040] In one embodiment, when the controller 101 is turned on, it turns on at least one of the upper arm's PMOS transistors 180A, 181A, and 182A according to the amount of drive current, and turns off all of the lower arm's NMOS transistors 180B, 181B, and 182B. As a result, current flows from the power node 57 to the control electrode G of the power semiconductor element 50, and charge flows into the control electrode G. When the controller 101 is turned off, it turns on at least one of the lower arm's NMOS transistors 180B, 181B, and 182B according to the amount of drive current, and turns off the upper arm's PMOS transistors 180A, 181A, and 182A. As a result, current flows from the control electrode G of the power semiconductor element 50 to ground 52, and charge flows out from the control electrode G.

[0041] As a variation of the above, during a certain period of time when the device is turned on, at least one of the NMOS transistors 180B, 181B, and 182B of the lower arm may be turned on and the PMOS transistors 180A, 181A, and 182A of the upper arm may be turned off depending on the amount of drive current. This allows current to flow from the control electrode G of the power semiconductor element 50 to ground 52 during a certain period of time when the device is turned on, thereby drawing charge from the control electrode G.

[0042] Furthermore, as a variation of the above, during a certain period of time during turn-off, at least one of the PMOS transistors 180A, 181A, and 182A of the upper arm may be turned on according to the amount of drive current, while all of the NMOS transistors 180B, 181B, and 182B of the lower arm may be turned off. This makes it possible to supply current from the power node 57 to the control electrode G of the power semiconductor element 50 and inject charge into the control electrode G during a certain period of time during turn-off.

[0043] As described above, with the configuration of the variable gate driver 170 shown in Figure 4, not only the current driving force (i.e., the amount of driving current) of the variable gate driver 170, but also the direction of the driving current (i.e., the gate current) can be varied.

[0044] [Operation of the drive control circuit] Next, we will describe a typical operation of the drive control circuit 100 shown in Figure 1.

[0045] Figure 5 is a conceptual diagram showing the voltage or current waveforms of each part of the drive control circuit 100 in Figure 1. From top to bottom, Figure 5 shows the waveforms of the gate voltage VGE, collector current ICE, collector voltage VCE, and the derivative of the gate voltage, a signal waveform showing the Miller period, the on-period of the MOS (Metal Oxide Semiconductor) transistor (MOS-Tr) inside the IGBT, and an example of gate current intensity control.

[0046] The waveform of the gate voltage VGE during turn-on has three sections: period A from time t1 to time t2 where the first stage has a positive slope, period B from time t2 to time t3 where the slope is 0, and period C from time t3 to time t4 where the second stage has a positive slope. During period C, the gate voltage reaches its maximum value. The period during which the gate voltage VGE is flat, i.e., period B, corresponds to the Miller period. Similarly, the waveform of the gate voltage VGE during turn-off has three sections: period D from time t5 to time t6 where the first stage has a negative slope, period E from time t6 to time t7 where the slope is 0, and period F from time t7 to time t8 where the second stage has a negative slope. During period F, the gate voltage returns to 0 voltage. The period during which the gate voltage VGE is flat, i.e., period E, corresponds to the Miller period.

[0047] The collector current ICE increases during period A and overshoots at the beginning of period B. Then, for the remainder of period B, period C, from time t4 to time t5, period D, and period E, the collector current ICE remains constant. During period F, the collector current ICE decreases to 0.

[0048] The collector voltage VCE is constant during period A, but decreases to a voltage close to ground voltage during period B. A small voltage may remain until the beginning of period C. After that, for the remainder of period C, from time t4 to time t5, and during period D, the collector voltage VCE is constant, approximately ground voltage. The collector voltage VCE increases during period E and returns to the same voltage value as during period A during period F.

[0049] The derivative of the gate voltage VGE is positive when the gate voltage VGE increases and negative when the gate voltage VGE decreases. That is, the derivative of the gate voltage VGE is positive in periods A and C, negative in periods D and E, and zero in all other periods.

[0050] The Miller period can be determined based on the time derivative information of the gate voltage VGE detected by the Miller period determination circuit 190 in Figure 1. Specifically, the Miller period determination circuit 190 outputs a high-level signal when it detects the falling edge of the derivative of the gate voltage VGE from positive to zero, and outputs a low-level signal when it detects the rising edge of the derivative of the gate voltage VGE from zero to positive. Furthermore, the Miller period determination circuit 190 outputs a high-level signal when it detects the rising edge of the derivative of the gate voltage VGE from negative to zero, and outputs a low-level signal when it detects the falling edge of the derivative of the gate voltage VGE from zero to negative.

[0051] The IGBT, as the power semiconductor element 50, has a structure that combines an NMOS transistor and a PNP bipolar transistor. In Figure 5, the period required to strongly turn on the MOS transistor inside the IGBT is shown as the MOS transistor on-time.

[0052] As described above, by detecting the Miller period, the gate current at turn-on can be controlled by dividing it into three periods A, B, and C, and the gate current at turn-off can be controlled by dividing it into three periods D, E, and F. Based on the clock provided in the drive control circuit 100, each period may be further divided and the gate current may be controlled in more detail. Figure 5 shows an example in which the gate current strength is increased in periods A, C, D, and F, and the gate current strength is decreased in the Miller period of periods B and E.

[0053] [Flowchart and program example (turn-on)] The following describes a flowchart and program illustrating an example of a control algorithm for the power semiconductor element 50 by the drive control circuit 100.

[0054] Figure 6 is a flowchart showing an example of a control algorithm during turn-on. Figure 6 shows an example of a gate current strength command value (referred to as the current command value) output from the output port register (PORTOUT) 144 of the controller 101 to the variable gate driver 170. As mentioned above, the current command value stored in the output port register (PORTOUT) 144 is output to the variable gate driver 170. The current driving force of the variable gate driver 170 is represented by a value from 0 to 7, assuming 3 bits. A driving force of 0 indicates that no current is flowing, and a driving force of 7 indicates that the maximum current is flowing. The current value output from the variable gate driver 170 to the control electrode G of the power semiconductor element 50 changes in proportion to the numerical value representing the driving force.

[0055] In period A of Figure 5, the control strategy is to rapidly raise the voltage (gate voltage) of the control electrode G of the power semiconductor element 50 by applying the maximum current to the control electrode G. Specifically, in step S101, the controller 101 assigns the maximum driving force 7 to the output port register (PORTOUT) 144 over 5 clock cycles. As a result, the driving force 7 is output from the output port register (PORTOUT) 144 to the variable gate driver 170 for 5 clock cycles.

[0056] During period B, the control strategy is to reduce the gate current to its minimum value and then return it to its original value in order to suppress collector current surges. Specifically, in step S102, the controller 101 assigns a driving force of 1, which represents the minimum current, to the output port register (PORTOUT) 144. As a result, the output current of the variable gate driver 170 decreases to the minimum current.

[0057] In the next step S103, the controller 101 determines whether or not it is a mirror period based on the detection result of the mirror period determination circuit 190. If it is a mirror period (YES in step S103), the controller 101 assigns a driving force of 3 to the variable gate driver 170. If it is not a mirror period (NO in step S103), the value of the driving force stored in the output port register (PORTOUT) 144 remains at 1.

[0058] Subsequently, in step S105, the controller 101 assigns the drive force 7, which represents the maximum current, to the output port register (PORTOUT) 144 over a period of 5 clock cycles. As a result, the drive force 7 is output from the output port register (PORTOUT) 144 to the variable gate driver 170 for 5 clock cycles.

[0059] During period C, the control policy is to return the gate current to its maximum value if the Miller period has ended. First, in step S106, the controller 101 assigns the drive force 3 to the output port register (PORTOUT) 144. As a result, the drive force 3 is output from the output port register (PORTOUT) 144 to the variable gate driver 170.

[0060] Next, in step S107, the controller 101 determines whether or not it is a mirror period. If it is a mirror period (NO in step S107), it assigns the maximum driving force of 7 to the output port register (PORTOUT) 144 (step S108). Therefore, if the mirror period is not over (YES in step S107), the value representing the driving force stored in the output port register (PORTOUT) 144 remains at 3. The above step of assigning the maximum driving force of 7 to the output port register (PORTOUT) 144 if it is not a mirror period is performed a total of three times (steps S107 to S112). After that, the controller 101 fixes the value stored in the output port register (PORTOUT) 144 to the maximum driving force of 7 (step S113).

[0061] Next, we will explain how to implement the above representative control algorithms in a program. First, let's return to Figure 2 and explain the instructions used in the program. In Figure 2, each register represents one of the registers included in register file 140 in Figure 1. The immediate value is assumed to be 32 bits wide.

[0062] The LOAD_IM instruction in Figure 2 assigns an immediate value to a register. By specifying the output port register (PORTOUT) 144 as the register, the driving force of the variable gate driver 170 can be changed.

[0063] The MOV instruction performs an assignment between registers. The LOAD_MR instruction assigns an immediate value to the specified register when it is a mirror period. When it is not a mirror period, no immediate value is assigned to the register. If the output port register (PORTOUT) 144 is specified as the register, the driving force of the variable gate driver 170 changes to the immediate value assigned to the output port register (PORTOUT) 144 when it is a mirror period.

[0064] The LOAD_NMR instruction assigns an immediate value to the specified register when it is not a mirror period. When it is a mirror period, no immediate value is assigned to the register. If the output port register (PORTOUT) 144 is specified as the register, the driving force of the variable gate driver 170 changes to the immediate value assigned to the output port register (PORTOUT) 144 when it is not a mirror period.

[0065] The JUMP instruction assigns an immediate value to the program counter (PC) 141 in register file 140. This changes the address in program memory to which the next instruction to be executed will be located. As a variation of the JUMP instruction, a JUMP instruction may be provided that jumps to a specified address when the values ​​of two registers are compared, or when the values ​​of a register are compared with an immediate value, and the values ​​are equal or unequal, or when one is smaller or larger than the other. Alternatively, a JUMP instruction may be provided that jumps to a specified address when it is a mirror period or when it is not a mirror period.

[0066] The ADD_IM instruction adds the value stored in a register to an immediate value and stores the result of the addition in the register.

[0067] The ADD_MR instruction adds the value stored in a register to an immediate value during the mirror period and stores the result in the register. The addition operation is not performed when the mirror period is not active.

[0068] The ADD_NMR instruction adds the value stored in a register to an immediate value when it is not in the mirror period, and stores the result in the register. The addition operation is not performed during the mirror period.

[0069] The SUB_IM instruction subtracts an immediate value from the value stored in a register and stores the result of the subtraction in the register.

[0070] The SUB_MR instruction subtracts an immediate value from the value stored in a register and stores the result of the subtraction in the register when it is the mirror period. The subtraction is not performed when it is not the mirror period.

[0071] The SUB_NMR instruction subtracts an immediate value from the value stored in a register and stores the result of the subtraction in the register when it is not a mirror period. Subtraction is not performed when it is a mirror period.

[0072] The controller 101 may be configured to execute multiplication, division, and shift instructions in addition to addition and subtraction. With such an instruction set, the drive force can be calculated according to the length of the Miller period, collector voltage value, or collector current value, and the calculation result can be stored in the output port register (PORTOUT) 144. As a result, the drive force of the variable gate driver 170 can be changed.

[0073] Figure 7 shows an example of the control algorithm described in Figure 6 written in a program. From left to right in Figure 7, the program memory address 130, the instruction code, the registers required to execute the instruction, and operands such as immediate values ​​are shown.

[0074] During period A in Figure 7, the LOAD_IM instruction from address 0 to address 4 assigns the value 7, representing the maximum output, to the output port register (PORTOUT) 144. This causes the voltage of the control electrode G of the power semiconductor element 50 to rise rapidly.

[0075] The LOAD_IM instruction at address 5 during period B assigns the value 1, representing the minimum output, to the output port register (PORTOUT) 144. This reduces the current output from the variable gate driver 170 to the control electrode G of the power semiconductor element 50 to its minimum value, thereby suppressing surges in the collector current of the power semiconductor element 50.

[0076] Next, the LOAD_MR_IM instruction at address 6 during period B ensures that if the mirror period has not begun, the value of the output port register (PORTOUT) 144 remains at its minimum value of 1. If the mirror period has begun, the value 3 is assigned to the output port register (PORTOUT) 144. This allows the gate current value to be adjusted according to the change at the start of the mirror period.

[0077] Next, the LOAD_IM instruction from address 7 to address 11 in period B assigns the value 7 to the output port register (PORTOUT) 144. This causes the variable gate driver 170 to output a maximum current for 5 clock cycles to the control electrode G of the power semiconductor element 50.

[0078] Next, the LOAD_IM instruction at address 12 during period C assigns the value 3 to the output port register (PORTOUT) 144.

[0079] Next, the LOAD_NMR_IM instruction at address 13 ensures that if the Miller period is still in effect, the value of the output port register (PORTOUT) 144 remains at 3, and the control electrode G of the power semiconductor element 50 is charged with a moderate current. If the Miller period has ended, the output port register (PORTOUT) 144 is assigned the value 7, which corresponds to the maximum current. This causes the control electrode G of the power semiconductor element 50 to be rapidly charged. The same instruction as at address 13 is repeated at addresses 14 and 15. This allows the gate current value to be adjusted according to the changes at the end of the Miller period.

[0080] Next, the LOAD_IM instruction at address 16 assigns the value 7, corresponding to the maximum current, to the output port register (PORTOUT) 144. Furthermore, the JUMP instruction at address 17 repeats the LOAD_IM instruction at address 16. This fixes the output from the output port register (PORTOUT) 144 to the variable gate driver 170 at the maximum output.

[0081] As described above, thanks to the LOAD_MR_IM and LOAD_NMR_IM instructions included in periods B and C, nearly identical gate current control can be achieved even when the collector voltage and collector current waveforms change.

[0082] [Flowchart and program example (during turn-off)] Next, we will explain the gate current control during the turn-off of the power semiconductor element 50. The direction of the gate current during turn-off is opposite to the direction of the gate current during turn-on. Also, the control strategy during turn-off is similar to that during turn-on, but not exactly the same. This is because the freewheeling diode 51, which is connected in antiparallel to the power semiconductor element 50, cannot be controlled by the gate voltage, so even if the gate current control during turn-off is exactly the same as during turn-on, the same effect cannot be obtained.

[0083] Figure 8 is a flowchart showing an example of a control algorithm during turn-off. Referring to Figure 8, during period D, the control strategy is to rapidly lower the voltage (gate voltage) of the control electrode G by maximizing the current drawn from the control electrode G of the power semiconductor element 50. Specifically, in step S201, the controller 101 assigns the maximum driving force 7 to the output port register (PORTOUT) 144 over 5 clock cycles. As a result, the driving force 7 is output from the output port register (PORTOUT) 144 to the variable gate driver 170 for 5 clock cycles.

[0084] During period E, the control strategy is to suppress voltage changes at the control electrode G by minimizing the current drawn from the control electrode G of the power semiconductor element 50. Specifically, in step S202, the controller 101 assigns a minimum driving force of 1 to the output port register (PORTOUT) 144 over 7 clock cycles. As a result, the driving force of 1 is output from the output port register (PORTOUT) 144 to the variable gate driver 170 for 7 clock cycles.

[0085] During period F, the control strategy is to gradually lower the voltage of the control electrode G of the power semiconductor element 50. Therefore, the timing of returning the driving force of the variable gate driver 170 to its maximum value of 7 is delayed.

[0086] Specifically, in step S203, the controller 101 first assigns the driving force 3 to the output port register (PORTOUT) 144.

[0087] In the next step S204, the controller 101 determines whether or not it is a mirror period. If it is a mirror period (YES in step S204), it assigns the maximum driving force of 7 to the output port register (PORTOUT) 144 (step S205). If the mirror period has ended, the current driving force of 3 is maintained.

[0088] In the next step, S206, the controller 101 determines whether or not it is a mirror period. If it is a mirror period (YES in step S206), it assigns the driving force of 3 to the output port register (PORTOUT) 144 (step S207). If the mirror period has ended (NO in step S206), the current driving force of 3 or 7 is maintained.

[0089] In the next step, S208, the controller 101 determines whether or not it is the mirror period. If the mirror period has ended (NO in step S208), it assigns the maximum driving force of 7 to the output port register (PORTOUT) 144 (step S209). If the mirror period has not ended (YES in step S208), the current driving force of 3 is maintained. Subsequently, the controller 101 fixes the value stored in the output port register (PORTOUT) 144 to the maximum driving force of 7 (step S210).

[0090] Figure 9 shows an example of the control algorithm described in Figure 8 written in a program. From left to right in Figure 9, the program memory address 131, the instruction code, the registers required to execute the instruction, and operands such as immediate values ​​are shown.

[0091] During period D in Figure 9, the LOAD_IM instruction from address 0 to address 4 assigns the value 7, representing the maximum output, to the output port register (PORTOUT) 144. This causes the voltage of the control electrode G of the power semiconductor element 50 to fall rapidly.

[0092] The LOAD_IM instruction at addresses 5 through 11 during period E assigns the value 1, representing the minimum output, to the output port register (PORTOUT) 144. This suppresses voltage changes at the control electrode G of the power semiconductor element 50.

[0093] The LOAD_IM instruction at address 12 during period F assigns the value 3, representing a moderate current value, to the output port register (PORTOUT) 144.

[0094] Next, the LOAD_MR_IR instruction at address 13 assigns the value 7, representing the maximum current, to the output port register (PORTOUT) 144, if the mirror period is still in effect. If the mirror period has ended, the value of the output port register (PORTOUT) 144 remains at 3, representing a moderate current value.

[0095] Next, the LOAD_MR_IR instruction at address 14 assigns the value 3, representing a moderate current value, to the output port register (PORTOUT) 144, if the mirror period is still in effect. If the mirror period has ended, the value of the output port register (PORTOUT) 144 remains either 3 or 7.

[0096] Next, the LOAD_NMR_IM instruction at address 15 assigns the value 7, representing the maximum current, to the output port register (PORTOUT) 144 if the mirror period has ended. If the mirror period is still in progress, the value of the output port register (PORTOUT) 144 remains at 3, representing a moderate current value.

[0097] Next, the LOAD_IM instruction at address 16 assigns the value 7, corresponding to the maximum current, to the output port register (PORTOUT) 144. Furthermore, the JUMP instruction at address 17 repeats the LOAD_IM instruction at address 16. This fixes the output from the output port register (PORTOUT) 144 to the variable gate driver 170 at the maximum output.

[0098] [Simulation Results] To verify the effectiveness of the drive control circuit 100 in this embodiment, a circuit simulation simulating a double-pulse test of a power element was performed, and the losses during that test were calculated.

[0099] Figure 10 shows the simulation results of a double-pulse test of an IGBT using the comparative example's drive control circuit. In the comparative example's drive control circuit, a 20Ω gate resistor is provided, and the driving force of the gate driver is not changed. A SPICE model was used to simulate the IGBT.

[0100] Figure 10 shows the waveforms of the gate signal, loss (μJ), collector current IC (A), collector voltage VC (V), and gate voltage (V), from top to bottom. The loss can be calculated by multiplying the collector current and the collector voltage. Integrating the loss at a time of 20 μs and the loss at a time of 60 μs yielded 636 μJ.

[0101] Figure 11 shows the simulation results of a double-pulse test of an IGBT using the drive control circuit of this embodiment. In this embodiment, no gate resistor is provided. A SPICE model was used to simulate the IGBT.

[0102] Figure 11 shows, from top to bottom, the waveforms of the timing pulse that sets the output of the Miller period determination circuit 190 to a low level, the timing pulse that sets the output of the Miller period determination circuit 190 to a high level, the gate signal, loss (μJ), collector current IC (A), collector voltage VC (V), and gate voltage (V). The loss can be calculated by multiplying the collector current and the collector voltage. Integrating the loss when the time is 20 μs and the loss when the time is 60 μs yielded 359 μJ. Therefore, it was confirmed that the drive control circuit 100 of this embodiment can operate in a way that reduces the loss compared to the comparative example, even without providing a gate resistor.

[0103] [Modified example of Embodiment 1] Figure 12 is a block diagram showing the configuration of a drive control circuit 300 as a modified example of the drive control circuit 100 in Figure 1.

[0104] The drive control circuit 300 in Figure 12 differs from the drive control circuit 100 in Figure 1 in that it has a program memory 330 that shares the program memory 130 and program memory 131 of Figure 1. The program memory 330 stores both a program used for controlling the power semiconductor element 50 when it is turned on and a program used for controlling the power semiconductor element 50 when it is turned off.

[0105] For example, the program for control during turn-on is stored starting from address 0 in program memory 330, and the program for control during turn-off is stored starting from address 128 in program memory 330. In this case, during turn-on, addresses are executed in increments of 1 from address 0 according to the external clock, and during turn-off, addresses are executed in increments of 1 from address 128 according to the external clock. By setting the address where the program starts during turn-off to a power of 2, the circuit size can be reduced.

[0106] Other aspects of Figure 12 are the same as those in Figure 1, so the same reference numerals are used for the same or corresponding parts, and the explanation is not repeated.

[0107] [Effects of Embodiment 1] As described above, the drive control circuits 100 and 300 of this embodiment can adjust the driving force of the variable gate driver 170 and change the direction of the current when the power semiconductor element 50 is turned on and turned off by sequentially executing a plurality of instructions stored in the program memories 130, 131, and 330. The contents of the program memories 130, 131, and 330 can be arbitrarily rewritten after the drive control circuits 100 and 300 are manufactured as ICs (Integrated Circuits). Furthermore, by providing terminals for the program memory on the power module housing so that the program can be written after the power module is assembled, adjustment of the gate resistance in the later process becomes unnecessary.

[0108] Furthermore, the above-mentioned instructions include conditional instructions that execute or modify processing depending on the state of the power semiconductor element 50. This allows the gate drive current value to be adjusted or the direction of the current to be changed in response to changes in the collector voltage and / or collector current of the power semiconductor element 50. For example, in turn-on control, it is possible to rapidly charge the control electrode G before the start of the Miller period, reduce the driving force or change the direction of the current to extract charge from the control electrode G just before entering the Miller period, and then rapidly charge the control electrode G again when the Miller period begins. Similarly, at the end of the Miller period, it is possible to temporarily reduce the driving force or change the direction of the current to extract charge from the control electrode G, and then rapidly charge the control electrode G again. Therefore, instead of a fixed control of the power semiconductor element 50 according to a predetermined time progression, the power semiconductor element 50 can be flexibly controlled according to the state of the power semiconductor element 50. As a result, surges can be suppressed and switching losses can be reduced.

[0109] Furthermore, the drive control circuits 100 and 300 of this embodiment can also handle deterioration of the power semiconductor element 50 over time, deterioration of the wires in the power module, or deterioration of the cooling mechanism of the power module. If such deterioration causes changes in the collector voltage and / or collector current, or changes in the start and end timing of the Miller period, the program can be rewritten to reflect these changes. As a result, the driving force of the variable gate driver 170 can be adjusted to mitigate the effects of deterioration. In addition, since instructions can be freely added, changed, or deleted during program rewriting, situations not anticipated during the design phase can also be addressed.

[0110] Embodiment 2. Embodiment 2 describes a case in which a half-bridge circuit is configured as a power circuit by connecting two power semiconductor elements in series.

[0111] Figure 13 is a circuit diagram showing the configuration of the half-bridge 400. As shown in Figure 13, the half-bridge 400 includes power semiconductor elements 50A and 50B, freewheeling diodes 51A and 51B, diodes 53A and 53B, and drive control circuits 500A and 500B.

[0112] Power semiconductor elements 50B and 50A are connected in series between the power supply 56 and the ground 52 in this order. Power semiconductor element 50A is also referred to as the lower arm or low-side power semiconductor element 50A, and power semiconductor element 50B is also referred to as the upper arm or high-side power semiconductor element 50B. Freewheeling diodes 51A and 51B are connected in antiparallel to power semiconductor elements 50A and 50B, respectively. Diode 53A is connected between the main electrode C and control electrode G on the low-potential side of power semiconductor element 50A, such that the direction from the main electrode C to the control electrode G is the forward direction. Similarly, diode 53B is connected between the main electrode C and control electrode G on the low-potential side of power semiconductor element 50B, such that the direction from the main electrode C to the control electrode G is the forward direction.

[0113] The drive control circuit 500A is provided in correspondence with the power semiconductor element 50A and controls the switching of the corresponding power semiconductor element 50A based on the input gate signal GSA and the detected collector voltage and / or collector current of the power semiconductor element 50A. Similarly, the drive control circuit 500B is provided in correspondence with the power semiconductor element 50B and controls the switching of the corresponding power semiconductor element 50B based on the input gate signal GSB and the detected collector voltage and / or collector current of the power semiconductor element 50B. In the following description, the drive control circuits 500A and 500B will be collectively referred to as the drive control circuit 500.

[0114] The gate signals GSA and GSB described above are inverted signals of each other, and both have a dead time during which they are both at a low level. This prevents arm short circuits from occurring, where the power semiconductor element 50B on the upper arm and the power semiconductor element 50A on the lower arm are turned on simultaneously. However, arm short circuits may still occur due to signal delays or other reasons. Therefore, each of the drive control circuits 500A and 500B transmits the control timing of the corresponding power semiconductor element as an asynchronous signal 461 to the other drive control circuit. Based on the control timing received from the other, each of the drive control circuits 500A and 500B starts the turn-on operation of the corresponding power semiconductor element after the other's turn-off operation is completed.

[0115] Figure 14 is a block diagram showing the detailed configuration of the drive control circuits 500A and 500B shown in Figure 13. Referring to Figure 14, each edge trigger circuit 560 of the drive control circuits 500A and 500B differs from the edge trigger circuit 160 in Figure 1 in that it is configured to communicate an asynchronous signal 461 with the edge trigger circuit 560 of the other drive control circuit.

[0116] For example, the edge detection pulses representing rising and falling edges output from the edge trigger circuit 560 to the counter 150, or pulses for multiple clock cycles starting from the edge detection pulse, are used as the asynchronous signal 461. As explained with reference to Figure 1, when the edge trigger circuit 560 is configured using a D-FF, the generation of edge detection pulses can be suppressed while receiving the asynchronous signal 461 from the edge trigger circuit 560 of the drive control circuit 500 by inputting an inverted signal of the asynchronous signal 461 to the enable terminal of the D-FF. In other words, the asynchronous signal 461 is a suppression signal that suppresses the generation of edge detection pulses.

[0117] Other aspects of Figure 14 are the same as those in Figure 1, so the same or corresponding parts are denoted by the same reference numerals and the explanation is not repeated. Furthermore, as explained with reference to Figure 12, a common program memory may be provided in each of the drive control circuits 500A and 500B, with program memories 130 and 131 being shared.

[0118] As described above, Embodiment 2 describes the case in which the drive control circuit of Embodiment 1 is applied to a half-bridge. With the configuration described above, it is possible to provide drive control circuits 500A and 500B that can suppress surges and switching losses while preventing the occurrence of arm short circuits.

[0119] Embodiment 3. Embodiment 3 describes a modified version of the current estimation circuit 191 shown in Figure 1. The modified current estimation circuit 691 estimates the collector current ICE by detecting the sense current output from the sense electrode S of the power semiconductor element 50. Here, the sense electrode S is a part of the main electrode (emitter) E on the low-potential side of the power semiconductor element 50 that has been isolated. This makes it possible to detect a sense current in which the collector current ICE is reduced according to the ratio of the area of ​​the sense electrode S to the area of ​​the emitter E. A detailed explanation follows with reference to the drawings.

[0120] Figure 15 is a block diagram showing the configuration of the drive control circuit 600 according to Embodiment 3. In the drive control circuit 600 of Figure 15, the configuration of the current estimation circuit 691 differs from the configuration of the current estimation circuit 191 of the drive control circuit 100 in Figure 1.

[0121] The current estimation circuit 691 detects the sense current flowing out from the sense electrode S of the power semiconductor element 50 and stores the detected sense current value in register (CUR) 146 of the register file 140. The controller 101 can estimate the collector current ICE based on the detected sense current value.

[0122] More specifically, the current estimation circuit 691 converts the sense current into a voltage and then performs an analog-to-digital (AD) conversion on the converted voltage. As shown in Figure 15, the current estimation circuit 691 includes an operational amplifier 692 and a resistor 693 that constitute a current-to-voltage conversion circuit, and an analog-to-digital converter (ADC) 694. The non-inverting input terminal of the operational amplifier 692 is connected to ground 52, and the resistor 693 is connected between the inverting input terminal and the output terminal of the operational amplifier 692. The sense current is input to the inverting input terminal of the operational amplifier 692, and the output voltage of the operational amplifier 692 is AD converted by the ADC 694. If the resistance value of resistor 693 is R, then the output voltage of the operational amplifier 692 is equal to R times the sense current.

[0123] According to the configuration of the drive control circuit 600 described above, the potential of the sense electrode S is close to the ground potential, so the linearity of the current-voltage conversion realized by the operational amplifier 692 and the resistor 693 is high. As a result, the detection accuracy of the collector current ICE can be improved, and more accurate control of the power semiconductor element 50 can be achieved than in the case of the drive control circuit 100 of Embodiment 1.

[0124] Furthermore, if the current flowing through the power semiconductor element 50 is around several tens of amperes, a current sense IC may be placed directly between the emitter electrode and ground 52 without using a power semiconductor element with a sense electrode. In this case, the collector current ICE value detected by the current sense IC is stored in register (CUR) 146 of register file 140.

[0125] Other aspects of Figure 15 are the same as those in Figure 1, so the same or corresponding parts are denoted by the same reference numerals and their descriptions are not repeated. Furthermore, as explained with reference to Figure 12, the drive control circuit 600 may be provided with a program memory that combines the program memories 130 and 131.

[0126] Embodiment 4. Embodiment 4 describes a modified example in which a drive control circuit 700A used during turn-on and a drive control circuit 700B used during turn-off are separately provided as circuits for driving and controlling the power semiconductor element 50.

[0127] Figure 16 shows the configurations of drive control circuits 700A and 700B according to Embodiment 4. Referring to Figure 16, each of the drive control circuits 700A and 700B has a configuration similar to the drive control circuit 100 shown in Figure 1, but differs from the drive control circuit 100 in the following respects.

[0128] Specifically, the controller 701A of the turn-on drive control circuit 700A includes a program memory 130 for turn-on, but does not include a program memory 131 for turn-off. Furthermore, the variable gate driver 770A of the turn-on drive control circuit 700A has the function of supplying current from the power node 57 to the control electrode G of the power semiconductor element 50, but does not have the function of withdrawing current from the control electrode G.

[0129] More specifically, the variable gate driver 770A for turn-on includes a level shifter 771A and buffer PMOS transistors 180A, 181A, and 182A. The PMOS transistors 180A, 181A, and 182A are connected in parallel to each other between the power supply node 57 and the control electrode G of the power semiconductor element 50. The level shifter 171 outputs gate voltages to drive the MOS transistors 180A, 181A, and 182A based on a digital signal received from the output port register (PORTOUT) 144. To differentiate the drive current amounts of the PMOS transistors 180A, 181A, and 182A, the gate width of PMOS transistor 181A is, for example, twice the gate width of PMOS transistor 180A. Also, the gate width of PMOS transistor 182A is, for example, four times the gate width of PMOS transistor 180A. By increasing the number of buffer PMOS transistors, the drive current amount can be controlled more precisely.

[0130] On the other hand, the controller 701B of the turn-off drive control circuit 700B includes a program memory 131 for turn-off, but does not include a program memory 130 for turn-on. Furthermore, the variable gate driver 770B of the turn-off drive control circuit 700B has the function of drawing current from the control electrode G to ground 52, but does not have the function of supplying current to the control electrode G of the power semiconductor element 50.

[0131] More specifically, the variable gate driver 770B for turn-off includes a level shifter 771B and buffer NMOS transistors 180B, 181B, and 182B. The NMOS transistors 180B, 181B, and 182B are connected in parallel to each other between the control electrode G of the power semiconductor element 50 and ground 52. The level shifter 171 outputs gate voltages to drive the MOS transistors 180B, 181B, and 182B based on a digital signal received from the output port register (PORTOUT) 144. To differentiate the drive current amounts of the NMOS transistors 180B, 181B, and 182B, the gate width of NMOS transistor 181B is, for example, twice the gate width of NMOS transistor 180B. Also, the gate width of NMOS transistor 182B is, for example, four times the gate width of NMOS transistor 180B. By increasing the number of buffer NMOS transistors, the drive current amount can be controlled more precisely.

[0132] The gate signal GSA supplied to the controller 701A of the turn-on drive control circuit 700A and the gate signal GSB supplied to the controller 701B of the turn-off drive control circuit 700B may be a common gate signal GS. In this case, for example, the edge trigger circuit 160 of controller 701A detects the rising edge of the common gate signal GS, and the edge trigger circuit 160 (not shown) of controller 701B detects the falling edge of the common gate signal GS. Alternatively, different gate signals GSA and GSB may be supplied to controllers 701A and 701B, respectively.

[0133] The other configurations of the drive control circuits 700A and 700B in Figure 16 are the same as those of the drive control circuit 100 in Figure 1, so the same or corresponding parts are denoted by the same reference numerals and the description will not be repeated. Even with the above configurations of the drive control circuits 700A and 700B, switching losses and surge generation during turn-on and turn-off can be suppressed, as in the case of Embodiment 1. The current estimation circuit 691 with the configuration described in Figure 15 of Embodiment 3 can be combined with this embodiment.

[0134] Embodiment 5. Embodiment 5 describes a case where the voltage (collector voltage) of the main electrode C on the high-potential side of the power semiconductor element 50 is monitored for more precise control.

[0135] Figure 17 is a block diagram showing the configuration of the drive control circuit 800 according to Embodiment 5. The drive control circuit 800 shown in Figure 17 differs from the drive control circuit 100 shown in Figure 1 in that it further includes a collector voltage detection circuit 892 for detecting the collector voltage. Furthermore, the register file 840 provided in the controller 801 of the drive control circuit 800 in Figure 17 differs from the register file 140 provided in the controller 101 of the drive control circuit 100 in Figure 1 in that it further includes a register (VCE) 847 (also referred to as the second register) for storing the value of the collector voltage detected by the collector voltage detection circuit 892.

[0136] More specifically, the collector voltage detection circuit 892 includes resistors 893 and 894 as a voltage divider circuit for dividing the collector voltage, and an analog-to-digital converter (ADC) 895. Resistors 893 and 894 are connected in series between the collector C of the power semiconductor element 50 and ground 52. The ADC 895 performs A / D conversion on the voltages (divided voltages) at the connection nodes of resistors 893 and 894. The digital values ​​of the divided voltages obtained by A / D conversion are stored in register (VCE) 847.

[0137] Other aspects of Figure 17 are the same as those of the drive control circuit 100 in Figure 1, so the same or corresponding parts are denoted by the same reference numerals and the description will not be repeated. Note that the collector voltage detection circuit 892 and the register (VCE) 847 described in Embodiment 5 can be combined with any of Embodiments 1 to 4.

[0138] According to the drive control circuit 800 of the above embodiment, the controller 801 can control the power semiconductor element 50 based on the detected collector voltage of the power semiconductor element 50. Therefore, according to the drive control circuit 800 of Embodiment 5, more precise control of the power semiconductor element 50 becomes possible.

[0139] The embodiments disclosed herein should be considered in all respects to be illustrative and not restrictive. The scope of this application is indicated by the claims and not by the foregoing description, and all modifications within the meaning and scope equivalent to the claims are intended to be included. [Explanation of Symbols]

[0140] 50 Power semiconductor elements, 51 Freewheeling diodes, 52 Ground, 53 Diodes, 56 Power supplies, 57 Power supply nodes, 100, 300, 500, 600, 700, 800 Drive control circuits, 101, 701, 801 Controllers, 120 Instruction decoders, 130, 131, 330 Program memory, 140, 840 Register files, 142, 143 General-purpose registers, 144 Output port registers, 150 Counters, 160, 560 Edge trigger circuits, 170, 770 Variable gate drivers, 171, 771 Level shifters, 180, 181, 182 Buffers, 180A, 181A, 182A PMOS transistors, 180B, 181B, 182B NMOS transistors, 190 Miller period determination circuits, 191, 691 Current estimation circuits, 210 Differential circuits, 211, 221 Capacitors, 212, 222, 693, 893, 894 Resistors, 220 Integrating circuits, 223 Input nodes, 224 Output nodes, 230, 231 Comparators, 240 Edge detection circuits, 250, 251 Threshold voltage generation circuits, 400 Half-bridges, 461 Asynchronous signals, 692 Op-amps, 694, 895 ADCs, 892 Collector voltage detection circuits, C Collector (main electrode), E Emitter (main electrode), G Gate (control electrode), GS, GSA, GSB Gate signals, IC, ICE Collector current, S Sense electrode, VC, VCE Collector voltage, VGE Gate voltage, Vng, Vps Threshold voltage.

Claims

1. A drive control circuit for driving and controlling power semiconductor elements, A Miller period determination circuit that determines whether or not it is a Miller period based on the detected voltage of the control electrode of the power semiconductor element and stores the determination result in a flag register, A variable gate driver that applies a voltage to the control electrode of the power semiconductor element with a current driving force corresponding to the current command value stored in the output port register, The system includes a controller that sequentially executes a plurality of instructions stored in at least one program memory in response to a gate signal supplied from an external source to turn on and turn off the power semiconductor element, A drive control circuit, wherein the plurality of instructions include a conditional instruction that changes the current command value to be stored in the output port register according to the determination result of whether or not it is a mirror period stored in the flag register.

2. The aforementioned multiple instructions A plurality of first instructions are executed when the power semiconductor element is turned on, This includes a plurality of second instructions that are executed when the power semiconductor element is turned off, The plurality of first instructions include instructions to be executed before the start of the mirror period, instructions to be executed during the mirror period, and instructions to be executed after the end of the mirror period, based on the determination result stored in the flag register. The drive control circuit according to claim 1, wherein the plurality of second instructions include an instruction to be executed before the start of the mirror period, an instruction to be executed during the mirror period, and an instruction to be executed after the end of the mirror period, based on the determination result stored in the flag register.

3. The aforementioned at least one program memory is A first program memory that stores the plurality of first instructions, The drive control circuit according to claim 2, further comprising a second program memory for storing the plurality of second instructions.

4. The aforementioned at least one program memory is a single program memory, The drive control circuit according to claim 2, wherein the plurality of first instructions and the plurality of second instructions are stored at different addresses in the single program memory.

5. The drive control circuit further includes a current estimation circuit that estimates the main current flowing between the main electrodes of the power semiconductor element and stores the estimated value of the main current in a first register. The drive control circuit according to any one of claims 1 to 4, wherein the plurality of instructions stored in at least one program memory includes an instruction to calculate the current command value using the value of the main current stored in the first register, and an instruction to store the calculation result of the current command value in the output port register.

6. The drive control circuit according to claim 5, wherein the current estimation circuit estimates the value of the main current based on the voltage of the control electrode during the Miller period.

7. The power semiconductor element has a sense electrode for conducting a portion of the main current, The current estimation circuit is, A current-voltage conversion circuit that converts the current flowing through the sense electrode into a voltage, The drive control circuit according to claim 5, further comprising an analog-to-digital converter that converts the voltage converted by the current-to-voltage conversion circuit into a digital value.

8. The aforementioned variable gate driver is Between the power supply node of the drive control circuit and the control electrode of the power semiconductor element, a plurality of PMOS (P-channel Metal Oxide Semiconductor) transistors are connected in parallel to each other, The drive control circuit includes a plurality of NMOS (N-channel Metal Oxide Semiconductor) transistors connected in parallel to each other between the ground of the drive control circuit and the control electrode of the power semiconductor element, The current driving forces of each of the aforementioned PMOS transistors are different from one another. The drive control circuit according to any one of claims 1 to 7, wherein the current driving force of each of the plurality of NMOS transistors is different from that of the others.

9. The drive control circuit further includes a voltage detection circuit that detects the voltage between the main electrodes of the power semiconductor element between the main electrode on the high-potential side and the main electrode on the low-potential side, and stores the detected voltage value between the main electrodes in a second register. The drive control circuit according to any one of claims 1 to 8, wherein the plurality of instructions stored in at least one program memory include an instruction to calculate the current command value using the voltage value between the main electrodes stored in the second register, and an instruction to store the calculation result of the current command value in the output port register.

10. The voltage detection circuit is A voltage divider circuit generates divided voltages by dividing the voltage between the main electrodes, The drive control circuit according to claim 9, further comprising an analog-to-digital conversion circuit that converts the voltage divider into a digital value.

11. The aforementioned controller, An edge trigger circuit that generates a trigger pulse by detecting the rising edge and falling edge of the gate signal, A counter that starts reading the plurality of instructions from the at least one program memory in response to the trigger pulse, The drive control circuit according to any one of claims 1 to 10, wherein the edge trigger circuit does not generate the trigger pulse when it receives an external suppression signal that suppresses the generation of the trigger pulse.

12. A first power semiconductor element and a second power semiconductor element that are connected in series to each other to form a half-bridge, A first drive control circuit that drives and controls the first power semiconductor element, having the same configuration as the drive control circuit described in claim 11 except for the configuration of the edge trigger circuit, A second drive control circuit has the same configuration as the drive control circuit described in claim 11, except for the configuration of the edge trigger circuit, and drives and controls the second power semiconductor element, The edge trigger circuit of the first drive control circuit generates a first suppression signal as the suppression signal and transmits it to the edge trigger circuit of the second drive control circuit. The edge trigger circuit of the second drive control circuit generates a second suppression signal as the suppression signal and transmits it to the edge trigger circuit of the first drive control circuit. The edge trigger circuit of the first drive control circuit does not generate the trigger pulse when it receives the second suppression signal from the edge trigger circuit of the second drive control circuit. The edge trigger circuit of the second drive control circuit is a power circuit that does not generate the trigger pulse when it receives the first suppression signal from the edge trigger circuit of the first drive control circuit.

Images