Memory system

Abstract

To provide a memory system configured to enhance error correction capability for data.SOLUTION: A memory system includes: a semiconductor memory device 30 including a plurality of memory cells (cell unit CU) each configured to store data in a non-volatile manner according to a threshold voltage thereof and connected to a word line; and a controller 10 configured to perform an error correction based on hard bit data and soft bit data read from the plurality of memory cells, generate a first table (DLE1 table) based on corrected data, acquire a voltage difference between a first voltage (HB read voltage) and a second voltage (Vtr), the first voltage being a voltage applied to the word line when the corrected data is read, and correct the first table based on the voltage difference.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] Embodiments of the present invention relate to a memory system.

Background Art

[0002] A memory system including a semiconductor memory device and a memory controller that controls the semiconductor memory device is known. As an error correction method when reading data from a semiconductor memory device, soft decision decoding is known.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

Problems to be Solved by the Invention

[0004] One embodiment provides a memory system capable of improving the error correction ability of data.

Means for Solving the Problems

[0005] A memory system according to an embodiment includes a semiconductor memory device including a plurality of memory cells connected to a word line, each of which is configured to store data non-volatilely according to a threshold voltage, and It comprises a controller electrically connected to a semiconductor memory device. The controller is performs error correction based on hard bit data and soft bit data obtained from the plurality of memory cells, and generates a first table based on the data corrected by the error correction It is configured to do so. When the corrected data is acquired, a second voltage is applied to the word line The first voltage is applied Furthermore, the controller ensures that the number of error bits in the data obtained from multiple memory cells when the first voltage is applied to the word line is less than the number of error bits in the data obtained from multiple memory cells when the first voltage is applied to the word line. second voltage The first voltage and the second voltage are calculated andIt is configured to acquire the voltage difference and correct the first table based on the voltage difference. ru . The first table shows the relationship between the voltage range to which the threshold voltage of each of the multiple memory cells belongs and the likelihood of the data stored in each of the multiple memory cells. [Brief explanation of the drawing]

[0006] [Figure 1] Figure 1 is a block diagram showing an example of an information processing system including a memory system according to the first embodiment. [Figure 2] Figure 2 is a block diagram showing an example of the configuration of an ECC (Error Checking and Correcting) circuit in a memory controller included in the memory system according to the first embodiment. [Figure 3] Figure 3 is a block diagram showing an example of the configuration of a semiconductor memory device included in the memory system according to the first embodiment. [Figure 4] Figure 4 is a circuit diagram of a memory cell array in a semiconductor memory device included in the memory system according to the first embodiment. [Figure 5] Figure 5 shows an example of the relationship between the threshold voltage distribution of a memory cell transistor included in the memory system according to the first embodiment and the data stored by the memory cell transistor. [Figure 6] Figure 6 shows an example of the relationship between the threshold voltage distribution of a memory cell transistor included in the memory system according to the first embodiment, the voltage for data reading, and the read data. [Figure 7] Figure 7 is a diagram illustrating the process related to soft decision decoding according to the first embodiment. [Figure 8] Figure 8 is a conceptual diagram of the log-likelihood ratio (LLR) table according to the first embodiment. [Figure 9] Figure 9 is a table showing an example of a channel matrix according to the first embodiment. [Figure 10] Figure 10 is a diagram illustrating the shift value generation process according to the first embodiment. [Figure 10-2]FIG. 10-2 is a diagram for explaining the relationship between the threshold voltage distribution of memory cell transistors included in the memory system according to the first embodiment and the channel matrix according to the first embodiment. [Figure 10-3] FIG. 10-3 is a diagram for explaining the relationship between the threshold voltage distribution of memory cell transistors included in the memory system according to the first embodiment and the channel matrix according to the first embodiment. [Figure 10-4] FIG. 10-4 is a diagram for explaining the relationship between the threshold voltage distribution of memory cell transistors included in the memory system according to the first embodiment and the channel matrix according to the first embodiment. [Figure 10-5] FIG. 10-5 is a diagram for explaining the relationship between the threshold voltage distribution of memory cell transistors included in the memory system according to the first embodiment and the channel matrix according to the first embodiment. [Figure 11] FIG. 11 is a diagram for explaining a first example of the correction process of the DLE1 (Dynamic LLR Estimation 1) table according to the first embodiment. [Figure 11-2] FIG. 11-2 is a diagram for explaining a second example of the correction process of the DLE1 table according to the first embodiment. [Figure 11-3] FIG. 11-3 is a diagram for explaining a third example of the correction process of the DLE1 table according to the first embodiment. [Figure 12] FIG. 12 is a flowchart showing a read operation by a memory controller included in the memory system according to the first embodiment. [Figure 13] [[ID=二十四]]FIG. 13 is a diagram for explaining the effect of the memory system according to the first embodiment. [Figure 13-2] FIG. 13-2 is a diagram for explaining the effect of the memory system according to the first embodiment. [Figure 14] FIG. 14 is a block diagram showing an example of an information processing system including the memory system according to the second embodiment. [Figure 15] FIG. 15 is a block diagram showing an example of the configuration of an ECC circuit in a memory controller included in the memory system according to the second embodiment. [Figure 16] FIG. 16 is a diagram for explaining a process related to soft decision decoding according to the second embodiment. [Figure 17] FIG. 17 is a diagram for explaining the first correction process and the second correction process of the DLE1 table according to the second embodiment. [Figure 18] FIG. 18 is a flowchart showing a read operation by a memory controller included in a memory system according to the second embodiment. [Figure 19] FIG. 19 is a flowchart showing a read operation by a memory controller included in a memory system according to the second embodiment. [Figure 20] FIG. 20 is a conceptual diagram of an LLR pattern table according to the third embodiment. [Figure 21] FIG. 21 is a diagram for explaining a correction process of the DLE1 table according to the third embodiment. [Figure 22] FIG. 22 is a diagram for explaining a correction process of the DLE1 table according to the fourth embodiment. [Figure 23] FIG. 23 is a flowchart showing a read operation of a memory controller included in a memory system according to the fifth embodiment. [Figure 24] FIG. 24 is a diagram for explaining the symmetry of LLR in the DLE1 table according to the fifth embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. In this description, throughout all the drawings, common reference numerals are assigned to common parts.

[0008] Each functional block may not be distinguished as in the following examples. For example, some functions may be executed by a functional block different from the exemplified functional block. Further, the exemplified functional block may be further divided into finer functional sub-blocks. The embodiments are not limited by which functional block realizes the function.

[0009] Furthermore, each functional block can be implemented as hardware, computer software, or a combination of both.

[0010] [1] First Embodiment A memory system according to the first embodiment will be described below. In the following description, a memory system including NAND flash memory as a semiconductor memory device will be used as an example.

[0011] [1-1] Composition [1-1-1] Memory System Configuration The configuration of the memory system according to this embodiment will be explained with reference to Figure 1. Figure 1 is a block diagram showing an example of an information processing system including the memory system according to this embodiment.

[0012] The information processing system includes a memory system 1 and a host device 2.

[0013] Memory system 1 may be, for example, an SSD (solid state drive), a UFS (Universal Flash Storage) device, a USB (Universal Serial Bus) memory, an MMC (Multi-Media Card), or an SD card. TM It is a card. Memory system 1 is connectable to host device 2. Memory system 1 performs processing based on request signals or spontaneous processing requests received from host device 2.

[0014] Host device 2 is, for example, a personal computer, a server system, a mobile device, an in-vehicle device, or a digital camera.

[0015] Next, we will describe the internal configuration of memory system 1.

[0016] The memory system 1 includes a memory controller 10 and a semiconductor memory device 30. The semiconductor memory device 30 is a non-volatile memory, such as a NAND flash memory. Hereinafter, the semiconductor memory device 30 will be referred to as a NAND flash memory 30.

[0017] The memory controller 10 is, for example, a System On a Chip (SoC). The memory controller 10 is connected to the host device 2 via a host bus. The memory controller 10 receives request signals from the host device 2 via the host bus. The type of host bus depends on the application applied to the memory system 1. If the memory system 1 is an SSD, the host bus could be, for example, SAS (Serial Attached SCSI), SATA (Serial ATA), or PCIe. TM The Peripheral Component Interconnect Express (CPC) interface is used. If memory system 1 is a UFS device, the M-PHY interface is used as the host bus. If memory system 1 is a USB memory device, the USB interface is used as the host bus. If memory system 1 is an MMC, the eMMC (Embedded Multi Media Card) interface is used as the host bus. TM If it is a card, the host bus is SD TM A standard interface is used.

[0018] The memory controller 10 controls the NAND flash memory 30 via the NAND bus based on a request signal received from the host device 2 or a spontaneous processing request. The NAND bus transmits and receives signals according to the NAND interface.

[0019] The NAND flash memory 30 includes multiple memory cell transistors. Each of the multiple memory cell transistors stores data nonvolatilously according to a threshold voltage. The NAND flash memory 30 stores the data received from the memory controller 10 nonvolatilously in the multiple memory cell transistors. The NAND flash memory 30 outputs the data read from the multiple memory cell transistors to the memory controller 10.

[0020] Next, we will describe the internal configuration of the memory controller 10.

[0021] The memory controller 10 includes a host interface (I / F) circuit 11, a processor (CPU: Central Processing Unit) 12, a buffer memory 13, an ECC (Error Checking and Correcting) circuit 14, a ROM (Read-only memory) 15, a RAM (Random Access Memory) 16, a read information generation circuit 17, and a NAND interface (I / F) circuit 18.

[0022] The host interface circuit 11 is responsible for communication between the memory controller 10 and the host device 2. The host interface circuit 11 is connected to the host device 2 via the host bus.

[0023] The processor 12 is the control circuit for the memory controller 10. The processor 12 controls the operation of the entire memory controller 10 by executing the program stored in the ROM 15. For example, when the processor 12 receives a write request from the host device 2, it controls the write operation based on that request. The same applies to read and erase operations.

[0024] The buffer memory 13 is, for example, SRAM (Static Random Access Memory). The buffer memory 13 temporarily stores data to be written and data to be read. The data to be written is the data to be written to the NAND flash memory 30. The data to be read is the data read from the NAND flash memory 30.

[0025] The ECC circuit 14 is a circuit that performs ECC processing. ECC processing includes data encoding and decoding. Encoding is the operation of generating error correction codes (hereinafter also referred to as "parity") based on data (user data) received from the host device 2 during a write operation. The error correction codes are added to the user data. Encoding is completed by adding the error correction codes to the user data. Hereinafter, in the ECC circuit 14, the set of data that is decoded all at once will be referred to as an "ECC frame". An ECC frame includes user data and error correction codes. Decoding is the operation of correcting errors in the user data based on the ECC frame received from the NAND flash memory 30 during a read operation. Error correction codes are used for error detection and correction.

[0026] Write and read operations are performed in page units, as described later. In this specification, written and read data having the data length of one page is also referred to as "page data." Page data may contain multiple ECC frames. The data length of the page data and the data length of the ECC frames may be the same.

[0027] In this embodiment, the read operation includes hard bit (HB) reads and soft bit (SB) reads.

[0028] HB read is a process that reads data using a single read voltage (hereinafter also referred to as "HB read voltage") corresponding to the boundary of the threshold voltage distribution of the memory cell transistor, and obtains a determination result that determines whether the data stored in the memory cell transistor is "0" or "1". The page data obtained by HB read is called "HB data". Each bit of the HB data is called a "hard bit".

[0029] SB read is a process that reads data using multiple voltages set relative to the HB read voltage (hereinafter also referred to as "SB read voltage"), and obtains the result of a logical operation performed on the multiple read data. SB read is performed when error correction by the hard-decision decoding circuit 20, described later, fails. The page data obtained by SB read is called "SB data". Each bit of the SB data is called a "soft bit".

[0030] ROM15 is, for example, an EEPROM. TM It is (Electrically Erasable Programmable Read-Only Memory). ROM15 stores programs such as firmware.

[0031] RAM16 is, for example, SRAM. RAM16 is used as a work area for processor 12. RAM16 stores firmware for managing NAND flash memory 30 and various management information. RAM16 stores, for example, a log-likelihood ratio (LLR) table and a read voltage value Vst (hereinafter also simply referred to as "shifted value Vst") shifted from the default HB read voltage (initial value of HB read voltage). Hereinafter, the default HB read voltage will also be referred to as "default voltage Vdt".

[0032] The LLR table is a table that associates read data with LLR. LLR is information that expresses the probability of the data stored in the memory cell transistor being "0" and the probability of it being "1" in a logarithmic ratio. Details of the LLR table and shift value Vst will be described later. The LLR table is loaded from the NAND flash memory 30 to the RAM 16, for example, immediately after power-on. The shift value Vst is written to the RAM 16, for example, when the shift value Vst is generated. The initial value of the shift value Vst is equal to the default voltage Vdt.

[0033] The read information generation circuit 17 is a circuit that generates a DLE1 (Dynamic LLR Estimation 1) table and a shift value Vst as information regarding HB reads and SB reads. The DLE1 table is a table that shows the relationship between the voltage range of the threshold voltages of multiple memory cell transistors and LLR, and is generated based on data that has been successfully corrected by the soft-decision decoding circuit 21, which will be described later. Details of the processing of the read information generation circuit 17 and the DLE1 table will be described later.

[0034] The NAND interface circuit 18 manages communication between the memory controller 10 and the NAND flash memory 30. The NAND interface circuit 18 is connected to the NAND flash memory 30 via a NAND bus. For example, the NAND interface circuit 18 controls the transfer of data, commands, and addresses between the memory controller 10 and the NAND flash memory 30.

[0035] [1-1-2] Configuration of the ECC circuit The internal configuration of the ECC circuit 14 will be explained using Figure 2. Figure 2 is a block diagram showing an example of the configuration of the ECC circuit.

[0036] The ECC circuit 14 includes an encoding circuit 19, a hard-decision decoding circuit 20, a soft-decision decoding circuit 21, an LLR conversion circuit 22, and a channel matrix generation circuit 23.

[0037] The encoding circuit 19 is a circuit that performs encoding processing. The encoding circuit 19 generates parity. Parity includes, for example, hard-decision parity and soft-decision parity. Examples of hard-decision parity are BCH (Bose-Chaudhuri-Hocquenghem) codes and RS (Reed-Solomon) codes. An example of soft-decision parity is LDPC (Low-Density Parity-Check) codes. The encoding circuit 19 assigns parity to user data.

[0038] The hard-decision decoding circuit 20 is a circuit that performs hard-decision decoding. The hard-decision decoding circuit 20 performs error correction using hard-decision parity. Specifically, the hard-decision decoding circuit 20 detects errors in user data on an ECC frame basis using hard-decision parity for HB data. If an error is detected, the hard-decision decoding circuit 20 corrects the error in the user data. Hereinafter, the error correction by the hard-decision decoding circuit 20 will also be referred to as "HB correction".

[0039] The soft-decision decoding circuit 21 is a circuit that performs soft-decision decoding. The soft-decision decoding circuit 21 performs error correction using LLR and soft-decision parity. Specifically, the soft-decision decoding circuit 21 performs probability-based iterative calculations on HB data and SB data on an ECC frame basis using LLR and soft-decision parity. Based on the results of the iterative calculations, the soft-decision decoding circuit 21 corrects errors in the user data. Hereinafter, the error correction by the soft-decision decoding circuit 21 will also be referred to as "SB correction". LLR is obtained by the LLR conversion circuit 22.

[0040] The LLR conversion circuit 22 is a circuit that performs LLR conversion processing. The LLR conversion circuit 22 uses an LLR table to convert combinations of hard bits and soft bits into LLR on an ECC frame basis.

[0041] The channel matrix generation circuit 23 is a circuit that performs the channel matrix generation process. The channel matrix generation circuit 23 generates a channel matrix on an ECC frame basis using the combination of hard bits and soft bits and the data that has been successfully corrected by the soft-decision decoding circuit 21. Hereafter, the data that has been successfully corrected by the soft-decision decoding circuit 21 will also be referred to as "corrected data". The channel matrix is ​​the count of the number of data "0"s and data "1"s in the corrected data for each combination of hard bits and soft bits. Details of the channel matrix will be described later.

[0042] The soft-decision decoding circuit 21 includes a memory 24. The memory 24 is, for example, SRAM. The memory 24 stores HB data and SB data acquired from the buffer memory 13, LLR obtained by the conversion in the LLR conversion circuit 22, data corrected by the soft-decision decoding circuit 21, and the DLE1 table generated by the read information generation circuit 17, etc.

[0043] Details of the ECC circuit 14's processing will be described later.

[0044] [1-1-3] Configuration of NAND flash memory The configuration of the NAND flash memory 30 will be explained using Figure 3. Figure 3 is a block diagram showing an example of the configuration of the NAND flash memory 30. The NAND flash memory 30 includes a memory cell array 31, an input / output circuit 32, a logic control circuit 33, a ready / busy control circuit 34, a register 35, a sequencer 36, a driver module 37, a raw decoder module 38, and a sense amplifier module 39.

[0045] The memory cell array 31 includes multiple blocks BLK0 to BLKn (where n is an integer greater than or equal to 1). A block BLK is, for example, a collection of multiple memory cell transistors whose data is erased collectively. For example, a block BLK is used as a unit of data erasure operation. A block BLK includes multiple word lines. Memory cell transistors are capable of storing data non-volatilely. The memory cell array 31 is provided with multiple bit lines and multiple word lines. Each memory cell transistor is associated with, for example, one bit line and one word line. Details of the memory cell array 31 will be described later.

[0046] The input / output circuit 32 transmits and receives input / output signals DQ (for example, 8-bit signals DQ0 to DQ7), as well as data strobe signals DQS and DQSn (inverted signals of signal DQS) to and from the memory controller 10. Signal DQ is the actual data transmitted and received between the NAND flash memory 30 and the memory controller 10. Signal DQ is, for example, a command CMD, an address ADD, status information STS, and data DAT. Signals DQS and DQSn are signals for controlling the timing of the transmission and reception of signal DQ. For example, when writing data, signals DQS and DQSn are transmitted from the memory controller 10 to the NAND flash memory 30 along with signal DQ containing the data to be written. The NAND flash memory 30 receives signal DQ containing the data to be written in synchronization with signals DQS and DQSn. When reading data, signals DQS and DQSn are transmitted from the NAND flash memory 30 to the memory controller 10 along with signal DQ containing the data to be read. The memory controller 10 receives signal DQ, which contains read data, in synchronization with signals DQS and DQSn. The input / output circuit 32 may also receive signals DQS and DQSn from the memory controller 10 via the logic control circuit 33.

[0047] Furthermore, the input / output circuit 32 transmits the command CMD in signal DQ to the command register 35A. The input / output circuit 32 transmits the address ADD in signal DQ to the address register 35B. The input / output circuit 32 receives the status information STS from the status register 35C. The input / output circuit 32 transmits and receives the data DAT in signal DQ to and from the sense amplifier module 39.

[0048] The logic control circuit 33 receives the chip enable signal CEn, command latch enable signal CLE, address latch enable signal ALE, write enable signal WEn, and read enable signal REn from the memory controller 10. Signal CEn is a signal for enabling the NAND flash memory 30. Signal CLE is a signal indicating that the signal DQ received by the NAND flash memory 30 is the command CMD. Signal ALE is a signal indicating that the signal DQ received by the NAND flash memory 30 is the address ADD. Signal WEn is a signal that commands the NAND flash memory 30 to input signal DQ. Signal REn is a signal that commands the NAND flash memory 30 to output signal DQ. The NAND flash memory 30 generates signals DQS and DQSn based on signal REn. The NAND flash memory 30 outputs signal DQ to the memory controller 10 based on the generated signals DQS and DQSn. The logic control circuit 33 controls the input / output circuit 32 and the sequencer 36 based on the received signal.

[0049] The ready / busy control circuit 34 transmits a ready / busy signal RBn to the memory controller 10 based on the operating status of the sequencer 36. Signal RBn indicates whether the NAND flash memory 30 is in a ready state or a busy state. For example, signal RBn is set to a "Low" level when the NAND flash memory 30 is in a busy state. The ready state is when the NAND flash memory 30 is able to accept commands from the memory controller 10. The busy state is when the NAND flash memory 30 is unable to accept commands from the memory controller 10.

[0050] Register 35 includes the command register 35A, the address register 35B, and the status register 35C.

[0051] Command register 35A stores command CMDs. Command CMDs include, for example, instructions that cause the sequencer 36 to perform read, write, and erase operations.

[0052] Address register 35B stores address ADD. Address ADD includes, for example, the block address BAd, the page address PAAd, and the column address CAD. The block address BAd, page address PAAd, and column address CAD are used, for example, for selecting the block BLK, word line, and bit line, respectively.

[0053] The status register 35C temporarily stores status information STS, for example, during read, write, and erase operations. The status information STS is used to notify the memory controller 10 whether the operation was completed successfully or not.

[0054] The sequencer 36 controls the operation of the entire NAND flash memory 30. For example, the sequencer 36 controls the ready / busy control circuit 34, the driver module 37, the raw decoder module 38, and the sense amplifier module 39 based on the command CMD stored in the command register 35A. For example, the sequencer 36 performs read, write, and erase operations.

[0055] The driver module 37 generates the voltages used in read, write, and erase operations. Based on the page address PAd stored in the address register 35B, the driver module 37 applies the generated voltage to the signal line corresponding to the selected word line.

[0056] The row decoder module 38 selects one block BLK in the memory cell array 31 based on the block address BAd stored in the address register 35B. The row decoder module 38 transfers the voltage applied to the signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0057] During a write operation, the sense amplifier module 39 applies a voltage to the bit line based on the write data DAT received from the input / output circuit 32. During a read operation, the sense amplifier module 39 determines the data stored in the memory cell transistor based on the voltage of the bit line. The sense amplifier module 39 then transfers the determination result to the input / output circuit 32 as read data DAT.

[0058] [1-1-4] Circuit configuration of memory cell array The circuit configuration of the memory cell array 31 will be explained using Figure 4. Figure 4 is a circuit diagram of the memory cell array 31. Figure 4 shows the circuit configuration of one of the multiple block blocks included in the memory cell array 31 as an example of the circuit configuration of the memory cell array 31. The other block blocks have the same configuration as shown in Figure 4.

[0059] Block BLK includes, for example, four string units SU0 to SU3. Each string unit SU is a set of multiple NAND strings NS that are selected collectively, for example, in a write or read operation. Each string unit SU includes multiple NAND strings NS associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). A NAND string NS is a set of multiple memory cell transistors connected in series. Each NAND string NS includes, for example, memory cell transistors MC0 to MC7, as well as selection transistors ST1 and ST2. The memory cell transistors MC store data non-volatilely. The memory cell transistors MC include a control gate and a charge storage layer. The selection transistors ST1 and ST2 are switching elements. Each of the selection transistors ST1 and ST2 is used to select the string unit SU during various operations.

[0060] In each NAND string NS, memory cell transistors MC0 to MC7 are connected in series. The drain of selection transistor ST1 is connected to the associated bit line BL. The source of selection transistor ST1 is connected to one end of the series-connected memory cell transistors MC0 to MC7. The drain of selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MC0 to MC7. The source of selection transistor ST2 is connected to the source line SL.

[0061] Within the same block BLK, the control gates of memory cell transistors MC0 to MC7 are commonly connected to word lines WL0 to WL7, respectively. The gates of each selection transistor ST1 within string units SU0 to SU3 are commonly connected to selection gate lines SGD0 to SGD3, respectively. The gate of selection transistor ST2 included in the same block BLK is commonly connected to selection gate line SGS.

[0062] In the circuit configuration of the memory cell array 31 described above, the bit line BL is shared, for example, by NAND strings NS to which the same column address CAd is assigned in each string unit SU. The source line SL is shared, for example, between multiple blocks BLK.

[0063] A collection of multiple memory cell transistors MC connected to a common word line WL within a single string unit SU is called, for example, a cell unit CU. A cell unit CU is also called a page. The data stored in a cell unit CU, which contains multiple memory cell transistors MC, each storing 1 bit of data according to a threshold voltage, corresponds to one page of data. A cell unit CU can store two or more pages of data, depending on the number of bits of data stored in the memory cell transistors MC.

[0064] Note that the circuit configuration of the memory cell array 31 is not limited to the configuration described above. For example, the number of string units SU included in each block BLK, and the number of memory cell transistors MC and selection transistors ST1 and ST2 included in each NAND string NS, can be any number. Hereafter, the memory cell transistor MC will also be referred to as memory cell MC.

[0065] [1-1-5] Threshold voltage distribution of memory cells The possible threshold voltage distribution of a memory cell MC will be explained using Figure 5. Figure 5 shows an example of the relationship between the threshold voltage distribution of a memory cell MC and the data stored in the memory cell MC. The horizontal axis of Figure 5 represents the threshold voltage of the memory cell MC. The vertical axis of Figure 5 represents the number of memory cell MCs.

[0066] Each memory cell (MC) can store, for example, 1 bit of data based on its threshold voltage. In this case, the threshold voltage of the memory cell MC can take a value that falls within one of two threshold voltage distributions. Each threshold voltage distribution is assigned, in descending order of threshold voltage, for example, data "1" and data "0". Data "1" corresponds to the threshold voltage when charge has been removed from the charge storage layer of the memory cell MC. The threshold voltage distribution of multiple memory cell MCs corresponding to data "1" is denoted as the "Er" state. The threshold voltage of the memory cell MC corresponding to the "Er" state is either a positive or negative value. Data "0" corresponds to the threshold voltage when charge has been stored in the charge storage layer of the memory cell MC. The threshold voltage distribution of multiple memory cell MCs corresponding to data "0" is denoted as the "A" state. The threshold voltage of the memory cell MC corresponding to the "A" state is higher than that of the "Er" state. The read voltage used to determine whether the threshold voltage of the memory cell MC is in the "A" state is denoted as voltage AR(0). For example, the threshold voltage of a memory cell MC in the "Er" state is less than voltage AR(0). For example, the threshold voltage of a memory cell MC in state "A" is greater than or equal to voltage AR(0).

[0067] For example, the sequencer 36 performs an HB read with voltage AR(0) as the HB read voltage. As shown in Figure 5, if the threshold voltage distribution of the “Er” state and the threshold voltage distribution of the “A” state do not overlap, the memory controller 10 can determine that the threshold voltage of a certain memory cell MC belongs to the same threshold voltage distribution as the threshold voltage distribution at the time of writing, and thus succeeds in hard determination decoding.

[0068] However, as shown in Figure 6, due to various influences on the memory cell MC, the threshold voltage distribution of the "Er" state and the threshold voltage distribution of the "A" state may overlap. In this case, even if the sequencer 36 performs an HB read with voltage AR(0) as the HB read voltage, if the threshold voltage of a certain memory cell MC belongs to the same threshold voltage distribution as the threshold voltage distribution at the time of writing, a bit (fail bit) that the memory controller 10 cannot determine will occur. If the number of fail bits exceeds the number that can be error corrected, the memory controller 10 fails to perform hard judgment decoding. If hard judgment decoding fails, an SB read is performed.

[0069] As shown in Figure 6, the sequencer 36 performs SB readings using multiple SB read voltages (here, voltages AR(-3), AR(-2), AR(-1), AR(+1), AR(+2), and AR(+3)). As shown in Figure 6, voltage dR represents the amount of voltage shift. Voltage AR(-1) is lower in voltage dR than voltage AR(0). Voltage AR(-2) is lower in voltage dR than voltage AR(-1). Voltage AR(-3) is lower in voltage dR than voltage AR(-2). Voltage AR(+1) is higher in voltage dR than voltage AR(0). Voltage AR(+2) is higher in voltage dR than voltage AR(+1). Voltage AR(+3) is higher in voltage dR than voltage AR(+2).

[0070] The initial values ​​of the HB read voltage and SB read voltage can be preset based on design and manufacturing conditions, etc. These initial values ​​are stored, for example, in the NAND flash memory 30. The initial values ​​of the HB read voltage and SB read voltage are loaded from the NAND flash memory 30 to the RAM 16, for example, immediately after power-on. Note that the number of SB read voltages is not limited to three each on the low-voltage and high-voltage sides of the HB read voltage.

[0071] In the example in Figure 6, the threshold voltages of the memory cell MC are classified into eight categories corresponding to the HB read voltage (AR(0)) and the six SB read voltages (AR(-3) to AR(-1), AR(+1) to AR(+3)). Specifically, the threshold voltage for category D1 is less than AR(-3). The threshold voltage for category D2 is greater than or equal to AR(-3) and less than AR(-2). The threshold voltage for category D3 is greater than or equal to AR(-2) and less than AR(-1). The threshold voltage for category D4 is greater than or equal to AR(-1) and less than AR(0). The threshold voltage for category D5 is greater than or equal to AR(0) and less than AR(+1). The threshold voltage for category D6 is greater than or equal to AR(+1) and less than AR(+2). The threshold voltage for category D7 is greater than or equal to AR(+2) and less than AR(+3). The threshold voltage for category D8 is AR(+3) or higher.

[0072] In Figure 6, "HB" represents the possible values ​​of the hard bit depending on the threshold voltage of the memory cell MC. The hard bit is obtained, for example, by determining the data read from the memory cell MC in an HB read using voltage AR(0). When the threshold voltage of the memory cell MC corresponds to categories D1 to D4, the hard bit value is "1". When the threshold voltage of the memory cell MC corresponds to categories D5 to D8, the hard bit value is "0".

[0073] In Figure 6, "SB1" represents the first soft bit. The first soft bit is obtained, for example, by an ENOR (negative exclusive OR) operation of multiple data read from the memory cell MC using voltages AR(-2) and AR(+2), respectively. When the threshold voltage of the memory cell MC corresponds to sections D1 to D2, the value of the first soft bit is "1". When the threshold voltage of the memory cell MC corresponds to sections D3 to D6, the value of the first soft bit is "0". When the threshold voltage of the memory cell MC corresponds to sections D7 to D8, the value of the first soft bit is "1".

[0074] In Figure 6, "SB2" represents the second soft bit. The second soft bit is obtained by an ENOR operation of multiple data read from the memory cell MC using voltages AR(-3), AR(-1), AR(+1), and AR(+3), respectively. When the threshold voltage of the memory cell MC corresponds to section D1, the value of the second soft bit is "1". When the threshold voltage of the memory cell MC corresponds to sections D2 to D3, the value of the second soft bit is "0". When the threshold voltage of the memory cell MC corresponds to sections D4 to D5, the value of the second soft bit is "1". When the threshold voltage of the memory cell MC corresponds to sections D6 to D7, the value of the second soft bit is "0". When the threshold voltage of the memory cell MC corresponds to section D8, the value of the second soft bit is "1".

[0075] The combinations of voltages used in the SB lead to obtain the first and second soft bits are not limited to the above combinations.

[0076] Each of the categories D1 to D8 includes one bit corresponding to the hard bit, one bit corresponding to the first soft bit, and one bit corresponding to the second soft bit. In the example in Figure 6, the indices corresponding to categories D1 to D8 are set to 0 to 7, respectively. Arranging the threshold voltages in the voltage ranges corresponding to each of the indices 0 to 7 in ascending order, we get index 0, index 1, index 2, index 3, index 4, index 5, index 6, and index 7.

[0077] [1-1-6] Processing related to soft-decision decoding The process related to soft-decision decoding will be explained using Figure 7. Figure 7 is a diagram illustrating the process related to soft-decision decoding.

[0078] [1-1-6-1] Processing of ECC circuits First, let's explain the processing of the ECC circuit 14.

[0079] Buffer memory 13 stores HB data, SB1 data, and SB2 data. SB1 data includes one page of first soft bits. SB2 data includes one page of second soft bits. RAM 16 stores multiple LLR tables (e.g., TBL1, TBL2, and TBL3). LLR tables TBL1, TBL2, and TBL3 are configured to account for fluctuations in the threshold voltage of the memory cell MC due to various influences. In LLR tables TBL1, TBL2, and TBL3, the LLR corresponding to the combination of hard bits, first soft bits, and second soft bits is different for each. The LLR conversion circuit 22 receives HB data, SB1 data, and SB2 data from buffer memory 13 in ECC frame units. The LLR conversion circuit 22 selects one of the multiple LLR tables stored in RAM 16. Using the selected LLR table, the LLR conversion circuit 22 converts the combination of hard bits, first soft bits, and second soft bits into LLR in ECC frame units. The LLR conversion circuit 22 transmits the LLR signal to the soft-decision decoding circuit 21.

[0080] The LLR table will be explained using Figure 8. Figure 8 is a conceptual diagram of the LLR table.

[0081] The LLR table stores LLR values ​​for each index representing a combination of hard bits, the first soft bit, and the second soft bit. Larger LLR values ​​(positive values) indicate a higher probability that the data stored in the memory cell MC is "0". Smaller LLR values ​​(negative values) indicate a higher probability that the bit is "1".

[0082] As mentioned above with reference to Figure 6, for example, when the threshold voltage of a certain memory cell MC corresponds to category D1, the values ​​of the hard bit, first soft bit, and second soft bit read from that memory cell MC are "1", "1", and "1", respectively. As mentioned above, the index of a memory cell MC with a threshold voltage corresponding to category D1 is 0, and the LLR value of this memory cell MC is -9. Also, when the threshold voltage of a certain memory cell MC corresponds to category D5, the values ​​of the hard bit, first soft bit, and second soft bit read from that memory cell MC are "0", "0", and "1", respectively. As mentioned above, the index of a memory cell MC with a threshold voltage corresponding to category D5 is 4, and the LLR value of this memory cell MC is +1. Note that the LLR values ​​in Figure 8 are just examples.

[0083] Return to Figure 7. The soft-decision decoding circuit 21 receives LLR from the LLR conversion circuit 22. The soft-decision decoding circuit 21 stores the LLR in memory 24. The soft-decision decoding circuit 21 receives HB data, SB1 data, and SB2 data from buffer memory 13 in ECC frame units. The soft-decision decoding circuit 21 stores the HB data, SB1 data, and SB2 data in memory 24. The soft-decision decoding circuit 21 performs error correction of user data using the LLR and the soft-decision parity in the HB data, SB1 data, and SB2 data. The soft-decision decoding circuit 21 stores the corrected data in memory 24. The soft-decision decoding circuit 21 transmits the corrected data to the channel matrix generation circuit 23.

[0084] The channel matrix generation circuit 23 receives HB data, SB1 data, and SB2 data from the buffer memory 13 in ECC frame units. The channel matrix generation circuit 23 receives the corrected data from the memory 24. The channel matrix generation circuit 23 obtains an index based on the HB data, SB1 data, and SB2 data. The channel matrix generation circuit 23 generates a channel matrix by counting the number of data "0"s and data "1"s DLECNT for each index in the corrected data. The channel matrix generation circuit 23 transmits the channel matrix to the read information generation circuit 17.

[0085] The channel matrix will be explained using Figure 9. Figure 9 is a table showing an example of a channel matrix.

[0086] In the example in Figure 9, the channel matrix is ​​2 rows and 8 columns in size. The rows represent the number of data "0" and data "1" in the corrected data, DLECNT. num1[0] to num1[7] represent the number of data "1". num0[0] to num0[7] represent the number of data "0". The columns represent indices.

[0087] For example, if the value of a bit in the corrected data is "1" and the index corresponding to this bit is 0, the element num1[0] in the first row and first column is incremented by 1. That is, num1[0] represents the number of memory cells MC that have a threshold voltage corresponding to section D1 and that stored the data "1". Also, if the value of a bit in the corrected data is "0" and the index corresponding to this bit is 0, the element num0[0] in the second row and first column is incremented by 1. That is, num0[0] represents the number of memory cells MC that have a threshold voltage corresponding to section D1 and that stored the data "0".

[0088] Similarly, if the value of a bit in the corrected data is "1" and the index corresponding to this bit is 4, the element num1[4] in the first row and fifth column is incremented by 1. That is, num1[4] represents the number of memory cells MC that have a threshold voltage corresponding to section D5 and that stored the data "1". Also, if the value of a bit in the corrected data is "0" and the index corresponding to this bit is 4, the element num0[4] in the second row and fifth column is incremented by 1. That is, num0[4] represents the number of memory cells MC that have a threshold voltage corresponding to section D5 and that stored the data "0".

[0089] [1-1-6-2] Processing of the read information generation circuit Next, we will explain the processing of the read information generation circuit 17.

[0090] Return to Figure 7. The read information generation circuit 17 receives the channel matrix from the channel matrix generation circuit 23.

[0091] (DLE1 table generation process) The read information generation circuit 17 generates a DLE1 table by statistically calculating the likelihood (specifically, LLR) of each index bit using a channel matrix. Specifically, the LLR[idx] for each index is calculated using the following formula (1).

number

number

[0092] (Shift value generation process) The process of generating the shift value Vst will be explained using Figure 10 and Figures 10-2 to 10-5. Figure 10 is a diagram illustrating the process of generating the shift value Vst. Figures 10-2 to 10-5 are diagrams illustrating the relationship between the threshold voltage distribution of the memory cell MC and the channel matrix.

[0093] The read information generation circuit 17 generates a shift value Vst using the channel matrix. Specifically, the read information generation circuit 17 uses the number of data "1"s DLECNT(num1[0]~num1[7]) and the number of data "0"s DLECNT(num0[0]~num0[7]) for each index of the channel matrix. For example, the shaded area in Figure 10-2 corresponds to the number of memory cell MCs DLECNT(num1[2]) among the multiple memory cell MCs whose threshold voltage is within the voltage range corresponding to index 2 and which stored "1"s in the corrected data (i.e., data that successfully underwent error correction). The shaded area in Figure 10-3 corresponds to the number of memory cell MCs DLECNT(num0[2]) among the multiple memory cell MCs whose threshold voltage is within the voltage range corresponding to index 2 and which stored "0"s in the corrected data. The shaded area in Figure 10-4 corresponds to the number of memory cells DLECNT(num1[3]) among the multiple memory cells MC whose threshold voltage falls within the voltage range corresponding to index 3 and which stored the "1" in the corrected data. The shaded area in Figure 10-5 corresponds to the number of memory cells DLECNT(num0[3]) among the multiple memory cells MC whose threshold voltage falls within the voltage range corresponding to index 3 and which stored the "0" in the corrected data.

[0094] The read information generation circuit 17 compares the number of data "1"s (DLECNT) with the number of data "0"s (DLECNT) in the channel matrix, starting from the first column. The read information generation circuit 17 detects the column where the order of the number of data "1"s (DLECNT) and the number of data "0"s (DLECNT) is reversed. As shown in Figures 10-2 and 10-3, in the third column of the channel matrix corresponding to index 2 (section D3), the number of data "1"s (num1[2]) is greater than the number of data "0"s (num0[2]). As shown in Figures 10-4 and 10-5, in the fourth column of the channel matrix corresponding to index 3 (section D4), the number of data "0"s (num0[3]) is greater than the number of data "1"s (num1[3]). The relative sizes of the number of data "1"s and data "0"s are swapped at the intersection of the two threshold voltage distributions of the memory cell MC. In other words, it is presumed that the intersection of the two threshold voltage distributions of the memory cell MC is where the relative sizes of the number of data "1"s and data "0"s are swapped. Therefore, by detecting the column in the channel matrix where the relative sizes of the number of data "1"s and data "0"s are swapped, it is possible to obtain a position with a small number of error bits, i.e., the intersection of the two threshold voltage distributions of the memory cell MC.

[0095] This process of searching for the intersection where two threshold voltage distributions overlap is called "tracking." The read information generation circuit 17 acquires the voltage (the voltage acquired by tracking) set between the column where the magnitudes are swapped and the column corresponding to the category where the threshold voltage is lower by voltage dR than this column. The read information generation circuit 17 generates a shift value Vst as the result of adding or subtracting the difference voltage between the voltage acquired by tracking (hereinafter also referred to as "tracking voltage Vtr") and the default voltage Vdt.

[0096] In the example shown in Figure 10, as mentioned above, the number of memory cell MCs (num1[2]) that had a threshold voltage corresponding to index 2 (section D3) and stored data "1" is greater than the number of memory cell MCs (num0[2]) that had a threshold voltage corresponding to index 2 and stored data "0". Also, the number of memory cell MCs (num1[3]) that had a threshold voltage corresponding to index 3 (section D4) and stored data "1" is smaller than the number of memory cell MCs (num0[3]) that had a threshold voltage corresponding to index 3 and stored data "0". In other words, in the example shown in Figure 10, the magnitude of DLECNT is reversed between the third and fourth columns of the channel matrix, that is, before and after the SB read voltage AR(-1). It is presumed that the intersection point where the two threshold voltage distributions of the memory cell MCs overlap is shifted 1 × dR towards the low voltage side from the HB read voltage AR(0). In this case, the lead information generation circuit 17 calculates the tracking voltage Vtr (the voltage at the intersection of the two overlapping threshold voltage distributions) based at least on the number of data "1"s (num1[2]) and the number of data "0"s (num0[2]) for index 2. Furthermore, the lead information generation circuit 17 calculates the tracking voltage Vtr based on the number of data "1"s (num1[3]) and the number of data "0"s (num0[3]) for index 3. For example, if any voltage in the voltage range corresponding to index 2 is smaller than any voltage in the voltage range corresponding to index 3, the lead information generation circuit 17 calculates the tracking voltage Vtr (e.g., voltage AR(-1)) from the voltage range between the voltage range corresponding to index 2 and the voltage range corresponding to index 3, depending on the fact that num1[2] is greater than num0[2] and num1[3] is smaller than num0[3]. The read information generation circuit 17 then generates a shift value Vst by adding or subtracting the difference voltage between the tracking voltage Vtr (voltage AR(-1)) and the default voltage Vdt (Vdif1 in the example of Figure 10) to the default voltage Vdt.

[0097] Note that, for example, when the magnitudes of DLECNT are swapped in the columns before and after the HB read voltage AR(0), the read information generation circuit 17 generates, as the shift value Vst, the result obtained by adding or subtracting the differential voltage between the voltage AR(0) and the default voltage Vdt (Vdif2 in the example of FIG. 10) to the default voltage Vdt. When the magnitudes of DLECNT are swapped in the columns before and after the SB read voltage AR(+2), the read information generation circuit 17 generates, as the shift value Vst, the result obtained by adding or subtracting the differential voltage between the voltage AR(+2) and the default voltage Vdt (Vdif3 in the example of FIG. 10) to the default voltage Vdt.

[0098] Also, as can be understood from Equation (1) or Equation (2), among the memory cells MC having a threshold voltage corresponding to a certain index idx, when the number of memory cells MC storing data “1” is larger than the number of memory cells MC storing data “0” (when num1[idx]>num0[idx]), the sign of LLR[idx] corresponding to this index idx becomes negative. On the other hand, among the memory cells MC having a threshold voltage corresponding to a certain index idx, when the number of memory cells MC storing data “1” is smaller than the number of memory cells MC storing data “0” (when num1[idx]<num0[idx]), the sign of LLR[idx] corresponding to this index idx becomes positive. That is, the index at which the magnitudes of DLECNT are swapped in the channel matrix and the index at which the sign of LLR is inverted in the DLE1 table match.

[0099] (DLE1 Table Correction Process) The correction process of the DLE1 table will be described with reference to FIGS. 11, FIG. 11-2, and FIG. 11-3. FIGS. 11, FIG. 11-2, and FIG. 11-3 are diagrams for explaining the correction process of the DLE1 table. FIG. 11 shows an example in which the intersection of the two threshold voltage distributions of the memory cell MC (i.e., the tracking voltage Vtr) is at the voltage AR(-1).

[0100] As shown in Figure 11, the DLE1 table contains LLRs corresponding to the voltage ranges corresponding to each of the indices 0 to 7. Hereafter, the LLRs corresponding to the voltage ranges corresponding to indices 0 to 7 will also be referred to as "LLR for index 0," "LLR for index 1," ..., "LLR for index 7," respectively. After the DLE1 table is generated, for example, the LLR for index 2 stores a setting value of -1 as the setting value corresponding to the voltage range corresponding to index 2. The LLR for index 3 stores a setting value of +1 as the setting value corresponding to the voltage range corresponding to index 3.

[0101] The read information generation circuit 17 acquires the voltage difference between the HB read voltage when SB correction was successful, i.e., the voltage applied to the word line when data with successful SB correction was acquired (here, voltage AR(0)), and the tracking voltage Vtr (voltage AR(-1)). Based on the acquired voltage difference, the read information generation circuit 17 corrects the DLE1 table.

[0102] Specifically, the read information generation circuit 17 shifts each LLR in the DLE1 table based on the acquired voltage difference. In Figure 11, the read information generation circuit 17 shifts each LLR from index 0 to 5 in the DLE1 table one position to the right. The LLR at index 0 (=-5) is shifted to index 1. The LLR at index 1 (=-3) is shifted to index 2. The LLR at index 2 (=-1) is shifted to index 3. That is, if the HB read voltage after successful SB correction is greater than the tracking voltage Vtr, the read information generation circuit 17 stores the LLR (=-1) that was stored at index 2 in the DLE1 table before correction as the LLR at index 3 in the DLE1 table after correction. The LLR at index 3 (=+1) is shifted to index 4. The LLR at index 4 (=+3) is shifted to index 5. The LLR at index 5 (=+5) is shifted to index 6. The LLR (=+9) at index 7 is temporarily removed as it will be replaced by the combined value described later. Due to the LLR shift, indexes 0 and 7 will no longer contain LLR.

[0103] The read information generation circuit 17 uses formula (1) to calculate the LLR (hereinafter also referred to as the "integrated value") based on the DLECNT of multiple indices in the channel matrix. In the example shown in Figure 11, the read information generation circuit 17 substitutes the sum of the number of "0"s at index 6 of the channel matrix (num0[6]) and the number of "0"s at index 7 (num0[7]) into num0[idx] of formula (1). The read information generation circuit 17 substitutes the sum of the number of "1"s at index 6 of the channel matrix (num1[6]) and the number of "1"s at index 7 (num1[7]) into num1[idx] of formula (1). In other words, the read information generation circuit 17 calculates the integrated value based on num0[6], num0[7], num1[6], and num1[7]. If the value calculated using formula (1) is greater than +9, the read information generation circuit 17 uses +9 as the integrated value. Here, we assume that the read information generation circuit 17 calculated +9 as the integrated value. The read information generation circuit 17 uses the calculated +9 as the LLR for index 7 in the DLE1 table.

[0104] The read information generation circuit 17 uses the value obtained by inverting the sign of the integrated value (LLR at index 7) (=-9) as the LLR at index 0 of the DLE1 table. This completes the correction process for the DLE1 table.

[0105] Figure 11-2 shows an example where the voltage applied to the word line when data successfully corrected by SB is obtained is voltage AR(0), and the intersection of the two threshold voltage distributions of the memory cell MC is at voltage AR(-2).

[0106] In Figure 11-2, the read information generation circuit 17 shifts each LLR from index 0 to 4 in the DLE1 table two units to the right. The LLR at index 0 (=-3) is shifted to index 2. The LLR at index 1 (=-1) is shifted to index 3. The LLR at index 2 (=+1) is shifted to index 4. The LLR at index 3 (=+3) is shifted to index 5. The LLR at index 4 (=+5) is shifted to index 6. The LLR at index 7 (=+9) is deleted because it is replaced by an integrated value. Due to the LLR shift, indices 0, 1, and 7 no longer contain LLRs.

[0107] The read information generation circuit 17 uses formula (1) to calculate an integrated value based on the three DLECNTs at indices 5 to 7 of the channel matrix. In the example shown in Figure 11-2, the read information generation circuit 17 substitutes the sum of the number of "0"s at index 5 of the channel matrix (num0[5]), the number of "0"s at index 6 (num0[6]), and the number of "0"s at index 7 (num0[7]) into num0[idx] of formula (1). The read information generation circuit 17 substitutes the sum of the number of "1"s at index 5 of the channel matrix (num1[5]), the number of "1"s at index 6 (num1[6]), and the number of "1"s at index 7 (num1[7]) into num1[idx] of formula (1). Here, the read information generation circuit 17 calculates +9 as the integrated value. The read information generation circuit 17 uses the calculated +9 as the LLR for index 7 in the DLE1 table. The read information generation circuit 17 uses the value obtained by inverting the sign of the integrated value (LLR for index 7) (=-9) as the LLR for index 0 in the DLE1 table. The read information generation circuit 17 uses the value obtained by inverting the sign of the LLR for index 6 in the DLE1 table (=+5) (=-5) as the LLR for index 1 in the DLE1 table.

[0108] The number of SB read voltages is represented by (k × 2) (where k is an integer greater than or equal to 1), and the indices of the channel matrix and DLE1 table are represented by integers greater than or equal to 0 and less than or equal to ((k × 2) + 1). If the intersection of the two threshold voltage distributions of the memory cell MC is at a voltage AR(-j) greater than the HB read voltage for which SB correction was successful (where j is an integer greater than or equal to 1 and less than or equal to k), the read information generation circuit 17 shifts the LLR from index 0 to index ((k × 2) - j) in the DLE1 table to the right by j. The read information generation circuit 17 calculates an integrated value based on the (j + 1) DLECNTs included in the channel matrix from index ((k × 2) - j + 1) to index ((k × 2) + 1). The read information generation circuit 17 sets the calculated integrated value as the LLR at index ((k × 2) + 1) in the DLE1 table. The read information generation circuit 17 uses the LLR values ​​obtained by inverting the sign of the LLR values ​​from index ((k×2)+1) to index ((k×2)+1-(j-1)) in the DLE1 table as the LLR values ​​from index 0 to index (j-1) in the DLE1 table.

[0109] Figure 11-3 shows an example where the voltage applied to the word line when data successfully corrected by SB is obtained is voltage AR(0), and the intersection of the two threshold voltage distributions of the memory cell MC is at voltage AR(+1).

[0110] As shown in Figure 11-3, after the DLE1 table is generated, for example, the LLR for index 2 stores -5 as the setting value corresponding to the voltage range corresponding to index 2. The LLR for index 3 stores -3 as the setting value corresponding to the voltage range corresponding to index 3.

[0111] In Figure 11-3, the read information generation circuit 17 shifts each LLR from index 2 to 7 in the DLE1 table one position to the left. The LLR at index 7 (=+5) is shifted to index 6. The LLR at index 6 (=+3) is shifted to index 5. The LLR at index 5 (=+1) is shifted to index 4. The LLR at index 4 (=-1) is shifted to index 3. The LLR at index 3 (=-3) is shifted to index 2. That is, if the HB read voltage after successful SB correction is smaller than the tracking voltage Vtr, the read information generation circuit 17 stores the LLR (=-3) that was stored at index 3 in the DLE1 table before correction as the LLR at index 2 in the DLE1 table after correction. The LLR at index 2 (=-5) is shifted to index 1. The LLR at index 0 (=-9) is replaced with an integrated value and is therefore deleted. Due to the LLR shift, indices 0 and 7 no longer contain LLRs.

[0112] The read information generation circuit 17 uses formula (1) to calculate an integrated value based on two DLECNTs from index 0 to index 1 of the channel matrix. In the example shown in Figure 11-3, the read information generation circuit 17 substitutes the sum of the number of "0"s at index 0 of the channel matrix (num0[0]) and the number of "0"s at index 1 (num0[1]) into num0[idx] of formula (1). The read information generation circuit 17 substitutes the sum of the number of "1"s at index 0 of the channel matrix (num1[0]) and the number of "1"s at index 1 (num1[1]) into num1[idx] of formula (1). If the value calculated using formula (1) is less than -9, the read information generation circuit 17 uses -9 as the integrated value. Here, we assume that the read information generation circuit 17 calculated -9 as the integrated value. The read information generation circuit 17 uses the calculated -9 as the LLR for index 0 in the DLE1 table. The read information generation circuit 17 then uses the value obtained by inverting the sign of the integrated value (LLR for index 0) (=+9) as the LLR for index 7 in the DLE1 table.

[0113] Thus, if the intersection of the two threshold voltage distributions of the memory cell MC is at a voltage AR(+j) higher than the HB read voltage for which SB correction was successful, the read information generation circuit 17 shifts the LLR from index (j+1) to index ((k×2)+1) in the DLE1 table to the left by j positions. The read information generation circuit 17 calculates an integrated value based on the (j+1) DLECNTs included in index 0 to index j of the channel matrix. The read information generation circuit 17 uses the calculated integrated value as the LLR for index 0 in the DLE1 table. The read information generation circuit 17 uses the value obtained by inverting the sign of the LLR from index 0 to index (j-1) in the DLE1 table as the LLR for index ((k×2)+1) to index ((k×2)+1-(j-1)) in the DLE1 table.

[0114] Returning to Figure 7, the read information generation circuit 17 transmits the shift value Vst generated in the shift value generation process described above to the RAM 16. The shift value Vst is applied to the HB read voltage when performing a read operation for the next page in the same block BLK. In the read operation for the next page in the same block BLK, the memory controller 10 performs an HB read using the HB read voltage to which the shift value Vst has been applied. The memory controller 10 performs an SB read using multiple SB read voltages based on the HB read voltage to which the shift value Vst has been applied.

[0115] The read information generation circuit 17 sends the DLE1 table generated in the DLE1 table generation process described above to the memory 24. The generated DLE1 table is used as an LLR table when the soft-decision decoding circuit 21 performs SB correction on the next ECC frame in the same page, for example, until the DLE1 table correction process described above is performed. The read information generation circuit 17 sends the corrected DLE1 table, corrected in the DLE1 table correction process described above, to the memory 24. If a DLE1 table is already stored in the memory 24, the DLE1 table is overwritten with the corrected DLE1 table. The corrected DLE1 table is used as an LLR table when the soft-decision decoding circuit 21 performs SB correction on the next ECC frame in the same page. When the soft-decision decoding circuit 21 performs multiple SB corrections on a given ECC frame, the soft-decision decoding circuit 21 can select LLR tables in the following order, for example: LLR table TBL1, the DLE1 table stored in the memory 24, LLR table TBL2, and LLR table TBL3.

[0116] [1-2] Read operation The read operation will be explained using Figure 12. Figure 12 is a flowchart showing the read operation by the memory controller 10 included in the memory system 1 according to this embodiment. In the following explanation, the case in which the cell unit CU stores one page of data will be used as an example.

[0117] When the memory controller 10 starts a read operation, it first applies an HB read voltage to the selected word line to read the HB data corresponding to one page in a certain block BLK (HB read) (S10). Here, it is assumed that one word line included in a certain block BLK (hereinafter also referred to as the "first word line") is selected. The HB read voltage is set based on the default voltage value Vdt or shift value Vst stored in the RAM 16. The read HB data (i.e., acquired from multiple memory cells MC connected to the first word line) is stored in the buffer memory 13.

[0118] After the HB read is executed, the memory controller 10 receives HB data from the buffer memory 13 in ECC frame units. The hard judgment decoding circuit 20 corrects errors in the user data of the ECC frame (HB correction).

[0119] If the HB correction of all ECC frames of the HB data corresponding to one page is successful (S11_Yes), and the current page is not the last page to be read within the same block BLK (hereinafter simply referred to as the "last page") (S12_No), the memory controller 10 executes the process of step S10 for the next page within the same block BLK. If the current page is the last page (S12_Yes), the memory controller 10 terminates the read operation.

[0120] On the other hand, if HB correction of at least one ECC frame of HB data corresponding to one page is unsuccessful (S11_No), the memory controller 10 reads out multiple SB data (e.g., SB1 data and SB2 data) by applying multiple SB read voltages to the selected word line (S13). The multiple SB read voltages are set based on the HB read voltage. The read SB1 data and SB2 data (i.e., acquired from multiple memory cells MC connected to the first word line) are stored in the buffer memory 13.

[0121] After the SB read is executed, the memory controller 10 receives HB data, SB1 data, and SB2 data from the buffer memory 13 in ECC frame units (S14).

[0122] The LLR conversion circuit 22 selects one of several LLR tables. Using the selected LLR table, the LLR conversion circuit 22 converts the combination of hard bits, first soft bits, and second soft bits into LLR on an ECC frame basis. The soft-decision decoding circuit 21 uses the LLR and the soft-decision parity in the HB data, SB1 data, and SB2 data to correct errors in the user data of the ECC frame (SB correction) (S15).

[0123] If the SB correction of the ECC frame is successful (S16_Yes), the read information generation circuit 17 generates a DLE1 table based on the data corrected by the SB correction, which is obtained from multiple memory cells MC connected to the first word line (S18). The generated DLE1 table is stored in the memory 24.

[0124] On the other hand, if the SB correction of the ECC frame is unsuccessful (S16_No), and there are no unselected LLR tables for the same ECC frame (S17_No), the memory controller 10 executes the process in step S19 described below. If there is an unselected LLR table for the same ECC frame (S17_Yes), the memory controller 10 executes the process in step S15 using the next LLR table. Note that "unselected LLR table" means, for example, an LLR table that has not been selected among LLR tables TBL1, TBL2, and TBL3, as well as the DLE1 table.

[0125] When performing SB correction on a given ECC frame, the soft-decision decoding circuit 21 first uses the LLR table TBL1 stored in RAM 16 to perform SB correction. If this SB correction is unsuccessful, and if the DLE1 table is stored in memory 24, the soft-decision decoding circuit 21 uses the DLE1 table to perform SB correction. If this SB correction is unsuccessful, or if the DLE1 table is not stored in memory 24, the soft-decision decoding circuit 21 uses the LLR table TBL2 stored in RAM 16 to perform SB correction. If this SB correction is unsuccessful, the soft-decision decoding circuit 21 uses the LLR table TBL3 stored in RAM 16 to perform SB correction.

[0126] After the DLE1 table generation process in step S18, or if there are no unselected LLR tables (S17_No), the memory controller 10 determines whether the current ECC frame is the last ECC frame in the same page (hereinafter simply referred to as the "last ECC frame"). If the current ECC frame is not the last ECC frame (S19_No), the memory controller 10 executes the process in step S14 for the next ECC frame in the same page. On the other hand, if the current ECC frame is the last ECC frame (S19_Yes), or if the current page is the last page (S20_Yes), the memory controller 10 terminates the read operation. If the current page is not the last page (S20_No), the read information generation circuit 17 generates a shift value Vst (S21). The generated shift value Vst is stored in the RAM 16 after the process in step S22, which will be described later.

[0127] If the generated shift value Vst is the same as the shift value stored in RAM 16 (S22_Yes), the memory controller 10 performs the process of step S10 for the next page in the same block BLK. On the other hand, if the generated shift value Vst is not the same as the shift value stored in RAM 16 (S22_No), the read information generation circuit 17 corrects the DLE1 table based on the voltage difference between the voltage applied to the first word line when data with successful SB correction is acquired and the tracking voltage Vtr (S23). The corrected DLE1 table is stored in memory 24. After that, the memory controller 10 performs the process of step S10 for the next page in the same block BLK.

[0128] The processing for the next page within the same block BLK is as follows, for example: In step S10, a word line different from the first word line included in the same block BLK (hereinafter also referred to as the "second word line") is selected, and the memory controller 10 performs an HB read by applying an HB read voltage (shift value Vst, i.e., tracking voltage Vtr) to the second word line. In step S13, the memory controller 10 performs an SB read by applying multiple SB read voltages to the second word line. In step S16, the memory controller 10 performs error correction on the data acquired from multiple memory cells MC connected to the second word line using a DLE1 table corrected based on the data acquired from multiple memory cells MC connected to the first word line included in the same block BLK.

[0129] [1-3] Effects According to the first embodiment, the error correction capability of the memory system 1 can be improved. This effect will be explained below with reference to Figures 13 and 13-2. Figures 13 and 13-2 are diagrams illustrating the effects of the memory system 1 according to this embodiment.

[0130] In memory system 1, the two threshold voltage distributions of memory cells MC in a given page (hereinafter also referred to as "page 1") (hereinafter also referred to as "page 1 threshold voltage distribution") and the two threshold voltage distributions of memory cells MC in the next page (hereinafter also referred to as "page 2") within the same block (hereinafter also referred to as "page 2 threshold voltage distribution") tend to have similar distributions. This is the case, for example, when page 1 and page 2 are connected to the same word line and each is contained within an adjacent string unit SU. The examples in Figures 13 and 13-2 show the threshold voltage distributions of page 1 and page 2, respectively.

[0131] Figure 13 shows an example of the threshold voltage distribution for the first page, where the distribution intersection is near voltage AR(0). Assume that a read operation is performed on the first page having this threshold voltage distribution, using voltage AR(+1) as the HB read voltage. When SB correction is successful during the read operation of the first page, a channel matrix like the one shown in Figure 13 is generated using the data for which SB correction was successfully performed. Using the generated channel matrix, a DLE1 table (hereinafter also referred to as "table D1A") like the one shown in Figure 13 is generated.

[0132] In the example shown in Figure 13, the magnitudes of DLECNT are swapped between index 2 and index 3 of the channel matrix. Therefore, as previously mentioned with reference to Figure 10, the sign of LLR is reversed between index 2 and index 3 of table D1A. As previously mentioned with reference to Figures 10-2 to 10-5, it is presumed that the intersection (voltage) of the threshold voltage distribution on page 1 is located at the position where the magnitudes of DLECNT in the channel matrix are swapped, that is, at the position where the sign of LLR in table D1A is reversed.

[0133] In this embodiment, the intersection point of the threshold voltage distribution on the first page (voltage AR(0)) is obtained by the tracking described above. However, the HB read voltage AR(+1), which is used in the read operation of the first page and for which SB correction was successful, does not coincide with the intersection point of the threshold voltage distribution on the first page (voltage AR(0)).

[0134] The threshold voltage distributions on page 1 and page 2 tend to have similar distributions. Therefore, it is presumed that the location of the intersection point of the threshold voltage distributions on page 2 is similar to the location of the intersection point of the threshold voltage distributions on page 1. As mentioned above, the location of the intersection point where the two threshold voltage distributions overlap represents a location with a small number of error bits. For this reason, for page 2, by performing the read operation using the voltage at the intersection point of the threshold voltage distributions on page 1 (voltage AR(0)) as the HB read voltage, the possibility of failure in SB correction on page 2 can be reduced.

[0135] Therefore, in this embodiment, the difference voltage between the voltage AR(0) obtained by tracking and the default voltage Vdt is added or subtracted to generate the shift value Vst. The shift value Vst(voltage AR(0)) is used as the HB read voltage for the read operation on page 2.

[0136] However, as shown in Figure 13, there is a discrepancy between the intersection point of the threshold voltage distribution on page 2 and the position where the sign of the LLR in table D1A is reversed. In this case, applying the LLR in table D1A to the data read from page 2 using the HB read voltage AR(0) increases the likelihood of failure in SB correction on page 2. On the other hand, if the position where the sign of the LLR is reversed is between index 3 and index 4, the discrepancy between the intersection point of the threshold voltage distribution on page 2 and the position where the sign of the LLR in table D1A is reversed is eliminated. In this case, the likelihood of failure in SB correction on page 2 decreases.

[0137] Therefore, in this embodiment, as shown in Figure 13-2, in the reading operation of the first page, table D1A is corrected based on the voltage difference between the HB read voltage (AR(+1)) for which SB correction was successful and the voltage at the intersection of the threshold voltage distribution on the first page (voltage AR(0)). By shifting the LLR of table D1A based on this voltage difference, table D1A is corrected to the DLE1 table (hereinafter also referred to as "table D1B") shown in Figure 13-2. As a result, the position where the sign of the LLR in table D1B is reversed is between index 3 and index 4. That is, the discrepancy between the position of the intersection of the threshold voltage distribution on the second page and the position where the sign of the LLR in table D1B is reversed is eliminated. Therefore, when the LLR of table D1B is applied to the data read from the second page using the HB read voltage AR(0), the probability of successful SB correction on the second page increases. Thus, the data error correction capability can be improved.

[0138] [2] Second embodiment A second embodiment will now be described. In the memory system 1 according to this embodiment, the configuration of the memory controller 10, the configuration of the ECC circuit 14, and the DLE1 table correction processing by the read information generation circuit 17 differ from those of the first embodiment. The following will focus on the differences from the first embodiment.

[0139] [2-1] Configuration of the memory controller 10 The internal configuration of the memory controller 10 will be explained using Figure 14. Figure 14 is a block diagram showing an example of an information processing system including the memory system 1 according to this embodiment.

[0140] The memory controller 10 further includes a DLE2 table (Dynamic LLR Estimation 2) generation circuit 25.

[0141] The DLE2 table generation circuit 25 is a circuit that performs the DLE2 table generation process. The DLE2 table is a table that shows the relationship between the voltage range of the threshold voltages of multiple memory cells MC and LLR, and is generated based on data that failed to be corrected by the soft-decision decoding circuit 21. Details of the processing of the DLE2 table generation circuit 25 will be described later.

[0142] Other configurations of the memory controller 10 are the same as those of the first embodiment described with reference to Figure 1. Other configurations of the memory system 1 are the same as those of the first embodiment described with reference to Figure 1.

[0143] [2-2] Configuration of ECC circuit 14 The internal configuration of the ECC circuit 14 will be explained using Figure 15. Figure 15 is a block diagram showing an example of the configuration of an ECC circuit.

[0144] The ECC circuit 14 further includes a channel matrix estimation circuit 26.

[0145] The channel matrix estimation circuit 26 is a circuit that performs channel matrix estimation processing. The channel matrix estimation circuit 26 estimates the channel matrix on an ECC frame basis using combinations of hard bits and soft bits, and data that the soft-decision decoding circuit 21 failed to correct. Hereafter, data that the soft-decision decoding circuit 21 failed to correct will also be referred to as "failed data".

[0146] Memory 24 stores the DLE2 table generated by the DLE2 table generation circuit 25.

[0147] Other configurations of the ECC circuit 14 are the same as those of the first embodiment described with reference to Figure 2.

[0148] [2-3] Processing of ECC circuit 14 The processing of the ECC circuit 14 will be explained using Figure 16. Figure 16 is a diagram illustrating the processing related to soft-decision decoding.

[0149] If the soft-decision decoding circuit 21 fails to correct the subband signal (SB), it stores the failure data in the memory 24. The soft-decision decoding circuit 21 then transmits the failure data to the channel matrix estimation circuit 26.

[0150] The channel matrix estimation circuit 26 receives data (HB data, SB1 data, and SB2 data) read from the NAND flash memory 30 in ECC frame units from the buffer memory 13. The channel matrix estimation circuit 26 receives failure data from the memory 24. The number of error bits contained in the failure data may differ from the number of error bits contained in the data received from the buffer memory 13. The channel matrix estimation circuit 26 aggregates the pairs of HB data, SB1 data, and SB2 data received from the buffer memory 13 and the failure data received from the memory 24, and estimates the channel matrix based on the aggregation results. The channel matrix estimation circuit 26 transmits the estimated channel matrix to the DLE2 table generation circuit 25.

[0151] Other operations of the ECC circuit 14 are the same as those described in the first embodiment with reference to Figure 7.

[0152] [2-4] Processing of the DLE2 table generation circuit 25 The processing of the DLE2 table generation circuit 25 will be explained using Figure 16.

[0153] The DLE2 table generation circuit 25 generates a DLE2 table by statistically calculating the likelihood (specifically, LLR) of each index bit using the estimated channel matrix. The DLE2 table generation circuit 25 calculates the DLE2 table from the estimated channel matrix. The calculation of the DLE2 table is described, for example, in Japanese Patent Application No. 2020-899, filed on January 7, 2020. This patent application is incorporated by reference in its entirety in this specification.

[0154] The DLE2 table generation circuit 25 sends the DLE2 table to the memory 24. If a DLE2 table is already stored in the memory 24, the DLE2 table stored in the memory 24 is overwritten with the DLE2 table received by the memory 24. The DLE2 table is used in the second correction process of the DLE1 table, which will be described later.

[0155] [2-5] Processing of the read information generation circuit 17 The DLE1 table correction process performed by the read information generation circuit 17 includes a first correction process and a second correction process.

[0156] The first and second correction processes will be explained using Figure 17. Figure 17 is a diagram illustrating the first and second correction processes for the DLE1 table. Figure 17 shows an example where the HB read voltage after successful SB correction is voltage AR(0), and the intersection of the two threshold voltage distributions of the memory cell MC is at voltage AR(-1).

[0157] As shown in Figure 17, the DLE2 table contains LLRs corresponding to the voltage ranges corresponding to each of the indices 0 to 7. In Figure 17, indices 0 to 7 in the DLE2 table correspond to indices 0 to 7 in the DLE1 table, respectively.

[0158] (First correction process) The read information generation circuit 17, similar to the first embodiment, shifts each LLR from index 0 to 5 in the DLE1 table one position to the right, calculates a combined value, and sets the combined value as the LLR for index 7. This completes the first correction process. At this stage, index 0 does not contain an LLR.

[0159] For example, if the intersection of the two threshold voltage distributions of the memory cell MC is at voltage AR(-2), the read information generation circuit 17, similar to the first embodiment, shifts each LLR from index 0 to 4 in the DLE1 table by 2 units to the right, calculates an integrated value, and sets the integrated value as the LLR at index 7.

[0160] (Second correction process) After the first correction process, the LLR of index 0 in the DLE2 table is set to the LLR of index 0 in the DLE1 table, which was corrected in the first correction process. This completes the second correction process.

[0161] For example, if the intersection of the two threshold voltage distributions of the memory cell MC is at voltage AR(-2), the read information generation circuit 17 sets the LLR of index 0 in the DLE2 table to the LLR of index 0 in the DLE1 table corrected in the first correction process. The read information generation circuit 17 also sets the LLR of index 1 in the DLE2 table to the LLR of index 1 in the DLE1 table corrected in the first correction process.

[0162] [2-6] Read operation The read operation will be explained using Figures 18 and 19. Figures 18 and 19 are flowcharts showing the read operation of the memory controller 10 included in the memory system 1 according to this embodiment. In this embodiment, operations S30 to S34 are added to the operations S10 to S23 in Figure 12 of the first embodiment. Furthermore, in this embodiment, operation S23 is replaced with a first correction process. Operations S10 to S22 are the same as in the first embodiment. Below, operations S23 and S30 to S34 will be explained in detail.

[0163] In Figure 18, if the SB correction of the ECC frame is unsuccessful (S16_No), and there are no unselected LLR tables for the same ECC frame (S17_No), the memory controller 10 executes the process in step S19. If there is an unselected LLR table (S17_Yes), the memory controller 10 determines whether the DLE1 table has already been selected as the LLR table for the same ECC frame.

[0164] If the DLE1 table has already been selected for the same ECC frame (S30_Yes), the memory controller 10 executes the process in step S15 using the next LLR table. On the other hand, if the DLE1 table has not been selected for the same ECC frame (S30_No), the memory controller 10 determines whether or not the DLE1 table exists in memory 24.

[0165] If the DLE1 table does not exist (S31_No), the memory controller 10 executes the process in step S15 using the following LLR table. On the other hand, if the DLE1 table exists (S31_Yes), the memory controller 10 determines whether or not the DLE1 table has indexes that do not contain LLR. Note that the state in which the DLE1 table has indexes that do not contain LLR is, for example, a state in which LLR has been shifted by the first correction process and there are empty indexes in the DLE1 table where LLR is not set.

[0166] If the DLE1 table does not contain an index that does not include LLR (S32_No), the memory controller 10 executes the process in step S15 using the next LLR table (for example, the DLE1 table). On the other hand, if the DLE1 table does contain an index that does not include LLR (S32_Yes), the memory controller 10 (more specifically, the DLE2 table generation circuit 25) generates the DLE2 table (S33). The generated DLE2 table is stored in memory 24. The read information generation circuit 17 performs a second correction process on the DLE1 table (S34). The DLE1 table corrected in the second correction process is stored in memory 24. After that, the memory controller 10 executes the process in step S15 using the next LLR table (for example, the DLE1 table corrected in the second correction process).

[0167] In Figure 19, if the generated shift value Vst is not the same as the shift value stored in RAM 16 (S22_No), the read information generation circuit 17 performs a first correction process on the DLE1 table (S23). The DLE1 table corrected in the first correction process is stored in memory 24. Subsequently, the memory controller 10 performs the process of step S10 for the next page in the same block BLK.

[0168] [2-7] Effects According to the configuration of this embodiment, the same effects as those of the first embodiment are achieved.

[0169] Furthermore, according to this embodiment, by performing the second correction process, it is possible to create a DLE1 table that is closer to the LLR of the threshold voltage distribution of the ECC frame to be corrected for SB.

[0170] [3] Third embodiment A third embodiment will now be described. In the memory system 1 according to this embodiment, the DLE1 table correction processing by the read information generation circuit 17 differs from that of the first embodiment. The flowchart showing the read operation of the memory controller 10 is the same as in the first embodiment. The following will focus on the differences from the first embodiment.

[0171] [3-1] Processing of the read information generation circuit 17 (DLE1 table correction process) The read information generation circuit 17 corrects the DLE1 table using the LLR pattern table. The LLR pattern table is a table that shows the relationship between the voltage range of the threshold voltages of multiple memory cells MC and LLR. The LLR pattern table is loaded from the NAND flash memory 30 to the RAM 16, for example, immediately after power-on. The LLR pattern table is managed by the memory controller 10.

[0172] The LLR pattern table will be explained using Figure 20. Figure 20 is a conceptual diagram of the LLR pattern table.

[0173] The LLR pattern table stores LLRs for each index from 0 to 7. As shown in Figure 20, the LLR pattern table contains LLRs corresponding to the voltage range corresponding to each index from 0 to 7. In the example in Figure 20, separate LLR pattern tables are created for indices 0 to 3 corresponding to the low-voltage section D1 to D4 of the HB lead voltage and indices 4 to 7 corresponding to the high-voltage section D5 to D8. The LLR pattern table for the low-voltage side of the HB lead voltage includes two LLR patterns, Pat1 and Pat2. LLR pattern Pat1 has LLRs corresponding to each index from 0 to 3. LLR pattern Pat2 is similar. The LLR pattern table for the high-voltage side of the HB lead voltage includes two LLR patterns, Pat3 and Pat4. LLR pattern Pat3 has LLRs corresponding to each index from 4 to 7. LLR pattern Pat4 is similar. Note that the LLR values ​​in Figure 20 are just examples. The LLR pattern tables for the low-voltage side of the HB read voltage and the LLR pattern tables for the high-voltage side of the HB read voltage may be combined into a single table. Each LLR pattern can be determined experimentally, for example, for each stress condition. The stress conditions include the temperature of the NAND flash memory 30 and the number of data erase operations performed on the NAND flash memory 30. For example, LLR pattern Pat1 has LLRs corresponding to indices 0 to 3 when the NAND flash memory 30 is at a high temperature. For example, LLR pattern Pat2 has LLRs corresponding to indices 0 to 3 when the NAND flash memory 30 is at a low temperature.

[0174] The correction process for the DLE1 table will be explained using Figure 21. Figure 21 is a diagram illustrating the correction process for the DLE1 table. Figure 21 shows an example where the HB read voltage after successful SB correction is voltage AR(0), and the intersection of the two threshold voltage distributions of the memory cell MC is at voltage AR(-1).

[0175] In Figure 21, indices 0 to 7 in the LLR pattern table correspond to indices 0 to 7 in the DLE1 table, respectively.

[0176] The read information generation circuit 17, similar to the first embodiment, shifts each LLR from index 0 to 5 in the DLE1 table one position to the right, calculates a combined value, and sets the combined value as the LLR at index 7. Then, the read information generation circuit 17 compares the set of three LLRs from index 1 to 3 in the DLE1 table (in the example shown in Figure 21, -5, -3, -1) with the set of three LLRs from index 1 to 3 in the LLR pattern table. As a result of the comparison, the read information generation circuit 17 selects an LLR pattern in which at least a portion of one set of LLRs matches the other set of LLRs. In the examples shown in Figures 20 to 21, the read information generation circuit 17 selects LLR pattern Pat1. The read information generation circuit 17 can, for example, select an LLR pattern with a larger number of matching indices. The example in Figure 21 shows the case where the number of matching indices is 3 (indices 1 to 3). The read information generation circuit 17 sets the LLR (=-9) at index 0 of the selected LLR pattern Pat1 as the LLR at index 0 of the DLE1 table. This completes the correction process for the DLE1 table.

[0177] For example, if the intersection of the two threshold voltage distributions of the memory cell MC is at voltage AR(-2), the read information generation circuit 17, similar to the first embodiment, shifts each LLR from index 0 to 4 in the DLE1 table by 2 to the right, calculates a combined value, and sets the combined value as the LLR at index 7. Subsequently, the read information generation circuit 17 compares the two sets of LLRs at indices 2 and 3 in the DLE1 table with the two sets of LLRs at indices 2 and 3 in the LLR pattern table. As a result of the comparison, the read information generation circuit 17 selects an LLR pattern in which at least a portion of one set of LLRs matches the other set of LLRs. The read information generation circuit 17 can, for example, select an LLR pattern with a larger number of matching indices. The read information generation circuit 17 sets the LLR at index 0 of the selected LLR pattern as the LLR at index 0 in the DLE1 table. The read information generation circuit 17 sets the LLR at index 1 of the selected LLR pattern as the LLR at index 1 in the DLE1 table.

[0178] [3-2] Effects According to the configuration of this embodiment, the same effects as those of the first embodiment are achieved.

[0179] Furthermore, according to this embodiment, it is possible to create a DLE1 table that is closer to the LLR of the threshold voltage distribution of the ECC frame to be corrected for SB.

[0180] [4] Fourth Embodiment A fourth embodiment will now be described. In the memory system 1 according to this embodiment, the DLE1 table correction processing by the read information generation circuit 17 differs from that of the first embodiment. The flowchart showing the read operation of the memory controller 10 is the same as in the first embodiment. The following will focus on the differences from the first embodiment.

[0181] [4-1] Processing of the read information generation circuit 17 (DLE1 table correction process) The lead information generation circuit 17 corrects the DLE1 table using LLR calculated based on the ratio of the sum of LLR on the high-voltage side of the HB lead voltage to the sum of LLR on the low-voltage side of the HB lead voltage.

[0182] The correction process for the DLE1 table will be explained using Figure 22. Figure 22 is a diagram illustrating the correction process for the DLE1 table. Figure 22 shows an example where the HB read voltage after successful SB correction is voltage AR(0), and the intersection of the two threshold voltage distributions of the memory cell MC is at voltage AR(-1).

[0183] The lead information generation circuit 17, similar to the first embodiment, shifts each LLR from index 0 to 5 in the DLE1 table one step to the right, calculates a combined value, and sets the combined value as the LLR for index 7. Subsequently, the lead information generation circuit 17 calculates the LLR for blank indices where an LLR has not been set, based on the ratio of the sum of the LLRs on the high-voltage side of the HB lead voltage to the sum of the LLRs on the low-voltage side of the HB lead voltage. Specifically, the LLR is calculated using the following formula (3). LLR1 =LLR8×{-1×(LLR2+LLR3+LLR4) / (LLR5+LLR6+LLR7)} (3) However, LLR1 is the LLR corresponding to index 0. LLR2 to LLR8 are the absolute values ​​of the LLRs corresponding to indices 1 to 7, respectively. The calculated LLRs are, for example, limited to integers with an absolute value of 9 or less.

[0184] The read information generation circuit 17 sets the value calculated by the above formula (3) (=-9) as the LLR for index 0 in the DLE1 table. This completes the correction process for the DLE1 table.

[0185] For example, if the intersection of the two threshold voltage distributions of the memory cell MC is at voltage AR(-2), the read information generation circuit 17, similar to the first embodiment, shifts each LLR from index 0 to 4 in the DLE1 table by 2 to the right, calculates a combined value, and sets the combined value as the LLR for index 7. Subsequently, the read information generation circuit 17 calculates the LLR for the blank index where an LLR has not been set, based on the ratio of the sum of the LLRs on the high-voltage side of the HB read voltage to the sum of the LLRs on the low-voltage side of the HB read voltage. Specifically, the LLR is calculated using the following formula (4). LLR2 =LLR7×{-1×(LLR3+LLR4) / (LLR5+LLR6)} (4) However, LLR2 is the LLR corresponding to index 1. Also, LLR3 to LLR7 are the absolute values ​​of the LLRs corresponding to indices 2 to 6, respectively. The calculated LLRs are, for example, limited to integers with an absolute value of 9 or less.

[0186] The read information generation circuit 17 uses the value calculated by formula (4) above as the LLR for index 1 of the DLE1 table. The read information generation circuit 17 uses the value calculated by formula (3) above as the LLR for index 0 of the DLE1 table.

[0187] [4-2] Effects According to the configuration of this embodiment, the same effects as those of the first embodiment are achieved.

[0188] Furthermore, according to this embodiment, it is possible to create a DLE1 table that is closer to the LLR of the threshold voltage distribution of the ECC frame to be corrected for SB.

[0189] [5] Fifth embodiment A fifth embodiment will now be described. In the memory system 1 according to this embodiment, the read operation by the memory controller 10 differs from that of the second embodiment. The following will focus on the differences from the second embodiment.

[0190] [5-1] Read operation The read operation will be explained using Figure 23. Figure 23 is a flowchart of the read operation of the memory controller 10 included in the memory system 1 according to this embodiment. In this embodiment, the process of step S23 in Figure 19 of the second embodiment is replaced by the processes of steps S40 to S46 in Figure 23. The processes of steps S10 to S22 and steps S30 to S34 are the same as in the second embodiment. The following explanation will focus on the operations of S40 to S46.

[0191] In Figure 23, if the generated shift value Vst is not the same as the shift value stored in RAM 16 (S22_No), and if the LLR is symmetrical in at least a part of the DLE1 table with respect to the position where the sign of the LLR in the DLE1 table is reversed (S40_Yes), the read information generation circuit 17 performs the DLE1 table correction processing of the first embodiment (S43). Figure 24 is a diagram illustrating the symmetry of the LLR in the DLE1 table. In the example in Figure 24, the absolute values ​​of the LLR are equal at index 2 and index 3, and the signs of the LLR are reversed. That is, the LLR at index 2 and the LLR at index 3 are symmetrical. The absolute values ​​of the LLR are equal at index 1 and index 4, and the signs of the LLR are reversed. That is, the LLR at index 1 and the LLR at index 4 are symmetrical.

[0192] Returning to Figure 23, if the LLR is not symmetrical across the entire DLE1 table (S40_No), or if at least a portion of the DLE1 table and the LLR pattern match (S41_Yes), the read information generation circuit 17 performs the DLE1 table correction processing according to the third embodiment (S44).

[0193] If the DLE1 table and the LLR pattern do not match completely (S41_No), or if at least a part of the DLE2 table and the DLE1 table match (S42_Yes), the read information generation circuit 17 performs the first correction process of the second embodiment (S45).

[0194] If the DLE2 table and the DLE1 table do not match completely (S42_No), the read information generation circuit 17 performs the DLE1 table correction process according to the fourth embodiment (S46).

[0195] [5-2] Effects According to the configuration of this embodiment, the same effects as those of the first embodiment are achieved.

[0196] Furthermore, according to this embodiment, an optimal DLE1 table can be used according to the shape of the threshold voltage distribution.

[0197] [6] Variations etc. As described above, the memory system according to the embodiment includes a semiconductor memory device (30) including a plurality of memory cells (cell unit CU) connected to a word line, each configured to non-volatilely store data according to a threshold voltage, and a controller (10) configured to perform error correction (21) based on hard bit data and soft bit data acquired from the plurality of memory cells, generate a first table (DLE1 Table) based on the data corrected by error correction (21), acquire the voltage difference between a first voltage (HB read voltage) and a second voltage (Vtr) applied to the word line when the corrected data is acquired, and correct the first table based on the voltage difference.

[0198] It should be noted that the embodiments are not limited to the forms described above, and various modifications are possible.

[0199] Furthermore, the flowchart described in the above embodiment allows for the order of processing to be changed as much as possible. For example, the order of the decision processes in steps S40, S41, and S42 is not limited to the order shown in the flowchart of Figure 23. Also, in the flowchart of Figure 23, steps S40 and S43 may be omitted. Steps S41 and S44 may be omitted. Steps S42 and S45 may be omitted. Step S46 may be omitted.

[0200] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0201] 1...Memory system, 2...Host device, 10...Memory controller, 11...Host interface circuit, 12...Processor, 13...Buffer memory, 14...ECC circuit, 15...ROM, 16...RAM, 17...Read information generation circuit, 18...NAND interface circuit, 19...Encoding circuit, 20...Hard decision decoding circuit, 21...Soft decision decoding circuit, 22...LLR conversion circuit, 23...Channel matrix generation circuit, 24...Memory, 25...DLE2 table generation circuit, 26...Channel matrix estimation circuit, 30...NAND flash memory, 31...Memory cell array, 32...Input / output circuit, 33...Logic control circuit, 34...Ready / busy control circuit, 35...Register, 35A...Command register, 35B...Address register, 35C...Status register, 36...Programmable logic controller, 37...Driver module, 38...Raw decoder module, 39...Sense amplifier module

Claims

1. A semiconductor memory device comprising multiple memory cells connected to a word line, each configured to non-volatilely store data according to a threshold voltage, A controller electrically connected to the aforementioned semiconductor memory device, Equipped with, The aforementioned controller, Error correction is performed based on the hard bit data and soft bit data obtained from the aforementioned plurality of memory cells. A first table is generated based on the data corrected by the error correction, and a first voltage is applied to the word line when the corrected data is acquired. A second voltage is calculated such that the number of error bits in the data obtained from the plurality of memory cells when the first voltage is applied to the word line is less than the number of error bits in the data obtained from the plurality of memory cells when the first voltage is applied to the word line. The voltage difference between the first voltage and the second voltage is obtained, The first table is corrected based on the voltage difference. It is configured in such a way, The first table is a table showing the relationship between the voltage range to which the threshold voltage of each of the plurality of memory cells belongs and the likelihood of the data stored in each of the plurality of memory cells. Memory system.

2. The aforementioned controller further, Among the plurality of memory cells, the first number of the plurality of first memory cells whose threshold voltage is included in the first voltage range and which store the first value in the corrected data, The second voltage is calculated based at least on a second number of the plurality of second memory cells, the threshold voltage of which falls within the first voltage range and which store a second value different from the first value in the corrected data. The memory system according to claim 1.

3. The aforementioned controller, Among the plurality of memory cells, the third number of plurality of third memory cells whose threshold voltage is included in a second voltage range different from the first voltage range and which stored the first value in the corrected data, The configuration is configured to calculate the second voltage based on the number of fourth memory cells among the plurality of memory cells, the number of which the threshold voltage falls within the second voltage range and which store the second value in the corrected data, and the number of fourth memory cells among the plurality of memory cells. The memory system according to claim 2.

4. The aforementioned controller, When any voltage in the first voltage range is smaller than any voltage in the second voltage range, the second voltage is calculated from the voltage range between the first voltage range and the second voltage range, depending on whether the first number is greater than the second number and the third number is smaller than the fourth number. The memory system according to claim 3.

5. The first table above is, It is configured to store a first set value corresponding to the first voltage range and a second set value corresponding to the second voltage range. The aforementioned controller, If the first voltage is greater than the second voltage, the third value that was stored as the first setting value in the first table before correction is stored as the second setting value in the first table after correction. The memory system according to claim 4.

6. The first table above is, It is configured to store a first set value corresponding to the first voltage range and a second set value corresponding to the second voltage range. The aforementioned controller, If the first voltage is smaller than the second voltage, the third value that was stored as the second setting value in the first table before correction is configured to be stored as the first setting value in the first table after correction. The memory system according to claim 4.

7. The semiconductor memory device includes a block which contains multiple word lines and is a unit of data erasure operation. The aforementioned controller further, The first voltage is applied to the first word line among the plurality of word lines included in the block, the first table is generated based on the corrected data obtained from the plurality of memory cells connected to the first word line, and the first table is corrected based on the voltage difference. The system is configured to apply the second voltage to the second word line among the plurality of word lines included in the block, and to perform error correction on the data obtained from the plurality of memory cells connected to the second word line using the corrected first table. The memory system according to claim 1.

8. The first table is a table that stores the log-likelihood ratio (LLR) that represents the likelihood, The first table before correction includes at least a first LLR corresponding to a first voltage range, a second LLR corresponding to a second voltage range, and a third LLR corresponding to a third voltage range. In correcting the first table, the controller At a minimum, an integrated value is calculated based on the following: a first number of multiple first memory cells in which the threshold voltage falls within the first voltage range and stores the first value in the corrected data; a second number of multiple second memory cells in which the threshold voltage falls within the first voltage range and stores a second value different from the first value in the corrected data; a third number of multiple third memory cells in which the threshold voltage falls within the second voltage range and stores the first value in the corrected data; and a fourth number of multiple fourth memory cells in which the threshold voltage falls within the second voltage range and stores the second value in the corrected data; and the integrated value is set as the fourth LLR corresponding to the first voltage range. The value obtained by inverting the sign of the aforementioned integrated value is configured to be the fifth LLR corresponding to the third voltage range. The memory system according to claim 1.

9. The third voltage range is a voltage range in which the threshold voltage is lower than that of the first voltage range and the second voltage range. The first voltage range is a voltage range in which the threshold voltage is higher than the second voltage range. The memory system according to claim 8.

10. The controller is further configured to generate a second table based on the data for which error correction failed. The second table is a table showing the relationship between the voltage range to which the threshold voltage of each of the plurality of memory cells belongs and the likelihood of the data stored in each of the plurality of memory cells. Each of the first and second tables is a table that stores the log-likelihood ratio (LLR) that represents the likelihood, The first table before correction includes at least a first LLR corresponding to a first voltage range, a second LLR corresponding to a second voltage range, and a third LLR corresponding to a third voltage range. The second table includes at least a fourth LLR corresponding to the third voltage range, In correcting the first table, the controller At a minimum, an integrated value is calculated based on the following: a first number of multiple first memory cells that store the first value in the corrected data and whose threshold voltage is included in the first voltage range; a second number of multiple second memory cells that store a second value different from the first value in the corrected data and whose threshold voltage is included in the first voltage range; a third number of multiple third memory cells that store the first value in the corrected data and whose threshold voltage is included in the second voltage range; and a fourth number of multiple fourth memory cells that store the second value in the corrected data and whose threshold voltage is included in the second voltage range, and the integrated value is set as the fifth LLR corresponding to the first voltage range. The fourth LLR is configured to be a sixth LLR corresponding to the third voltage range. The memory system according to claim 1.

11. The third voltage range is a voltage range in which the threshold voltage is lower than that of the first voltage range and the second voltage range. The first voltage range is a voltage range in which the threshold voltage is higher than the second voltage range. The memory system according to claim 10.

12. The controller is further configured to manage a second table, The second table is a table showing the relationship between the voltage range to which the threshold voltage of each of the plurality of memory cells belongs and the likelihood of the data stored in each of the plurality of memory cells. Each of the first and second tables is a table that stores the log-likelihood ratio (LLR) that represents the likelihood, The first table before correction includes at least a first LLR corresponding to a first voltage range, a second LLR corresponding to a second voltage range, a third LLR corresponding to a third voltage range, a fourth LLR corresponding to a fourth voltage range, a fifth LLR corresponding to a fifth voltage range, and a sixth LLR corresponding to a sixth voltage range. The second table includes a plurality of patterns, each of which includes at least a seventh LLR corresponding to the third voltage range, an eighth LLR corresponding to the fourth voltage range, a ninth LLR corresponding to the fifth voltage range, and a tenth LLR corresponding to the sixth voltage range. In correcting the first table, the controller At a minimum, an integrated value is calculated based on the following: a first number of multiple first memory cells in which the threshold voltage falls within the first voltage range and stores the first value in the corrected data; a second number of multiple second memory cells in which the threshold voltage falls within the first voltage range and stores a second value different from the first value in the corrected data; a third number of multiple third memory cells in which the threshold voltage falls within the second voltage range and stores the first value in the corrected data; and a fourth number of multiple fourth memory cells in which the threshold voltage falls within the second voltage range and stores the second value in the corrected data. The integrated value is then set as the 11th LLR corresponding to the first voltage range. Select the pattern such that at least a portion of the first set of LLR corresponding to each of the fourth to sixth voltage ranges in the first table and the second set of LLR corresponding to each of the fourth to sixth voltage ranges in the second table coincide. The 7th LLR of the selected pattern is configured to be the 12th LLR corresponding to the 3rd voltage range. The memory system according to claim 1.

13. The third voltage range is a voltage range in which the threshold voltage is lower than the first voltage range, the second voltage range, the fourth voltage range, the fifth voltage range, and the sixth voltage range. The first voltage range is a voltage range in which the threshold voltage is higher than the second voltage range, the fourth voltage range, the fifth voltage range, and the sixth voltage range. The memory system according to claim 12.

14. The first table is a table that stores the log-likelihood ratio (LLR) that represents the likelihood, The first table before correction includes at least a first LLR corresponding to a first voltage range, a second LLR corresponding to a second voltage range, a third LLR corresponding to a third voltage range, a fourth LLR corresponding to a fourth voltage range, a fifth LLR corresponding to a fifth voltage range, a sixth LLR corresponding to a sixth voltage range, a seventh LLR corresponding to a seventh voltage range, and an eighth LLR corresponding to an eighth voltage range. In correcting the first table, the controller At a minimum, an integrated value is calculated based on the following: a first number of multiple first memory cells that store the first value in the corrected data and whose threshold voltage is included in the first voltage range; a second number of multiple second memory cells that store a second value different from the first value in the corrected data and whose threshold voltage is included in the first voltage range; a third number of multiple third memory cells that store the first value in the corrected data and whose threshold voltage is included in the second voltage range; and a fourth number of multiple fourth memory cells that store the second value in the corrected data and whose threshold voltage is included in the second voltage range, and the integrated value is set as the 9th LLR corresponding to the first voltage range. The value calculated based on the ratio of the sum of the 4th LLR, the 5th LLR, and the 6th LLR to the sum of the 7th LLR, the 8th LLR, and the 2nd LLR is configured to be the 10th LLR corresponding to the 3rd voltage range. The memory system according to claim 1.

15. The value calculated above is determined based on the ratio and the 9LLR. The memory system according to claim 14.

16. The third voltage range is a voltage range in which the threshold voltage is lower than the first voltage range, the second voltage range, the fourth voltage range, the fifth voltage range, the sixth voltage range, the seventh voltage range, and the eighth voltage range. The first voltage range is a voltage range in which the threshold voltage is higher than the second voltage range, the fourth voltage range, the fifth voltage range, the sixth voltage range, the seventh voltage range, and the eighth voltage range. The memory system according to claim 14 or 15.

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