Memory system

Abstract

To provide a memory system to improve reliability.SOLUTION: A memory system of one embodiment includes: a non-volatile memory including a plurality of blocks each including a plurality of memory cell transistors; and a memory controller. The memory controller is configured to execute second processing for a first block when continuously executing first processing a number of times equal to or greater than a first threshold value. A polarity of a voltage applied between a gate and a channel of each of the plurality of memory cell transistors in the first block in the second processing is different from a polarity of a voltage applied between the gate and the channel of each of the plurality of memory cell transistors in the first block in the first processing.SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] The embodiment relates to a memory system.

Background Art

[0002] A memory system including a NAND flash memory as a non-volatile memory and a memory controller for controlling the non-volatile memory is known. The non-volatile memory includes a plurality of memory cells each constituted by a FeFET (Ferroelectric Field Effect Transistor).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] Improve reliability.

Means for Solving the Problems

[0005] The memory system of the embodiment includes a non-volatile memory including a plurality of blocks each including a plurality of memory cell transistors, and a memory controller. When the first process is continuously executed on the first block for a number of times equal to or greater than a first threshold value, the memory controller is configured to execute a second process on the first block. The polarity of the voltage applied between the gate and the channel of each of the plurality of memory cell transistors in the first block in the second process is different from the polarity of the voltage applied between the gate and the channel of each of the plurality of memory cell transistors in the first block in the first process.

Brief Description of the Drawings

[0006] [Figure 1] A block diagram showing an example of the configuration of an information processing system according to the first embodiment. [Figure 2] A block diagram showing an example of the configuration of a non-volatile memory according to the first embodiment. [Figure 3] A circuit diagram showing an example of the configuration of a memory cell array according to the first embodiment. [Figure 4] A figure showing an example of the threshold voltage distribution of a memory cell array according to the first embodiment. [Figure 5] A plan view showing an example of a planar layout of a memory cell array according to the first embodiment. [Figure 6] A plan view showing an example of a planar layout in the memory area of ​​a memory cell array according to the first embodiment. [Figure 7] A cross-sectional view along line VII-VII in Figure 6, showing an example of the cross-sectional structure in the memory region of the memory cell array according to the first embodiment. [Figure 8] A cross-sectional view along line VIII-VIII in Figure 7, showing an example of the cross-sectional structure of a memory pillar according to the first embodiment. [Figure 9] A diagram showing an example of the voltage applied to the memory cell array during a read operation in the memory system according to the first embodiment. [Figure 10] This figure shows a first example of the voltage applied to the memory cell array during detrapping in the memory system according to the first embodiment. [Figure 11] This figure shows a second example of the voltage applied to the memory cell array during the detrapping process in the memory system according to the first embodiment. [Figure 12] A flowchart showing an example of a series of processes, including read and detrapping, in the memory system according to the first embodiment. [Figure 13] A block diagram showing an example of the configuration of an information processing system according to the second embodiment. [Figure 14] A diagram showing an example of the data structure of block management information according to the second embodiment. [Figure 15]A diagram showing an example of the voltage applied to a memory cell array in the writing process in the memory system according to the second embodiment. [Figure 16] A diagram showing a first example of the voltage applied to a memory cell array in the erasing process in the memory system according to the second embodiment. [Figure 17] A diagram showing a second example of the voltage applied to a memory cell array in the erasing process in the memory system according to the second embodiment. [Figure 18] A diagram showing an example of the order of the rewriting process in the memory system according to the second embodiment. [Figure 19] A flowchart showing an example of a process for determining whether or not to execute the compaction process in the memory system according to the second embodiment. [Figure 20] A diagram showing an example of the order of the rewriting process before the execution of the compaction process in the memory system according to the second embodiment. [Figure 21] A diagram showing an example of the order of the rewriting process after the execution of the compaction process in the memory system according to the second embodiment.

Embodiments for Carrying Out the Invention

[0007] Hereinafter, embodiments will be described with reference to the drawings. In the following description, components having the same function and configuration are given common reference numerals. When distinguishing between a plurality of components having the same reference numeral, a suffix is added to the common reference numeral for distinction. When no distinction is particularly required for a plurality of components, only the common reference numeral is given to the plurality of components, and no suffix is added.

[0008] Hereinafter, negative values are distinguished from positive values by attaching "-". When no "-" is attached to the sign indicating a value, unless otherwise specified, the sign is a positive value.

[0009] 1. First Embodiment 1.1 Configuration 1.1.1 Information Processing System The configuration of the information processing system according to the first embodiment will be described.

[0010] FIG. 1 is a block diagram showing an example of the configuration of an information processing system according to the first embodiment. As shown in FIG. 1, the information processing system 1 includes a host 2 and a memory system 3.

[0011] The host 2 is a data processing device that processes data using the memory system 3. The host 2 is, for example, a personal computer or a server in a data center.

[0012] The memory system 3 is a storage device configured to be connected to the host 2. The memory system 3 is, for example,

[0016] , , a memory card such as an SD card, UFS (Universal Flash Storage), or SSD (Solid State Drive). The memory system 3 executes data writing, reading, and erasing processes in response to requests from the host 2. The memory system 3 may execute writing, reading, and erasing processes as internal processes. Examples of the writing, reading, and erasing processes executed as internal processes include, for example, compression processing.

[0013] 1.1.2 Memory System The internal configuration of the memory system according to the first embodiment will be described.

[0014] The memory system 3 includes a memory controller 10, a non-volatile memory 20, and a volatile memory 30.

[0015] The memory controller 10 is composed of an integrated circuit such as, for example, a SoC (System-on-a-Chip). The memory controller 10 controls the non-volatile memory 20 based on requests from the host 2.

[0016] Specifically, for example, the memory controller 10 writes data to the non-volatile memory 20 based on a write request from the host 2. The memory controller 10 also reads data from the non-volatile memory 20 based on a read request from the host 2. Then, the memory controller 10 sends data based on the read data to the host 2.

[0017] The non-volatile memory 20 is, for example, NAND flash memory. The non-volatile memory 20 stores data in a non-volatile manner.

[0018] The volatile memory 30 is, for example, DRAM (Dynamic Random Access Memory). The volatile memory 30 stores, for example, information about the read voltage used when reading data from the non-volatile memory 20.

[0019] 1.1.3 Memory Controller Next, referring to Figure 1, the internal configuration of the memory controller 10 will be described. The memory controller 10 includes a control circuit 11, a non-volatile memory interface (NVMI / F) 12, a host interface (host I / F) 13, a volatile memory interface (VMI / F) 14, and a counter 15. The functions of the memory controller 10 described below can be implemented using dedicated hardware, a processor that executes programs, or a combination of these.

[0020] The control circuit 11 is a circuit that controls the entire memory controller 10. The control circuit 11 includes, for example, a processor such as a CPU (Central Processing Unit), ROM (Read Only Memory), and RAM (Random Access Memory).

[0021] The non-volatile memory interface 12 is a hardware interface that manages communication between the memory controller 10 and the non-volatile memory 20. The non-volatile memory interface 12 is connected to the non-volatile memory 20 via a memory bus. The memory bus conforms to, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0022] The host interface 13 is a hardware interface that manages communication between the memory controller 10 and the host 2. The host interface 13 is connected to the host 2 via the host bus. The host bus is, for example, SD TM Interfaces include SAS (Serial Attached SCSI (Small Computer System Interface)), SATA (Serial ATA (Advanced Technology Attachment)), or PCIe. TM It conforms to the Peripheral Component Interconnect express standard.

[0023] The volatile memory interface 14 is a hardware interface that manages communication between the memory controller 10 and the volatile memory 30. The bus connecting the volatile memory 30 and the memory controller 10 conforms to, for example, the DRAM interface standard.

[0024] Counter 15 is, for example, a memory that stores the count value. Counter 15 increments the count value based on instructions from control circuit 11. Counter 15 resets the count value to 0 based on instructions from control circuit 11.

[0025] 1.1.4 Non-volatile memory Next, the internal configuration of the memory device according to the embodiment will be described. Figure 2 is a block diagram showing an example of the configuration of a non-volatile memory according to the first embodiment.

[0026] The non-volatile memory 20 includes an input / output circuit 21, a logic control circuit 22, a register 23, a sequencer 24, a voltage generation circuit 25, a driver set 26, a memory cell array 27, a low decoder module 28, and a sense amplifier module 29.

[0027] The input / output circuit 21 and the logic control circuit 22 transmit and receive various signals to and from the memory controller 10 via the memory bus BUS. The signals transmitted and received by the input / output circuit 21 include, for example, the signal DQ. <0> DQ <1> , ..., and DQ <7> (Signal DQ<7:0>), as well as DQS and DQSn. Signals transmitted and received by the logic control circuit 22 include, for example, signals CEn, CLE, ALE, WEn, RE and REn, WPn, and RBn. In this specification, the letter n at the end of a signal name means that the signal is asserted when it is at an "L (Low)" level.

[0028] Signal DQ<7:0> is an 8-bit signal. Signal DQ<7:0> is the entity of data DAT transmitted and received between the non-volatile memory 20 and the memory controller 10. Signal DQ<7:0> transmitted from the memory controller 10 to the non-volatile memory 20 includes, for example, write data DAT, address ADD, and command CMD. Signal DQ<7:0> transmitted from the non-volatile memory 20 to the memory controller 10 includes, for example, read data DAT.

[0029] Signals DQS and DQSn are strobe signals. Signal DQSn is the inverse signal of signal DQS.

[0030] The signal CEn is used to enable the non-volatile memory 20.

[0031] Signals CLE and ALE are signals that notify the non-volatile memory 20 that signal DQ<7:0> is command CMD and address ADD, respectively.

[0032] The signal WEn is used to input the signal DQ<7:0> into the non-volatile memory 20.

[0033] Signals RE and REn are signals used to read signal DQ<7:0> from the non-volatile memory 20.

[0034] The signal WPn is a signal used to instruct the non-volatile memory 20 to prohibit write and erase operations.

[0035] Signal RBn indicates whether the non-volatile memory 20 is in a ready state or a busy state. The ready state means the non-volatile memory 20 is able to receive instructions from the memory controller 10. The busy state means the non-volatile memory 20 is unable to receive instructions from the memory controller 10. A "L" level signal RBn indicates a busy state.

[0036] The input / output circuit 21 transmits the address ADD and command CMD within the signal DQ<7:0>, as well as the write data DAT, to the register 23 and the sense amplifier module 29, respectively. The input / output circuit 21 receives the read data DAT within the signal DQ<7:0> from the sense amplifier module 29.

[0037] The logic control circuit 22 receives signals CEn, CLE, ALE, WEn, RE, REn, and WPn from the memory controller 10. The logic control circuit 22 transmits signal RBn to the memory controller 10.

[0038] Register 23 stores the address ADD and the command CMD. The address ADD includes, for example, a column address, a block address, and a page address.

[0039] The sequencer 24 controls the operation of the entire non-volatile memory 20 based on the command CMD stored in register 23.

[0040] The voltage generation circuit 25 generates voltages used in write operations, read operations, erase operations, etc.

[0041] The driver set 26 supplies the voltage generated by the voltage generation circuit 25 to the memory cell array 27, the row decoder module 28, and the sense amplifier module 29.

[0042] The memory cell array 27 includes multiple block BLKs, multiple bit lines, and multiple word lines. The example in Figure 2 shows a memory cell array 27 containing n block BLK0, ..., and BLK(n-1) (where n is an integer greater than or equal to 2). A block BLK is, for example, the erasure unit of data DAT in an erasure process. Each block BLK contains multiple memory cells. Each memory cell is associated with a set of bit lines and word lines.

[0043] The row decoder module 28 selects one of blocks BLK0 to BLK(n-1) based on the block address in register 23. The row decoder module 28 further selects a word line in the selected block BLK based on the page address in register 23.

[0044] The sense amplifier module 29 selects a bit line based on the column address in register 23. In the data writing process, the sense amplifier module 29 transfers the data to be written DAT to the memory cell array 27 via the selected bit line. In the data reading process, the sense amplifier module 29 senses the threshold voltage of the memory cell via the selected bit line. Then, the sense amplifier module 29 generates the data to be read DAT based on the sense result.

[0045] 1.1.5 Memory Cell Array Next, the configuration of the memory cell array 27 will be described.

[0046] <Circuit Configuration> Figure 3 is a circuit diagram showing an example of the configuration of a memory cell array according to the first embodiment. Figure 3 shows the configurations of two blocks BLK0 and BLK1. The two blocks BLK0 and BLK1 have equivalent configurations. The (n-2) blocks BLK, which are not shown in Figure 3, also have equivalent configurations to blocks BLK0 and BLK1.

[0047] Each of blocks BLK0 and BLK1 includes, for example, four string units SU0 to SU3. In Figure 3, the configurations of string units SU2 and SU3 of block BLK0, and string units SU1, SU2, and SU3 of block BLK1 are shown in a simplified manner.

[0048] Each string unit SU includes multiple NAND strings NS associated with bit lines BL0, BL1, ..., and BL(m-1), respectively (where m is an integer greater than or equal to 3). The NAND strings NS include, for example, eight memory cell transistors MT0 to MT7, as well as selection transistors ST1 and ST2.

[0049] Each of the memory cell transistors MT0 to MT7 is an FeFET (Ferroelectric Field Effect Transistor). Each of the selection transistors ST1 and ST2 is used to select the string unit SU during various processing steps. Each of the selection transistors ST1 and ST2 may also be an FeFET.

[0050] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. A selection transistor ST1 is connected between one end of the series-connected memory cell transistors MT0 to MT7 and the associated bit line BL. The drain of selection transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source line SL is connected to the source of selection transistor ST2.

[0051] In the same block BLK, each gate of the multiple selection transistors ST1 included in string units SU0 to SU3 is connected to the selection gate lines SGD0 to SGD3, respectively. Each control gate of the multiple memory cell transistors MT0 to MT7 is connected to the word lines WL0 to WL7, respectively. Each gate of the multiple selection transistors ST2 is connected to the selection gate line SGS.

[0052] Bit lines BL0 to BL(m-1) are shared by multiple blocks BLK0 to BLK3. The same bit line BL is connected to the same NAND string NS corresponding to the same column address. Word lines WL0 to WL7 are provided individually for each of blocks BLK0 to BLK3. Source lines SL are shared, for example, by multiple blocks BLK0 to BLK3.

[0053] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string unit SU is referred to, for example, as a cell unit CU. A cell unit CU is, for example, the unit of data writing in a write operation. A cell unit CU may also be, for example, the unit of data erasure in an erase operation. For example, the storage capacity of a cell unit CU containing memory cell transistors MT, each storing 1 bit of data, is defined as "1 page of data". That is, 1 page of data is a data area of ​​1-bit data sequences having a number of columns corresponding to the number of memory cell transistors MT in the cell unit CU. 1 page of data is, for example, the unit of data read in a read operation. A cell unit CU may have a storage capacity of 2 pages of data or more, depending on the number of bit data stored by the memory cell transistors MT.

[0054] The circuit configuration of the block BLK described above is merely an example and is not limited thereto. For example, the number of bit lines BL is not limited to three or more; it may be one or two. The number of block BLKs included in the non-volatile memory 20 can be designed to any number. The number of string units SU included in each block BLK can be designed to any number. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can each be designed to any number.

[0055] <Threshold voltage distribution> The following describes the case where a single memory cell transistor (MT) can store 1 bit of data. The write mode that allows a memory cell transistor (MT) to store 1 bit of data is also called SLC (Single Level Cell) mode.

[0056] FIG. 4 is a schematic diagram showing an example of the threshold voltage distribution of a plurality of memory cell transistors according to the first embodiment. When the memory cell transistor MT stores 1-bit data, the distribution of its threshold voltage is divided into two. These two threshold voltage distributions are called the "Er" state (state) and the "A" state in order from the one with the higher threshold voltage.

[0057] The voltage Vvrf shown in FIG. 4 is used to distinguish between the "Er" state and the "A" state during the read process. The voltage Vread is a voltage that turns on the memory cell transistor MT regardless of whether the threshold voltage distribution is in the "Er" state or the "A" state. The relationship between these voltage values is 0 < Vvrf < VREAD. The voltage Vvrf may be a negative value.

[0058] Among the above-described threshold voltage distributions, the "Er" state corresponds to the erase state of the memory cell transistor MT. The threshold voltage in the "Er" state is greater than or equal to the voltage Vvrf and less than the voltage Vread. The threshold voltage in the "A" state is less than the voltage Vvrf.

[0059] <Planar layout> Hereinafter, an example of the planar layout of the memory cell array according to the first embodiment will be described. In the drawings referred to below, the XY plane corresponds to the surface of the semiconductor substrate used for forming the nonvolatile memory 20. The X direction and the Y direction are directions that intersect within the XY plane. The Z direction is a direction that intersects the XY plane.

[0060] FIG. 5 is a plan view showing an example of the planar layout of the memory cell array according to the first embodiment. In FIG. 5, regions corresponding to four blocks BLK0 to BLK3 are shown.

[0061] Viewed in the Z direction, the memory cell array 27 is divided into, for example, a lead-out region HA1 arranged in the X direction, a memory region MA, and a lead-out region HA2. The memory cell array 27 also includes a plurality of members SLT and SHE.

[0062] Memory area MA is located between extraction areas HA1 and HA2. Memory area MA is an area containing multiple NAND strings NS. Each of extraction areas HA1 and HA2 is an area used for connections between stacked wiring (e.g., word lines WL0 to WL7, and selection gate lines SGD and SGS) and the row decoder module 28.

[0063] Multiple SLT components each extend in the X direction and are aligned in the Y direction. Each SLT component traverses the memory area MA and the lead-out areas HA1 and HA2 in the X direction within the boundary region between adjacent blocks BLK. Each SLT component also has a structure in which, for example, an insulator or plate-shaped contact is embedded. Each SLT component then separates adjacent stacked wiring through itself.

[0064] Multiple members SHE each extend along the X direction and are aligned along the Y direction. In this example, four members SHE are positioned between adjacent members SLT. Each member SHE traverses the memory area MA in the X direction. Both ends of each member SHE are included in the draw-out areas HA1 and HA2, respectively. Each member SHE also has a structure in which an insulator is embedded, for example. Each member SHE then divides adjacent selection gate lines SGD through it.

[0065] In the planar layout of the memory cell array 27 described above, each region demarcated by the member SLT corresponds to one block BLK. Furthermore, each region demarcated by the members SLT and SHE corresponds to one string unit SU. The memory cell array 27 is arranged in a repeating manner in the Y direction, for example, the layout shown in Figure 5.

[0066] Furthermore, the planar layout of the memory cell array 27 according to the first embodiment is not limited to the layout described above. For example, the number of members SHE arranged between adjacent members SLT can be designed to be any number. The number of string units SU formed between adjacent members SLT can be changed based on the number of members SHE arranged between adjacent members SLT.

[0067] Figure 6 is a plan view showing an example of a detailed planar layout in the memory region of a memory cell array according to the first embodiment. Figure 6 shows a region containing one block BLK (i.e., string units SU0 to SU3) and two members SLT flanking the block. As shown in Figure 6, in the memory region MA, the memory cell array 27 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL. Each member SLT also includes a contact LI and a spacer SP.

[0068] Each memory pillar MP functions, for example, as a single NAND string NS. Multiple memory pillar MPs are arranged in a staggered pattern, for example, 19 rows, in the region between two adjacent members SLT. Then, for example, one member SHE overlaps the 5th, 10th, and 15th memory pillar MPs, counting from the top of the paper.

[0069] Multiple bit lines BL each extend in the Y direction and are aligned in the X direction. Each bit line BL is positioned to overlap with at least one memory pillar MP for each string unit SU. The example in Figure 6 shows a case where two bit lines BL are positioned to overlap with one memory pillar MP. One of the multiple bit lines BL overlapping with a memory pillar MP is electrically connected to the corresponding memory pillar MP via a contact CV.

[0070] For example, the contact CV between a memory pillar MP in contact with a component SHE and a bit line BL is omitted. In other words, the contact CV between a memory pillar MP in contact with two different selected gate lines SGD and a bit line BL is omitted. The number and arrangement of memory pillars MP and component SHE between adjacent component SLTs are not limited to the configuration explained with reference to Figure 6 and can be changed as appropriate. The number of bit lines BL overlapping each memory pillar MP can be designed to be any number.

[0071] Contact LI is a conductor extending in the XZ plane. Spacer SP is an insulator located on the side of contact LI. In other words, contact LI is surrounded by spacer SP in a plan view.

[0072] <Cross-sectional structure> Figure 7 is a cross-sectional view along line VII-VII in Figure 6, showing an example of the cross-sectional structure in the memory region of the memory cell array according to the first embodiment. As shown in Figure 7, the memory cell array 27 further includes a semiconductor substrate 50, conductive layers 51-55, and insulating layers 60-65.

[0073] The semiconductor substrate 50 is, for example, a P-type semiconductor. An insulating layer 60 is provided on the upper surface of the semiconductor substrate 50. The semiconductor substrate 50 and the insulating layer 60 include circuits not shown. The circuits included in the semiconductor substrate 50 and the insulating layer 60 correspond to a low decoder module 28, a sense amplifier module 29, etc. A conductive layer 51 is provided on the upper surface of the insulating layer 60.

[0074] The conductive layer 51 is, for example, a plate-shaped conductor extending along the XY plane. The conductive layer 51 is used as the source wire SL. The conductive layer 51 contains, for example, phosphorus-doped silicon.

[0075] An insulating layer 61 and a conductive layer 52 are stacked in this order on the upper surface of the conductive layer 51. The conductive layer 52 is formed in a plate shape that extends along the XY plane, for example. The conductive layer 52 is used as a selectable gate wire (SGS). The conductive layer 52 contains, for example, tungsten. The insulating layer 61 contains, for example, silicon oxide.

[0076] On the upper surface of the conductive layer 52, an insulating layer 62 and a conductive layer 53 are alternately stacked in this order. The conductive layer 53 is formed in a plate shape that extends along the XY plane, for example. The stacked conductive layers 53 are used as word lines WL0 to WL7, respectively, in order from the semiconductor substrate 50 side. The conductive layer 53 contains, for example, tungsten. The insulating layer 62 contains, for example, silicon oxide.

[0077] An insulating layer 63 and a conductive layer 54 are stacked in this order on the upper surface of the top conductive layer 53. The conductive layer 54 is formed in a plate shape that extends along the XY plane, for example. The conductive layer 54 is used as a selectable gate wire (SGD). The conductive layer 54 contains, for example, tungsten. The insulating layer 63 contains, for example, silicon oxide.

[0078] An insulating layer 64 and a conductive layer 55 are stacked in this order on the upper surface of the conductive layer 54. The conductive layer 55 is formed in a line shape extending in the Y direction, for example, and is used as a bit line BL. In other words, in a region not shown, multiple conductive layers 55 are aligned in the X direction. The conductive layer 55 contains, for example, copper. The insulating layer 64 contains, for example, silicon oxide.

[0079] An insulating layer 65 is provided on the upper surface of the conductive layer 55. The insulating layer 65 contains, for example, silicon oxide.

[0080] Each memory pillar MP includes, for example, a core film 70, a semiconductor film 71, and a multilayer film 72. The core film 70 extends in the Z direction. For example, the upper end of the core film 70 is located above the conductive layer 54, and the lower end of the core film 70 is located in the same layer as the conductive layer 51. The semiconductor film 71 surrounds the core film 70. The bottom of the semiconductor film 71 is in contact with the conductive layer 51. The multilayer film 72 covers the sides and bottom of the semiconductor film 71, except for the portion where the semiconductor film 71 and the conductive layer 51 are in contact. The core film 70 includes, for example, an insulator such as silicon oxide. The semiconductor film 71 includes, for example, silicon.

[0081] The portion where the memory pillar MP and the conductive layer 52 intersect functions as a selection transistor ST2. The portion where the memory pillar MP and one conductive layer 53 intersect functions as one memory cell transistor MT. The portion where the memory pillar MP and the conductive layer 54 intersect functions as a selection transistor ST1.

[0082] A columnar contact CV is provided on the upper surface of the semiconductor film 71 within the memory pillar MP. In the illustrated region, one contact CV is shown corresponding to one of the two memory pillar MPs in each cross-sectional region separated by members SLT and SHE. In the memory region MA, a corresponding contact CV is connected in an area not shown to the memory pillar MP that does not overlap with member SHE and to which no contact CV is connected.

[0083] A single conductive layer 55, i.e., a single bit line BL, is in contact with the upper surface of contact CV. Each conductive layer 55 is in contact with one contact CV in each of the spaces separated by members SLT and SHE. In other words, each conductive layer 55 is electrically connected to a memory pillar MP provided between adjacent members SLT and SHE, and to a memory pillar MP provided between two adjacent members SHE.

[0084] The component SLT separates the conductive layers 52, 53, and 54. The contact LI within the component SLT is provided along the spacer SP. The upper end of the contact LI is located in the layer between conductive layer 54 and conductive layer 55. The lower end of the contact LI is in contact with conductive layer 51. The spacer SP is provided between the contact LI and the conductive layers 52, 53, and 54. The contact LI and the conductive layers 52, 53, and 54 are separated and insulated by the spacer SP.

[0085] Component SHE separates the conductive layer 54. The upper end of component SHE is located in the layer between conductive layer 54 and conductive layer 55. The lower end of component SHE is located in the layer between the uppermost conductive layer 53 and conductive layer 54. Component SHE contains an insulator, such as silicon oxide. The upper end of component SHE and the upper end of component SLT may or may not be aligned. Similarly, the upper end of component SHE and the upper end of memory pillar MP may or may not be aligned. Furthermore, each of the conductive layers 52, 53, and 54 can take on any number. For example, if multiple conductive layers 54 are provided, the lower end of component SHE is located between the uppermost conductive layer 53 and the lowest conductive layer 54. That is, the depth of the lower end of component SHE increases in proportion to the number of conductive layers 54.

[0086] Figure 8 is a cross-sectional view along line VIII-VIII in Figure 7, showing an example of the cross-sectional structure of a memory pillar according to the first embodiment. More specifically, Figure 8 shows the cross-sectional structure of the memory pillar MP in a layer parallel to the XY plane and including a conductive layer 53. As shown in Figure 8, the laminated film 72 includes, for example, an insulating film 73 and a ferroelectric film 74.

[0087] In a cross-section including the conductive layer 53, the core film 70 is provided, for example, in the central part of the memory pillar MP. The semiconductor film 71 surrounds the sides of the core film 70. The insulating film 73 surrounds the sides of the semiconductor film 71. The ferroelectric film 74 surrounds the sides of the insulating film 73. The conductive layer 53 surrounds the sides of the ferroelectric film 74.

[0088] The insulating film 73 includes, for example, silicon oxide. The ferroelectric film 74 is, for example, an oxide containing hafnium (Hf) or zirconium (Zr) as the main component element. The ferroelectric film 74 has, for example, an orthorhombic crystal structure.

[0089] The ferroelectric film 74 functions as a block insulating film and also has the ability to reverse the direction of its electric polarization depending on the magnitude of the voltage applied to the conductive layer 53. When the direction of the electric polarization of the ferroelectric film 74 is reversed, the threshold voltage of the memory cell transistor MT changes. As a result, the memory cell transistor MT can store either data "1" or data "0". Therefore, the memory cell transistor MT can function as an FeFET.

[0090] The semiconductor film 71 is used as the channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. With this configuration, each memory pillar MP can function as a single NAND string NS.

[0091] 1.2 Operation Next, the operation of the memory system according to the first embodiment will be described.

[0092] 1.2.1 Read operation Figure 9 shows an example of the voltage applied to the memory cell array during a read operation in the memory system according to the first embodiment. In Figure 9, one NAND string NS of each string unit SU0 to SU3 is shown among the block BLK to be read. Figure 9 shows the voltages applied to the bit line BL, selection gate lines SGD0 to SGD3 and SGS, and word lines WL0 to WL7 connected to the block BLK to be read during the read operation.

[0093] Furthermore, Figure 9 shows the voltage applied when one page of data, which is the memory area of ​​cell unit CU connected to word line WL3 of string unit SU0, is to be read. In other words, in the following explanation, selected word line WL refers to word line WL3. Unselected word lines WL refer to word lines WL0 to WL2 and WL4 to WL7. Selected string unit SU refers to string unit SU0. Unselected string units SU refer to string units SU1 to SU3. Selected memory cell MT refers to the memory cell transistor MT included in the cell unit CU connected to word line WL3 within the selected string unit SU. Unselected memory cell MT refers to all memory cell transistors MT except for the selected memory cell MT.

[0094] The raw decoder module 28 applies a voltage Vsg to the selected gate lines SGD0 and SGS. The voltage Vsg is the voltage that turns on the selected transistors ST1 and ST2. The raw decoder module 28 applies a voltage VSS to the selected gate lines SGD1 to SGD3. The voltage VSS is, for example, 0V. The raw decoder module 28 applies a voltage Vread to the unselected word line WL. The voltage Vread is, for example, 3V. The raw decoder module 28 applies a voltage Vvrf to the selected word line WL.

[0095] As a result, all NAND strings NS of the non-selected string unit SU are electrically isolated from the bit line BL. On the other hand, all NAND strings NS of the selected string unit SU are electrically connected to the bit line BL.

[0096] The sense amplifier module 29 applies a voltage VBL to the bit line BL. As a result, when the selected memory cell MT is ON, a significant read current flows through the NAND string NS containing the selected memory cell MT. When the selected memory cell MT is OFF, no significant read current flows through the NAND string NS containing the selected memory cell MT. The sense amplifier module 29 senses the threshold voltage of the selected memory cell MT based on the magnitude of the read current. Then, based on the sense result, the sense amplifier module 29 determines the data to be stored in the selected memory cell MT.

[0097] In the read operation described above, regardless of whether it is a selected string unit SU or a non-selected string unit SU, the voltage Vread is applied to the memory cell transistor MT connected to the non-selected word line WL. As a result, in the non-selected memory cell transistor MT connected to the non-selected word line WL, charge may be accumulated at the interface between the insulating film 73 and the ferroelectric film 74. When charge accumulates at the interface between the insulating film 73 and the ferroelectric film 74, an effect equivalent to electrode reversal for an erased memory cell transistor MT may occur. Therefore, in the read operation, an unintended threshold voltage drop, i.e., unintended data writing, may occur in the memory cell transistor MT connected to the non-selected word line WL. Such unintended data writing in the read operation is also called "read disturb".

[0098] 1.2.2 Detrapping Process Read disturbance is undesirable because it can lead to incorrect data being read from a memory cell transistor MT whose threshold voltage has been lowered. Therefore, in the first embodiment, a detrapping process is performed to discharge the charge accumulated at the interface between the insulating film 73 and the ferroelectric film 74. In the detrapping process, a voltage with the opposite polarity to that used in the read operation is applied between the gate and channel of the memory cell transistor MT.

[0099] Figure 10 shows a first example of the voltage applied to the memory cell array during detrapping in the memory system according to the first embodiment. Figure 11 shows a second example of the voltage applied to the memory cell array during detrapping in the memory system according to the first embodiment. The first example corresponds to the case where a positive voltage is applied to the various wirings. The second example corresponds to the case where a negative voltage is applied to the various wirings.

[0100] Figures 10 and 11 show one NAND string NS from each of the string units SU0 to SU3 within the block BLK to be detrapped. Figures 10 and 11 show the voltages applied to the bit line BL, selection gate lines SGD0 to SGD3 and SGS, and word lines WL0 to WL7 connected to the block BLK to be detrapped. Figures 10 and 11 also show the voltages applied when all memory cell transistors MT within the block BLK are to be detrapped.

[0101] <Example 1> First, we will explain the first example of the detrapping process with reference to Figure 10.

[0102] The sense amplifier module 29 applies a voltage Vdtp to the bit line BL. The voltage Vdtp is, for example, about 3V.

[0103] The low decoder module 28 applies a voltage VSS to the selected gate lines SGD0 to SGD3. This turns on all the selected transistors T1 in the block BLK that are to be detrapped.

[0104] The low decoder module 28 applies a voltage Vsgs to the selected gate line SGS. This turns off all the selected transistors T2 in the block BLK that are to be detrapped.

[0105] The row decoder module 28 applies a voltage VSS to the word lines WL0 to WL7. This increases the potential on the channel side relative to the gate of the memory cell transistor MT. As a result, the charge accumulated at the interface between the insulating film 73 and the ferroelectric film 74 of the memory cell transistor MT can be discharged to the channel side.

[0106] <Example 2> Next, we will explain a second example of the detrapping process with reference to Figure 11.

[0107] The sense amplifier module 29 applies a voltage VSS to the bit line BL.

[0108] The low decoder module 28 applies a voltage -Vsgd to the selection gate lines SGD0 to SGD3. This turns on all selection transistors T1 in the block BLK to be detrapped.

[0109] The low decoder module 28 applies a voltage -Vsgs to the selected gate line SGS. This turns off all the selected transistors T2 in the block BLK that are to be detrapped.

[0110] The row decoder module 28 applies a voltage -Vdtp to the word lines WL0 to WL7. This increases the potential on the channel side relative to the gate of the memory cell transistor MT. As a result, the charge accumulated at the interface between the insulating film 73 and the ferroelectric film 74 of the memory cell transistor MT can be discharged to the channel side.

[0111] 1.2.3 A series of processes including read and detrapping. Next, we will describe a series of processes including the reading process and the detrapping process.

[0112] Figure 12 is a flowchart showing an example of a series of processes, including read and detrapping, in the memory system according to the first embodiment.

[0113] When the read condition is met (start), the memory controller 10 determines whether the block BLK to be read matches the block BLK to be read in the previous read operation (S11).

[0114] The fulfillment of the read condition includes the fulfillment of the start condition for the read process executed internally by the memory controller 10. The fulfillment of the read condition may also include the memory controller 10 receiving a read request from the host 2.

[0115] If the block BLK to be read matches the block BLK to be read in the previous read operation (S11; yes), the memory controller 10 increments the count value of the counter 15 (S12).

[0116] The memory controller 10 determines whether the count value of the counter 15 is equal to or greater than the first threshold (S13).

[0117] The first threshold is, for example, a number greater than or equal to the number of word lines WL in a block BLK. The first threshold may also be less than the number of word lines WL in a block BLK.

[0118] If the count value of counter 15 is equal to or greater than the first threshold (S13; yes), the memory controller 10 instructs the non-volatile memory 20 to perform detrapping on the block BLK to be read (S14).

[0119] After the detrapping process in S14, or if the count value of counter 15 is less than the first threshold (S13; no), the memory controller 10 causes the non-volatile memory 20 to perform a read operation from the block BLK to be read (S15).

[0120] If the block BLK to be read is different from the block BLK to be read in the previous read operation (S11; no), the memory controller 10 determines whether the count value of the counter 15 is equal to or greater than the second threshold (S16).

[0121] The second threshold is a number lower than the first threshold. The second threshold may be, for example, 5% or more of the number of word lines (WL) within a block (BLK).

[0122] If the count value of counter 15 is equal to or greater than the second threshold (S16; yes), the memory controller 10 instructs the non-volatile memory 20 to perform detrapping on the block BLK to be read (S17). The detrapping process in S17 is equivalent to the detrapping process in S14.

[0123] After the detrapping process in S17, or if the count value of counter 15 is less than the second threshold (S17; no), the memory controller 10 resets the count value of counter 15 (S18).

[0124] After the processing in S18, the memory controller 10 causes the non-volatile memory 20 to perform the read operation from the block BLK to be read (S15).

[0125] After the read operation in S15, the series of processes including the read operation and detrapping operation are completed (end).

[0126] 1.3 Effects of the First Embodiment According to the first embodiment, the degradation of the reliability of the non-volatile memory 20 can be suppressed. This effect will be explained below.

[0127] FeFETs, which are memory cell transistors (MTs) containing a ferroelectric film 74, can perform high-speed write and erase operations at low voltages compared to memory cell transistors containing a charge storage film, but they are more prone to erroneous writing and erasing. For example, in FeFETs, during read operations, a potential difference of approximately 3V (Vread) is applied between the gate and channel of a memory cell transistor (MT) connected to an unselected word line (WL) among the unselected memory cells (MTs), which can cause read disturbance. The degree of read disturbance increases as read operations are performed consecutively on the same block (BLK).

[0128] According to the first embodiment, the memory controller 10 performs a detrapping process on a certain block BLK if the number of consecutive read operations performed on the same block BLK is equal to or greater than a first threshold. This allows the charge accumulated at the interface between the ferroelectric film 74 and the insulating film 73 of the memory cell transistor MT to be discharged by the consecutive read operations. As a result, the occurrence of read disturbance can be suppressed.

[0129] Furthermore, the memory controller 10 performs a detrapping process on a certain block BLK if a read operation is performed on another block after a second threshold or higher read operation has been performed consecutively on the same block BLK. This allows the charge accumulated at the interface between the ferroelectric film 74 and the insulating film 73 of the memory cell transistor MT by the consecutively performed read operations to be discharged. As a result, the occurrence of read disturbance can be suppressed.

[0130] 2. Second Embodiment Next, a memory system according to the second embodiment will be described. The second embodiment differs from the first embodiment in that it mitigates disturbances that occur during write and erase operations. In the following description, the same configuration and operation as the first embodiment will be omitted, and the configuration and operation that differ from the first embodiment will be described in detail.

[0131] 2.1 Memory System Figure 13 is a block diagram showing an example of the configuration of an information processing system according to the second embodiment. Figure 13 corresponds to Figure 1 in the first embodiment. The configuration of the host 2, memory controller 10, and non-volatile memory 20 in Figure 13 is the same as in Figure 1.

[0132] The volatile memory 30 stores block management information 31. The block management information 31 is information for managing the usage status of block BLK in the non-volatile memory 20 (the percentage of valid data in the memory area).

[0133] Figure 14 shows an example of the data structure of block management information according to the second embodiment.

[0134] The block management information 31 stores, for each block BLK, the number of cell units CU that do not store valid data, as the number of rewritable cell units. Cell units CU that do not store valid data either store invalid data or have no data stored in them. Valid data is data associated with a logical address. Invalid data is data that is not associated with a logical address (and can be erased).

[0135] In this specification, "rewriting" data means writing new valid data to a memory area where no valid data is currently stored. In other words, performing a rewrite operation includes both performing a write operation on an erased memory area and performing an erase operation on a memory area where invalid data is stored, followed by further write operations on that area.

[0136] The example in Figure 14 shows that the number of rewritable cell units in block BLK0 is "0", ..., and the number of rewritable cell units in block BLK(n-1) is "32". According to the example in Figure 14, by referring to the block management information 31, the memory controller 10 can determine that no further valid data can be written to block BLK0. The memory controller 10 can also determine that valid data can be written to all pages within block BLK(n-1).

[0137] 2.2 Rewrite Process The rewrite process in the memory system according to the second embodiment will be described.

[0138] 2.2.1 Writing Process Figure 15 shows an example of the voltage applied to the memory cell array during a write operation in the memory system according to the second embodiment. In Figure 15, one NAND string NS is shown for each of the string units SU0 to SU3 in the block BLK to be written. Figure 15 shows the voltages applied to the bit line BL, selection gate lines SGD0 to SGD3 and SGS, and word lines WL0 to WL7 connected to the block BLK to be written during the write operation. Figure 15 shows the voltage applied when the cell unit CU connected to the word line WL3 of string unit SU0 is the target of the write operation.

[0139] The raw decoder module 28 applies a voltage Vsg to the selected gate lines SGD0 and SGS. Note that the voltage Vsg used during the write operation may differ from the voltage Vsg used during the read operation.

[0140] The low decoder module 28 applies voltage VSS to the selected gate lines SGD1 to SGD3.

[0141] The sense amplifier module 29 applies a voltage VSS to the bit line BL connected to the memory cell transistor MT that writes the data "0". The sense amplifier module 29 also applies a voltage higher than the voltage VSS to the bit line BL connected to the memory cell transistor MT that writes the data "1".

[0142] By applying the voltages described above, the NAND string NS of the non-selected string unit SU is electrically isolated from the bit line BL. The NAND string NS of the selected string unit SU that includes the memory cell transistor MT for writing data "0" is electrically connected to the bit line BL. The NAND string NS of the selected string unit SU that includes the memory cell transistor MT for writing data "1" is electrically isolated from the bit line BL.

[0143] The low decoder module 28 applies a voltage Vpgm to the selected word line WL. The voltage Vpgm is, for example, about 7-8V.

[0144] The row decoder module 28 applies a voltage Vpass to the unselected word line WL. Voltage Vpass is the voltage that turns on the memory cell transistor MT, regardless of the threshold voltage of the memory cell transistor MT. Voltage Vpass is lower than voltage Vpgm. Voltage Vpass is, for example, 3V. As a result, the potential of the channel of the memory cell transistor MT connected to the unselected word line WL within the selected string unit SU becomes approximately Vpass lower than the gate potential.

[0145] Furthermore, the NAND string NS included in the non-selected string unit SU is in a floating state. As a result, the channel potential of the NAND string NS included in the non-selected string unit SU is coupled to approximately the voltage Vpass of the non-selected word line WL, which accounts for a large portion of the word line WL. Therefore, among the memory cell transistors MT in the non-selected string unit SU, the channel potential of the memory cell transistor MT connected to the selected word line WL is approximately (Vpgm-Vpass) lower than the gate potential.

[0146] Thus, during the write operation, the channel potential of the memory cell transistors MT connected to the unselected word line WL within the selected string unit SU, and the memory cell transistors MT connected to the selected word line WL within the unselected string unit SU, becomes approximately 3V to 5V lower than the gate. Therefore, during the write operation, unintended data may be written to the memory cell transistors MT connected to the unselected word line WL within the selected string unit SU, and to the memory cell transistors MT connected to the selected word line WL within the unselected string unit SU. Such unintended data writing during the write operation is also called "program disturbance".

[0147] 2.2.2 Deletion Process Figure 16 shows a first example of the voltage applied to the memory cell array during the erase process in the memory system according to the second embodiment. Figure 17 shows a second example of the voltage applied to the memory cell array during the erase process in the memory system according to the second embodiment. The first example corresponds to the case where a positive voltage is applied. The second example corresponds to the case where a negative voltage is applied.

[0148] Figures 16 and 17 show one NAND string NS from each of the string units SU0 to SU3 within the block BLK to be erased. Figures 16 and 17 show the voltages applied to the bit line BL, selection gate lines SGD0 to SGD3 and SGS, and word lines WL0 to WL7 connected to the block BLK to be erased. Figures 16 and 17 also show the voltage applied when the cell unit CU connected to word line WL3 within the block BLK is the one to be erased.

[0149] <Example 1> First, we will explain the first example of the erasure process with reference to Figure 16.

[0150] The sense amplifier module 29 applies a voltage Vera to the bit line BL. The voltage Vera is, for example, about 7-8V.

[0151] The row decoder module 28 applies a voltage VSS to the selection gate line SGD0. This turns on the selection transistor T1 of the selection string unit SU.

[0152] The row decoder module 28 applies a voltage Vsgd to the selected gate lines SGD1 to SGD3. This turns off the selection transistor T1 of the unselected string unit SU. Note that the voltage Vsgd in the second example of the erase process may be different from the voltage Vsgd in the second example of the detrap process.

[0153] The low decoder module 28 applies a voltage Vsgs to the selected gate line SGS. This turns off all the selected transistors T2 of the block BLK to be erased. Note that the voltage Vsgs in the second example of the erasure process may be different from the voltage Vsgs in the second example of the detrapping process.

[0154] The row decoder module 28 applies a voltage VSS to the selected word line WL. This erases the data written to the selected memory cell MT.

[0155] The row decoder module 28 applies a voltage Vpass to the unselected word line WL. This causes the potential of the channel of the memory cell transistor MT connected to the unselected word line WL within the selected string unit SU to be approximately (Vera-Vpass) higher than the gate.

[0156] Furthermore, the NAND string NS included in the non-selected string unit SU is in a floating state. As a result, the channel potential of the NAND string NS included in the non-selected string unit SU is coupled to approximately the voltage Vpass of the non-selected word line WL, which is the majority of the word lines WL. Therefore, among the memory cell transistors MT in the non-selected string unit SU, the channel potential of the memory cell transistor MT connected to the selected word line WL is approximately Vpass higher than the gate potential.

[0157] <Example 2> Next, we will explain a second example of the erasure process with reference to Figure 17.

[0158] The sense amplifier module 29 applies a voltage VSS to the bit line BL.

[0159] The raw decoder module 28 applies a voltage -Vsgd to the selection gate line SGD0. This turns on the selection transistor T1 of the selection string unit SU. Note that the voltage -Vsgd in the first example of the erase process may be different from the voltage -Vsgd in the first example of the detrap process.

[0160] The row decoder module 28 applies a voltage VSS to the selected gate lines SGD1 to SGD3. This turns off the selection transistor T1 of the non-selected string unit SU.

[0161] The low decoder module 28 applies a voltage -Vsgs to the selected gate line SGS. This turns off all the selected transistors T2 of the block BLK to be erased. Note that the voltage -Vsgs in the first example of the erasure process may be different from the voltage -Vsgs in the first example of the detrapping process.

[0162] The row decoder module 28 applies a voltage -Vera to the selected word line WL. This erases the data written to the selected memory cell MT.

[0163] The row decoder module 28 applies a voltage -Vpass to the unselected word line WL. This causes the potential of the channel of the memory cell transistor MT connected to the unselected word line WL within the selected string unit SU to be approximately Vpass higher than the gate potential.

[0164] Furthermore, the NAND string NS included in the non-selected string unit SU is in a floating state. As a result, the channel potential of the NAND string NS included in the non-selected string unit SU is coupled to the voltage of the non-selected word line WL, which is the majority of the word lines WL, by approximately -Vpass. Therefore, among the memory cell transistors MT in the non-selected string unit SU, the channel potential of the memory cell transistor MT connected to the selected word line WL is approximately (Vera-Vpass) higher than the gate.

[0165] Thus, during the erase process, the channel potential of the memory cell transistors MT connected to the unselected word line WL within the selected string unit SU, and the memory cell transistors MT connected to the selected word line WL within the unselected string unit SU, becomes approximately 3V higher than the gate potential. Therefore, during the erase process, unintended data erasure may occur in the memory cell transistors MT connected to the unselected word line WL within the selected string unit SU, and in the memory cell transistors MT connected to the selected word line WL within the unselected string unit SU. Such unintended data erasure during the erase process is also called "erase disturb".

[0166] 2.2.3 Order of rewriting process During the rewrite process, the write process described above, or a combination of the erase process and the write process, is executed. The order of the rewrite process is explained below.

[0167] Figure 18 shows an example of the order of rewrite operations in the memory system according to the second embodiment. Figure 18 shows an example of the order of rewrite operations performed on 32n cell units CU in the memory cell array 27. Note that Figure 18 shows the case where all cell units CU are rewritable for all blocks BLK in the memory cell array 27.

[0168] In the first to nth rewrite operations, the memory controller 10 sequentially selects cell units CU associated with pairs of string units SU0 and word lines WL0 of blocks BLK0 to BLKn.

[0169] In the (n+1) to 2nth rewrite operations, the memory controller 10 sequentially selects cell units CU associated with pairs of string units SU1 and word lines WL0 of blocks BLK0 to BLKn.

[0170] In the (2n+1) to 3nth rewrite operations, the memory controller 10 sequentially selects the cell unit CU associated with the string unit SU2 and word line WL0 of blocks BLK0 to BLKn.

[0171] In the (3n+1) to 4nth rewrite operations, the memory controller 10 sequentially selects the cell unit CU associated with the string unit SU3 and word line WL0 of blocks BLK0 to BLKn.

[0172] In the (4n+1) to 5nth rewrite operations, the memory controller 10 sequentially selects the cell unit CU associated with the string unit SU0 and word line WL1 of blocks BLK0 to BLKn.

[0173] Finally, in the (31n+1) to 32nth rewrite operations, the memory controller 10 sequentially selects the cell unit CU associated with the string unit SU3 and word line WL7 of blocks BLK0 to BLKn.

[0174] Once the 32nth rewrite operation is complete, the memory controller 10 will execute the rewrite operations again, starting from the first rewrite operation.

[0175] If the cell unit CU corresponding to the kth cell is not rewritable, the memory controller 10 may perform the rewrite operation for the kth cell on another cell unit CU in the same block BLK as the cell unit CU corresponding to the kth cell (for example, the cell unit CU corresponding to the (k+n)th cell).

[0176] Thus, when the memory controller 10 performs a rewrite operation on one cell unit CU of a certain block BLK, it performs the next rewrite operation on one cell unit CU of a different block BLK.

[0177] Furthermore, the memory controller 10 selects cell units CU such that as many rewrite operations as possible are performed between two rewrite operations on a given block BLK. Specifically, it selects cell units CU such that one rewrite operation is performed on each of blocks BLK1 to BLK(n-1) between two rewrite operations on block BLK0.

[0178] 2.3 Compaction Treatment Next, the compaction process in the memory system according to the second embodiment will be described. The compaction process is a process that suppresses the degradation of the reliability of the memory cell array 27 by reallocating the memory area in which valid data is stored.

[0179] Figure 19 is a flowchart showing an example of a process for determining whether or not to perform compaction processing in the memory system according to the second embodiment.

[0180] When the determination start condition is met (start), the memory controller 10 refers to the block management information 31 to determine whether the number of block BLKs with zero rewritable cell units is equal to or greater than the third threshold (S21).

[0181] The condition for starting the determination may be, for example, that a predetermined period of time has elapsed since the immediately preceding determination process. Alternatively, the condition for starting the determination may be that a predetermined number of write processes have been executed.

[0182] The third threshold is, for example, an integer between 1 and (n-1) inclusive.

[0183] If the number of block BLKs with zero rewritable cell units is greater than or equal to the third threshold (S21; yes), the memory controller 10 performs compaction processing on the non-volatile memory 20 (S22).

[0184] After processing in S22, or if the number of block BLKs with zero rewritable cell units is less than the third threshold (S21; no), the determination process ends (end).

[0185] Figure 20 shows an example of the order of rewrite operations before compaction processing in the memory system according to the second embodiment. Figure 21 shows an example of the order of rewrite operations after compaction processing in the memory system according to the second embodiment. In Figures 20 and 21, cell units CU that are not rewritable (i.e., those storing valid data) are hatched.

[0186] As shown in Figure 20, before the compaction process is performed, all cell units CU within a number of blocks BLKs greater than or equal to the third threshold, including blocks BLK0, BLK2, and BLK3, are considered unrewritable. In such a case, the frequency of rewriting a particular block BLK will be higher than once every (n-third threshold) times.

[0187] The memory controller 10 performs a compaction process on the memory cell array 27 as shown in Figure 20. Specifically, the memory controller 10 reallocates the memory area where valid data is stored so that the number of non-rewritable cell units CU is equalized across blocks BLK.

[0188] As a result, as shown in Figure 21, after the compaction process, the number of non-rewritable cell units (CU) becomes approximately equal across all blocks (BLK). In other words, the number of rewritable cell units becomes approximately equal across all blocks (BLK). Therefore, the frequency of rewriting operations for a given block (BLK) can be reduced to once every n operations.

[0189] 2.4 Effects according to the second embodiment According to the second embodiment, the degradation of the reliability of the non-volatile memory 20 can be suppressed. This effect will be explained below.

[0190] In FeFETs, program disturbance can occur during the write process when a potential difference of approximately 3V (Vpass or (Vpgm-Vpass)) is applied between the gate-channel of a memory cell transistor MT connected to the unselected word line WL within a selected string unit SU, and between a memory cell transistor MT connected to the selected word line WL within a non-selected string unit SU. Similarly, in FeFETs, erase disturbance can occur during the erase process when a potential difference of approximately 3V (Vpass or (Vera-Vpass)) is applied between the gate-channel of a memory cell transistor MT connected to the unselected word line WL within a selected string unit SU, and between a memory cell transistor MT connected to the selected word line WL within a non-selected string unit SU.

[0191] According to the second embodiment, when two rewrite operations are performed consecutively, the memory controller 10 performs the first rewrite operation on one block BLK and the second rewrite operation on the other block. This reduces the frequency of rewrite operations performed on the same block BLK. As a result, the occurrence of program disturb and erase disturb can be suppressed.

[0192] Furthermore, the memory controller 10 executes a compaction process if the number of blocks without memory cell transistors MT containing invalid data or erased memory cells is greater than or equal to the third threshold. In the compaction process, valid data stored in block blocks BLK where rewriting cannot be performed is moved to block blocks BLK where rewriting can be performed. This equalizes the amount of valid data stored between block blocks. As a result, the frequency of rewriting operations performed on the same block block can be reduced. This suppresses the occurrence of program disturb and erase disturb.

[0193] 4. Variations, etc. The first and second embodiments described above are not limited to the examples given, and various modifications are applicable.

[0194] The first embodiment described above describes the case where detrapping is applied to read operations performed consecutively within the same block BLK, but it is not limited to this. For example, detrapping may be applied to write operations performed consecutively within the same block BLK. Also, for example, detrapping may be applied to erase operations performed consecutively within the same block BLK. Note that the detrapping applied to erase operations has the opposite polarity to the detrapping applied to read operations and write operations.

[0195] Furthermore, while the second embodiment described above explains the order of rewrite operations to reduce the frequency of rewrite operations on the same block BLK, the order is not limited to this. For example, this order may also be applied to read operations on the same block BLK.

[0196] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0197] 1… Information processing system 2… Host 3…Memory System 10…Memory controller 11…Control circuits 12…Non-volatile memory interface 13…Host Interface 14. Volatile memory interface 15... Counter 20... Non-volatile memory 21…Input / Output Circuits 22...Logic control circuits 23…Register 24... Sequencer 25...Voltage generation circuit 26... Driver set 27…Memory cell array 28… Raw Decoder Module 29...Sense Amp Module 30…Volatile memory 31…Block Management Information 50… Semiconductor substrates 51, 52, 53, 54, 55… Conductive layer 60, 61, 62, 63, 64, 65… Insulating layer 70…Core film 71… Semiconductor film 72…Multilayer film 73…Insulator film 74... Ferroelectric film

Claims

1. A non-volatile memory comprising multiple blocks, each containing multiple memory cell transistors, The memory controller, Equipped with, The memory controller is configured to execute a second process on the first block if the first process is executed consecutively for a number of times equal to or greater than a first threshold for the first block. In the second process, the polarity of the voltage applied between the gate and channel of each of the plurality of memory cell transistors in the first block is different from the polarity of the voltage applied between the gate and channel of each of the plurality of memory cell transistors in the first block in the first process. Memory system.

2. The memory controller is configured to execute the second process on the first block after the first process has been executed consecutively on the first block for a number of times equal to or greater than a second threshold lower than the first threshold, The memory system according to claim 1.

3. Executing the above first process consecutively means Performing read operations consecutively, performing write operations consecutively, or performing erase operations consecutively. including, The memory system according to claim 2.

4. The gate of each of the plurality of memory cell transistors is A ferroelectric film containing hafnium (Hf) or zirconium (Zr), An insulating film in contact with the ferroelectric film, including, The memory system according to claim 2.

5. The ferroelectric film has an orthorhombic crystal structure. The memory system according to claim 4.

6. The aforementioned non-volatile memory further includes bit lines, Each of the plurality of blocks includes a first selection gate line, a second selection gate line, a word line, and a first memory string and a second memory string, each connected to the bit line, The first memory string is, A first selection transistor having a gate connected to the first selection gate line, A first memory cell transistor having a gate connected in series with the first selection transistor and connected to the word line, Includes, The second memory string is, A second selection transistor having a gate connected to the second selection gate line, A second memory cell transistor is connected in series with the second selection transistor and has a gate connected to the word line, including, The memory system according to claim 2.

7. The first threshold is greater than or equal to the number of memory cell transistors connected in series with the first selected gate line within the first memory string. The memory system according to claim 6.

8. The second threshold is 5% or more of the number of memory cell transistors connected in series with the first selected gate line within the first memory string. The memory system according to claim 6.

9. A non-volatile memory comprising multiple blocks, each containing multiple memory cell transistors, The memory controller, Equipped with, The memory controller is configured such that, when the first process is executed twice consecutively, it executes the first process once on the first block and the second process twice on the second block. Memory system.

10. Executing the above first process consecutively means Performing read operations consecutively, performing write operations consecutively, or performing erase operations consecutively. including, The memory system according to claim 9.

11. The memory controller is configured to execute a third process if the number of third blocks that do not contain memory cell transistors with invalid data stored or erased is greater than or equal to a third threshold. The memory system according to claim 9.

12. The third process includes moving the valid data stored in the third block to the fourth block. The memory system according to claim 11.

13. The third process includes leveling the amount of valid data stored in the plurality of blocks. The memory system according to claim 11.

14. The gate of each of the plurality of memory cell transistors is A ferroelectric film containing hafnium (Hf) or zirconium (Zr), An insulating film in contact with the ferroelectric film, including, The memory system according to claim 9.

15. The ferroelectric film has an orthorhombic crystal structure. The memory system according to claim 14.

16. The aforementioned non-volatile memory further includes bit lines, Each of the plurality of blocks includes a first selection gate line, a second selection gate line, a word line, and a first memory string and a second memory string, each connected to the bit line, The first memory string is, A first selection transistor having a gate connected to the first selection gate line, A first memory cell transistor having a gate connected in series with the first selection transistor and connected to the word line, Includes, The second memory string is, A second selection transistor having a gate connected to the second selection gate line, A second memory cell transistor is connected in series with the second selection transistor and has a gate connected to the word line, including, The memory system according to claim 9.

Images