Memory and its control method, electronic device

Abstract

The present invention provides a memory, a control method thereof, and electronic equipment, wherein in a first chip of the memory, each local bit line is coupled to a common bit line on one side via a respective bit line selector, and each local bit line is coupled to a common bit line on the other side via a respective precharge switch, the bit line selector is configured to receive a sub-word line drive signal and selectively bring the connected local bit line and the connected common bit line into conduction based on the sub-word line drive signal, and the precharge switch is configured to receive a complementary sub-word line drive signal and selectively bring the connected local bit line and the connected common bit line into conduction based on the complementary sub-word line drive signal.

Description

Technical Field

[0001] (Cross-reference to related applications) This application claims the priority of a Chinese patent application filed with the Chinese Patent Office on December 29, 2023, with an application number of 202311869141.2 and an invention title of "Memory and Its Control Method, Electronic Device", and all of its content is incorporated herein by reference.

[0002] This application relates to the field of semiconductors, and particularly to memory and its control method, and electronic devices.

Background Art

[0003] With the development of semiconductor technology, semiconductor memories are widely applied in electronic devices. DRAM (Dynamic Random Access Memory) is a type of volatile memory and is often used as a cache memory because of its fast access speed.

[0004] DRAM is mainly composed of two parts: a peripheral circuit (Periphery) and a memory array (Core). In order to further improve the memory density, in 3D DRAM, the peripheral circuit (Periphery) and the memory array (Core) are respectively provided on two independent chips, and the two chips are connected by bonding. Therefore, the three-dimensional structure of the memory array becomes more complex and additional control logic is required.

Summary of the Invention

[0005] Embodiments of the present invention provide a memory and its control method, and an electronic device.

[0006] The technical solution of the present invention is realized as follows.

[0007] In a first aspect, the present invention provides a memory comprising a first chip, the first chip comprising a plurality of memory array tiles, each of the memory array tiles comprising a plurality of local bit lines and a plurality of common bit lines, the local bit lines extending along a first direction, the common bit lines extending along a second direction, one common bit line on each side of the local bit lines along the first direction, the first direction and the second direction intersect. Each of the local bit lines is connected to the common bit line on one side via its own bit line selector, and each of the local bit lines is connected to the common bit line on the other side via its own precharge switch. The bit line selector is configured to receive a subword line drive signal and, based on the subword line drive signal, selectively conduct a connected local bit line and a connected common bit line. The precharge switch is configured to receive a subword line drive complementary signal and selectively conduct a connected local bit line and a connected common bit line based on the subword line drive complementary signal, and both the subword line drive signal and the subword line drive complementary signal are generated by decoding the row address signal in the command address signal received by the memory.

[0008] In some embodiments, each memory array tile includes a plurality of sub-array tiles arranged sequentially along a second direction, each sub-array tile includes a plurality of storage regions stacked sequentially along a third direction, each storage region includes two storage layer groups arranged along a first direction, each storage layer group is provided with a plurality of local bit lines, each storage layer group is provided with a first common bit line on the outside, away from the other storage layer group within the same storage region, and each storage layer group is provided with a second common bit line on the inside, closer to the other storage layer group within the same storage region. For each memory layer group, each local bit line is coupled to the second common bit line via its own bit line selector, and each local bit line is coupled to the first common bit line via its own precharge switch.

[0009] In some embodiments, each memory array tile includes a plurality of sub-array tiles arranged sequentially along a second direction, each sub-array tile includes a plurality of storage regions stacked sequentially along a third direction, each storage region includes two storage layer groups arranged along a first direction, each storage layer group is provided with a plurality of local bit lines, each storage layer group is provided with a first common bit line on the outside, away from the other storage layer group within the same storage region, and each storage layer group is provided with a second common bit line on the inside, closer to the other storage layer group within the same storage region. For the same subarray tile, the storage area is numbered along the third direction. For the odd-numbered memory areas, each local bit line is connected to the first common bit line via its own bit line selector, and each local bit line is connected to the second common bit line via its own precharge switch. For the even-numbered memory regions, each local bit line is connected to the second common bit line via its own bit line selector, and each local bit line is connected to the first common bit line via its own precharge switch.

[0010] In some embodiments, the memory array tile further includes a plurality of local word lines, each of which penetrates a plurality of stacked memory layer groups along a third direction, the third direction being perpendicular to the first direction and perpendicular to the second direction. Multiple local word lines that penetrate the same memory layer group and are aligned along the first direction form a subword line group. One of the local bit lines corresponds to one of the subword line groups, and one memory cell is formed at the intersection of the local bit line and each of the corresponding local word lines. All local word lines within the same subword line group share the same subword line drive signal and the same subword line drive complementary signal; the bit line selector of the local bit line receives the subword line drive signal of the corresponding subword line group; and the precharge switch of the local bit line receives the subword line drive complementary signal of the corresponding subword line group.

[0011] In some embodiments, each of the memory array tiles further includes a plurality of common word lines extending along a second direction, In each of the subarray tiles, the local word lines are numbered sequentially and independently, and local word lines with the same number in different subarray tiles are electrically connected to the same common word line and share the same subword line drive signal and the same subword line drive complementary signal.

[0012] In some embodiments, in the memory array tile, the common word lines are numbered sequentially along a first direction, and N consecutively numbered common word lines form one main word line group. The memory comprises a decoding unit and a plurality of subword line driving units, where N is a positive integer. The decoding unit is configured to encode the row address signal and generate a main word line drive signal, a subword line drive signal, and a subword line drive complementary signal for each of the common word lines. The subword line drive unit is coupled to one of the common word lines and is configured to receive a corresponding main word line drive signal, a corresponding subword line drive signal, and a corresponding subword line drive complementary signal, and to turn the coupled common word line on or off based on these signals. The two memory layer groups in each memory region are treated sequentially along a first direction as the first memory layer group and the second memory layer group, the main word line drive signal is used to select one main word line group from each of the first and second memory layer groups, and the subword line drive signal and the subword line drive complementary signal are used to select one common word line from the main word line group selected in the first memory layer group, or to select one common word line from the main word line group selected in the second memory layer group.

[0013] In some embodiments, the subword line drive unit comprises a first switch transistor, a second switch transistor, and a third switch transistor. The control terminals of the first switch transistor and the second switch transistor both receive the main word line drive signal, the first terminal of the first switch transistor receives the subword line drive signal, the second terminal of the first switch transistor, the first terminal of the second switch transistor, and the first terminal of the third switch transistor are all connected to the common word line, the second terminal of the second switch transistor and the second terminal of the third switch transistor are both connected to the power supply terminal, and the control terminal of the third switch transistor receives the subword line drive complementary signal.

[0014] In some embodiments, the memory further comprises a second chip, the first chip and the second chip are stacked along a third direction, and the first chip is bonded to the second chip. The second chip includes a sense amplification region, In the first chip, a stepped contact structure is provided between two adjacent memory layer groups along a first direction, and the common bit line, which is directly connected to the bit line selector, is coupled to the sense amplification region via the stepped contact structure.

[0015] In a second aspect, an embodiment of the present invention provides a memory control method, wherein a first chip in the memory comprises a plurality of memory array tiles, each of which includes a plurality of local bit lines and a plurality of common bit lines, each of which local bit lines is coupled to one common bit line via a bit line selector, and each of which local bit lines is coupled to the other common bit line via its own precharge switch. The memory control method is as follows: The steps include receiving a command address signal, decoding the line address signal within the command address signal, and generating a plurality of main word line drive signals, a plurality of subword line drive signals, and a plurality of subword line drive complementary signals, The steps include controlling whether the corresponding bit line selector conducts to a connected local bit line and a connected common bit line based on each of the subword line drive signals, The process includes controlling whether the corresponding precharge switch conducts to a connected local bit line and a connected common bit line based on each of the subword line drive complementary signals.

[0016] In some embodiments, each memory array tile includes a plurality of sub-array tiles arranged sequentially along a second direction, each sub-array tile includes a plurality of storage regions stacked sequentially along a third direction, each storage region includes two storage layer groups arranged along a first direction, each storage layer group is provided with a plurality of local bit lines, and each storage layer group is provided with one common bit line on each side along the first direction. The memory array tile further includes a plurality of local word lines, each of which penetrates a plurality of stacked memory layer groups along a third direction, a plurality of which penetrate the same memory layer group and are aligned along a first direction form a subword line group, all which local word lines share the same subword line drive signal and the same subword line drive complementary signal, one which local bit line corresponds to one which subword line group, and one which memory cell is formed at the intersection of the local bit line and each of the corresponding local word lines. Each subword line group has a subword line drive signal and a subword line drive complementary signal, and the memory control method is, The steps include transmitting the subword line drive signal of the subword line group to the corresponding local bit line bit line selector, The further step includes transmitting a subword line drive complementary signal for the subword line group to a precharge switch for the corresponding local bit line.

[0017] In some embodiments, in each subarray tile, local word lines are numbered sequentially and independently, and local word lines with the same number in different subarray tiles are electrically connected to the same common word line and share the same subword line drive signal and the same subword line drive complementary signal, and in the memory array tile, the common word lines are numbered along a first direction, and N common word lines of consecutive numbers form one main word line group, The two memory layer groups of each memory area are treated sequentially along the first direction as the first memory layer group and the second memory layer group, and the memory control method is as follows: The steps include selecting one main word line group from each of the first and second storage layer groups based on the main word line drive signal, Based on the sub-word line drive signal and the sub-word line drive complementary signal, selecting one of the common word lines from the main word line group selected in the first memory layer group or the main word line group selected in the second memory layer group; further comprising: turning on the selected common word line and executing the operation indicated by the command address signal.

[0018] In a third aspect, an embodiment of the present invention provides an electronic device, and the electronic device includes the memory in the first aspect.

[0019] [[ID=,10]]Embodiments of the present invention provide a memory, a control method thereof, and an electronic device. By using a sub-word line drive signal and a sub-word line drive complementary signal generated by decoding a row address signal to control the operating states of a local bit line precharge switch and a bit line selector, even if additional precharge switches and bit line selectors are introduced into the three-dimensional memory, there is no need to introduce additional control information or redundant decoding logic, so the control efficiency is improved and redundant devices are reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] [Figure 1A] It is a schematic diagram showing the configuration of a memory array tile in a first chip. [Figure 1B] It is a schematic diagram showing the configuration of a memory array tile in a first chip. [Figure 2] It is a schematic diagram showing a cross-sectional configuration of a memory array tile. [Figure 3] It is a schematic diagram showing a cross-sectional configuration of another memory array tile. [Figure 4] It is a first schematic diagram showing the configuration of a sub-array tile according to an embodiment of the present invention. [Figure 5] It is a schematic diagram showing a stacked structure of a memory according to an embodiment of the present invention. [Figure 6] It is a second schematic diagram showing the configuration of a sub-array tile according to an embodiment of the present invention. [Figure 7] This is a schematic diagram showing the configuration of another memory array tile according to an embodiment of the present invention. [Figure 8A] This is a schematic diagram showing a cross-sectional configuration of a memory array tile according to an embodiment of the present invention. [Figure 8B] This is a schematic diagram showing a cross-sectional configuration of a memory array tile according to an embodiment of the present invention. [Figure 9] This is a schematic diagram showing the circuit configuration of the first chip according to an embodiment of the present invention. [Figure 10] This is a schematic diagram showing the configuration of a subword line drive unit according to an embodiment of the present invention. [Figure 11] This is a flowchart of a control method according to an embodiment of the present invention. [Modes for carrying out the invention]

[0021] To further clarify the object, technical solutions and advantages of the present invention, the present invention will be described in more detail below with reference to the drawings. The embodiments described are not limiting to the present invention, and all other embodiments that can be obtained without creative effort by those skilled in the art are included within the scope of the present invention.

[0022] In the following, the phrase "several embodiments" describes a subset of all possible embodiments, but understandably, "several embodiments" may be the same subset or a different subset of all possible embodiments, and can be combined with each other without contradiction.

[0023] The terms "first / second" in this application are explained below. In the following explanation, the terms "first / second / third" do not limit a specific order, but rather distinguish similar objects. Understandably, "first / second / third" can be changed in a specific order or sequence where appropriate, so the embodiments of the present invention described herein may be performed in an order other than those illustrated or described herein.

[0024] Unless otherwise specified, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art. The terms used herein are employed solely to illustrate embodiments of the invention and are not intended to limit the invention.

[0025] Explanation of terms: WL (WordLine): Word line, BL (BitLine): Bit line, CMOS (Complementary Metal Oxide Semiconductor): Complementary metal oxide semiconductor, TSV (Through-Silicon-Via): Silicon through-hole, Mat (Memory Array Tile): Memory array tile.

[0026] Before describing embodiments of the present invention, we first define three directions that describe the three-dimensional structure relating to the plane in the following embodiments. Taking the Cartesian coordinate system as an example, the three directions may include the first direction, the second direction, and the third direction.

[0027] A semiconductor chip may include a top surface located at the front and a bottom surface located at the back opposite the front. Assuming that the flatness of the top and bottom surfaces is not considered, the direction in which the top and bottom surfaces of the semiconductor chip intersect (for example, perpendicularly) is defined as the third direction, the direction in which the local bit lines within the semiconductor chip extend is defined as the first direction, and the direction in which the local word lines within the semiconductor chip extend is defined as the second direction, with the first and second directions intersecting.

[0028] 3D DRAM includes a first and second chip stacked along a third direction, with the memory array (Core) distributed on the first chip and peripheral control areas (Periphery), sense amplification areas, etc., distributed on the second chip. On the first chip, the memory array (Core) contains a large number of memory cells, which are divided into multiple memory array tiles (Mat), thereby enabling better control and management.

[0029] Referring to Figure 1A, Figure 1A is a schematic diagram showing the configuration of the memory array tile 11 in the first chip. As shown in Figure 1A, each memory array tile 11 includes a plurality of sub-array tiles Sub Mat0, Sub Mat1, Sub Mat2, etc., arranged sequentially along the second direction, and each sub-array tile includes a plurality of storage areas stacked sequentially along the third direction, and each storage area includes two storage layer groups, a first storage layer group and a second storage layer group, arranged along the first direction, with a staircase structure 14 provided between the first storage layer group and the second storage layer group. Referring to Figure 1B, Figure 1B shows the locations of the local bit line Local BL, common bit line Common BL, local word line Local WL, and common word line Common WL. As shown in Figure 1B, local word lines penetrate multiple memory layer groups along a third direction, and in each subarray tile, local word lines are numbered along a second direction, and local word lines with the same number in different subarray tiles are joined to the same common word line, which extends along the second direction, and each memory layer group includes multiple local bit lines that extend along a first direction, and one common bit line is provided on both the left and right sides of each memory layer group.

[0030] Referring to Figures 2 and 3, both are schematic cross-sectional views of a memory array tile along the third direction, illustrating a memory array tile containing 20 sub-array tiles (Sub Mat0, Sub Mat1...Sub Mat19). As shown in Figure 2, a first common bit line is provided on the outside of each memory layer group (meaning the side away from the other memory layer group within the same memory area), and a second common bit line is provided on the inside of each memory layer group (meaning the side closer to the other memory layer group within the same memory area). Referring to Figure 3, all local bit lines within a memory layer group are connected to the first common bit line via a precharge switch Eq, all local bit lines within a memory layer group are connected to the second common bit line via a bit line selector Se, a stepped contact structure is provided between the first and second memory layer groups, and each second common bit line is coupled to a sense amplifier in the sense amplification area via the stepped contact structure.

[0031] Taking data retrieval as an example, opening a common word line turns on multiple groups of target memory cells, aligning each group of target memory cells along a third direction, and conducting the bit line selector Se of the local bit lines connected to each group of target memory cells. At this time, each target memory cell conducts to its corresponding second common bit line, and as a result, the second common bit lines of one group aligned along the third direction share charge with their respective target memory cells and are sense-amplified, becoming high or low potential after sense amplification (depending on the data stored in the target memory cells), the bit line selector Se of the unselected local bit lines is turned off, the precharge switch Eq is turned on, and all first common bit lines are charged to the precharge potential, thereby bringing all unselected local bit lines to the precharge potential. Here, the precharge potential may be an intermediate potential, which may be half of the memory array power supply voltage (Vblh), i.e., intermediate potential = 1 / 2Vblh.

[0032] Simply put, in a three-dimensional memory (3D DRAM), local bit lines within the same memory layer group share one first common bit line and the same second common bit line. The bit line selector Se determines whether to access the second common bit line, and the precharge switch Eq determines whether to access the first common bit line. Therefore, additional control logic for the bit line selector Se and precharge switch Eq must be designed.

[0033] Each embodiment of the present invention will be described in detail below with reference to the drawings.

[0034] In one embodiment of the present invention, a memory is provided, the memory comprising a first chip, the first chip comprising a plurality of memory array tiles 11, referring to Figure 4, which is a schematic diagram of the local structure of a memory array tile 11 according to an embodiment of the present invention, specifically, a diagram showing the remaining portion of a single sub-array tile (e.g., Sub Mat0, Sub Mat1, etc.) with the stepped contact structure omitted. As shown in Figure 4, each memory array tile includes a plurality of local bit lines and a plurality of common bit lines (e.g., the first common bit line 12 and the second common bit line 13 in Figure 4), the local bit lines extending along a first direction, the common bit lines extending along a second direction, with one common bit line on each side of the local bit lines along the first direction, and the first and second directions intersect. Each local bit line is connected to one side's common bit line via its own bit line selector Se, and each local bit line is connected to the other side's common bit line via its own precharge switch Eq. The bit line selector Se is controlled by the subword line drive signal Phdec (i is a positive integer) is received, and the subword line drive signal Phdec Based on this, it is configured to selectively conduct electricity between the connected local bit line and the connected common bit line. The precharge switch Eq is the subword line driving complementary signal PhdecN (i is a positive integer) is received, and the subword line drive complementary signal PhdecN Based on this, it is configured to selectively conduct electricity between the connected local bit lines and the connected common bit lines.

[0035] Here, the subword line drive signal Phdec and subword line driving complementary signal PhdecN These are all generated by decoding the line address signal within the command address signal received by memory. Generally, the subword line driving complementary signal PhdecN This is the subword line drive signal Phdec It is obtained by performing an inversion process on it. In addition, in some embodiments, the subword line driving complementary signal PhdecN This is the subword line drive signal Phdec The subword line drive signal Phdec is obtained by performing inversion and delay processing on it. and subword line driving complementary signal PhdecN These are not completely and strictly inverted states.

[0036] It should be understood that the row address signal is used to indicate the word line information to be selected (i.e., turned on) in this operation. In other words, in the embodiments of the present invention, word line information is multiplexed to control the operating state of the local bit line precharge switch Eq and bit line selector Se, and the specific principle can be found in the description below. As a result, even if additional precharge switches Eq and bit line selector Se are introduced in the three-dimensional memory, there is no need to introduce additional control information or extra decoding logic, thus improving control efficiency and reducing redundant devices.

[0037] Note that Figure 4 shows an example where each memory layer group contains four local bit lines, but this does not constitute a relevant limitation.

[0038] Referring to Figures 1A and 1B, each memory array tile includes multiple sub-array tiles Sub Mat0, Sub Mat1, Sub Mat2, etc., arranged sequentially along a second direction, and each sub-array tile includes multiple storage areas stacked sequentially along a third direction. Both Figures 1A and 1B show examples where each sub-array tile contains five storage areas, but the number of storage areas may be greater. Each storage area includes a first storage layer group and a second storage layer group arranged along a first direction.

[0039] In some embodiments, as shown in Figure 4, each storage layer group is provided with a plurality of local bit lines, and in each storage layer group, a first common bit line 12 is provided on the outside, away from the other storage layer group within the same storage area, and a second common bit line 13 is provided on the inside, closer to the other storage layer group within the same storage area.

[0040] For each memory layer group, each local bit line is connected to the second common bit line 13 via its own bit line selector Se, and each local bit line is connected to the first common bit line 12 via its own precharge switch Eq.

[0041] In some embodiments, the memory further comprises a second chip, the first and second chips stacked along a third direction, the first chip bonded to the second chip, and the second chip includes a sense amplification region. In the first chip, a stepped contact structure is provided between two adjacent memory layer groups along the first direction, and a common bit line directly connected to the bit line selector Se is coupled to the sense amplification region via the stepped contact structure.

[0042] The first and second chips are connected by bonding, which means that the two chips are electrically connected by a hybrid bonding structure (also called a bonding pillar). Hybrid bonding is a process that forms permanent bonds between different or identical chips. "Hybrid" means that dielectric-dielectric bonding and metal-metal bonding are formed between the two surfaces, and specifically offers the following advantages: (1) Shorter interconnection distance: Not only is it unnecessary to interconnect with lead wires, but it is also unnecessary to penetrate the entire CMOS layer with TSVs, and interconnection can be achieved simply by connecting copper contacts in the back channel. (2) Higher interconnection density: The area of ​​the copper contacts is very small, and the spacing dimension of the copper contacts in the hybrid bonding process is less than 10 microns compared to solder balls or TSVs with a diameter of 100 microns, so it is certain that a higher interconnection density can be achieved. (3) Lower cost: Undoubtedly, interconnecting each chip individually takes more time, and wafer bonding enables high-density interconnection over a large area, which dramatically improves production capacity. Naturally, production costs can also be reduced.

[0043] The sense amplification region includes multiple sense amplifiers (SAs), also known as sense amplifiers, and amplifies the electrical signal of the common bit line connected to the selected memory cell. This ultimately causes the potential of the common bit line to become low or high, achieving the objective of reading data from or writing data to the selected memory cell.

[0044] In 3D DRAM, since multilayer memory cells (i.e., multiple memory layer groups) are often stacked vertically to form the memory structure, a 3D staircase contact structure is necessary to allow the sense amplifier to smoothly connect to the common bit line within each memory layer group. Different staircases in the staircase contact structure are electrically isolated, and one staircase is connected to one common bit line (connected to the bit line connector Se). As a result, the common bit line is connected to the sense amplifier SA in the sense amplification region, enabling sense amplification processing.

[0045] In this way, the local bit lines within each memory layer group are connected via a bit line selector Se to a second common bit line 13 located in the center of the memory area to which they belong. Furthermore, a stepped contact structure is provided in the center of the memory area, meaning that the second common bit line 13 of each memory layer group can be externally connected to a sense amplifier in the sense amplification area via the stepped contact structure located in the center of the memory area.

[0046] In some other embodiments, referring to Figure 6, for the same subarray tile, the storage areas are numbered along the third direction as storage area 0, storage area 1, storage area 2, storage area 3, storage area 4, and so on.

[0047] For odd-numbered memory areas 1 and 3, each local bit line is connected to the first common bit line 12 via its own bit line selector Se, and each local bit line is connected to the second common bit line 13 via its own precharge switch Eq. For even-numbered memory areas 0, 2, and 4, each local bit line is connected to the second common bit line 13 via its own bit line selector Se, and each local bit line is connected to the first common bit line 12 via its own precharge switch Eq.

[0048] In other words, the first common bit lines 12 of two adjacent memory layer groups are adjacent in the third direction, and the second common bit lines 13 of two adjacent memory layer groups are adjacent in the third direction, but neither the first common bit line 12 nor the second common bit line 13 is adjacent in the third direction. Furthermore, for odd-numbered memory areas 1 and 3, the local bit lines are connected to the first common bit line 12 via the bit line selector Se and to the second common bit line 13 via the precharge switch Eq. For even-numbered memory areas 0, 2, and 4, the local bit lines are connected to the second common bit line 13 via the bit line selector Se and to the first common bit line 12 via the precharge switch Eq. Consequently, during the sense amplification process, for a selected group of memory layers, for two adjacent first common bit lines 12, one first common bit line 12 is necessarily in a sense amplification state (after the sense amplification state ends, it becomes high or low potential depending on the specific data value), and the other first common bit line 12 is in a precharge potential. Similarly, for two adjacent second common bit lines 13, one second common bit line 13 is necessarily in a sense amplification state (after the sense amplification state ends, it becomes high or low potential depending on the specific data value), and the other second common bit line is in a precharge potential, where low potential < precharge potential < high potential. However, since two adjacent common bit lines along the third direction do not undergo sense amplification simultaneously, two adjacent common bit lines along the third direction do not enter a sense amplification state simultaneously, and therefore the coupling between two adjacent common bit lines is clearly weakened, improving the sense amplification margin.

[0049] Of course, no matter how the positions of the precharge switch Eq and bit line selector Se change, the control signals they receive remain the same, and are still the subword line drive complementary signal PhdecN generated by the row address signal. and subword line drive signal Phdec This can be controlled by using multiple instances of it.

[0050] Referring to Figure 7, the stepped contact structure is located in the center of each memory area and on the outside of each memory area, respectively. In this case, for the even-numbered memory areas 0, 2, and 4, the local bit lines are connected to the inner second common bit line 13 and further coupled to the sense amplifier via the internal stepped contact structure. For the odd-numbered memory areas 1 and 3, the local bit lines are connected to the outer first common bit line 12 and further coupled to the sense amplifier via the external stepped contact structure.

[0051] In some embodiments, referring to Figure 1B, the memory array tile further includes multiple local word lines, each local word line passing through multiple stacked memory layer groups along a third direction, and one memory cell is formed at the intersection of a local bit line and each corresponding local word line, it should be noted that the local bit lines and local word lines are not directly connected. Exemplarily, the memory cell has a 1T1C structure and comprises one transistor and one capacitor, the gate of the transistor connected to the local word line, and the source and drain of the transistor connected to the local bit line and the capacitor, respectively, and the third direction is perpendicular to the first and second directions.

[0052] Referring to Figure 8A, which illustrates the control logic for local word lines and local bit lines, using a cross-section along the third direction of a subarray tile Sub Mat0 as an example. As shown in Figure 8A, multiple local word lines that penetrate the same memory layer group and are aligned along the first direction form a subword line group. All local word lines within the same subword line group share the same subword line drive signal and the same subword line drive complementary signal.

[0053] For example, for the first memory layer group, local word line WL <0> WL <4> ...WL <1592> WL <1596> This forms a subword line group, and this subword line group is Phdec <0> and PhdecN <0> Share local word lines WL <1> WL <5> ...WL <1593> WL <1597> This forms a subword line group, and this subword line group is Phdec <1> and PhdecN <1> Share local word lines WL <2> WL <6> ...WL <1594> WL <1598> This forms a subword line group, and this subword line group is Phdec <2> and PhdecN <2> Share local word lines WL <3> WL <7> ...WL <1595> WL <1599> This forms a subword line group, and this subword line group is Phdec <3> and PhdecN <3> Share.

[0054] For the second memory layer group, local word line WL <1600> WL <1604> ...WL <3192> WL <3196> This forms a subword line group, and this subword line group is Phdec <4> and PhdecN <4> Share local word lines WL <1601> WL <1605> ...WL <3193> WL <3197> This forms a subword line group, and this subword line group is Phdec <5> and PhdecN <5> Share local word lines WL <1602> WL <1606> ...WL <3194> WL <3198> This forms a subword line group, and this subword line group is Phdec <6> and PhdecN <6> Share local word lines WL <1603> WL <1607> ...WL <3195> WL <3199> This forms a subword line group, and this subword line group is Phdec <7> and PhdecN <7> Share.

[0055] Each local bit line corresponds to a group of subword lines, and a memory cell is formed at the intersection of each local bit line and its corresponding local word line. For example, local bit line BL0 corresponds to local word line WL. <0> WL <4> ...WL <1592> WL <1596> This corresponds to the local bit line BL0 and the local word line WL. <0> At the intersection of these two points, there is one memory cell, and local bit lines BL0 and WL <4> At the intersection of these two points, there is one memory cell, ... and local bit lines BL0 and WL <1596> A single memory cell exists at the intersection of these lines.

[0056] The bit line selector Se of the local bit line receives the subword line drive signal of the corresponding subword line group, and the precharge switch Eq of the local bit line receives the subword line drive complementary signal of the corresponding subword line group. For example, the control signal Sel of the bit line selector Se of the local bit line BL0. <0> =Phdec <0> Then, the control signal Eq of the precharge switch Eq on local bit line BL0. <0> =PhdecN <0> That is the case.

[0057] In some embodiments, as shown in Figure 8B, each memory array tile further includes a plurality of common word lines (Common WLs) extending along a second direction, and in each subarray tile, local word lines are sequentially and independently numbered, and local word lines of the same number in different subarray tiles are electrically connected to the same common word line and share the same subword line drive signal and the same subword line drive complementary signal.

[0058] In other words, within each sub-array tile Sub Mat0, Sub Mat1...Sub Mat19, there is a local word line WL. <0> WL <4> ...WL <1596> These are all subword line drive signals Phdec <0> and subword line driving complementary signal PhdecN <0> Share.

[0059] Specifically, this refers to the local word lines WL within each subarray tile Sub Mat0, Sub Mat1...Sub Mat19. <0> Common word The line Common WL0 is connected to the local word line WL within each subarray tile Sub Mat0, Sub Mat1...Sub Mat19. <4> Common word The line Common WL4 is connected to the local word line WL within each sub-array tile Sub Mat0, Sub Mat1...Sub Mat19. <1596> Common word The line is connected to Common WL1596, but common word Lines Common WL0, Common WL4, ..., Common WL1596 are subword line drive signals Phdec <0> and subword line driving complementary signal PhdecN <0> Share.

[0060] Furthermore, the bit line selector Se of the first local bit line BL0 in each memory area within each subarray tile is the subword line drive signal Phdec <0> Upon receiving the signal, the precharge switch Eq of the local bit line BL0 in each memory area within each subarray tile is triggered by the subword line drive signal PhdecN. <0> Receive.

[0061] In some embodiments, as shown in Figure 8B, in a memory array tile, common word lines are numbered sequentially along a first direction, and N common word lines of consecutive numbers form one main word line group, Figure 8B shows N=4 as an example, i.e., WL <0> ~WL <3> This is one main word line group, WL <4> ~WL <7> This is one main word line group...

[0062] Referring to Figure 9, the memory comprises a decoding unit 21 and a plurality of subword line driving units 22, where N is a positive integer. The decoding unit 21 is configured to encode the row address signals to generate the main word line drive signal GrDec<399:0>, the subword line drive signal Phdec<7:0>, and the subword line drive complementary signal PhdecN<7:0> for each common word line.

[0063] The subword line drive unit 22 is coupled to a common word line and is configured to receive a corresponding main word line drive signal, a corresponding subword line drive signal, and a corresponding subword line drive complementary signal, and to turn the coupled common word line on or off based on these signals. Here, the main word line drive signal is used to select one main word line group from each of the first and second storage layer groups, and the subword line drive signal and the subword line drive complementary signal are used to select one common word line from the main word line group selected in the first storage layer group, or to select one common word line from the main word line group selected in the second storage layer group.

[0064] For example, the main word line drive signal GrDec <0> =0, GrDec <1> ~GrDec <399> =1 (indicates selection when the main word line drive signal is low level, and not selection when the main word line drive signal is high level), subword line drive signal Phdec <0> =1, Phdec <1> ~Phdec <7> =0, Subword line drive complementary signal PhdecN <0> =0, PhdecN <1> ~PhdecN <7> If = 1, common word Common WL <0> This is selected, meaning that the WLs within each subarray tile Sub Mat0, Sub Mat1...Sub Mat19 are selected. <0> Both are selected (turned on). At the same time, for each memory area of ​​each subarray tile Sub Mat0, Sub Mat1...Sub Mat19 (Figure 8B is a cross-sectional view, i.e., it shows only one memory area from each subarray tile Sub Mat0, Sub Mat1...Sub Mat19), the bit line selector Se of the local bit line BL0 within it is made conductive (its control signal Sel <0> =Phdec <0> =1), the precharge switch Eq is blocked (its control signal Eq <0> =PhdecN <0> =0), on the other hand, the bit line selector Se for local bit lines BL1~BL4 is disconnected, and the precharge switch Eq is conducted. In this way, common word Common WL <0> When this is turned on, BL0 conducts to the adjacent common bit line via the bit line selector Se, and the common bit line is coupled to the sense amplifier via a stepped contact structure, so each WL <0> The memory cell formed at the intersection of and BL0 shares charge with the corresponding common bit line (via BL0 and the bit line selector Se), and the potential of the common bit line is amplified under the action of the sense amplifier. Simultaneously, WL <1> ~WL <4> The switch is not turned on, and BL1 to BL4 conduct to an adjacent common bit line via the precharge switch Eq, which is controlled to a precharge potential, which may be an intermediate potential of 1 / 2Vblh, where Vblh is the power supply potential of the memory array (or sense amplifier).

[0065] In some embodiments, referring to Figure 10, the subword line drive unit 22 comprises a first switch transistor 301, a second switch transistor 302, and a third switch transistor 303. The control terminals of the first switch transistor 301 and the second switch transistor 302 both receive the main word line drive signal Grdec, the first terminal of the first switch transistor 301 receives the subword line drive signal Phdec, the second terminal of the first switch transistor 301, the first terminal of the second switch transistor 302, and the first terminal of the third switch transistor 303 are all connected to the common word line Common WL, the second terminal of the second switch transistor 302 and the second terminal of the third switch transistor 303 are both connected to the power supply terminal, and the control terminal of the third switch transistor 303 receives the subword line drive complementary signal PhdecN.

[0066] The power terminal may also be a ground terminal. The first switch transistor 301 is P-type doped, while the second switch transistor 302 and the third switch transistor 303 are both N-type doped.

[0067] Thus, in one case, if Grdec=0, it means that the main word line group to which the common word line belongs is selected, and the first switch transistor 301 conducts. If Phdec=1, it means that the common word line is selected, in which case the common word line Common WL is at a high level (i.e., selected / on), and turns on the transistor in the connected memory cell. In another case, if Grdec=0 and Phdec=0, it means that the main word line group to which the common word line belongs is selected, but the common word line itself is not selected, the common word line Common WL is at a low level, and the transistor in the connected memory cell does not turn on. In yet another case, if Grdec=1, it means that the entire main word line group to which the common word line belongs is not selected, the first switch transistor 301 does not conduct, the common word line Common WL is at a low level, and the transistor in the connected memory cell does not turn on.

[0068] Furthermore, the third switch transistor 303 is used to quickly turn off the corresponding common word line after the corresponding common word line has been selected and the corresponding operation has been completed.

[0069] As described above, embodiments of the present invention provide a three-dimensional memory comprising a first chip and a second chip, the first and second chips stacked along a third direction and connected by hybrid bonding. The first chip is mainly used to create a memory array (Core), which is further divided into multiple memory array tiles (Mat) for better control and management. The second chip is mainly used to create peripheral control regions (Periphery) and sense amplification regions, etc. In the first chip, each memory array tile includes a plurality of sub-array tiles sequentially arranged along a second direction, each sub-array tile includes a plurality of storage areas sequentially stacked along a third direction, each storage area includes two storage layer groups arranged along a first direction, each storage layer group includes a plurality of local bit lines, and one common bit line is provided on each side of each storage layer group along the first direction, each local bit line is coupled to the common bit line on one side via its own bit line selector, and each local bit line is coupled to the common bit line on the other side via its own precharge switch, the bit line selector operates based on a subword line drive signal, and the precharge switch operates based on a subword line drive complementary signal. Thus, in this embodiment of the present invention, word line information is multiplexed to control the operating state of the local bit line precharge switch Eq and bit line selector Se, thereby improving control efficiency and reducing redundant devices, as there is no need to introduce additional control information or extra decoding logic even when additional precharge switches Eq and bit line selector Se are introduced.

[0070] In another embodiment of the present invention, referring to Figure 11, a flowchart of a memory control method according to an embodiment of the present invention is shown. The memory control method is applied to the above memory, referring to Figure 1A, the memory comprises a first chip and a second chip stacked along a first direction, the first chip comprising a plurality of memory array tiles, each memory array tile comprising a plurality of sub-array tiles sequentially arranged along a second direction, each sub-array tile comprising a plurality of storage areas sequentially stacked along a third direction, each storage area comprising two storage layer groups arranged along the first direction, each storage layer group comprising a plurality of local bit lines, each storage layer group having one common bit line on each side along the first direction, each local bit line being coupled to the common bit line on one side via its own bit line selector, and each local bit line being coupled to the common bit line on the other side via its own precharge switch.

[0071] As shown in Figure 11, the memory control method includes the following steps.

[0072] In step S501, the command address signal is received, the line address signal within the command address signal is decoded, and multiple main word line drive signals, multiple subword line drive signals, and multiple subword line drive complementary signals are generated.

[0073] In step S502, based on each subword line drive signal, the corresponding bit line selector controls whether or not to conduct between the connected local bit line and the connected common bit line.

[0074] In step S503, based on the complementary drive signals for each subword line, the corresponding precharge switch controls whether or not to conduct between the connected local bit line and the connected common bit line.

[0075] In some embodiments, referring to Figure 8B, the memory array tile further includes a plurality of local word lines, each local word line passing through a plurality of stacked memory layer groups along a third direction, a plurality of local word lines passing through the same memory layer group and aligned along a first direction form a subword line group, all local word lines within the same subword line group share the same subword line drive signal and the same subword line drive complementary signal, one local bit line has a correspondence with one subword line group, and one memory cell is formed at the intersection of a local bit line and each corresponding local word line. Each subword line group has a subword line drive signal and a subword line drive complementary signal, and the memory control method is as follows: The steps include transmitting the subword line drive signal of a subword line group to the bit line selector of the corresponding local bit line, The further step includes transmitting a subword line drive complementary signal for a subword line group to a precharge switch for the corresponding local bit line.

[0076] In some embodiments, in each subarray tile, local word lines are sequentially and independently numbered, and local word lines with the same number in different subarray tiles are electrically connected to the same common word line and share the same subword line drive signal and the same subword line drive complementary signal; in a memory array tile, common word lines are sequentially numbered along a first direction, and N common word lines with consecutive numbers form one main word line group; The two memory layer groups of each memory area are treated sequentially as the first memory layer group and the second memory layer group along the first direction, and the memory control method is as follows: The steps include selecting one main word line group from each of the first and second storage layer groups based on the main word line drive signal, A step of selecting one common word line from the main word line group selected in the first storage layer group or the main word line group selected in the second storage layer group, based on the subword line drive signal and the subword line drive complementary signal, The further steps include turning on the selected common word line and performing the action indicated by the command address signal.

[0077] Thus, in the embodiments of the present invention, word line information is multiplexed to control the operating state of the local bit line precharge switch Eq and bit line selector Se. As a result, even if additional precharge switches Eq and bit line selector Se are introduced, there is no need to introduce additional control information or extra decoding logic, thus improving control efficiency and reducing redundant devices.

[0078] In yet another embodiment of the present invention, an electronic device is provided, the electronic device comprising a memory shown in Figure 4, the memory comprising a first chip and a second chip stacked along a third direction, the first chip and the second chip being bonded together.

[0079] Referring to Figure 1A, in the first chip, each memory array tile includes a plurality of sub-array tiles sequentially arranged along a second direction, each sub-array tile includes a plurality of storage areas sequentially stacked along a third direction, each storage area includes two storage layer groups arranged along a first direction, each storage layer group includes a plurality of local bit lines, and one common bit line is provided on each side of each storage layer group along the first direction, each local bit line is coupled to the common bit line on one side via its own bit line selector, and each local bit line is coupled to the common bit line on the other side via its own precharge switch. Referring to Figure 4, the bit line selector operates based on a subword line drive signal, and the precharge switch operates based on a subword line drive complementary signal. Thus, in this embodiment of the present invention, word line information is multiplexed to control the operating state of the local bit line precharge switch Eq and bit line selector Se, thereby improving control efficiency and reducing redundant devices, as there is no need to introduce additional control information or extra decoding logic even when additional precharge switches Eq and bit line selector Se are introduced.

[0080] In this specification, the terms “includes,” “contains,” or any other variation thereof are intended to encompass non-exclusive inclusion, so that a process, method, article, or apparatus containing a set of elements includes not only those elements but also other elements not expressly enumerated, or elements specific to such process, method, article, or apparatus. Unless otherwise specified, an element defined by the expression “contains…” does not preclude the presence of another identical element in a process, method, article, or apparatus containing that element.

[0081] The sequence numbers of the above embodiments of the present invention are for illustrative purposes only and do not indicate any superiority or inferiority of the embodiments. The methods disclosed in the embodiments of some methods provided in the present invention can be arbitrarily combined without contradiction to obtain embodiments of new methods. The features disclosed in the embodiments of some products provided in the present invention can be arbitrarily combined without contradiction to obtain embodiments of new products. The features disclosed in the embodiments of some methods or devices provided in the present invention can be arbitrarily combined without contradiction to obtain embodiments of new methods or devices.

[0082] The above description is merely an embodiment of the present invention, and the scope of protection of the present invention is not limited thereto. Any modifications or substitutions that are readily conceivable to those skilled in the art within the technical scope disclosed herein should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of protection of the claims.

Claims

1. A memory comprising a first chip, the first chip comprising a plurality of memory array tiles, each of the memory array tiles comprising a plurality of local bit lines and a plurality of common bit lines, the local bit lines extending along a first direction, the common bit lines extending along a second direction, one common bit line on each side of the local bit lines along the first direction, the first direction and the second direction intersect. Each of the local bit lines is coupled to the common bit line on one side via its own bit line selector (Se), and each of the local bit lines is coupled to the common bit line on the other side via its own precharge switch (Eq). The bit line selector (Se) is configured to receive a subword line drive signal and, based on the subword line drive signal, selectively conduct the connected local bit line and the connected common bit line. The precharge switch (Eq) is configured to receive a subword line drive complementary signal and selectively conduct a connected local bit line and a connected common bit line based on the subword line drive complementary signal, and both the subword line drive signal and the subword line drive complementary signal are generated by decoding the row address signal in the command address signal received by the memory.

2. Each memory array tile includes a plurality of sub-array tiles arranged sequentially along a second direction, each sub-array tile includes a plurality of storage regions stacked sequentially along a third direction, each storage region includes two storage layer groups arranged along a first direction, each storage layer group is provided with a plurality of local bit lines, each storage layer group has a first common bit line on the outside, away from the other storage layer group within the same storage region, and each storage layer group has a second common bit line on the inside, closer to the other storage layer group within the same storage region. For each memory layer group, each local bit line is coupled to the second common bit line via its own bit line selector, and each local bit line is coupled to the first common bit line via its own precharge switch. The memory according to claim 1.

3. Each memory array tile includes a plurality of sub-array tiles arranged sequentially along a second direction, each sub-array tile includes a plurality of storage regions stacked sequentially along a third direction, each storage region includes two storage layer groups arranged along a first direction, each storage layer group is provided with a plurality of local bit lines, each storage layer group has a first common bit line on the outside, away from the other storage layer group within the same storage region, and each storage layer group has a second common bit line on the inside, closer to the other storage layer group within the same storage region. For the same subarray tile, the storage area is numbered along the third direction. For the odd-numbered memory areas, each local bit line is connected to the first common bit line via its own bit line selector, and each local bit line is connected to the second common bit line via its own precharge switch. For the even-numbered memory regions, each local bit line is connected to the second common bit line via its own bit line selector, and each local bit line is connected to the first common bit line via its own precharge switch. The memory according to claim 1.

4. The memory array tile further includes a plurality of local word lines, each of which penetrates a plurality of stacked memory layer groups along a third direction, the third direction being perpendicular to the first direction and perpendicular to the second direction. Multiple local word lines that penetrate the same memory layer group and are aligned along the first direction form a subword line group. One of the local bit lines corresponds to one of the subword line groups, and one memory cell is formed at the intersection of the local bit line and each of the corresponding local word lines. All local word lines within the same subword line group share the same subword line drive signal and the same subword line drive complementary signal; the bit line selector of the local bit line receives the subword line drive signal of the corresponding subword line group; and the precharge switch of the local bit line receives the subword line drive complementary signal of the corresponding subword line group. The memory according to claim 2.

5. Each of the memory array tiles further includes a plurality of common word lines extending along a second direction, In each of the subarray tiles, the local word lines are numbered sequentially and independently, and local word lines with the same number in different subarray tiles are electrically connected to the same common word line and share the same subword line drive signal and the same subword line drive complementary signal. The memory according to claim 4.

6. In the memory array tile, the common word lines are numbered sequentially along a first direction, and N consecutively numbered common word lines form one main word line group. The memory comprises a decoding unit (21) and a plurality of subword line driving units (22), where N is a positive integer. The decoding unit (21) is configured to encode the row address signal and generate a main word line drive signal, a subword line drive signal, and a subword line drive complementary signal for each of the common word lines. The subword line drive unit (22) is coupled to one of the common word lines and is configured to receive a corresponding main word line drive signal, a corresponding subword line drive signal, and a corresponding subword line drive complementary signal, and to turn the coupled common word line on or off based on these signals. The two memory layer groups in each memory region are treated sequentially along a first direction as the first memory layer group and the second memory layer group, the main word line drive signal is used to select one main word line group from each of the first and second memory layer groups, and the subword line drive signal and the subword line drive complementary signal are used to select one common word line from the main word line group selected in the first memory layer group, or to select one common word line from the main word line group selected in the second memory layer group. The memory according to claim 5.

7. The subword line drive unit (22) comprises a first switch transistor (301), a second switch transistor (302), and a third switch transistor (303), The control terminals of the first switch transistor and the second switch transistor both receive the main word line drive signal, the first terminal of the first switch transistor receives the subword line drive signal, the second terminal of the first switch transistor, the first terminal of the second switch transistor, and the first terminal of the third switch transistor are all connected to the common word line, the second terminal of the second switch transistor and the second terminal of the third switch transistor are both connected to the power supply terminal, and the control terminal of the third switch transistor receives the subword line drive complementary signal. The memory according to claim 6.

8. The memory further comprises a second chip, the first chip and the second chip are stacked along a third direction, and the first chip is bonded to the second chip. The second chip includes a sense amplification region, In the first chip, a stepped contact structure is provided between two adjacent memory layer groups along a first direction, and the common bit line, which is directly connected to the bit line selector, is coupled to the sense amplification region via the stepped contact structure. The memory according to claim 7.

9. A method for controlling memory, wherein a first chip in the memory comprises a plurality of memory array tiles, each of the memory array tiles includes a plurality of local bit lines and a plurality of common bit lines, each of the local bit lines is coupled to one common bit line via a bit line selector, and each of the local bit lines is coupled to the other common bit line via its own precharge switch. The memory control method is as follows: The steps include receiving a command address signal, decoding the line address signal within the command address signal, and generating a plurality of main word line drive signals, a plurality of subword line drive signals, and a plurality of subword line drive complementary signals, The steps include controlling whether the corresponding bit line selector conducts to a connected local bit line and a connected common bit line based on each of the subword line drive signals, A memory control method comprising the step of controlling whether the corresponding precharge switch conducts a connected local bit line and a connected common bit line based on each of the subword line drive complementary signals.

10. Each memory array tile includes a plurality of sub-array tiles arranged sequentially along a second direction, each sub-array tile includes a plurality of storage regions stacked sequentially along a third direction, each storage region includes two storage layer groups arranged along a first direction, each storage layer group is provided with a plurality of local bit lines, and each storage layer group is provided with one common bit line on each side along the first direction. The memory array tile further includes a plurality of local word lines, each of which penetrates a plurality of stacked memory layer groups along a third direction, a plurality of which penetrate the same memory layer group and are aligned along a first direction form a subword line group, all local word lines within the same subword line group share the same subword line drive signal and the same subword line drive complementary signal, one local bit line corresponds to one subword line group, and one memory cell is formed at the intersection of the local bit line and each of the corresponding local word lines. Each subword line group has a subword line drive signal and a subword line drive complementary signal, and the memory control method is, The steps include transmitting the subword line drive signal of the subword line group to the corresponding local bit line bit line selector, The further step includes transmitting a subword line drive complementary signal for the subword line group to the corresponding local bit line precharge switch, The memory control method according to claim 9.

11. In each subarray tile, local word lines are numbered sequentially and independently, and local word lines with the same number in different subarray tiles are electrically connected to the same common word line and share the same subword line drive signal and the same subword line drive complementary signal; in the memory array tile, the common word lines are numbered along a first direction, and N common word lines with consecutive numbers form one main word line group. The two memory layer groups of each memory area are treated sequentially along the first direction as the first memory layer group and the second memory layer group, and the memory control method is as follows: The steps include selecting one main word line group from each of the first and second storage layer groups based on the main word line drive signal, A step of selecting one of the common word lines from the main word line group selected in the first storage layer group or the main word line group selected in the second storage layer group, based on the subword line drive signal and the subword line drive complementary signal. The steps further include turning on the selected common word line and performing the action indicated by the command address signal, The memory control method according to claim 10.

12. An electronic device comprising a memory according to any one of claims 1 to 8.

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