Data storage device and method for combining a predictive model for readout threshold calibration

Abstract

To provide a data storage device comprising a memory and one or more processors for combining prediction models for read threshold calibration, and a method.SOLUTION: The method combines the outputs of the binary tree model and the linear regression model to generate recommended read thresholds. Binary tree models can describe complex output functions, but can be limited to a finite set of output values, whereas linear regression models provide the best results in both worlds because they have continuous-valued outputs.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] One of the main challenges posed by the scaling of NAND processes and three-dimensional stacking is maintaining process uniformity. In addition, data storage devices may need to support a wide range of operating conditions (such as different program / erase cycles, retention times, and temperatures), which can lead to increased variability between memory dies, blocks, and pages across different operating conditions. Due to these variations, the read threshold (RT) used to read memory pages in some data storage devices is not fixed and can vary significantly as a function of physical location and operating conditions, especially for less mature memory nodes.

Brief Description of the Drawings

[0002] [Figure 1A] A block diagram of a data storage device according to one embodiment. [Figure 1B] A block diagram illustrating a memory module according to one embodiment. [[ID=1​​​​​​​​​​​​​​​​​​​ [Figure 7] This is an illustrative diagram of an implementation of a linear regression model in one embodiment. [Figure 8] This graph shows the results of one embodiment. [Modes for carrying out the invention]

[0003] The following embodiments generally relate to data storage devices and methods for combining predictive models for read threshold calibration. In one embodiment, a data storage device is provided comprising memory and one or more processors. The one or more processors are configured to individually or in combination to input a plurality of previously generated read thresholds into a linear regression model and a binary tree model, input a plurality of features of memory into the binary tree model, generate a recommended read threshold from the outputs of the linear regression model and the binary tree model, and read the memory using the recommended read threshold.

[0004] In another embodiment, a method is provided that is performed in a data storage device having memory. This method includes: inputting previously generated read thresholds into a linear regression model, the linear regression model being configured to output predicted corrections to previously generated read thresholds; inputting a plurality of features relating to memory into a binary symmetric tree model, the binary symmetric tree model being configured to output a plurality of read thresholds; determining a recommended read threshold by combining the previously generated read thresholds output from the linear regression model and the plurality of read thresholds output from the binary symmetric tree model; and reading the memory using the recommended read threshold.

[0005] In yet another embodiment, a data storage device is provided, comprising: a memory; and means for combining the multiple different inference models, each inference model configured to use a different subset of memory features, and combining the predictions of the multiple different inference models to generate a final read threshold.

[0006] Other embodiments are also possible, and each embodiment can be used individually or in combination. Accordingly, various embodiments are described herein with reference to the accompanying drawings.

[0007] Embodiment The following embodiments relate to data storage devices (DSDs). As used herein, “data storage device” refers to a non-volatile device that stores data. Examples of DSDs include, but are not limited to, hard disk drives (HDDs), solid state drives (SSDs), tape drives, and hybrid drives. Illustrative details of DSDs are provided below.

[0008] Examples of data storage devices suitable for use in implementing aspects of these embodiments are shown in Figures 1A and 1C. Note that these are merely examples, and other implementations may be used. Figure 1A is a block diagram illustrating a data storage device 100 according to one embodiment. Referring to Figure 1A, the data storage device 100 in this example includes a controller 102 coupled to a non-volatile memory which may consist of one or more non-volatile memory dies 104. As used herein, the term die refers to a collection of non-volatile memory cells and associated circuits for managing the physical operation of those non-volatile memory cells, formed on a single semiconductor substrate. The controller 102 interfaces with a host system and transmits command sequences for read, program, and erase operations to the non-volatile memory dies 104. Also as used herein, the phrases “communicate with” or “coupled with” may mean directly communicating / coupled, or indirectly communicating / coupled through one or more components, which may or may not be illustrated or described herein. The communication / coupled may be wired or wireless.

[0009] The controller 102 (which may be a non-volatile memory controller (e.g., a flash, resistive random-access memory (ReRAM), phase-change memory (PCM), or magnetoresistive random-access memory (MRAM) controller)) may include, individually or in combination, one or more components configured to perform certain functions, including but not limited to those described herein and illustrated in the flowcharts. For example, as shown in Figure 2A, the controller 102 may include one or more processors 138 configured individually or in combination to perform functions, including but not limited to those described herein and illustrated in the flowcharts, by executing computer-readable program code stored in one or more non-temporary memories 139 (e.g., random access memory (RAM) 116 or read-only memory (ROM) 118) inside and / or outside the controller 102. As another example, one or more components may include, but are not limited to, circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0010] In one exemplary embodiment, the non-volatile memory controller 102 is a device that manages data stored in non-volatile memory and communicates with a host, such as a computer or electronic device having any suitable operating system. In addition to the specific functions described herein, the non-volatile memory controller 102 may have a variety of other functions. For example, the non-volatile memory controller may format the non-volatile memory to ensure that the memory is functioning properly, map out faulty non-volatile memory cells, and allocate spare cells to replace future failed cells. Some portions of the spare cells may be used to operate the non-volatile memory controller and hold firmware (and / or other metadata used for housekeeping and tracking) to implement other features. While operating, the host can communicate with the non-volatile memory controller when it needs to read data from or write data to the non-volatile memory. If the host provides a logical address from which data is read / written, the non-volatile memory controller can translate the logical address received from the host into a physical address in the non-volatile memory. Non-volatile memory controllers can also perform a variety of memory management functions, including, but are not limited to, wear leveling (distributing writes to avoid wearing out specific blocks of memory that would otherwise be repeatedly written to) and garbage collection (moving only valid pages of data to new blocks after a block is full, so that full blocks can be erased and reused).

[0011] The non-volatile memory die 104 may include any suitable non-volatile storage medium, including resistive random-access memory (ReRAM), magnetoresistive random-access memory (MRAM), phase-change memory (PCM), NAND flash memory cells, and / or NOR flash memory cells. The memory cells may take the form of solid-state (e.g., flash) memory cells and may be once programmable, multiple times programmable, or many times programmable. The memory cells may also be single-level cells (SLC), multiple-level cells (MLC) (e.g., dual-level cells, triple-level cells (TLC), quad-level cells (QLC), etc.), or other memory cell level technologies currently known or to be developed may be used. Furthermore, the memory cells may be manufactured in two-dimensional or three-dimensional manner.

[0012] The interface between the controller 102 and the non-volatile memory die 104 may be any preferred flash interface, such as toggle mode 200, 400, or 800. In one embodiment, the data storage device 100 may be a card-based system such as a Secure Digital (SD) or Micro Secure Digital (microSD) card. In another embodiment, the data storage device 100 may be part of an embedded data storage device.

[0013] In the example illustrated in Figure 1A, the data storage device 100 (sometimes referred to herein as a storage module) includes a single channel between the controller 102 and the non-volatile memory die 104; however, the subject matter described herein is not limited to having a single memory channel. For example, in some architectures (such as those shown in Figures 1B and 1C), depending on the capabilities of the controller, two, four, eight or more memory channels may exist between the controller and the memory device. In any of the embodiments described herein, even if a single channel is shown in the drawings, two or more channels may exist between the controller and the memory die.

[0014] Figure 1B illustrates a storage module 200 including a plurality of non-volatile data storage devices 100. Thus, the storage module 200 may include a host and a storage controller 202 that interfaces with a data storage device 204 containing the plurality of data storage devices 100. The interface between the storage controller 202 and the data storage devices 100 may be a bus interface such as a serial advanced technology attachment (SATA), peripheral component interconnect express (PCIe) interface, double-data-rate (DDR) interface, or serial attached small-scale compute interface (SAS / SCSI). In one embodiment, the storage module 200 may be a solid-state drive (SSD) or a non-volatile dual in-line memory module (NVDIMM), as found in server PCs or portable computing devices such as laptop computers and tablet computers.

[0015] Figure 1C is a block diagram illustrating a hierarchical storage system. The hierarchical storage system 250 includes a plurality of storage controllers 202, each controlling its own data storage device 204. A host system 252 can access the memory in the storage system 250 via a bus interface. In one embodiment, the bus interface may be a Non-Volatile Memory Express (NVMe) or Fibre Channel over Ethernet (FCoE) interface. In one embodiment, the system illustrated in Figure 1C may be a rack-mountable mass storage system accessible by multiple host computers, such as those found in data centers or other locations where mass storage is required.

[0016] Referring again to Figure 2A, the controller 102 in this example also includes a front-end module 108 that interfaces with the host, a back-end module 110 that interfaces with one or more non-volatile memory dies 104, and various other components or modules, including, but not limited to, a buffer manager / bus controller module that manages buffers in RAM 116 and controls internal bus arbitration of the controller 102. The modules may include one or more processors or components, as considered above. ROM 118 can store system boot code. Although illustrated separately in Figure 2A, in other embodiments, one or both of RAM 116 and ROM 118 may be located within the controller 102. In yet another embodiment, parts of RAM 116 and ROM 118 may be located both within and outside the controller 102.

[0017] The front-end module 108 includes a host interface 120 and a physical layer interface (PHY) 122 that provide an electrical interface with the host or a next-level storage controller. The choice of host interface 120 may depend on the type of memory being used. Examples of host interface 120 include, but are not limited to, SATA, SATA Express, serially attached small computer system interface (SAS), Fibre Channel, universal serial bus (USB), PCIe, and NVMe. The host interface 120 typically facilitates the transfer of data, control signals, and timing signals.

[0018] The backend module 110 includes an error correction code (ECC) engine 124 that encodes data bytes received from the host and decodes and error-corrects data bytes read from the non-volatile memory. The command sequencer 126 generates command sequences, such as program and erase command sequences, which are sent to the non-volatile memory die 104. The RAID (Redundant Array of Independent Drive) module 128 manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data written to the memory device 104. In some cases, the RAID module 128 may be part of the ECC engine 124. The memory interface 130 provides command sequences to the non-volatile memory die 104 and receives status information from the non-volatile memory die 104. In one embodiment, the memory interface 130 may be a double data rate (DDR) interface, such as a toggle mode 200, 400, or 800 interface. In this example, the controller 102 also includes a media management layer 137 and a flash control layer 132 that controls the overall operation of the backend module 110.

[0019] The data storage device 100 also includes other discrete components 140, such as an external electrical interface, external RAM, resistors, capacitors, or other components that can interface with the controller 102. In an alternative embodiment, one or more of the physical layer interface 122, RAID module 128, media management layer 138, and buffer management / bus controller are optional components that are not required for the controller 102.

[0020] FIG. 2B is a block diagram illustrating the components of the non-volatile memory die 104 in more detail. The non-volatile memory die 104 includes a peripheral circuit 141 and a non-volatile memory array 142. The non-volatile memory array 142 includes non-volatile memory cells used to store data. The non-volatile memory cells can be any suitable non-volatile memory cells including ReRAM, MRAM, PCM, NAND flash memory cells, and / or NOR flash memory cells in a two-dimensional and / or three-dimensional configuration. The non-volatile memory die 104 further includes a data cache 156 that caches data and address decoders 148, 150. The peripheral circuit 141 in this example includes a state machine 152 that provides status information to the controller 102. The peripheral circuit 141 can also include one or more components configured to perform certain functions, including but not limited to, the functions described herein and illustrated in the flowcharts. For example, as shown in FIG. 2B, the memory die 104 can include one or more processors 168 configured individually or in combination to execute computer-readable program code stored in one or more non-transitory memories 169, stored in the memory array 142, or stored outside the memory die 104. As another example, the one or more components can include, without limitation, circuits such as logic gates, switches, application-specific integrated circuits (ASICs), programmable logic controllers, and embedded microcontrollers.

[0021] In addition to, or instead of, one or more processors 138 (or, more generally, components) within controller 102 and one or more processors 168 (or, more generally, components) within memory die 104, data storage device 100 can include another set of one or more processors (or, more generally, components). In general, one or more processors (or, more generally, components) within data storage device 100, regardless of their location and number, can be configured to perform various functions, including but not limited to the functions described herein and illustrated in the flowcharts, either individually or in combination. For example, one or more processors (or components) can be located within controller 102, memory device 104, and / or other locations within data storage device 100. Also, different functions can be performed using different processors (or components) or combinations of processors (or components). Further, the means for performing the functions can be implemented using a controller that includes one or more components (e.g., the processors or other components described above).

[0022] Returning again to FIG. 2A, flash control layer 132 (referred to herein as flash translation layer (FTL)) processes flash errors and interfaces with the host. In particular, the FTL, which can be an algorithm within the firmware, is responsible for the internal memory management and converts writes from the host into writes to memory 104. The FTL can be needed because memory 104 can have limited durability, can only be written to a plurality of pages, and / or cannot be written unless erased as a block. The FTL understands these potential limitations of memory 104 that may not be visible to the host. Thus, the FTL attempts to convert writes from the host into writes to memory 104.

[0023] The FTL may include a logical-to-physical address (L2P) map (sometimes referred to herein as a table or data structure) and allocated cache memory. In this way, the FTL translates logical block addresses ("logical block addresses, LBAs") from the host to physical addresses in memory 104. The FTL may include, but is not limited to, power-off recovery (so that the data structures of the FTL can be recovered in the event of a sudden power loss) and wear leveling (so that wear across memory blocks is uniform to prevent excessive wear on some blocks, which would lead to a greater likelihood of failure).

[0024] Referring again to the drawings, Figure 3 is a block diagram of a host 300 and a data storage device 100 according to one embodiment. The host 300 can take any preferred form, including but not limited to a computer, mobile phone, tablet, wearable device, digital video recorder, surveillance system, etc. The host 300 in this embodiment (here, a computing device) comprises one or more processors 330 and one or more memories 340. In one embodiment, computer-readable program code stored in one or more memories 340 configures one or more processors 330 to perform operations described herein as being executed by the host 300. Thus, actions performed by the host 300 may be referred to herein as being performed by an application (computer-readable program code) running on the host 300. For example, the host 300 may be configured to send data (e.g., initially stored in the host's memory 340) to the data storage device 100 for storage in the memory 104 of the data storage device.

[0025] As mentioned above, one of the main challenges posed by the reduction and three-dimensional stacking of the NAND process is maintaining process uniformity. In addition, data storage devices may need to support a wide range of operating conditions (different program / erase cycles, retention times, and temperatures, etc.), which can lead to increased variability between memory dies, blocks, and pages across different operating conditions. Due to these variability, the read threshold (RT) used to read memory pages within some data storage devices is not fixed and can vary significantly as a function of physical location and operating conditions, especially with respect to newer, less mature memory nodes.

[0026] Reads using inaccurate read thresholds can lead to higher bit error rates (BER), which can degrade performance and quality of service (QoS) due to decoding failures, and may necessitate invoking high-latency recovery flows, resulting in performance delays and hiccups. Maintaining optimal read thresholds can be particularly critical for enterprise memory systems with very stringent quality of service requirements, as well as for mobile, Internet of Things (IoT), and automotive memory systems where the range of required operating conditions is wide and conditional changes (e.g., temperature) can be frequent. This problem is even more challenging during migrations to new, less mature memory nodes.

[0027] Current solutions for read threshold calibration, such as scanning RT for a threshold that induces the smallest estimated bit error rate (also known as BER estimation scan - BES) or generating a cell voltage distribution (CVD) through multiple reads and setting RT to a valley in the CVD (also known as valley search - VS), are high-latency operations aimed at optimizing the read threshold for a particular word line. This is good for infrequent read recovery flows in case of data decoding failure, but may not be suitable for frequent operations in the case of frequent read threshold changes. Therefore, to address this problem, flash memory systems may implement read threshold management schemes that attempt to track changes in the read threshold in the background via a maintenance process to ensure that the appropriate read threshold is used when the host issues a read command.

[0028] One approach is to track read thresholds for each group of blocks that share the same conditions. More specifically, blocks written at approximately the same time and temperature are grouped into time and temperature (TT) groups. Read thresholds are tracked for each time-temperature group and are typically obtained from several representative word lines from the blocks within the group. When the host performs a read operation, the read threshold associated with the time-temperature group corresponding to the read block is used, and any further adaptations to the read threshold by specific read word lines are performed based on a pre-calibrated word line zoning table.

[0029] Some read threshold management schemes may fail to adequately track read thresholds under frequently changing conditions and high variability between memory pages. Various solutions are possible to address this problem. For example, U.S. Patent Application No. 17 / 838,481, filed June 13, 2022, incorporated herein by reference, describes a read threshold calibration method that applies a machine learning (ML) predictive model, specifically including a system and method for inferring an optimal read threshold from various available information, including time and temperature group information, temperature information, bit error rate (BER) information, program-erase count (PEC) information, and physical page location.

[0030] As another example, U.S. Patent Applications No. 17 / 899,073 filed August 30, 2022, No. 18 / 220,363 filed July 11, 2023, and No. 18 / 242,061 filed September 5, 2023, incorporated herein by reference, describe a method enabling an implementation of an inference engine for faster and more accurate acquisition of read thresholds. In one embodiment described therein, a binary tree model is used to efficiently store only a subset of the relevant correction data. Furthermore, it does not require direct reading from memory to perform threshold calibration and is therefore much faster than BES / VS-based calibration. The unique structure of the binary tree enables a fast, low-area, and low-power solution.

[0031] Furthermore, U.S. Patent Application No. 18 / 658,074, filed 8 May 2024, incorporated herein by reference, describes a hardware implementation. Hardware implementations can impose strict limitations on the complexity of the implemented predictive model. Therefore, a set of efficient predictive model-based symmetric trees can be used, as described in the references to the aforementioned patent application. However, while symmetric predictive tree models may be capable of describing complex nonlinear functions of input features, they may have the inherent drawback of being discrete (discontinuous). This property of random forest models can limit predictive accuracy because they have only a finite number of potential output values. The impact of this limitation on model performance can increase as hardware requirements become more stringent.

[0032] Linear regression (LR) is a statistical model that estimates a linear relationship between a scalar response and one or more explanatory variables (also known as dependent and independent variables). In linear regression, the relationship is modeled using a linear predictive function in which unknown model parameters are estimated from the data. The advantage of linear regression in this context is its ability to describe a wide continuous range of output values ​​when the output values ​​are a linear function of the input values. Linear regression can be particularly useful because the identity function can be easily predicted, which often retains an advantage when estimating the optimal readout threshold.

[0033] As mentioned above, the basic hardware implementations of tree model-based predictive models can be limited by their discrete nature (i.e., having a finite, limited number of arbitrarily selected outputs). The following embodiments recognize that it may be beneficial to improve the capabilities of this predictive model without requiring the addition of large and complex hardware. The following embodiments can achieve this goal by combining predictions of different model types, namely, symmetric trees, random forest models (which are nonlinear, discrete, and relatively simple to implement in hardware), and simple continuous models such as linear regression models. This leverages the capabilities of the random forest model (in its symmetric tree configuration, as described above) by combining a nonlinear tree model with another simplified linear regression predictive model. Such a model configuration allows the readout threshold calibration model to provide continuous outputs while still maintaining the efficiency provided by the fundamental principles of the symmetric tree model.

[0034] As mentioned above, these embodiments present a novel approach for a hardware engine to perform read threshold calibration by combining two different prediction models: a binary tree hardware module and a simple linear regression model. The first model (e.g., a random forest with a symmetric tree model) is a powerful nonlinear model that can be implemented in hardware with a relatively small footprint, but can be limited to a finite set of output values. The other (linear) model, while having continuous output values, may be oversimplified and unable to describe complex output functions. A combination of both approaches provides a nonlinear continuous model that can offer excellent read threshold calibration capabilities with a low hardware footprint.

[0035] Referring again to the drawings, Figure 4 is a flowchart 400 of a method for training a model that combines both linear regression and tree-based models. This method can be used to tune the model parameters to generate an optimized read threshold. As shown in Figure 4, the controller 102 of the data storage device 100 obtains input features for the entire model (410). Examples of input features include, but are not limited to, physical addresses (page index, WL#, String#, Plane#, ...), program temperature ("Prog-Temp"), read temperature ("Read-Temp"), the difference between the Prog-Temp of a representative word line stored in the TT table and the current Prog-Temp (also referred to as "X-Temp"), NAND cycling level, data retention level (which is also related to cumulative exposure to high temperature and time elapsed since data refresh), and time tag / read audit input read threshold.

[0036] Controller 102 may take a subset of input features to simplify hardware design and for efficiency analysis (420). If readout thresholds currently used in a linear regression model are provided (430), this may provide corrections to those readout thresholds without considering all extraneous information in the system (440). Also, due to the simplicity of the model, extraneous information may not provide significant improvement to the readout thresholds and may even cause some overfitting. All of the corrected amounts of input features are provided to a binary symmetric tree model (450) which outputs a binary tree (460). The outputs of the binary tree and the linear regression model are combined to provide recommended readout thresholds (470).

[0037] Figure 5 is a flowchart 500 of using an inference model provided by one embodiment. As shown in Figure 5, the controller 102 of the data storage device 100 obtains input features (510). Next, the controller 102 may take only a portion of the input features (520). If a readout threshold currently used in a linear regression model is provided (530), the controller 102 can predict a correction to the default readout threshold (540). Alternatively, all input features can be provided to a binary symmetric tree model (550) which outputs a binary tree (560). The outputs of the binary tree and the linear regression model are combined (570) to obtain a recommended readout threshold (580).

[0038] These embodiments can be implemented in any preferred manner, for example, using the hardware implementations shown in Figures 6 and 7. Figure 6 is a schematic design of machine learning hardware in one embodiment. As shown in Figure 6, threshold features 600 are provided to both the linear regression model 620 and the tree model 630, while ordinary features 610 are provided only to the tree model 630. The outputs of both models are combined in a combiner 650 to output a new threshold. Figure 7 is an illustrative diagram of an exemplary hardware implementation of a linear regression model 700 in one embodiment. As considered above, the hardware can include a random forest model and a linear regression model. The linear regression model can be a weighted sum of all computed features, where each THi* in the output is a linear combination of thresholds in the input (e.g., 15 in the example of a quad-level cell (QLC)).

[0039] Figure 8 is a graph showing the results of one embodiment, specifically a sigma plot of the failed bit count (FBC) distribution. The probability of obtaining the corresponding FBC on the x-axis is shown on the y-axis in sigma, where 0-sigma represents the median FBC, and higher sigma represents a rarer FBC. "BES" represents the FBC provided by reading with the optimal threshold, "Reference" represents the reference result, "Symmetric Trees" represents the symmetric tree implementation, and "Linear Regression + Symmetric Trees" represents an exemplary implementation of one embodiment. In the exemplary implementation, only some of the arbitrarily selected features were used as input to the linear regression model, and quantization was applied to the unbiased linear regression model calculation. This graph shows that the resulting FBC distribution provided by using this embodiment is lower than the reference case.

[0040] There are several advantages associated with these embodiments. For example, by combining two different types of predictive models, additional descriptive capability for the continuous output space can be provided. Thereafter, these embodiments can provide improved read thresholds with only a slight addition of hardware complexity. Furthermore, by providing better read thresholds, these embodiments can provide improved throughput, quality of service (QoS), and power consumption, which may be desirable for the operation of data storage devices.

[0041] Finally, as mentioned above, any suitable type of memory can be used. Semiconductor memory devices include volatile memory devices such as dynamic random access memory ("DRAM") or static random access memory ("SRAM") devices, non-volatile memory devices such as resistive random access memory ("ReRAM"), electrically erasable programmable read-only memory ("EEPROM"), flash memory (which can also be considered a subset of EEPROM), ferroelectric random access memory ("FRAM"), and magnetoresistive random access memory ("MRAM"), as well as other semiconductor elements capable of storing information. Each type of memory device may have a different configuration. For example, flash memory devices may be configured in a NAND or NOR configuration.

[0042] Memory devices can be formed from passive and / or active elements in any combination. As a non-limiting example, passive semiconductor memory elements include ReRAM device elements, which in some embodiments include resistivity switching memory elements such as antifuses and phase-change materials, and optionally steering elements such as diodes. Furthermore, as a non-limiting example, active semiconductor memory elements include EEPROM and flash memory device elements, which in some embodiments include elements comprising charge storage regions such as floating gates, conductive nanoparticles, or charge storage dielectric materials.

[0043] Multiple memory elements can be configured so that they are connected in series, or so that each element is individually accessible. As a non-limiting example, a flash memory device with a NAND configuration (NAND memory) typically includes memory elements connected in series. A NAND memory array can be configured so that the array consists of multiple strings of memory, each string consisting of multiple memory elements that share a single bit line and are accessed as a group. Alternatively, memory elements can be configured so that each element is individually accessible (e.g., a NOR memory array). NAND and NOR memory configurations are examples, and memory elements can be configured in other ways.

[0044] Semiconductor memory elements located within and / or on the substrate may be arranged in two or three dimensions, such as in a two-dimensional memory structure or a three-dimensional memory structure.

[0045] In a two-dimensional memory structure, semiconductor memory elements are arranged on a single plane or at the level of a single memory device. Typically, in a two-dimensional memory structure, memory elements are arranged on a plane (e.g., the xz plane) that extends substantially parallel to the main plane of the substrate supporting the memory elements. The substrate may be a wafer on which layers of memory elements are formed or within it, or a carrier substrate to which memory elements are attached after they have been formed. In non-limiting examples, the substrate may include semiconductors such as silicon.

[0046] Memory elements may be arranged in an ordered array, such as multiple rows and / or columns, at the level of a single memory device. However, memory elements may be arranged in an irregular or non-orthogonal configuration. Each memory element may have two or more electrodes or contact lines, such as bit lines and word lines.

[0047] A three-dimensional memory array is arranged such that memory elements occupy multiple planes or multiple memory device levels, thereby forming a three-dimensional structure (i.e., in the x, y, and z directions, where the y direction is substantially perpendicular to the main surface of the substrate, and the x and z directions are substantially parallel to the main surface of the substrate).

[0048] As a non-limiting example, a three-dimensional memory structure may be arranged vertically as a stack of multiple two-dimensional memory devices. As another non-limiting example, a three-dimensional memory array may be arranged as multiple vertical columns (e.g., columns substantially perpendicular to the main plane of the substrate, i.e., extending in the y-direction) where each column has multiple memory elements. The columns may be arranged in a two-dimensional configuration, e.g., in the xz-plane, resulting in a three-dimensional arrangement of memory elements having elements on multiple vertically stacked memory planes. Other configurations of three-dimensional memory elements can also constitute a three-dimensional memory array.

[0049] As a non-restrictive example, in a three-dimensional NAND memory array, memory elements may be joined together to form a NAND string within a single horizontal (e.g., xz) memory device level. Alternatively, memory elements may be joined together to form a vertical NAND string that spans multiple horizontal memory device levels. Other three-dimensional configurations can be envisioned where some NAND strings contain memory elements within a single memory level, and others contain memory elements that span multiple memory levels. Three-dimensional memory arrays can also be designed in NOR and ReRAM configurations.

[0050] Typically, in a monolithic three-dimensional memory array, one or more memory device levels are formed on a single substrate. Optionally, a monolithic three-dimensional memory array may also have one or more memory layers at least partially within a single substrate. In a non-limiting example, the substrate may include a semiconductor such as silicon. In a monolithic three-dimensional array, the layers constituting each memory device level of the array are typically formed on layers of memory device levels beneath the array. However, adjacent memory device level layers in a monolithic three-dimensional memory array may be shared, or there may be intervening layers between the memory device levels.

[0051] In this case as well, the two-dimensional arrays may be formed separately and then packaged together to form a non-monolithic memory device having multiple memory layers. For example, a non-monolithic stacked memory can be constructed by forming memory levels on separate substrates and then stacking the memory levels on top of each other. The substrates may be thinned or removed from the memory device levels before stacking, but since the memory device levels are initially formed on separate substrates, the resulting memory array is not a monolithic three-dimensional memory array. Furthermore, multiple two-dimensional or three-dimensional memory arrays (monolithic or non-monolithic) may be formed on separate chips and then packaged together to form a stacked chip memory device.

[0052] Associated circuitry is typically required for the operation of memory elements and for communication with them. In a non-limiting example, a memory device may have circuitry used to control and drive memory elements to achieve functions such as programming and reading. This associated circuitry may be on the same board as the memory elements and / or on a separate board. For example, a controller for memory read-write operations may be located on a separate controller chip and / or on the same board as the memory elements.

[0053] Those skilled in the art will recognize that the present invention is not limited to the two-dimensional and three-dimensional structures described herein, but encompasses all relevant memory structures within the spirit and scope of the invention as described herein and as understood by those skilled in the art.

[0054] The above detailed description is intended to be understood not as a definition of the present invention, but as an illustrative example of selected forms that the invention may take. Only the following claims, including all equivalents, are intended to define the scope of the claimed invention. Finally, it should be noted that any aspect of the embodiments described herein may be used individually or in combination with others.

Claims

1. A data storage device, Memory and A combination of multiple different inference models, each inference model configured to use a different subset of the memory features, A data storage device comprising means for generating a final readout threshold by combining the predictions of a plurality of different inference models.

2. The data storage device according to claim 1, wherein the features of the memory include features related to the physical address being read and / or features related to the conditions of the memory.

3. The data storage device according to claim 1, wherein the predictions of the first inference model are supplied to the second inference model as part of the input features.

4. The data storage device according to claim 3, wherein the first inference model includes a linear regression model.

5. The data storage device according to claim 4, wherein the second inference model includes a tree-based model.

6. A data storage device, Memory and A system comprising one or more processors, wherein the one or more processors can be operated individually or in combination. Multiple previously generated readout thresholds are input into a linear regression model and a binary tree model. Multiple features of the memory are input into the binary tree model, A recommended readout threshold is generated from the outputs of the linear regression model and the binary tree model. A data storage device configured to read the memory using the recommended read threshold.

7. The data storage device according to claim 6, wherein the binary tree model includes a random forest having a symmetric tree model.

8. The data storage device according to claim 6, wherein the linear regression model includes a weighted sum of the plurality of features of the memory calculated for each of the previously generated read thresholds.

9. The data storage device according to claim 6, wherein one or more processors are further configured to predict corrections to the previously generated read thresholds, individually or in combination.

10. The data storage device according to claim 9, wherein one or more processors are further configured to input the predicted corrections to the previously generated read thresholds into the binary tree model, individually or in combination.

11. The data storage device according to claim 6, wherein the plurality of features of the memory include a program temperature.

12. The data storage device according to claim 6, wherein the plurality of features of the memory include read temperature.

13. The data storage device according to claim 6, wherein the plurality of features of the memory include the difference between the program temperature of a typical word line and the current program temperature.

14. The data storage device according to claim 6, wherein the plurality of features of the memory include the cycling level of the memory.

15. The data storage device according to claim 6, wherein the plurality of features of the memory include a data retention level.

16. The data storage device according to claim 6, wherein the plurality of features of the memory include a time tag / read audit input read threshold.

17. The data storage device according to claim 6, wherein the one or more processors are composed purely of hardware.

18. The data storage device according to claim 6, wherein the memory includes a three-dimensional memory.

19. A method for a data storage device equipped with memory, Inputting a previously generated read threshold into a linear regression model, wherein the linear regression model is configured to output a predicted correction to the previously generated read threshold, The plurality of features relating to the memory are input to a binary symmetric tree model, which is configured to output a plurality of read thresholds. The recommended read threshold is determined by combining the predicted correction to the previously generated read threshold output from the linear regression model and the multiple read thresholds output from the binary symmetric tree model. A method comprising reading the memory using the recommended read threshold.

20. The method according to claim 19, further comprising inputting the predicted correction to the previously generated read threshold into the binary symmetric tree model.

21. The method according to claim 19, wherein the linear regression model includes a weighted sum of the plurality of features of the memory calculated for each of the previously generated read thresholds.

22. The method according to claim 19, wherein the binary symmetric tree model includes a random forest having a symmetric tree model.

23. The method according to claim 19, wherein the plurality of features of the memory include one or more of the following: physical address, program temperature, read temperature, difference between the program temperature of a representative word line and the current program temperature, cycling level of the memory, data retention level, and time tag / read audit input read threshold.

24. The method according to claim 19, wherein the method is performed in a dedicated hardware module within the data storage device.

Images