Semiconductor modules and semiconductor devices

Abstract

To suppress current concentration on some of a plurality of parallel-connected semiconductor elements.SOLUTION: Provided is an electronic circuit in which a plurality of switching elements (MOS1 to MOS4) including a first switching element, and a second switching element having an ON voltage higher than that of the first switching element are connected in parallel. An inductance of a first path (P1') from a first terminal (32) to a second terminal (31) via the first switching element is larger than that of a second path (P2') from the first terminal to the second terminal via the second switching element.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] This invention relates to electronic circuits, semiconductor modules, and semiconductor devices. [Background technology]

[0002] Semiconductor devices have a substrate on which semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors), power MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), and FWDs (Free Wheeling Diodes) are provided, and are used in inverter devices and the like. For example, Patent Document 1 describes a specific configuration of this type of semiconductor device.

[0003] The semiconductor device described in Patent Document 1 has multiple IGBTs and diodes connected in parallel. Because the current is distributed and flows through each of the IGBTs connected in parallel, this semiconductor device is suitable for use in inverter devices that require a large current.

[0004] In the semiconductor device described in Patent Document 1, the metal plate on which the IGBT and diode are mounted is formed to be small. As a result, the parasitic inductance of the metal plate is kept small, and the surge voltage generated when the inverter device is operating is kept small. [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2004-31590 [Overview of the project] [Problems that the invention aims to solve]

[0006] Semiconductor devices such as IGBTs and diodes have manufacturing variations. For example, in Patent Document 1, the forward voltage (VF) of each diode connected in parallel is different, and the on-voltage (VF) of each IGBT connected in parallel is different. ON These also differ from one another. Due to these individual differences, when the inverter device is operated, current concentrates in some diodes and some IGBTs. Some semiconductor elements where the current concentrates will generate more heat than other semiconductor elements, and in some cases, may overheat and be damaged.

[0007] The present invention has been made in view of the above, and one of its objectives is to provide an electronic circuit, a semiconductor module, and a semiconductor device that can suppress the concentration of current in some of a plurality of semiconductor elements connected in parallel. [Means for solving the problem]

[0008] An electronic circuit according to one aspect of the present invention is an electronic circuit in which a plurality of switching elements are connected in parallel, including a first switching element and a second switching element having a higher on-voltage than the first switching element, wherein the inductance of the first path from the first terminal through the first switching element to the second terminal is greater than the inductance of the second path from the first terminal through the second switching element to the second terminal.

[0009] A semiconductor module according to one aspect of the present invention comprises a substrate on which the electronic circuit is mounted, wherein the wiring member of the first path includes a first conductive wire connecting the first terminal or the second terminal arranged on the substrate to the first switching element, and the wiring member of the second path includes a second conductive wire connecting the first terminal or the second terminal arranged on the substrate to the second switching element, wherein the inductance of the first conductive wire is greater than the inductance of the second conductive wire.

[0010] A semiconductor device according to one aspect of the present invention comprises a plurality of semiconductor modules connected in parallel between a pair of terminals, wherein each path from one of the pair of terminals to the other of the pair of terminals, passing through each of the plurality of semiconductor modules, has a larger inductance the more it passes through a semiconductor module with a lower forward voltage. [Effects of the Invention]

[0011] According to one aspect of the present invention, in an electronic circuit, semiconductor module, and semiconductor device, it is possible to suppress the concentration of current in a portion of a plurality of semiconductor elements connected in parallel. [Brief explanation of the drawing]

[0012] [Figure 1] This is a schematic plan view showing a semiconductor module according to one embodiment of the present invention. [Figure 2] This is an equivalent circuit diagram showing a semiconductor module according to one embodiment of the present invention. [Figure 3A] This diagram conceptually shows the length relationship of bonding wires connecting a plurality of diodes connected in parallel and electrodes on a circuit board in one embodiment of the present invention. [Figure 3B] This diagram conceptually shows the length relationship of bonding wires connecting a plurality of diodes connected in parallel and electrodes on a circuit board in one embodiment of the present invention. [Figure 4] This diagram conceptually shows the length relationship of bonding wires connecting a plurality of diodes connected in parallel and electrodes on a circuit board in one embodiment of the present invention. [Figure 5] This diagram conceptually shows the relationship between the cross-sectional areas of bonding wires connecting a plurality of diodes connected in parallel and electrodes on a circuit board in one embodiment of the present invention. [Figure 6] This diagram conceptually shows the relationship between the cross-sectional areas of bonding wires connecting a plurality of diodes connected in parallel and electrodes on a circuit board in one embodiment of the present invention. [Figure 7]This diagram conceptually shows the length relationships of the wiring patterns connected to each of the multiple diodes in one embodiment of the present invention. [Figure 8] This diagram conceptually shows the relative sizes of the cross-sectional areas of the wiring patterns connected to each of the multiple diodes in one embodiment of the present invention. [Figure 9] This diagram conceptually shows the relationship between the lengths and cross-sectional areas of the wiring patterns connected to each of the multiple diodes in one embodiment of the present invention. [Figure 10] This diagram conceptually shows the length relationship of bonding wires connecting a plurality of diodes connected in parallel and electrodes on a circuit board in one embodiment of the present invention. [Figure 11] This figure schematically shows a semiconductor device according to one embodiment of the present invention. [Modes for carrying out the invention]

[0013] The following describes semiconductor modules to which the present invention can be applied. Figures 1 and 2 are a schematic plan view and an equivalent circuit diagram, respectively, showing a semiconductor module 1 according to one embodiment of the present invention. Note that the semiconductor module 1 according to one embodiment of the present invention is merely an example and can be modified as appropriate without limitation.

[0014] As shown in Figure 1, the semiconductor module 1 is applied to a power module, for example, and comprises a base plate 10, a laminated substrate 2 placed on the base plate 10, and a case member 12 that houses the laminated substrate 2.

[0015] The base plate 10 is a metal plate with a rectangular shape in plan view, made of, for example, copper, aluminum, or an alloy thereof, and acts as a heat sink that radiates heat from the laminated substrate 2 and the electronic components mounted thereon to the outside.

[0016] The case member 12 is a rectangular resin frame that conforms to the outer shape of the base plate 10, and is, for example, bonded to the base plate 10. The space surrounded by the base plate 10 and the case member 12 is filled with a sealing resin (not shown). This sealing resin seals the laminated substrate 2 and the electronic components mounted thereon within the aforementioned space.

[0017] The laminated substrate 2 is composed of, for example, a DBA (Direct Bonded Aluminum registered trademark) substrate, a DBC (Direct Bonded Copper registered trademark) substrate, or an AMB (Active Metal Brazing) substrate. The laminated substrate 2 has an insulating layer 20 formed of an insulator such as ceramic, for example, alumina (Al2O3), aluminum nitride (AlN), silicon nitride (Si3N4), or other ceramic material. A first circuit board 21, a second circuit board 22, and a third circuit board 23 are formed on the upper surface of the insulating layer 20. These circuit boards are metal layers such as copper foil and are formed in an island-like manner on the insulating layer 20, electrically insulated from each other.

[0018] The first circuit board 21, the second circuit board 22, and the third circuit board 23 are each provided with a P terminal (positive potential point) 31, a U terminal (intermediate potential point) 32, and an N terminal (negative potential point) 33, respectively, via a bonding material such as solder. The P terminal 31, U terminal 32, and N terminal are external connection terminals that input and output the main current to the semiconductor module 1.

[0019] Multiple electronic components are arranged on the first circuit board 21 and the second circuit board 22 via a bonding material such as solder. Specifically, switching elements MOS1 to MOS4 and diodes SBD1 to SBD4 are arranged on the first circuit board 21 via a bonding material. Switching elements MOS5 to MOS8 and diodes SBD5 to SBD8 are arranged on the second circuit board 22 via a bonding material.

[0020] Switching elements MOS1 to MOS8 are semiconductor switching elements made using, for example, silicon (Si), silicon carbide (SiC), or gallium carbide (GaN), and specifically, power MOSFETs. When switching elements MOS1 to MOS8 are power MOSFETs, they have a drain electrode as the main electrode on the back surface and a gate electrode and a source electrode as the main electrode on the front surface. Switching elements MOS1 to MOS8 may include a body diode that parasitizes the power MOSFET. The body diode is connected in antiparallel to the power MOSFET and has a cathode electrode on the back surface and an anode electrode on the front surface. Switching elements MOS1 to MOS8 may also be switching elements with other structures, such as IGBTs. When switching elements MOS1 to MOS8 are IGBTs, they have a collector electrode as the main electrode on the back surface and a gate electrode and an emitter electrode as the main electrode on the front surface. Furthermore, switching elements MOS1 to MOS8 may be RC (Reverse-Conducting) IGBTs, which integrate the IGBT and diode into a single chip. In this case, the diode is connected in antiparallel to the IGBT, with the cathode electrode on its back and the anode electrode on its front.

[0021] Switching elements MOS1 to MOS4 are connected in parallel. The drain electrodes of switching elements MOS1 to MOS4 are placed on the first circuit board 21 via a bonding material such as solder and are electrically connected to terminal P 31. The source electrodes are electrically connected to the second circuit board 22 via bonding wires and are electrically connected to terminal U 32.

[0022] The gate electrodes of switching elements MOS1 to MOS4 are connected by a single bonding wire. This single bonding wire connecting these gate electrodes is electrically connected to a terminal member 13 embedded in the case member 12. During the period when a voltage exceeding a predetermined threshold is applied from the terminal member 13 to the gate electrodes, switching elements MOS1 to MOS4 are turned on and current flows from the drain electrode to the source electrode. During the period when a voltage exceeding a predetermined threshold is not applied from the terminal member 13 to the gate electrodes, switching elements MOS1 to MOS4 are turned off and the current from the drain electrode to the source electrode is interrupted.

[0023] Switching elements MOS5 to MOS8 are also connected in parallel. The drain electrodes of switching elements MOS5 to MOS8 are placed on the second circuit board 22 via a bonding material such as solder and are electrically connected to the U terminal 32. The source electrodes are electrically connected to the third circuit board 23 via bonding wires and are electrically connected to the N terminal 33.

[0024] The gate electrodes of the switching elements MOS5 to MOS8 are also connected by a single bonding wire. This single bonding wire connecting these gate electrodes is electrically connected to a terminal member 14 embedded in the case member 12 via a control circuit board. During the period when a voltage exceeding a predetermined threshold is applied from the terminal member 14 to the gate electrodes, the switching elements MOS5 to MOS8 are turned on and current flows from the drain electrode to the source electrode. During the period when a voltage exceeding a predetermined threshold is not applied from the terminal member 14 to the gate electrodes, the switching elements MOS5 to MOS8 are turned off and the current from the drain electrode to the source electrode is interrupted. Note that the wiring between the source electrode and the third circuit board 23, and the wiring between the gate electrode and the control circuit board, may be replaced with other conductive wiring materials such as ribbon wires or lead frames, not just bonding wires.

[0025] Diodes SBD1 to SBD8 are diodes made using SiC, specifically Schottky barrier diodes. Diodes SBD1 to SBD8 may be diodes made using Si or SiC. Furthermore, some or all of diodes SBD1 to SBD8 may be replaced with diodes having other structures, such as JBS (junction barrier Schottky) diodes, MPS (Merged PN Schottky) diodes, or PN diodes. In addition, diodes SBD1 to SBD8 may be diodes built into an RC-IGBT. That is, diodes SBD1 to SBD8 are not limited to Schottky barrier diodes, and each may be a diode with a different structure. However, it is preferable that diodes connected in parallel have the same structure. Diodes SBD1 to SBD8 have a cathode electrode as the main electrode on the back surface and an anode electrode as the main electrode on the front surface.

[0026] Diodes SBD1 to SBD4 are multiple diodes connected in parallel, including a first diode and a second diode with a higher forward voltage than the first diode. Diodes SBD5 to SBD8 are also multiple diodes connected in parallel, including a first diode and a second diode with a higher forward voltage than the first diode. Here, forward voltage is the voltage generated when a forward current flows through a diode. For example, it is the voltage generated between the anode and cathode electrodes when the rated current flows from the anode to the cathode.

[0027] Diodes SBD1 to SBD4 are respectively connected in parallel with switching elements MOS1 to MOS4. More specifically, diodes SBD1 to SBD4 are free-wheeling diodes and are respectively connected in anti-parallel with switching elements MOS1 to MOS4. The anode electrodes of diodes SBD1 to SBD4 are electrically connected to U terminal 32, and the cathode electrodes of diodes SBD1 to SBD4 are electrically connected to P terminal 31.

[0028] As shown in FIG. 2, paths P1 to P4 are assigned to each path from U terminal 32 through each of diodes SBD1 to SBD4 to P terminal 31. Each of paths P1 to P4 is respectively composed of each wiring member W1 A ~W4 A that electrically connects U terminal 32 and the anode electrodes of each of diodes SBD1 to SBD4 B ~W4 B and each wiring member W1

[0029] that electrically connects the cathode electrodes of each of diodes SBD1 to SBD4 and P terminal 31. A ~W4 A Inductances parasitic between U terminal 32 and the anode electrodes of each of diodes SBD1 to SBD4 (in other words, each of wiring members W1 A ~W4 A ) are respectively denoted by symbols L1 B ~L4 B and inductances parasitic between the cathode electrodes of each of diodes SBD1 to SBD4 and P terminal 31 (in other words, each of wiring members W1 B ~L4 B ) are respectively denoted by symbols L1

[0030] Each of the wiring members W1 shown in FIG. 2 A ~W4 AAs shown in Figure 1, each includes the wiring patterns on the second circuit board 22 that connect the U terminal 32 to each electrode T1 to T4 on the second circuit board 22, and the bonding wires BW1 to BW4 that connect each electrode T1 to T4 to the anode electrode of each diode SBD1 to SBD4. Each wiring member W1 shown in Figure 2 B ~W4 B As shown in Figure 1, each of these includes the wiring patterns on the first circuit board 21 that connect the cathode electrodes of each diode SBD1 to SBD4 to the P terminal 31. These wiring patterns are omitted from the illustration to avoid complicating the drawing. Note that the bonding wires BW1 to BW4 may be replaced with other conductive wiring materials such as ribbon wires or lead frames.

[0031] Diodes SBD5 to SBD8 are connected in parallel with switching elements MOS5 to MOS8, respectively. More specifically, diodes SBD5 to SBD8 are FWD and are connected in antiparallel to switching elements MOS5 to MOS8, respectively. The anode electrodes of diodes SBD5 to SBD8 are connected to terminal N 33, and the cathode electrodes of diodes SBD5 to SBD8 are connected to terminal U 32.

[0032] As shown in Figure 2, each path from terminal N 33 through diodes SBD5 to SBD8 to terminal U 32 is denoted by symbols P5 to P8. Each path P5 to P8 is connected to the wiring member W5 that connects terminal N 33 to the anode electrode of each diode SBD5 to SBD8. A ~W8 A and each wiring member W5 that connects the cathode electrode of each diode SBD5 to SBD8 to the U terminal 32. B ~W8 B It is composed of.

[0033] Of the paths P5 to P8, the N terminal 33 and the anode electrodes of each diode SBD5 to SBD8 (in other words, each wiring component W5 A ~W8 A The parasitic inductances of ) are each marked with the symbol L5. A ~L8 AAttached, the cathode electrode of each diode SBD5~SBD8 and the U terminal 32 (in other words, each wiring component W5 B ~W8 B The parasitic inductances of ) are each marked with the symbol L5. B ~L8 B Attach it.

[0034] Each wiring component W5 shown in Figure 2 A ~W8 A As shown in Figure 1, each includes the wiring patterns on the third circuit board 23 that connect the N terminal 33 to each electrode T5 to T8 on the third circuit board 23, and the bonding wires BW5 to BW8 that connect each electrode T5 to T8 to the anode electrode of each diode SBD5 to SBD8. Each wiring member W5 shown in Figure 2 B ~W8 B As shown in Figure 1, each of these includes the wiring patterns on the second circuit board 22 that connect the cathode electrodes of each diode SBD5 to SBD8 to the U terminal 32. These wiring patterns are also omitted from the illustration to avoid complicating the drawing. Note that the bonding wires BW5 to BW8 may be replaced with other conductive wiring materials such as ribbon wires or lead frames.

[0035] In Figure 2, the labels BD1 to BD8 are body diodes parasitic to the switching elements MOS1 to MOS8, respectively. As shown in Figure 2, the diodes BD1 to BD8 are connected in antiparallel to the channels of the switching elements MOS1 to MOS8, respectively.

[0036] In the semiconductor module 1 configured in this way, there is a period during which a current flows in the reverse direction from the negative potential side to the positive potential side as each switching element MOS1 to MOS8 is switched on or off. The Schottky barrier diodes SBD1 to SBD8, which are connected in antiparallel to each switching element MOS1 to MOS8, have a forward voltage lower than the body diodes BD1 to BD8, which are parasitic on each switching element MOS1 to MOS8. Therefore, the current from terminal U 32 to terminal P 31 flows through diodes SBD1 to SBD4 as long as the applied voltage does not exceed the forward voltage of diodes BD1 to BD4. The current from terminal N 33 to terminal U 32 flows through diodes SBD5 to SBD8 as long as the applied voltage does not exceed the forward voltage of diodes BD5 to BD8.

[0037] For example, consider a case where the switching elements MOS1 to MOS8 are power MOSFETs made using SiC. In this case, the diodes BD1 to BD8 parasitic on the switching elements MOS1 to MOS8 may experience current degradation, where the forward voltage increases over time, potentially damaging the switching elements MOS1 to MOS8. However, in this embodiment, by connecting diodes SBD1 to SBD8, which have a low forward voltage, in parallel with diodes BD1 to BD8, current is less likely to flow through diodes BD1 to BD8. As a result, current degradation of diodes BD1 to BD8 is suppressed, and the long-term reliability of the switching elements MOS1 to MOS8 is improved.

[0038] Diodes SBD1 to SBD8 have the same structure, but there are individual differences due to manufacturing. Therefore, the forward voltage of diodes SBD1 to SBD8 will vary.

[0039] When multiple diodes are connected in parallel, current typically concentrates on the diode with the lowest forward voltage. If the current from terminal U 32 to terminal P 31 concentrates on the diode with the lowest forward voltage among diodes SBD1 to SBD4, that diode will heat up more than the other diodes due to the current concentration, and in some cases may overheat and be damaged. Similarly, if the current from terminal N 33 to terminal U 32 concentrates on the diode with the lowest forward voltage among diodes SBD5 to SBD8, that diode will heat up more than the other diodes due to the current concentration, and in some cases may overheat and be damaged.

[0040] Therefore, the inventor of this invention focused on the variation in forward voltage between multiple diodes and came up with the present invention. In this embodiment, in order to prevent the damage of the diodes due to the abnormal heat generation described above, the semiconductor module 1 is configured to suppress the concentration of current on some of the diodes.

[0041] More specifically, in this embodiment, to obtain the above configuration, the forward voltages of the four Schottky barrier diodes are measured in advance. The Schottky barrier diode with the lowest forward voltage is placed in path P1, and thereafter, the Schottky barrier diodes are placed in paths P2 to P4 in order of increasing forward voltage. That is, for diodes SBD1 to SBD4, the smaller the sign number, the lower the forward voltage.

[0042] Furthermore, in the semiconductor module 1 according to this embodiment, among the parallel-connected paths P1 to P4, the parasitic inductance is increased in the path where a Schottky barrier diode with a lower forward voltage is located. That is, among the parasitic inductance of paths P1 to P4, path P1 (in other words, wiring member W1 A and W1 B ) Parasitic inductance (inductance L1 A and inductance L1 B This is the sum of the above, and below, "Inductance (L1 A +L1 B) is noted. The parasitic inductance of the other paths is noted similarly. ) is the largest, followed by paths P2~P4 (in other words, wiring member W2 A and W2 B Wiring component W3 A and W3 B Wiring component W4 A and W4 B The parasitic inductance increases in the order of (P1, P4). In other words, for paths P1 to P4, the parasitic inductance is larger the smaller the sign number.

[0043] Thus, the semiconductor module 1 has an electronic circuit configuration in which the inductance of the first path (e.g., path P1) from the first terminal (e.g., terminal U 32) through the first diode (e.g., diode SBD1) to the second terminal (e.g., terminal P 31) is greater than the inductance of the second path (e.g., path P2) from the first terminal through the second diode (e.g., diode SBD2) to the second terminal.

[0044] Furthermore, semiconductor module 1 satisfies at least one of the following conditions (1) to (4) such that the parasitic inductance increases as the sign number of paths P1 to P4 decreases. (1) The bonding wires constituting the path (hereinafter referred to as "first conductive wires") are longer in total length than the bonding wires constituting the path in which a Schottky barrier diode with a higher forward voltage than that path is arranged (hereinafter referred to as "second conductive wires"). (2) The first conductive wire has a smaller cross-sectional area than the second conductive wire. (3) The wiring pattern constituting the path (hereinafter referred to as the "first wiring pattern") is longer in overall length than the wiring pattern constituting the path in which a Schottky barrier diode with a higher forward voltage than that path is placed (hereinafter referred to as the "second wiring pattern"). (4) The first wiring pattern has a smaller cross-sectional area than the second wiring pattern.

[0045] Conditions (1) and (2) indicate the conditions under which the parasitic inductance of the first conductive wire is greater than the parasitic inductance of the second conductive wire. Conditions (3) and (4) indicate the conditions under which the parasitic inductance of the first wiring pattern is greater than the parasitic inductance of the second wiring pattern.

[0046] Figures 3A, 3B, and 4 conceptually illustrate condition (1). As shown in Figures 3A, 3B, and 4, the bonding wires BW1 to BW4 have longer overall lengths as the number in their designation decreases.

[0047] In the example shown in Figure 3A, diodes SBD1 to SBD4 are arranged in a single row in this order on the first circuit board 21. The second circuit board 22 is formed on the side closer to diode SBD4, which has a higher forward voltage. Each diode SBD1 to SBD4 is electrically connected to electrodes T1 to T4 on the second circuit board 22 via bonding wires BW1 to BW4. That is, each diode SBD1 to SBD4 is positioned so that the smaller the sign number (the lower the forward voltage of the diode), the greater the distance from the connected electrodes T1 to T4. Therefore, bonding wires BW1 to BW4 have a longer overall length as the sign number decreases. For example, bonding wire BW1, which constitutes path P1 where diode SBD1 is located, is longer than bonding wire BW2, which constitutes path P2 where diode SBD2, which has a higher forward voltage than diode SBD1, is located. Consequently, bonding wires BW1 to BW4 have a larger parasitic inductance as the sign number decreases. Therefore, for each path P1 to P4, including each bonding wire BW1 to BW4, the smaller the sign number, the larger the parasitic inductance.

[0048] Figure 3B shows a modified example of the example shown in Figure 3A. In the example shown in Figure 3B, diodes SBD1, SBD3, SBD4, and SBD2 are arranged in a row in this order on the first circuit board 21. The second circuit board 22 is formed at a position slightly shifted from the center of the first circuit board 21 towards diode SBD4. In the example shown in Figure 3B, as in the example shown in Figure 3A, each diode SB1 to SBD4 is arranged such that the smaller the sign number (the lower the forward voltage of the diode), the greater the distance from the connected electrodes T1 to T4. Therefore, the bonding wires BW1 to BW4 have a longer overall length and larger parasitic inductance the smaller the sign number. Consequently, each path P1 to P4 including each bonding wire BW1 to BW4 has a larger parasitic inductance the smaller the sign number.

[0049] In the example shown in Figure 4, diodes SBD1 to SBD4 are arranged in this order in a single row on the first circuit board 21. The second circuit board 22 is formed adjacent to the first circuit board 21. As shown in the plan view of Figure 4, the distance between each diode SBD1 to SBD4 and each electrode T1 to T4 is equal in the plan view. On the other hand, as shown in the plan view and side view of Figure 4, the bonding wires BW1 to BW4 are wired with a gentle bend, and the smaller the sign number (the lower the forward voltage of the diode), the greater the bend (curvature) (smaller radius of curvature). In other words, the smaller the sign number of the bonding wires BW1 to BW4, the greater the bend and the longer their total length, resulting in a larger parasitic inductance. Therefore, each path P1 to P4, including each bonding wire BW1 to BW4, has a larger parasitic inductance with a smaller sign number.

[0050] Figures 5 and 6 conceptually illustrate condition (2). In the examples shown in Figures 5 and 6, diodes SBD1 to SBD4 are arranged in a single row in that order on the first circuit board 21, similar to the example in Figure 4. The second circuit board 22 is formed adjacent to the first circuit board 21. Unlike the examples in Figures 3A, 3B, and 4, the total length of each bonding wire BW1 to BW4 is the same.

[0051] As shown in Figures 5 and 6, bonding wires BW1 to BW4 have smaller cross-sectional areas as their sign numbers decrease. Specifically, in the example in Figure 5, each bonding wire BW1 to BW4 consists of a single wire, and the smaller the sign number (the lower the forward voltage of the diode), the thinner the wire diameter and the smaller the cross-sectional area. In the example in Figure 6, each bonding wire BW1 to BW4 consists of multiple wires of the same diameter, and the smaller the sign number (the lower the forward voltage of the diode), the fewer wires there are and the smaller the total cross-sectional area. In other words, in both examples in Figures 5 and 6, bonding wires BW1 to BW4 have smaller cross-sectional areas and larger parasitic inductances as their sign numbers decrease. Therefore, each path P1 to P4, including each bonding wire BW1 to BW4, has a larger parasitic inductance as its sign number decreases.

[0052] Figure 7 is a diagram that conceptually illustrates condition (3). In the example of Figure 7, as in the example of Figure 4, diodes SBD1 to SBD4 are arranged in a single row in this order on the first circuit board 21. In the example of Figure 7, the distance between each diode SBD1 to SBD4 and the P terminal 31 is different. Specifically, for each diode SBD1 to SBD4, the smaller the sign number (the lower the forward voltage of the diode), the greater the distance from the P terminal 31, and the longer the wiring pattern formed on the first circuit board 21 between the diode and the P terminal 31. Therefore, the wiring patterns on the first circuit board 21 that constitute paths P1 to P4 have a longer overall length and larger parasitic inductance for the paths that consist of diodes SBD1 to SBD4 with smaller sign numbers. Consequently, for each path P1 to P4, the smaller the sign number, the larger the parasitic inductance.

[0053] Figure 8 is a diagram conceptually illustrating condition (4). Note that the arrows shown in Figure 8 and the later-described Figures 9 and 10 are added for explanatory purposes only and do not indicate constituent elements. In the example in Figure 8, terminal P 31 is placed in the center of the first circuit board 21 via a bonding material such as solder. Each diode SBD1 to SBD4 is arranged on all four sides of terminal P 31, and the distance from terminal P 31 is equal. Multiple slits 41 to 46 of different widths are formed in the first circuit board 21. Each slit 41 to 44 is formed between each diode SBD1 to SBD4 and terminal P 31, with the smaller the sign number, the wider the slit. Slit 45 is formed between diode SBD1 and diode SBD3, and slit 46 is formed between diode SBD2 and diode SBD4. Slits 45 and 46 are narrower than slit 42 and wider than slit 43. By forming these slits 41-46 on the first circuit board 21, the wiring patterns that form paths with diodes SBD1-SBD4 having smaller sign numbers have smaller average cross-sectional areas between each diode SBD1-SBD4 and the P terminal 31, resulting in larger parasitic inductances. Therefore, for each path P1-P4, the smaller the sign number, the larger the parasitic inductance.

[0054] Figure 9 is a conceptual diagram showing the combination of conditions (3) and (4). In the example shown in Figure 9, diodes SBD1, SBD3, SBD4, and SBD2 are arranged in a row in this order on the first circuit board 21. Also, a P terminal 31 is placed near the center of the first circuit board 21 via a bonding material such as solder. Diodes SBD1 and SBD2 are at the same distance from the P terminal 31. Diodes SBD3 and SBD4 are at the same distance from the P terminal 31, and are at a shorter distance from the P terminal 31 than diodes SBD1 and SBD2. In addition, slits 51 to 54 of equal width are formed in close proximity to each of the diodes SBD1 to SBD4. By forming these slits 51 to 54 on the first circuit board 21, the wiring pattern on the first circuit board 21 has a smaller average cross-sectional area and larger parasitic inductance for the wiring pattern that forms the path where diode SBD1 or SBD3 is placed than for the wiring pattern that forms the path where diode SBD2 or SBD4 is placed.

[0055] In other words, in the example shown in Figure 9, although diodes SBD1 and SBD2 are at the same distance from terminal P 31, the average cross-sectional area of ​​the wiring pattern that makes up the path where diode SBD1 is located is smaller. Therefore, the parasitic inductance of path P1 where diode SBD1 is located is larger than that of path P2 where diode SBD2 is located.

[0056] The distance between diodes SBD3 and SBD4 and terminal P 31 is shorter than the distance between diodes SBD1 and SBD2 and terminal P 31. Although diodes SBD3 and SBD4 are the same distance from terminal P 31, the average cross-sectional area of ​​the wiring pattern in the path where diode SBD3 is located is smaller. Therefore, the parasitic inductance of path P3 where diode SBD3 is located is smaller than that of paths P1 and P2, and the parasitic inductance of path P4 where diode SBD4 is located is larger.

[0057] Thus, in the example shown in Figure 9, the parasitic inductance of each path P1 to P4 increases as the sign number decreases.

[0058] The path from terminal U 32 in Figure 1 to terminal P 31 via diodes SBD1 to SBD4 is a combination of conditions (1) and (3). Similarly, the path from terminal N 33 in Figure 1 to terminal U 32 via diodes SBD5 to SBD8 is also a combination of conditions (1) and (3).

[0059] Specifically, as shown in Figure 1, bonding wires BW1 to BW4 have longer overall lengths and greater parasitic inductances as their sign numbers decrease. Also, for each diode SBD1 to SBD4, the smaller the sign number (the lower the forward voltage of the diode), the greater the distance from the P terminal 31, and the longer the wiring pattern formed on the first circuit board 21 between the diode and the P terminal 31. Therefore, the wiring patterns on the first circuit board 21 that constitute paths P1 to P4 have longer overall lengths and greater parasitic inductances as the paths containing diodes SBD1 to SBD4 with smaller sign numbers are arranged. As a result, each path P1 to P4 has a larger parasitic inductance as its sign number decreases.

[0060] Similarly, for bonding wires BW5 to BW8, the smaller the sign number, the longer the overall length and the greater the parasitic inductance. Also, for each diode SBD5 to SBD8, the smaller the sign number (the lower the forward voltage of the diode), the greater the distance from terminal P 31, and the longer the wiring pattern between it and terminal U 32 formed on the second circuit board 22. Therefore, the wiring patterns on the second circuit board 22 that constitute paths P5 to P8 are longer in overall length and have greater parasitic inductance for the paths where diodes SBD5 to SBD8 with smaller sign numbers are arranged. As a result, for each path P5 to P8, the smaller the sign number, the greater the parasitic inductance.

[0061] Note that the semiconductor module 1 does not need to satisfy all of conditions (1) to (4). For example, even if the total length of bonding wire BW2 is longer than the total length of bonding wire BW1, the wiring member W1 can satisfy at least one of conditions (2) to (4) so ​​that the parasitic inductance of the entire path P1 is greater than the parasitic inductance of the entire path P2. A W2 A W1 B and W2 B It is sufficient if it is formed.

[0062] Thus, conditions (1) to (4) are given as examples. The semiconductor module 1 only needs to have a parasitic inductance that is larger for paths with smaller sign numbers, and it may not have a configuration that satisfies all of conditions (1) to (4).

[0063] The current from terminal U 32 to terminal P 31 begins to flow through the path where the Schottky barrier diode with the lowest forward voltage among paths P1 to P4 is located (i.e., path P1). As the current flowing through path P1 changes (increases), the wiring component W1 A and W1 B Parasitic inductance (L1 A +L1 B A back electromotive force proportional to the current is generated in path P1. This back electromotive force makes it difficult for current to flow through path P1. In other words, current flows more easily through paths P2 to P4.

[0064] If the current increases in path P2, wiring member W2 A and W2 B Parasitic inductance (L2 A +L2 B A back electromotive force proportional to the current is generated in path P2, making it difficult for current to flow through path P2. Therefore, current is more likely to flow through paths P3 and P4 than through path P2. The same phenomenon occurs in path P3 as the current increases, so current is more likely to flow through path P4 than through path P3.

[0065] As the rate of change of the current flowing through each path P1 to P4 decreases, the back electromotive force generated in each path P1 to P4 also decreases. When the current flowing through each path P1 to P4 converges to a constant value, the back electromotive force in each path P1 to P4 also becomes zero. In this steady state, a uniform current flows through each path P1 to P4.

[0066] In this way, by shaping the wiring components for each path such that the parasitic inductance increases for paths passing through Schottky barrier diodes with lower forward voltages, the current from terminal U 32 to terminal P 31 is quickly distributed to each of the parallel-connected paths P1 to P4, suppressing current concentration in some paths (for example, path P1). Therefore, abnormal heat generation and damage to semiconductor elements such as Schottky barrier diodes due to current concentration are prevented.

[0067] Similarly, diodes SBD5 to SBD8 have lower forward voltages as their sign numbers decrease, and paths P5 to P8 have larger parasitic inductances as their sign numbers decrease. Therefore, in paths P5 to P8, as in paths P1 to P4, the current is quickly distributed, and current concentration in some paths is suppressed.

[0068] By suppressing abnormal heat generation in some semiconductor elements due to current concentration, the rated current of semiconductor module 1 can be increased. Furthermore, this current concentration suppression effect becomes more pronounced as the number of parallel-connected diodes increases.

[0069] Next, a specific embodiment will be described. Figure 10 is a conceptual diagram showing the length relationship of bonding wires connecting multiple diodes connected in parallel to electrodes on a circuit board. In this embodiment, for convenience, only the relationship between path P1 and path P2 will be described.

[0070] In this embodiment, paths P1 and P2 satisfy only condition (1) of conditions (1) to (4). That is, paths P1 and P2 in this embodiment have the same configuration except that the total lengths of bonding wire BW1 and bonding wire BW2 are different. In other words, the parasitic inductances of paths P1 and P2 differ only depending on the difference in total length between bonding wires BW1 and BW2.

[0071] Let "I1" and "I2" be the currents flowing through paths P1 and P2, respectively, and let "VF1" and "VF2" be the forward voltages of diodes SBD1 and SBD2, respectively, and let "t" be the time. In this case, the concentration of current in path P1 is suppressed by satisfying the relationship shown in equation (1) below.

[0072] VF1+(L1 A +L1 B )dI1 / dt=VF2+(L2 A +L2 B )dI2 / dt···(1)

[0073] Let the forward voltages of diodes SBD1 and SBD2 be X±Y (V: volts) according to their specifications, and let their measured values ​​be XY (V) and X+Y (V), respectively. In this embodiment, a current of α (A: amperes) is passed through paths P1 and P2 for β (ns: nanoseconds). Substituting the values ​​given in this example into equation (1) above, we obtain equation (2). Furthermore, equation (3) is obtained from equation (2).

[0074] -2Y(V)={(L2 A +L2 B )-(L1 A +L1 B )} × α(A) / β(ns)···(2) (L1 A +L1 B )-(L2 A +L2 B ) = 2Y × β / α (nH: nanohenry) ... (3)

[0075] As shown in equation (3) above, the parasitic inductance of path P1 (L1 A +L1B ) parasitic inductance (L2) of path P2 A +L2 B By making it 2Y × β / α (nH) larger than ), current concentration in path P1 is suppressed.

[0076] For example, parasitic inductance (L2 A +L2 B Let's consider the case where the parasitic inductance (L1) is 12nH. In this case, the total length of bonding wire BW2 is made 10% shorter than the total length of bonding wire BW1. This reduces the parasitic inductance (L1) A +L1 B ) is parasitic inductance (L2 A +L2 B This becomes 0.12 nH greater than ).

[0077] In the above embodiment, the number and placement of switching elements and diodes on the laminated substrate 2 are not limited to the above configuration and can be changed as appropriate.

[0078] In the above embodiment, the number and layout of circuit boards on the insulating layer 20 are not limited to the above configuration and can be changed as appropriate.

[0079] In the above embodiment, the parasitic inductance of all parallel-connected paths is defined (specifically, the parasitic inductances are larger in the order of paths P1 to P4 (or P5 to P8)), but the effect of suppressing current concentration in some paths can be obtained by defining the parasitic inductance of at least two paths (for example, making the parasitic inductance of path P1 larger than that of path P2).

[0080] In the above embodiment, the parasitic inductance in a predetermined path of the diode is set to the inductance on the anode electrode side (for example, L1 A ) and the inductance on the cathode electrode side (for example, L1 BIt was configured to be represented by the sum of B - W4 B The inductance L1 B - L4 B of the wiring members W1 A - W4 A connected electrically to the cathode electrode is made equal, and the inductance L1 A - L4 A of the wiring members W1

[0081] connected electrically to the anode electrode may be made larger as the numerical value of the symbol is smaller. The anode electrode appears on the surface side of the semiconductor module 1, and it is possible to easily adjust the inductance by changing the wiring length etc. of the bonding wires BW1 to BW4. Note that the adjustment of the inductance between the diodes is not limited to the wiring members on the anode electrode side, and may be adjusted by the wiring members on the cathode electrode side. ON ).

[0082] Therefore, in the above embodiment, the switching element with the lowest on-voltage is arranged as the switching element MOS1, and thereafter, the switching elements with lower on-voltages are arranged as the switching elements MOS2 to MOS4 in order. That is, the switching elements MOS1 to MOS4 are arranged such that the on-voltage becomes lower as the numerical value of the symbol is smaller.

[0083] In this configuration, where switching elements MOS1 to MOS4 are arranged, the wiring members are formed such that the parasitic inductance of each path P1' to P4' from terminal P 31 through each switching element MOS1 to MOS4 to terminal U 32 is larger for paths passing through switching elements with smaller sign numbers. As a result, the current is quickly distributed through each path P1' to P4', and current concentration in some paths is suppressed.

[0084] The switching elements MOS5 to MOS8 may also be configured such that the smaller the sign number, the lower the on-voltage, and the smaller the sign number, the larger the parasitic inductance of each path P5' to P8' from terminal U 32 through each switching element MOS5 to MOS8 to terminal N 33. With this configuration, the current is quickly distributed in paths P5' to P8', similar to paths P1' to P4', and current concentration in some paths is suppressed.

[0085] In other words, the semiconductor module 1 is an electronic circuit in which a plurality of switching elements are connected in parallel, including a first switching element (e.g., switching element MOS1) and a second switching element (e.g., switching element MOS2) having a higher on-voltage than the first switching element, in order to suppress current concentration on some switching elements, and the inductance of the first path from the first terminal (e.g., terminal P31) through the first switching element to the second terminal (e.g., terminal U32) is greater than the inductance of the second path from the first terminal through the second switching element to the second terminal.

[0086] In the above embodiment, the wiring members are formed such that the parasitic inductance increases as the sign number of the paths P1 to P4 decreases. However, in another embodiment, inductance elements with different inductances (for example, inductors with cores having different permeability) may be arranged in each path P1 to P4 such that the inductance increases as the sign number of the paths P1 to P4 decreases.

[0087] FIG. 11 is a diagram schematically showing a semiconductor device 100 according to an embodiment of the present invention. This semiconductor device 100 includes semiconductor modules 1A and 1B connected in parallel. The semiconductor modules 1A and 1B have the same configuration as the semiconductor module 1 according to the above-described embodiment. In FIG. 4, for convenience, the semiconductor module 1A is shown as a block having a P terminal 31A and an N terminal 33A, and the semiconductor module 1B is shown as a block having a P terminal 31B and an N terminal 33B.

[0088] The P terminals 31A and 31B are electrically connected to a positive potential point 200A (one of a pair of terminals) on the positive electrode side of the power supply 200. The N terminals 33A and 33B are electrically connected to a negative potential point 200B (the other of a pair of terminals) on the negative electrode side of the power supply 200. A path from the positive potential point 200A through the semiconductor module 1A to the negative potential point 200B is denoted by a reference symbol P A 1. A path from the positive potential point 200A through the semiconductor module 1B to the negative potential point 200B is denoted by a reference symbol P B 1 as well.

[0089] There are variations in the forward voltage of the entire semiconductor module 1A and the forward voltage of the entire semiconductor module 1B. Therefore, there is a concern that current may concentrate in the semiconductor module with a lower forward voltage. Thus, the semiconductor device 100 is configured such that the inductance is larger for a path passing through a semiconductor module with a lower forward voltage.

[0090] In this example, the forward voltage of the semiconductor module 1A is lower than the forward voltage of the semiconductor module 1B, and the parasitic inductance of the path P A 1 is larger than the parasitic inductance of the path P B 1.

[0091] Current starts to flow through the path P A 1 in which the semiconductor module 1A with a lower forward voltage is arranged. As the current flowing through the path P A 1 changes (increases), a back electromotive force proportional to the parasitic inductance of the wiring member of the path P A 1 is generated in the path P AThis occurs in path P1. A Current becomes less likely to flow through path P1. In other words, the current flows through path P1. B It becomes easier for current to flow through path P1. In other words, the current flows through the parallel-connected path P1. A and route P1 B It is quickly distributed to route P1 A Current concentration is suppressed. Therefore, in this example as well, abnormal heat generation and damage to semiconductor elements such as Schottky barrier diodes due to current concentration are prevented.

[0092] Figure 11 shows a semiconductor device in which two semiconductor modules are connected in parallel, but semiconductor devices in which three or more semiconductor modules are connected in parallel are also within the scope of the present invention.

[0093] Although this embodiment and its variations have been described, other embodiments may be combinations of the above embodiment and its variations, either entirely or partially.

[0094] Furthermore, this embodiment is not limited to the embodiments and modifications described above, and may be modified, substituted, or transformed in various ways without departing from the spirit of the technical idea. Moreover, if the technical idea can be realized in a different way by advances in the technology or by other derived technologies, it may be implemented by that method. Accordingly, the claims cover all embodiments that may fall within the scope of the technical idea.

[0095] The key features of the above embodiment are summarized below.

[0096] The electronic circuit described in the above embodiment is an electronic circuit in which a plurality of switching elements are connected in parallel, including a first switching element and a second switching element having a higher on-voltage than the first switching element, wherein the inductance of the first path from the first terminal through the first switching element to the second terminal is greater than the inductance of the second path from the first terminal through the second switching element to the second terminal.

[0097] The semiconductor module described in the above embodiment includes a substrate on which the electronic circuit is mounted, the wiring member of the first path includes a first conductive wire connecting the first terminal or the second terminal arranged on the substrate to the first switching element, and the wiring member of the second path includes a second conductive wire connecting the first terminal or the second terminal arranged on the substrate to the second switching element, wherein the inductance of the first conductive wire is greater than the inductance of the second conductive wire.

[0098] The semiconductor module described in the above embodiment satisfies at least one of the following conditions (1) to (2): (1) The first conductive wire is longer in overall length than the second conductive wire. (2) The first conductive wire has a smaller cross-sectional area than the second conductive wire.

[0099] In the semiconductor module described above, the wiring member of the first path includes a first wiring pattern connecting the first terminal or the second terminal arranged on the substrate to the first switching element, and the wiring member of the second path includes a second wiring pattern connecting the first terminal or the second terminal arranged on the substrate to the second switching element, wherein the inductance of the first wiring pattern is greater than the inductance of the second wiring pattern.

[0100] The semiconductor module described in the above embodiment satisfies at least one of the following conditions (3) to (4): (3) The first wiring pattern is longer in overall length than the second wiring pattern. (4) The first wiring pattern has a smaller cross-sectional area than the second wiring pattern.

[0101] In the semiconductor module described in the above embodiment, the plurality of switching elements are switching elements having the same structure.

[0102] In the semiconductor module described above, the plurality of switching elements are switching elements made using silicon carbide (SiC).

[0103] The semiconductor device described in the above embodiment comprises a plurality of semiconductor modules connected in parallel between a pair of terminals, and each path from one of the pair of terminals to the other of the pair of terminals, passing through each of the plurality of semiconductor modules, has a larger inductance the more it passes through a semiconductor module with a lower forward voltage. [Industrial applicability]

[0104] As described above, the present invention has the effect of suppressing the concentration of current in some of a plurality of semiconductor elements connected in parallel, and is particularly useful for electronic circuits, semiconductor modules, and semiconductor devices. [Explanation of Symbols]

[0105] 1: Semiconductor module 2: Multilayer substrate 10: Base plate 12: Case components 13,14: Terminal members 20: Insulating layer 21 :1st circuit board 22: 2nd circuit board 23:Third circuit board 31 :P terminal (positive potential point) 32: U terminal (intermediate potential point) 33 :N terminal (negative potential point) BD1~BD8: Diodes BW1~BW8: Bonding wires L1 A ~L8 A ,L1 B ~L8 B :Inductance MOS1~MOS8: Switching elements P1~P8: Route SBD1~SBD8: Diodes T1~T8: Electrode W1 A ~W8 A ,W1 B ~W8 B : Wiring components

Claims

1. An electronic circuit comprising a first switching element and a second switching element having a higher on-voltage than the first switching element, wherein multiple switching elements with manufacturing variations are connected in parallel between a first terminal and a second terminal, A circuit board on which the aforementioned electronic circuit is mounted, A circuit board comprising a metal layer arranged on the substrate, wherein one side of each of the first switching element and the second switching element is connected to the circuit board, Equipped with, A semiconductor module in which a plurality of slits are formed on the circuit board path, thereby partially reducing the cross-sectional area of ​​the circuit board, such that the inductance of the first path from the first terminal through the first switching element to the second terminal is greater than the inductance of the second path from the first terminal through the second switching element to the second terminal.

2. Conductive wires are connected to the other side of the first switching element and the second switching element, The semiconductor module according to claim 1, wherein the inductance of the conductive wire connected to the other side of the first switching element is greater than the inductance of the conductive wire connected to the other side of the second switching element.

3. Satisfying at least one of the following conditions (1) to (2): (1) The conductive wire of the first switching element is longer in overall length than the conductive wire of the second switching element. (2) The semiconductor module according to claim 2, wherein the conductive wire of the first switching element has a smaller cross-sectional area than the conductive wire of the second switching element.

4. The semiconductor module according to claim 2 or 3, wherein the plurality of switching elements are switching elements having the same structure.

5. The semiconductor module according to any one of claims 2 to 4, wherein the plurality of switching elements are switching elements made using silicon carbide (SiC).

6. A semiconductor module according to any one of claims 2 to 5, comprising a plurality of semiconductor modules connected in parallel between a pair of terminals, A semiconductor device in which each path from one of the pair of terminals to the other of the pair of terminals, passing through each of the plurality of semiconductor modules, has a larger inductance the path passes through a semiconductor module with a lower forward voltage.

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