Compilation device, compilation method, and program

Abstract

To generate a highly efficient purpose program without requiring a user to rewrite a source program.SOLUTION: A compile device (30) according to the present disclosure includes: a detection unit (31) for detecting first processing of adding the product of the elements of two sequences using a double loop in a source program (21) written in a high-level language; and an optimization unit (32) for converting the detected first processing into a vector-operable form and generating a purpose program (22).SELECTED DRAWING: Figure 12

Description

Technical Field

[0001] The present disclosure relates to a compilation device, a compilation method, and a program.

Background Art

[0002] A compilation device translates a source program written in a high-level language such as the C language to generate an object program. In particular, a compilation device for a vector processor generates an object program including vector instructions that can be vector-operated from a source program.

[0003] In a compilation device for a vector processor according to related art, conversion to vector instructions is possible only for loops explicitly specified by a user (programmer) using directive lines or loops for which a compilation device can resolve the dependency of the execution order between loops.

[0004] Patent Document 1 describes a method in which a compilation device detects not only explicit loops such as a for loop in the C language or a DO loop in the Fortran language but also loops using a goto statement and automatically converts these loops to vector instructions.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, in the method described in Patent Document 1, when translating a source program as shown in FIG. 1, the loops in the source program are not regarded as being vector-operable, and an object program that is executed by scalar instructions is generated, which may cause a problem that the computational performance of the vector processor cannot be fully utilized.

[0007] This is because, in the source program shown in Figure 1, reading and writing are performed on a single variable `sum` between nested loops, and therefore the method described in Patent Document 1 cannot resolve the dependencies between iterations. The source program shown in Figure 1 uses a for statement to perform a double loop process, calculates the product of all combinations of elements in two arrays a and b, and assigns the sum of these products to the variable `sum`.

[0008] Therefore, for source programs like the one shown in Figure 1, it is necessary to rewrite the source program into a form that can perform vector operations. Furthermore, the computational complexity of the source program shown in Figure 1 is proportional to the product of the lengths of each array. Therefore, it is necessary to rewrite this source program into a form that can perform vector operations, thereby converting it into a more efficient calculation method that is proportional to the sum of the lengths of each array. However, the task of rewriting the source program shown in Figure 1 into a form that requires less computation and allows vector operations had to be done manually by the user. This presented a problem in that it could lead to user errors during the rewriting process.

[0009] Therefore, the purpose of this disclosure is to provide a compilation device, a compilation method, and a program that can generate a highly efficient target program without the user having to rewrite the source program, in light of the above-mentioned problems. [Means for solving the problem]

[0010] A compilation device according to one embodiment is: A detection unit that detects a first process in a source program written in a high-level language, which uses a nested loop to add up the products of each element of two arrays, An optimization unit that converts the detected first process into a form that can be processed by vector operations and generates a target program, It is equipped with.

[0011] One compilation method is: A compilation method executed by a compilation device, A detection step to detect a first process in a source program written in a high-level language that uses a nested loop to sum the products of each element of two arrays, An optimization step of converting the detected first process into a form that can be operated on by vector operations to generate an objective program, Includes.

[0012] A program according to one aspect is: To the compilation device, A detection procedure for detecting a first process in a source program written in a high-level language that uses a nested loop to sum the products of each element of two arrays, An optimization procedure that converts the detected first process into a form that can be operated on by vector operations to generate an objective program, Make it run. [Effects of the Invention]

[0013] According to the above-described embodiment, the effect is obtained in that a compilation device, compilation method, and program can be provided that enable users to generate a highly efficient target program without rewriting the source program. [Brief explanation of the drawing]

[0014] [Figure 1] This figure shows an example of a source program. [Figure 2] This is a block diagram showing an example configuration of a compilation device according to Embodiment 1. [Figure 3] This figure shows an example of the first intermediate text generated from the source program shown in Figure 1 by the intermediate text generation unit according to Embodiment 1. [Figure 4] This figure shows an example of a second intermediate text generated from the first intermediate text shown in Figure 3 by the optimization unit according to Embodiment 1. [Figure 5]FIG. 4 is a diagram showing an image example in C language of the second intermediate text shown in FIG. 4. [Figure 6] FIG. 5 is a diagram showing an image example of an instruction sequence constituting a target program generated from the second intermediate text shown in FIG. 4 by the vector instruction generation unit according to Embodiment 1. [Figure 7] FIG. 6 is a flowchart showing an example of the operation flow of the compilation device according to Embodiment 1. [Figure 8] FIG. 7 is a diagram showing another example of a source program. [Figure 9] FIG. 9 is a diagram showing an image example in C language of the second intermediate text finally generated from the source program shown in FIG. 8 by the optimization unit according to Embodiment 1. [Figure 10] FIG. 11 is a diagram showing yet another example of a source program. [Figure 11] FIG. 13 is a diagram showing an image example in C language of the second intermediate text finally generated from the source program shown in FIG. 10 by the optimization unit according to Embodiment 1. [Figure 12] FIG. 14 is a block diagram showing a configuration example of the compilation device according to Embodiment 2. [Figure 13] FIG. 15 is a block diagram showing a hardware configuration example of the compilation device according to Embodiment 3. MODE FOR CARRYING OUT THE INVENTION

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. Note that the following description and drawings are appropriately omitted and simplified for clarity of explanation. In addition, in the following drawings, the same elements are denoted by the same reference numerals, and redundant explanations are omitted as necessary.

[0016] <Embodiment 1> First, with reference to Figure 2, an example configuration of the compilation device 10 according to this embodiment 1 will be described. The compilation device 10 according to this embodiment 1 is a compilation device for a vector processor that translates a source program 21 written in a high-level language such as C language to generate an objective program 22 for a vector processor (not shown) that has vector operation capabilities, in order to reduce the amount of computation and perform calculations using vector instructions.

[0017] As shown in Figure 2, the compilation device 10 according to this embodiment 1 comprises a syntactic analysis unit 11, an intermediate text generation unit 12, a detection unit 13, an optimization unit 14, and a vector instruction generation unit 15.

[0018] The parsing unit 11 reads the source program 21, which is written in a high-level language such as C, and performs parsing of the source program 21 to generate a syntax tree. The intermediate text generation unit 12 generates intermediate text (hereinafter referred to as the first intermediate text) divided into multiple basic blocks from the source program 21 based on the syntax tree generated by the syntactic analysis unit 11. A basic block is a sequence of several intermediate texts in which control proceeds in a straight line without any branching or jumps in the middle, and without any control interruptions. Figure 3 shows an example of the first intermediate text generated by the intermediate text generation unit 12 when the source program 21 is the source program shown in Figure 1.

[0019] The detection unit 13 detects a process in the source program 21 that uses a nested loop to sum the products of each element of two arrays, based on the control flow between multiple basic blocks in the first intermediate text generated by the intermediate text generation unit 12.

[0020] The optimization unit 14 converts the processing detected by the detection unit 13 into a form that can be used for vector operations (i.e., a form that does not contain nested loops) (i.e., it is made single-layered and vectorized) and generates an intermediate text (hereinafter referred to as the second intermediate text as appropriate). Figure 4 shows an example of the second intermediate text generated by the optimization unit 14 when the first intermediate text generated by the intermediate text generation unit 12 is the intermediate text shown in Figure 3. Figure 5 shows an example of the second intermediate text shown in Figure 4 in C language.

[0021] The vector instruction generation unit 15 generates and outputs the target program 22 based on the second intermediate text generated by the optimization unit 14. Figure 6 shows an example image of the instruction sequence that constitutes the target program 22 generated by the vector instruction generation unit 15, when the second intermediate text generated by the optimization unit 14 is the intermediate text shown in Figure 4.

[0022] The following describes an example of the operation flow of the compilation device 10 according to this embodiment 1, with reference to Figure 7. As shown in Figure 7, when the source program 21 is input to the compilation unit 10 (step S1), the parsing unit 11 first generates a syntax tree from the source program 21 (step S2).

[0023] Next, the intermediate text generation unit 12 generates a first intermediate text divided into multiple basic blocks from the source program 21 based on the syntax tree (step S3). Next, the detection unit 13 analyzes the control flow between basic blocks in the first intermediate text to detect a process in the source program 21 that uses a nested loop to add up the products of each element of two arrays (step S4).

[0024] Next, the optimization unit 14 generates a second intermediate text by converting the detected process into a form that can be operated on by vector operations (i.e., a form that does not contain nested loops) (i.e., unreducing and vectorizing) (step S5).

[0025] Subsequently, the vector instruction generation unit 15 converts the second intermediate text into an instruction sequence as shown in Figure 6, and generates and outputs the target program 22 containing the converted instruction sequence (step S6).

[0026] In Figure 6, the VSUM instruction is a vector operation instruction that calculates the sum of vector elements, and the LVS instruction is an instruction that loads the value of one element of a vector register into a scalar register. The fact that the calculation result does not change before and after the transformation by the optimization unit 14 is guaranteed by the distributive law of product and sum ΣΣai×bj=(Σai)×(Σbj).

[0027] As described above, according to this embodiment 1, the detection unit 13 detects a process in the source program 21 that uses a double loop to add up the products of each element of two arrays, the optimization unit 14 converts the detected process into a form that can be used for vector operations, and the vector instruction generation unit 15 generates the target program 22. Therefore, even without the user rewriting the source program 21, it is possible to generate a highly efficient target program 22 that requires less computation and can be used for vector operations.

[0028] Furthermore, the detection unit 13 may use a nested loop of any depth N (where N is an integer greater than or equal to 3) of two or more layers to detect a process that sums the products of each element of N arrays, and the optimization unit 14 may transform this process (i.e., make it single and vectorize it).

[0029] Furthermore, although the optimization unit 14 performed the transformation of the process using the distributive property of product and sum, the transformation of the process may also be performed using other combinations of operations for which the distributive property holds, such as logical AND and exclusive OR, or sum and minimum value.

[0030] For example, in the case of logical AND and exclusive OR (Figure 8), the detection unit 13 analyzes the intermediate text divided into multiple basic blocks, finds the logical AND of each element, and detects the process of finding their exclusive OR. The optimization unit 14 then converts the detected process into a form (Figure 9) in which the exclusive OR of each array is calculated and their logical AND is calculated. This enables vector operations.

[0031] Similarly, in the cases of sum and minimum values ​​(Figure 10), the detection unit 13 analyzes the intermediate text divided into multiple basic blocks, finds the sum of each element, and detects the process of finding the minimum value of those sums. The optimization unit 14 then converts the detected process into a form where the minimum value of each array is found and their sum is calculated (Figure 11). This enables vector operations.

[0032] <Embodiment 2> Next, with reference to Figure 12, an example of the configuration of the compilation device 30 according to this second embodiment will be described. This second embodiment corresponds to a schematic representation of the first embodiment described above.

[0033] As shown in Figure 12, the compilation device 30 according to this second embodiment includes a detection unit 31 and an optimization unit 32. The detection unit 31 detects a first process, which is included in the source program 21 written in a high-level language, that uses a nested loop to add up the products of each element of two arrays. The detection unit 31 corresponds to the detection unit 13 in the embodiment 1 described above.

[0034] The optimization unit 32 converts the detected first process into a form that can be used for vector operations and generates the target program 22. The optimization unit 32 corresponds to the optimization unit 14 and the vector instruction generation unit 15 in the embodiment 1 described above.

[0035] Therefore, according to this embodiment 2, similar to embodiment 1 described above, the user can generate a highly efficient objective program 22 that requires less computation and is capable of vector operations, without having to rewrite the source program 21.

[0036] Furthermore, the compilation device 30 according to this second embodiment may further include a parsing unit that performs syntactic analysis of the source program 21 and generates a syntax tree, and an intermediate text generation unit that generates intermediate text divided into a plurality of basic blocks from the source program 21 based on the syntax tree. These parsing unit and intermediate text generation unit correspond to the parsing unit 11 and intermediate text generation unit 12 according to the first embodiment described above, respectively. In this case, the detection unit 31 may detect the first process based on the control flow between the plurality of basic blocks.

[0037] Furthermore, the detection unit 31 may further detect a second process, based on the control flow between multiple basic blocks, which involves summing the products of each element of N arrays using a nested loop of any depth N (where N is an integer greater than or equal to 3) that is included in the source program 21. In this case, the optimization unit 32 may convert the detected second process into a form that can be used for vector operations to generate the target program 22.

[0038] Furthermore, the detection unit 31 may further detect a third process that calculates the logical AND of each element in the source program 21 and then calculates their exclusive OR, based on the control flow between multiple basic blocks. In this case, the optimization unit 32 may convert the detected third process into a form that can be operated on by vector operations and generate the target program 22.

[0039] Furthermore, the detection unit 31 may further detect a fourth process in the source program 21, which calculates the sum of each element and finds the minimum value of those sums, based on the control flow between multiple basic blocks. In this case, the optimization unit 32 may convert the detected fourth process into a form that can be used for vector operations and generate the target program 22.

[0040] <Embodiment 3> Next, with reference to Figure 13, an example of the hardware configuration of the compilation device 40 according to this third embodiment will be described. As shown in Figure 13, the compilation device 40 according to this embodiment 3 is a computer comprising a processor 41 and memory 42.

[0041] The processor 41 may be, for example, a microprocessor, an MPU (Micro Processing Unit), or a CPU (Central Processing Unit). The processor 41 may include multiple processors.

[0042] Memory 42 is composed of a combination of volatile and non-volatile memory. Memory 42 may also include storage located away from the processor 41. In this case, the processor 41 may access memory 42 via an I(Input) / O(Output) interface, which is not shown.

[0043] The compilation devices 10 and 30 according to the embodiments 1 and 2 described above may have the hardware configuration shown in Figure 13. A program is stored in the memory 42. This program, when loaded into a computer, includes a set of instructions (or software code) for causing the computer to perform one or more of the functions described for the compilation devices 10 and 30 in embodiments 1 and 2 described above. The components of the compilation devices 10 and 30 described above may also be realized by the processor 41 loading and executing the program stored in the memory 42. Furthermore, the storage function of the components of the compilation devices 10 and 30 described above may also be realized by the memory 42.

[0044] Furthermore, the programs described above may be stored on non-temporary computer-readable media or tangible storage media. Examples, but not limited to, include random-access memory (RAM), read-only memory (ROM), flash memory, solid-state drives (SSDs) or other memory technologies, CD-ROMs, digital versatile discs (DVDs), Blu-ray® discs or other optical disc storage, magnetic cassettes, magnetic tapes, magnetic disk storage or other magnetic storage devices. The programs may also be transmitted over temporary computer-readable media or communication media. Examples, but not limited to, include electrical, optical, acoustic, or other forms of propagating signals.

[0045] Although the present disclosure has been described above with reference to embodiments, the present disclosure is not limited to the embodiments described above. Various modifications to the structure and details of the present disclosure can be understood by those skilled in the art within the scope of the present disclosure. [Explanation of Symbols]

[0046] 10 Compilation Unit 11. Parsing Unit 12 Intermediate text generation unit 13 Detection unit 14 Optimization Unit 15 Vector instruction generation unit 21 Source Program 22 Objective Program 30 Compilation Unit 31 Detection unit 32 Optimization Unit 40 Compilation Unit 41 processors 42 memory

Claims

1. A parser that performs syntax analysis on a source program written in a high-level language and generates a syntax tree, An intermediate text generation unit generates intermediate text divided into multiple basic blocks from the source program based on the aforementioned syntax tree, A detection unit detects a first process included in the source program, which uses a nested loop to add up the products of each element of two arrays, based on the control flow between the plurality of basic blocks, An optimization unit that converts the detected first process into a form that can be processed by vector operations and generates a target program, A compilation device equipped with the following features.

2. Based on the control flow between the plurality of basic blocks, the detection unit further detects a second process that sums the products of each element of N arrays using a nested loop of any depth N (where N is an integer of 3 or more) that is included in the source program, and The optimization unit converts the detected second process into a form that can be processed by vector operations and generates the target program. The compilation device according to claim 1.

3. The detection unit further detects a third process, which calculates the logical AND of each element included in the source program and then calculates their exclusive OR, based on the control flow between the plurality of basic blocks. The optimization unit converts the detected third process into a form that can be processed by vector operations and generates the target program. The compilation device according to claim 1 or 2.

4. The detection unit further detects a fourth process, which calculates the sum of each element included in the source program and finds its minimum value, based on the control flow between the plurality of basic blocks. The optimization unit converts the detected fourth process into a form that can be processed by vector operations and generates the target program. A compilation device according to any one of claims 1 to 3.

5. A compilation method executed by a compilation device, The parsing step involves analyzing the syntax of a source program written in a high-level language to generate a syntax tree, and An intermediate text generation step that generates intermediate text divided into multiple basic blocks from the source program based on the syntax tree, A detection step that detects a first process included in the source program, which uses a nested loop to add up the products of each element of two arrays, based on the control flow between the plurality of basic blocks, An optimization step of converting the detected first process into a form that can be used for vector operations and generating an objective program, Compilation method, including the method itself.

6. To the compilation device, A parsing procedure that performs syntactic analysis of a source program written in a high-level language and generates a syntax tree, An intermediate text generation procedure that generates intermediate text divided into multiple basic blocks from the source program based on the aforementioned syntax tree, A detection procedure that detects a first process, included in the source program, which uses a nested loop to sum the products of each element of two arrays, based on the control flow between the aforementioned plurality of basic blocks, An optimization procedure for generating an objective program by converting the detected first process into a form that can be operated on by vector operations, A program to execute.

Images