LED device and method for manufacturing an LED device

Abstract

A method for fabricating an LED device includes forming an n-doped connection layer of III-nitride material over a porous region of III-nitride material, forming a first electrically insulating mask layer over the n-doped connection layer, removing a portion of the first mask layer to expose a first exposed region of the n-doped connection layer, forming a first LED structure on the first exposed region of the n-doped connection layer, the first LED structure configured to emit light at a first emission wavelength, forming a second electrically insulating mask layer over the first LED structure and the n-doped connection layer, removing a portion of the second mask layer to expose a second exposed region of the n-doped connection layer, and forming a second LED structure on the second exposed region of the n-doped connection layer, the second LED structure configured to emit light at a second emission wavelength different from the first emission wavelength. LED devices, arrays of LEDs, and tri-color LED devices are also provided.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing a semiconductor device, and more particularly to an LED device, an array of LED devices, and an improved method for manufacturing an LED device.

Background Art

[0002] Standard light-emitting diodes (LEDs) for light emission are typically larger than 200 μm × 200 μm. A micro-LED is an array of high-density microscale LEDs with a lateral size reduced to less than 100 μm × 100 μm. For this reason, a micro-LED is defined as an LED structure having lateral dimensions (length and width) smaller than 100 μm × 100 μm, in the tens of nanometers, and even smaller.

[0003] Attempts have been made to manufacture micro-LEDs using known techniques. For example, conventional attempts use normal LED epitaxy and laser lift-off, electrostatic carriers, and an elastomeric stamp for transfer. However, there are problems in applying this approach to devices as small as micro-LEDs. 7]

[0004] These problems include the following. - It is difficult to generate all three primary colors (RGB: red, green, blue) on the same chip of a micro-LED using normal LED epitaxy. - Green and red micro-LEDs have low efficiency. - Dry etching is always required to define a microscale LED mesa. As the LED size decreases, plasma damage to the sidewalls of the LED structure affects the light-emitting efficiency and lifetime of the device. - Laser lift-off has low yield and high cost. - Low yield of transfer due to pre-existing stress / warpage problems.

[0005] Due to these issues, conventional LED manufacturing technologies are unsatisfactory for producing high-quality microLEDs. In particular, conventional LED manufacturing technologies are unsatisfactory for producing multi-color LED devices containing multiple LEDs of different colors on the same substrate. [Overview of the Initiative]

[0006] This application relates to an improved method for manufacturing LED devices and LED devices manufactured using this manufacturing method. The present invention is defined in the independent claims, which are referred to herein. Preferred or advantageous features of the present invention are described in the dependent subclaims.

[0007] The LED device is preferably formed from a III-V semiconductor material, and particularly preferably from a III nitride semiconductor material.

[0008] Group III-V semiconductors include binary, ternary, and quaternary alloys of Group III elements such as Ga, Al, and In, and Group V elements such as N, P, As, and Sb, and are of interest in numerous application fields, including optoelectronics.

[0009] Of particular importance are the semiconductor material class known as "Group III nitrides," which include gallium nitride (GaN), indium nitride (InN), and aluminum nitride (AlN), and their ternary and quaternary alloys. Group III nitride materials have not only achieved commercial success in semiconductor lighting and power electronics, but also possess special advantages in quantum light sources and the interaction of light and matter.

[0010] While a variety of Group III nitride materials are commercially interesting, gallium nitride (GaN) is widely recognized as one of the most important new semiconductor materials and is particularly important in numerous application areas.

[0011] It is known that introducing pores into bulk GaN can significantly affect material properties such as refractive index. Therefore, porous GaN is of particular interest in the field of optoelectronics because it may be possible to adjust the optical properties of GaN by changing its porosity.

[0012] Although this invention is described with reference to GaN, it can also be advantageously applied to alternative group III nitride materials.

[0013] Previous publications relating to the porosity of III-V semiconductor materials include international patent applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0014] The inventors have found that the present invention can be used to advantageously provide multicolor LED devices and arrays of multicolor LED devices.

[0015] Manufacturing method for LED devices According to a first aspect of the present invention, a method for manufacturing an LED device is provided. This method is The steps include forming an n-doped connecting layer of a group III nitride material on a porous region of a group III nitride material, The steps include forming a first electrical insulation mask layer on an n-doped connection layer, The steps include removing a portion of the first mask layer to expose the first exposed region of the n-doped connection layer, The steps include forming a first LED structure configured to emit light at a first emission wavelength on a first exposed region of an n-doped connection layer, The steps include forming a second electrical insulation mask layer on a first LED structure and an n-doped connection layer, The steps include removing a portion of the second mask layer to expose the second exposed region of the n-doped connection layer, The steps include forming a second LED structure on a second exposed region of the n-doped connection layer, configured to emit light at a second emission wavelength different from the first emission wavelength, Includes.

[0016] A multicolor LED device is provided by forming a first LED structure configured to emit light at a first emission wavelength and a second LED structure configured to emit light at a second emission wavelength on an n-doped connection layer. Both the first and second LED structures are provided on the same porous template but emit light at different wavelengths.

[0017] The first LED structure and the second LED structure are configured to emit light at various wavelengths. For example, the first LED structure can be a green-emitting LED structure, a blue-emitting LED structure, or a red-emitting LED structure. The second LED structure can also be a green-emitting LED structure, a blue-emitting LED structure, or a red-emitting LED structure, and is configured to emit light in a different color than the first LED structure.

[0018] In a preferred embodiment, the first LED structure is configured to emit light at a first emission wavelength of 515 nm to 540 nm, preferably around 530 nm, under electrical bias, and the second LED structure is configured to emit light at a second emission wavelength of 570 nm to 630 nm, preferably above 600 nm, under electrical bias.

[0019] LED devices are preferably multilayer structures formed from a stack of planar layers of semiconductor material. During the epitaxial deposition of each layer or region of the structure, the thickness, composition, and charge carrier concentration of each layer of the structure can be controlled. Since the device is formed by the continuous deposition of layers, subsequent layers are deposited on top of previous layers, and within the formed structure, subsequent layers are positioned above previous layers. Such devices are typically deposited as extremely thin layers on a planar substrate, and therefore the width of these layers is significantly greater than their height. The relative position of device components can be controlled by controlling the order in which the layers are deposited, as well as by controlling the lateral size of each layer and its position relative to the layer below it. Unless otherwise specified, when a layer or region described herein is formed or positioned "over" or "above" another layer, that layer or region is located vertically above the other layer within the semiconductor structure and extends laterally over an area corresponding to at least a portion of the area of ​​the other layer below it within the structure.

[0020] The n-type connection layer acts advantageously as a current-diffusing layer for supplying current to both the first and second LED structures. Furthermore, by using multiple LED structures in contact with the same conductive connection layer, electrical n-contacts between the two LED structures can be fabricated very easily.

[0021] A template or "footprint" on which an LED structure can be formed is created by forming an electrically insulating (dielectric) mask layer, and then removing a portion of the mask to expose the exposed area of ​​the n-doped connection layer. The size and shape of the exposed area can be controlled by controlling the size and shape of the portion of the mask that is removed. Subsequently, the first and second LED structures can be formed by depositing subsequent semiconductor material layers on the first and second exposed areas, respectively. By controlling the size and shape of the exposed area, the lateral size (length and width) and shape of the subsequently formed LED structure can be controlled. This size control is particularly advantageous for growing micro-LED structures with extremely small lateral dimensions.

[0022] Conventional techniques involve growing a large LED structure, then etching grooves, and finally cutting this structure into micro-LEDs by micro-platforms or "mesas" of the desired lateral size. In micro-LEDs fabricated using such conventional techniques, etching damage to the sidewalls of the LED structure significantly affects the extremely small pixels formed by the micro-LEDs. This can impair the reliability and brightness of the micro-LEDs.

[0023] The method of the present invention advantageously allows the formation of first and second LED structures in a predetermined exposure area, optionally in the correct size and shape for forming micro-LEDs. Since the exposure area in the present invention controls the footprint of each LED structure, the first and second LED structures are advantageously formed to the appropriate size from the outset, and therefore there is no need to etch the LED structures of the present invention to reduce their lateral size. Accordingly, the resulting LED device can avoid the dry etching damage that occurs in conventional methods.

[0024] By avoiding dry etching damage to the active layer of the LED structure, significant advantages are obtained compared to micro-LEDs prepared using conventional techniques, and LED devices manufactured using this method are highly reliable and have high brightness.

[0025] Another benefit of the present invention is that even with extremely small micro-LED structures measuring only a few microns in size, electrical n-contacts with the n-doped portion of the LED structure can be easily fabricated. In this invention, n-contacts can be fabricated simply by removing a further portion of the electrical insulation mask layer to expose a second exposed region on the n-doped connection layer, and then depositing a conductive contact on this second exposed region.

[0026] The n-doped connecting layer of the group III nitride material is formed on the porous region of the group III nitride material. Preferably, at least one of the LED structures is formed on the connecting layer of the group III nitride material and positioned on the porous region of the group III nitride material.

[0027] In some preferred embodiments, the porous region is a continuous region covering the substrate and is located beneath the entire connecting layer, so all LED structures are formed on top of the porous region. Preferably, both the first and second LED structures can be positioned on top of the porous region.

[0028] In other embodiments, the n-doped connecting layer of the group III nitride material is formed on multiple porous regions of the group III nitride material arranged in the same plane, for example, on multiple regions having different porosity. Since the different porous regions occupy different lateral positions on the substrate, different LED structures can be positioned on the different porous regions. For example, a first LED structure is formed on a first porous region having a first porosity, and a second LED structure is formed on a second porous region having a second porosity.

[0029] In another preferred embodiment, the n-doped connecting layer of the group III nitride material is formed on porous regions and non-porous regions of the group III nitride material. The porous and non-porous regions are arranged in the same plane on the substrate, for example, such that the layers of the structure consist of part porous group III nitride material and part non-porous material. Thus, the porous region is located beneath only a portion of the n-doped connecting layer, and the non-porous region is located beneath the other portion of the n-doped connecting layer. In this embodiment, one of the first LED structure and the second LED structure is positioned on the porous region, and the other is positioned on the non-porous region.

[0030] The inventors have recognized that electrochemical porosity of group III nitride materials reduces strain within the group III nitride lattice, thereby reducing warping or bending of the wafer as a whole. While we do not wish to be bound by theory, the process of porosizing the porous regions of group III nitride materials is thought to involve etching away structural defects, such as threading dislocations, that formed during layer growth on top of the first group III nitride material layer.

[0031] When dislocations are removed from the semiconductor material in the porous region during porosity formation, strain within the porous region is significantly reduced, especially when the lattice dimensions of the porous region and the underlying material do not match. Therefore, when a group III nitride material layer is deposited above the porous region, the porous material becomes more easily aligned with the lattice of the non-porous layer above it during the epitaxial growth of the semiconductor structure. As a result, the strain in the layer above the porous region is significantly smaller compared to the case where the porous region is absent.

[0032] Compositional Entrapment Effect: Kawaguchi et al. reported a so-called InGaN compositional entrapment effect, in which the proportion of indium is small in the early stages of growth but increases with increasing growth thickness. This observation was, to some extent, independent of the underlying GaN or AlGaN. The authors suggested that this effect arises from strain caused by lattice mismatch at the interface. The authors found that as the lattice mismatch between InGaN and the lower epitaxial layer increases, the change in In content becomes larger.

[0033] In the paper "Theoretical study of the composition pulling effect in InGaN metalorganic vapor-phase epitaxy growth" by Inatomi et al. (Japanese Journal of Applied Physics, Volume 56, Number 7), it was found that compressive strain suppresses InN uptake, while tensile strain promotes InN uptake compared to relaxed bulk growth.

[0034] The inventors have found that using porous regions within a semiconductor structure results in "strain relaxation," which reduces strain within the semiconductor structural layer, potentially leading to improvements in terms of compositional incorporation effect. Porous formation reduces strain within the group III nitride layer, resulting in less strain in the semiconductor structure and, consequently, creating conditions for incorporating more In. Therefore, the present invention can facilitate the incorporation of more indium into the layer of an LED structure grown on a porous region, which is highly desirable for long-wavelength emission.

[0035] By introducing porous regions of Group III nitride material into the LED, one or more LED structures can be grown on top of the porous regions with less strain than would be possible without them. Therefore, reducing the strain level of such a multilayer semiconductor structure helps to incorporate more indium into one or more light-emitting layers of the LED, resulting in the growth of a high-quality InGaN light-emitting layer with a high indium content. This allows sufficient indium to be incorporated into the indium gallium nitride light-emitting layer, so that the LED emits light at a peak wavelength of 600-750 nm when an electrical bias is applied.

[0036] There is a very high demand for red LEDs that emit light in the 600-750nm range, but achieving red InGaN LEDs has been difficult because it is technically challenging to incorporate sufficient indium into one or more light-emitting layers. However, LEDs with shorter wavelengths, such as green (500-550nm) and yellow (550-600nm), can be fabricated using InGaN light-emitting regions with a lower indium content than required for red light emission, making them much easier to manufacture.

[0037] The inventors discovered that when an LED structure is grown on a porous region of a group III nitride material, the emission wavelength shifts significantly to longer wavelengths compared to when the same LED structure is grown on a non-porous substrate.

[0038] To demonstrate this, the inventors grew a conventional green / yellow (emitting in the 500-550 nm or 550 nm-600 nm range) InGaN LED structure on a non-porous GaN wafer and confirmed that this LED emitted green / yellow light as expected. Next, they grew the same "green / yellow" InGaN LED structure on a template containing porous regions, and when an electrical bias was applied to this LED, the LED emitted light in the red range of 600-750 nm.

[0039] In a preferred embodiment, the present invention includes a first LED structure, which is a green / yellow (emitting at 500-550 nm or 550-600 nm) InGaN LED structure, formed on a connecting layer above a porous region, and a second LED structure, which is a green / yellow (emitting at 500-550 nm or 550-600 nm) InGaN LED structure, formed on a connecting layer above a non-porous region. The first and second LED structures have the same structure and composition. Nevertheless, the emission wavelength of the first LED structure is shifted by its position on the first porous region, so that the first LED structure emits light at a different wavelength than the second LED structure. The second LED structure emits light at the expected green / yellow wavelength (emitting at 500-550 nm or 550-600 nm), while the first LED structure emits light at a longer wavelength of 600-650 nm. Therefore, by forming the same conventional LED structure twice, that is, once on a non-porous region and once on a porous region, multiple emission colors can be achieved.

[0040] The step of forming the first and second LED structures includes growing the LED structures according to conventional methods in the art. That is, the LED structures can be grown using known semiconductor deposition techniques and have various conventional LED epitaxial layers. A typical LED structure is described here as an example, but it will be understood by those skilled in the art that a wide variety of LED structures (including various combinations of layer thickness, material, and doping level) are known in the art and can be used in the present invention. However, in the present invention, the first and second LED structures are formed, grown, or deposited only on one or more exposed regions of the n-doped connecting layer, respectively.

[0041] The step of forming the first LED structure preferably involves, on the first exposed region of the n-doped connecting layer, The first n-doped section, The first p-doped section, A first light-emitting region is positioned between the first n-doped portion and the first p-doped portion, This includes forming.

[0042] The step of forming the second LED structure is to place on the second exposed region of the n-doped connection layer, The second n-doped section, The second p-doped section, A second light-emitting region is positioned between the second n-doped region and the second p-doped region, This includes forming.

[0043] A method for manufacturing an LED device includes a first step of electrochemically porousizing a group III nitride material layer to form a porous region of the group III nitride material. This is achieved using a wafer-scale porosification process described in international patent applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728). This step is performed before forming an n-doped connecting layer of group III nitride material on the porous region, so that the connecting layer is not electrically porous.

[0044] The method preferably includes the step of forming a porous region of a group III nitride material by electrochemical porosification through a non-porous layer of the group III nitride material, the non-porous layer of the group III nitride material forming a non-porous intermediate layer. The intermediate layer is positioned between the porous region and an n-doped group III nitride connecting layer, and advantageously, the non-porous intermediate layer provides a smooth surface for the growth of the connecting layer.

[0045] Porous regions are formed by porousizing one or more layers or regions of group III nitride material on a substrate. For a group III nitride material to be porous, the material to be porous must be n-type doped, and 1 × 10⁻⁶ 17 ~1 × 10 20 It is necessary to have a doping concentration within the specified range.

[0046] The substrate can be silicon, sapphire, SiC, or β-Ga2O3. The crystal orientation of the substrate can be polar, semipolar, or nonpolar. The thickness of the substrate typically varies between 100 μm and 1500 μm.

[0047] The porous region is a single porous layer, and therefore the method includes the step of forming an n-doped connecting layer of group III nitride material on top of a porous layer of group III nitride material. Preferably, the porous region is a porous layer that is uniformly porous, for example, formed from a continuous layer of porous group III nitride material.

[0048] The porous region includes multiple porous layers and optionally multiple non-porous layers. In a preferred embodiment of the present invention, the porous region is a stack of alternating porous and non-porous layers, where the upper surface of the stack defines the upper part of the porous region and the lower surface of the stack defines the lower part of the porous region. An n-doped connecting layer of group III nitride material can be formed on top of the porous region which includes a stack of porous layers of group III nitride material.

[0049] Alternatively, the porous region can be a group III nitride material layer containing one or more porous regions, for example, one or more porous regions are contained within a non-porous layer of group III nitride material.

[0050] In a preferred embodiment, the porous region or porous layer has lateral dimensions (width or length) equivalent to those of the substrate on which the porous layer or porous region is grown. For example, conventional substrate wafer sizes can vary, for instance, 1 cm. 2 These are 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, or 16 inches in diameter. However, it is also possible to form small porous regions that do not extend to the entire substrate by patterning one or more layers and / or depositing regions with different charge carrier concentrations within the same layer. Therefore, the lateral dimensions of the porous layer or porous region vary from about one-tenth the size of a pixel (e.g., 0.1 μm) to the lateral dimensions of the substrate itself.

[0051] One or more layers of n-doped group III nitride semiconductor material are grown on a substrate. The group III nitride layer contains one or more combinations of the elements Al, Ga, and In (quaternary layer, ternary layer). The thickness of the group III nitride stack is preferably 10 to 4000 nm. The porous group III nitride layer is 1 × 10⁻¹⁶ 17 cm -3 ~5×10 20 cm -3 It has a doping concentration of [value].

[0052] Preferably, an intermediate layer of undoped group III nitride material is deposited on the doped material before the doped material is porous. The thickness of the intermediate layer is preferably 1 nm to 3000 nm, preferably 5 nm to 2000 nm, or 1000 nm to 1500 nm.

[0053] As is known in this art, electrochemical porosity is used to remove material from the n-type doped region of a group III nitride material, thereby creating empty pores in the semiconductor material.

[0054] In a preferred embodiment, the doped region before porosity formation consists of a stack in which layers are arranged alternately in the order of highly doped layers / lowly doped layers. The stack consists of pairs of highly / lowly doped layers, preferably containing 2 to 50 pairs of layers. The thickness of each highly doped layer varies between 10 nm and 200 nm, or 20 nm and 150 nm, or 50 nm and 100 nm. The lowly doped layers have a thickness of 5 nm and 180 nm, or 20 nm and 150 nm, or 50 nm and 100 nm.

[0055] The stack of porous layers is preferably a stack consisting of alternating layers of porous and non-porous layers. Preferably, the stack includes 2 to 50 pairs of porous and non-porous layers stacked on top of each other. The porous layers preferably have a thickness of 2 nm to 200 nm, or 10 nm to 150 nm, or 20 nm to 100 nm. The non-porous layers preferably have a thickness of 2 nm to 180 nm, or 10 nm to 150 nm, or 50 nm to 100 nm.

[0056] In a preferred embodiment, the n-doped connecting layer of the group III nitride material is formed on a stack of multiple porous layers of the group III nitride material. Thus, the porous region is not a single porous layer of the group III nitride material, but a stack of multiple layers of the group III nitride material in which at least some layers are porous.

[0057] The porous region or each porous layer within the porous region has a porosity of 1% to 99%. Preferably, each porous layer in the porous region or stack has a porosity of 10% to 90%, or 10% to 70%.

[0058] Preferably, an n-doped connecting layer of group III nitride material is grown on this region by depositing it on a non-porous intermediate layer.

[0059] Optionally, the thickness of the non-porous intermediate layer may be reduced by etching before growing the n-doped connecting layer of the group III nitride material.

[0060] The n-doped connection layer of the group III nitride material preferably has a thickness of 200 nm to 2000 nm. The n-doped connection layer of the group III nitride material preferably has an n-type charge carrier concentration of 1×10 17 cm -3 to 5×10 20 cm -3 and preferably has a charge carrier concentration of at least 1×10 18 cm -3 .

[0061] The first mask layer is referred to as the first passivation layer. The first mask layer is preferably formed by depositing a dielectric material layer on the n-doped connection layer of the group III nitride material. Preferably, the first mask layer is deposited on the entire surface of the n-doped connection layer of the group III nitride material so that the connection layer is completely covered with the dielectric material. The mask layer can be formed from SiO2, SiN, SiON, Al2O3, or any other suitable dielectric material.

[0062] The thickness of the first mask layer is 20 nm to 1000 nm, preferably 100 nm to 800 nm, particularly preferably 200 nm to 600 nm.

[0063] The deposition of the first mask layer is performed by a conventional deposition technique such as plasma-enhanced chemical vapor deposition (PECVD), sputtering, atomic layer deposition (ALD), evaporation, or in-situ metalorganic chemical vapor deposition (MOCVD).

[0064] Using standard lithography techniques, a portion of the first mask layer is removed to create one or more openings in the non-conductive mask layer that expose the first region of the underlying n-doped connection layer. The step of removing a portion of the first mask layer includes photolithography, wet etching or dry etching, such as inductively coupled dry etching (ICP-RIE).

[0065] The lateral size (length and width of the opening in the mask layer) and shape of the one or more exposed regions control the lateral size and shape of the LED structure grown within the exposed regions.

[0066] One or more exposed areas of the connecting layer can be formed into any desired shape, controlled by patterning and lithographically removing a portion of the mask layer. For example, the exposed areas may be circular, square, rectangular, hexagonal, or triangular in shape.

[0067] The size of the first exposed area is 0.2 μm to 100 μm, preferably 1 μm to 30 μm, and particularly preferably 2 μm to 10 μm.

[0068] Particularly preferably, the size of the exposed area must be the size of the microLED. For example, the width and / or length (or, if the exposed area is circular, the diameter) of one or more exposed areas is 0.05 μm to 100 μm, preferably 0.05 μm to 30 μm, particularly preferably less than 10 μm, for example, 0.1 μm to 10 μm or 0.5 μm to 10 μm. In a preferred embodiment, the length, width, or diameter of the exposed area is less than 50 μm, or less than 40 μm, or less than 30 μm, or less than 20 μm, or less than 10 μm. Particularly preferably, since the exposed area has a width or diameter of less than 10 μm, the LED structure grown within the exposed area forms a microLED pixel of a size of less than 10 μm.

[0069] Once a first exposed region of the n-doped connection layer is formed in the dielectric mask layer, the first LED structure is grown within the first exposed region, thereby bringing the first LED structure into contact with the n-doped connection layer.

[0070] The lateral dimensions of the first LED structure, including the n-doped area, light-emitting area, and p-doped area, are preferably the same as those of the first exposed area. This is because the first LED structure grows within the first exposed area and inherits the lateral size of the first exposed area. Therefore, it is possible to grow the first LED to an appropriate size without requiring an etching step to reduce the lateral dimensions of the LED structure.

[0071] Once the first LED structure is grown, a second electrical insulation mask layer is formed on top of the first LED structure and the n-doped connection layer. The second electrical insulation mask layer is called the second passivation layer. The second mask layer is formed from SiO2, SiN, SiON, aluminum oxide, tantalum oxide, hafnium oxide, or a combination thereof. The second mask layer is deposited by PECVD, sputtering, ALD, vapor deposition, in situ MOCVD, or any other prior art.

[0072] The second mask layer covers the surface and sidewalls of the first LED structure, as well as the connecting layer. The second mask layer can be, for example, Al2O3 (thickness 10-100 nm) deposited by atomic layer deposition, followed by the deposition of SiO2, SiN, or SiON (thickness 50-300 nm) by sputtering or plasma-excited chemical vapor deposition. Al2O3 is deposited at 50-150°C, while SiO2, SiN, and SiON are deposited at 250-350°C. The sputtering process is performed at room temperature.

[0073] The thickness of the second mask layer can be 20 to 2000 nm. The thickness of the second mask layer is 20 nm to 1800 nm, preferably 200 nm to 1500 nm, and particularly preferably 500 nm to 1000 nm.

[0074] The first mask layer is removed before depositing the second mask layer. The first mask layer is removed by wet etching using buffer oxide etching chemicals.

[0075] The step of removing a portion of the second mask layer to expose a second exposed region of the n-doped connection layer includes photolithography, wet etching, or dry etching, such as inductively coupled dry etching (ICP-RIE).

[0076] The size of the second exposed area is 0.2 μm to 100 μm, preferably 1 μm to 50 μm, and particularly preferably 2 μm to 10 μm.

[0077] Particularly preferably, the size of the second exposed area must be the size of the microLED. For example, the width and / or length (or, if the exposed area is circular, the diameter) of one or more second exposed areas is 0.05 μm to 100 μm, preferably 0.05 μm to 30 μm, particularly preferably less than 10 μm, for example, 0.1 μm to 10 μm or 0.5 μm to 10 μm. In a preferred embodiment, the length, width, or diameter of the exposed area is less than 50 μm, or less than 40 μm, or less than 30 μm, or less than 20 μm, or less than 10 μm. Particularly preferably, since the exposed area has a width or diameter of less than 10 μm, the second LED structure grown within the exposed area forms a microLED pixel of less than 10 μm in size.

[0078] Once a second exposed region of the n-doped connection layer is formed in the second dielectric mask layer, the second LED structure is grown within the second exposed region and brought into contact with the n-doped connection layer.

[0079] Various first and second LED structures are grown within the exposed region while enjoying the benefits of the present invention. All such LED structures typically include an n-doped region, a light-emitting region, and a p-doped region, and optionally include other semiconductor material layers typical in LED epitaxy.

[0080] The first LED structure, the second LED structure, and optionally the third LED structure are formed in any order.

[0081] The following describes exemplary LED structures suitable for use as the first or second LED structure of the present invention. The following description is applicable to both the first and second LED structures.

[0082] In a preferred embodiment, the n-doped portion of each LED structure is grown on the exposed area of ​​the connecting layer and brought into direct contact with the n-doped connecting layer.

[0083] The n-doped region includes an n-doped layer of a group III nitride material. The n-doped layer includes a group III nitride layer containing indium, or a stack of thin group III nitride layers that may or may not contain indium, or a bulk layer of group III nitride or a stack of group III nitride layers in which the atomic percentage of indium fluctuates within the layer or stack. For example, the n-doped region is a stack consisting of an n-GaN layer, or an n-InGaN layer, or an alternating layer of n-GaN / n-InGaN layers, or an alternating layer of n-InGaN / n-InGaN layers having different amounts of indium.

[0084] The percentage of indium atoms in the n-doped area varies between 0.5 and 25%. The total thickness of the n-doped area varies between 2 nm and 200 nm, for example, between 10 nm and 150 nm, or between 20 nm and 100 nm. If the n-doped area includes a stack of layers, the thickness of each individual layer within the stack preferably varies between 1 nm and 40 nm or between 5 nm and 30 nm.

[0085] The n-doped area is 1 × 10 17 cm -3 ~5×10 20 cm -3 It has an n-type doping concentration.

[0086] After growing the n-type portion of the LED structure in the exposed area, the light-emitting region of the LED is grown on top of the n-type portion.

[0087] The light-emitting regions of the first and / or second LED structures include one or more group III nitride light-emitting layers, preferably indium gallium nitride (InGaN) light-emitting layers. A single light-emitting layer or each light-emitting layer preferably includes a nanostructure layer containing quantum structures such as quantum wells, quantum dots, fragmentary quantum wells, or discontinuous quantum wells.

[0088] The quantum wells and barriers are grown using known techniques, preferably within a temperature range of 600-800°C. Upon completion of the growth of the first luminescent region, the QWs are within ±200 nm of the height of the first mask layer.

[0089] A single light-emitting layer or each light-emitting layer preferably contains a group III nitride material with an atomic indium content of 10 to 40%. The indium content of the light-emitting layer is selected at different levels depending on the desired emission wavelengths for the first and second LED structures. In a preferred embodiment, the indium content of the light-emitting layer is 12 to 18%, preferably more than 13%, or can be 20 to 30%, preferably more than 22%, or can be 30 to 40%, preferably more than 33%.

[0090] The first light-emitting region of the first LED structure preferably contains a different atomic indium content than the second light-emitting region of the second LED structure, and as a result, the first and second LED structures emit light at different wavelengths.

[0091] In a preferred embodiment, one or more light-emitting layers in the first LED structure are composed of In x Ga 1-x N is such that 0.10 ≤ x ≤ 0.40, preferably 0.18 ≤ x ≤ 0.30, and particularly preferably 0.22 ≤ x ≤ 0.30. In some embodiments, one or more light-emitting layers in the second LED structure have this composition.

[0092] In a preferred embodiment, the electroluminescent (EL) emission wavelength of the target of the first LED structure under electrical bias is 500 nm to 560 nm, preferably 515 nm to 540 nm, or 520 nm to 540 nm, preferably 530 nm.

[0093] In a preferred embodiment, one or more light-emitting layers in the second LED structure are composed of In y Ga 1-y N is such that 0.20 ≤ y ≤ 0.40, preferably 0.26 ≤ y ≤ 0.40, and particularly preferably 0.30 ≤ y ≤ 0.40. In some embodiments, one or more light-emitting layers in the first LED structure also have this composition.

[0094] Under electrical bias, the EL emission wavelength of the target from which the second LED structure emits light is 560 nm to 650 nm, preferably 600 nm to 650 nm, or greater than 600 nm. In certain embodiments, the first and second LED structures have the same structure and include light-emitting regions having the same composition.

[0095] In a preferred embodiment, each light-emitting region includes one or more InGaN quantum wells, preferably 1 to 7 quantum wells. The thickness of each quantum well layer varies between 1.5 and 8 nm.

[0096] The quantum well may or may not be covered with a thin (0.5-3 nm) group III nitride layer.

[0097] The Group III nitride barrier layer contains one or more combinations of the elements Al, Ga, and In (ternary or quaternary layer).

[0098] The quantum wells and barriers in the light-emitting region are preferably grown within a temperature range of 600 to 800°C.

[0099] The LED structure includes a cap layer of group III nitride material between the quantum well and the p-doped portion, preferably the cap layer is undoped and has a thickness of 5 nm to 30 nm.

[0100] The p-doped portions of the first and second LED structures are grown above the light-emitting region. The p-doped portion includes a p-doped group III nitride layer and a p-doped aluminum gallium nitride layer positioned between the p-doped group III nitride layer and the light-emitting region. The p-doped aluminum gallium nitride layer is an electron blocking layer (EBL) between the cap layer and the p-type layer. The electron blocking layer contains 5 to 25 at% aluminum, and preferably the thickness of the electron blocking layer is 10 nm to 100 nm or 20 nm to 50 nm.

[0101] The p-doped group III nitride layer is preferably 5 × 10 18 cm -3 ~8×1020 cm -3 It has a p-type doping concentration. The p-doped Group III nitride layer contains In and Ga, and has a thickness of 20-200 nm, preferably 50-100 nm. The doping concentration may vary within this layer, with a spike in doping level in the last 10-30 nm of the layer. To activate the Mg acceptor, the structure is annealed in an MOCVD reactor or annealing oven. The annealing temperature is in the range of 700-850°C in an N2 or N2 / O2 atmosphere.

[0102] Since both the EBL and the p-doped layer are p-doped, these layers are called p-doped regions.

[0103] The method includes the further steps of forming a second LED structure, removing a portion of the second mask to expose the region of the first LED structure, forming electrical contacts in the exposed region of the first LED structure, and preferably forming an electrical connection with the p-doped portion of the first LED structure. An electrical connection is also formed with the p-doped portion of the second LED structure.

[0104] The passivation layer and a portion of the dielectric mask layer can be removed by wet etching, dry etching, or a combination of both. For wet etching, buffer oxide etching, diluted hydrofluoric acid, phosphoric acid, or mixtures thereof may be used.

[0105] The formation of the p-doped electrical connections involves the step of depositing a transparent conductive oxide (e.g., ITO, ZnO, or other compatible oxides) or metal layer on the p-type regions of the first and second LED structures. This covering can be performed in a single step or multiple steps. The metal completely or partially covers the p-type regions. The metals include Ti, Pt, Pd, Rh, Ni, Au, Ag, etc. The thickness of a complete metal stack is 200 nm to 2000 nm or 500 nm to 1000 nm.

[0106] This structuring can be performed using standard semiconductor processing methods, including resist coating, photolithography, and lift-off. Combined with dry or wet structuring, this allows the conductive metal layer to completely or partially cover the top surface of the p-doped region.

[0107] The method preferably includes the step of forming an electrical connection with the p-doped area, then exposing the region of the n-type connection layer, and forming an electrical contact with the n-type connection layer. The region of the n-type connection layer is preferably exposed by removing a portion of the second mask layer. Openings are generated in the second mask layer using standard photolithography techniques. The size of the openings varies between 200 nm and 50,000 nm. The distance between the openings is between 500 nm and 30,000 nm. Openings are generated only in areas of the device that do not contain the LED structure. Dry etching is used, and the passivation layer is etched using a fluorine-based gas.

[0108] Formation of the n-doped electrical connection preferably involves depositing metal contacts on the exposed region of the n-type connection layer by depositing metal within openings created in a second mask layer. This covering can be performed in one or more steps. The metals include Ti, Pt, Pd, Rh, Ni, Au, Ag, etc. The thickness of the metal stack contacts is, for example, 200 nm to 2000 nm, or 500 nm to 1000 nm.

[0109] Third LED structure By advantageously using the method of the present invention, an LED device having three different emission wavelengths can be provided by forming a third LED structure on an n-doped connection layer.

[0110] The third LED structure can be formed on the n-doped connecting layer so as to be positioned above the porous region, or it can be positioned above the non-porous region below the connecting layer.

[0111] In one preferred embodiment, the third LED structure may be formed simultaneously with either the first LED structure or the second LED. Therefore, the third LED structure has the same structure as either the first or second LED structure.

[0112] In another preferred embodiment, a second LED structure can be formed on a second exposed region of the connecting layer, and then the second LED structure can be passedivated by covering it with a third mask layer of dielectric material. The third mask layer and a portion of the mask layer beneath it are then removed to expose a third exposed region of the n-doped connecting layer. A third LED structure, configured to emit light at a third wavelength different from the first and second wavelengths, is then formed on the third exposed region.

[0113] Next, the step of creating electrical contacts for all three LED structures can be performed as described above.

[0114] The third LED structure is an LED structure as described above, configured to emit light at a different wavelength than the first and second LED structures. In a particularly preferred embodiment, the LED device includes one red-emitting LED structure, one green-emitting LED structure, and one blue-emitting LED structure.

[0115] Preferred Embodiment In a preferred embodiment, the method for manufacturing an LED includes the following steps.

[0116] Step 1: On the substrate, the n-type charge carrier density is 1 × 10⁻⁶. 18 cm -3 A GaN layer is deposited, and a porous region of a group III nitride material is formed using the porosity technique described in international patent application PCT / GB2017 / 052895.

[0117] Step 2: An n-type connection layer of n-(Al,In)GaN (a highly doped n-type (Al,In)GaN such as n-GaN, n-AlGaN, or n-InGaN) is grown on top of the porous DBR.

[0118] Step 3: A first mask layer of a dielectric material, such as SiO2, is deposited on the upper surface of the n-GaN.

[0119] Step 4 The dielectric material is patterned by lithography, nanoimprint, or other suitable technique, and then a portion of the mask layer 1 is removed by a wet chemical etching or dry etching process. Removing a portion of the dielectric layer exposes the first exposed region of n-GaN underneath. The dielectric removal area is preferably the shape and size of a microLED, for example, 100 μm × 100 μm or less.

[0120] Step 5: A first LED structure is formed on the first exposed region by depositing an n-doped region of n-(Al,In)GaN onto the exposed portion of n-(Al,In)GaN, and then growing a quantum well (QW) active light-emitting region (which may include multiple quantum wells). The quantum wells can be InGaN, AlGaN, InN, InAlN, or AlInGaN, and the quantum barrier surrounding the quantum well layer can be GaN, AlN, AlGaN, AlInGaN, or InAlN. The quantum wells, their structure, and their function are defined in international patent application PCT / GB2019 / 050213. The lateral dimensions of the QW are the same as those of the exposed portion of n-(Al,In)GaN. This means that the QW region is of a desirable size for a microLED.

[0121] Step 6 A layer of p-(Al,In)GaN (highly doped p-type (Al,In)GaN) is deposited on top of the quantum well region. The lateral dimensions of the p-GaN layer are the same as the QW region and also the same as the exposed n-GaN region. Thus, the p-GaN, QW region, and n-doped region form a first LED structure with desirable lateral dimensions for a microLED.

[0122] Step 7 A second mask layer of dielectric material, such as SiO2, is deposited on the first dielectric layer so that the second dielectric layer covers the edges or sidewalls of the QW and p-(Al,In)GaN layers. This second layer of dielectric material is a passivation layer for the first LED structure.

[0123] Step 8 The second mask layer is patterned by lithography, nanoimprint, or other suitable technique, and then a portion of the second mask layer is removed by a wet chemical etching or dry etching process. Removing a portion of the second mask layer exposes a second exposed region of the underlying n-GaN connection layer without damaging the passivated first LED structure. The dielectric removal area is preferably the shape and size of a microLED, for example, 100 μm × 100 μm or less. The second exposed region can be positioned, for example, adjacent to the first LED structure.

[0124] Step 9 A second LED structure is grown on a second exposed region of the n-GaN n-doped connection layer. The second LED structure has a layered structure similar to that of the first LED structure as described above, but the second LED structure is configured to emit light at a different wavelength than that of the first LED structure.

[0125] Step 10: A portion of the second mask layer is removed by a wet chemical etching or dry etching process to expose the p-(Al,In)GaN layer of the first LED structure.

[0126] Step 10 Electrical p-contacts are deposited on the exposed p-(Al,In)GaN portions of both the first and second LED structures, so that the p-contacts make electrical contact with the p-(Al,In)GaN layers of these LED structures.

[0127] Step 11 In order to form an electrical n-contact with the n-doped connection layer, one or more regions of the second mask layer (from the wafer areas not occupied by the first and second LED structures) are removed to expose the region of the n-doped connection layer. Then, an electrical n-contact with the connection layer is formed by depositing a metal contact according to known techniques.

[0128] This method provides LED structures that emit light at two different wavelengths on the same substrate. A further advantage is that the active QW layer and p-(Al,In)GaN layer of the two LED structures are not etched at any point during the manufacturing process. Furthermore, n-contacts for small LED structures can be formed very easily by positioning them on an n-type connection layer.

[0129] Avoiding dry etching damage to the active layer of micro-LEDs offers significant advantages compared to micro-LEDs prepared using conventional techniques. In conventionally fabricated micro-LEDs, etching damage to the sidewalls of the p-GaN and QW layers significantly affects the extremely small pixels formed by the micro-LEDs. This can impair the reliability and brightness of the micro-LEDs.

[0130] Micro-LEDs fabricated using this method are not susceptible to plasma etching damage to the sidewalls of the LED stack, thus offering the advantages of high reliability and high brightness.

[0131] If desired, the process of making a semiconductor structural layer porous by electrochemical etching is described in international patent applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0132] The method described above relates to the configuration of a p-side light-emitting LED.

[0133] n-side light-emitting micro-LEDs can be manufactured using a similar method by incorporating a "flip-chip" step and bonding the micro-LED to a silicon CMOS backplane.

[0134] SiO2 is just one example of a dielectric suitable for masking and passivation; other dielectrics may be used instead.

[0135] Semiconductor material layers can be deposited by epitaxial growth. The aforementioned layers can be formed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD) (also known as metal-organic vapor phase epitaxy (MOVPE)), hydride vapor phase epitaxy (HVPE), amonothermal processes, or other conventional processes suitable for the growth of group III nitride materials.

[0136] Manufacturing of MicroLED Arrays A second aspect of the present invention provides a method for manufacturing an array of LEDs. This method is The steps include forming an n-doped connecting layer of a group III nitride material on a porous region of a group III nitride material, The steps include forming a first electrical insulating mask layer on an n-doped group III nitride layer, The steps include removing a portion of the first mask to expose the first array of the exposed region of the n-doped connection layer, The steps include forming a first LED structure configured to emit light at a first emission wavelength on each exposed region of a first array on an n-doped connection layer, The steps include forming a second electrical insulation mask layer on a first LED structure and an n-doped connection layer, The steps include removing a portion of the second mask layer to expose the second array of the exposed region of the n-doped connection layer, The steps include forming a second LED structure on each exposed region of a second array on an n-doped connection layer, configured to emit light at a second emission wavelength different from the first emission wavelength, Includes.

[0137] A method for manufacturing an LED array preferably includes the method of the first embodiment, in which a plurality of exposed regions of an n-doped connection layer are formed and a plurality of LED structures are formed in these exposed regions. By removing a portion of the mask layer to expose the array of exposed regions, the layout of the LED array can be designed so that pixels of a desired size and density are formed by the LEDs.

[0138] Preferably, the LED structure is a micro-LED structure.

[0139] Preferably, the first LED structure and / or the second LED structure are positioned on a porous region. In some embodiments, the first LED structure may be positioned on a porous region and the second LED structure on a non-porous region, or vice versa.

[0140] The first array of exposed areas and the second array of exposed areas are preferably a uniform arrangement or pattern of identical exposed areas. For example, the first and / or second array includes multiple rows and columns of regularly spaced exposed areas.

[0141] The method involves forming a first LED structure on each exposed region of a first array of exposed regions, and this involves forming a plurality of first LED structures. The step of forming a second LED structure on each exposed region of a second array of exposed regions can be said to be forming a plurality of second LED structures.

[0142] When exposing the first array of exposed regions and the second array of exposed regions, the distance between adjacent exposed regions is preferably 500 nm to 30000 nm, or 750 nm to 20000 nm, or 1000 nm to 15000 nm.

[0143] The LED array is advantageously formed on a single substrate. By using a deposition step in which a semiconductor material layer is simultaneously deposited on each exposed region of the connecting layer, multiple first LED structures and multiple second LED structures can be formed simultaneously.

[0144] The method optionally includes the steps of forming a third electrical insulating mask layer on the first and second LED structures and the n-doped connection layer, removing a portion of the third mask layer to expose a third array in the exposed region of the n-doped connection layer, and forming a third LED structure on each exposed region of the third array on the n-doped connection layer, configured to emit light at a third emission wavelength different from the emission wavelengths of the first and second.

[0145] This method allows arrays of LEDs or micro-LEDs of different colors to be formed on the same wafer without requiring an etching step to cut the LED structure into individual pixels to the desired lateral dimensions. Therefore, the micro-LEDs in the array avoid etching damage to the sidewalls of the LED structure.

[0146] The method of the second embodiment is advantageous in relation to all of the features described above in connection with the first embodiment of the present invention.

[0147] Manufacturing method for 3-color LED devices According to a third aspect of the present invention, a method for manufacturing a three-color LED device is provided. This method is The steps include forming an n-doped connecting layer of a group III nitride material on a porous region of a group III nitride material and on a non-porous region of a group III nitride material in the same plane as the porous region, The steps include forming a first electrical insulation mask layer on an n-doped connection layer, The steps include removing a portion of the first mask layer to expose the first exposed region of the (upper) n-doped connecting layer above the porous region, The steps include removing a portion of the first mask layer to expose a second exposed region of the (upper) n-doped connecting layer above the non-porous region, The steps include forming a first LED structure configured to emit light at a first emission wavelength on a first exposed region of an n-doped connection layer, The steps include forming a second LED structure configured to emit light at a second emission wavelength on a second exposed region of the n-doped connection layer, The steps include forming a second electrical insulation mask layer on a first LED structure, a second LED structure, and an n-doped connection layer, The steps include removing a portion of the second mask layer to expose a third exposed region of the n-doped connection layer, The steps include forming a third LED structure on a third exposed region of an n-doped connection layer, configured to emit light at a third emission wavelength different from the first and second emission wavelengths, Includes.

[0148] Since the three LED structures emit light at three different wavelengths in response to the electrical bias applied to them, this device is a three-color LED device.

[0149] In a particularly preferred embodiment, the first, second, and third emission wavelengths are red, green, and blue. Thus, the three-color LED device is a red-green-blue (RGB) LED device.

[0150] In a preferred embodiment, the second LED structure can be identical to the first LED structure, and the first and second LED structures are formed simultaneously. In this embodiment, the first and second LED structures generate different first and second emission wavelengths due to a wavelength shift caused by a porous region beneath the first LED structure that is not present in the second LED structure. For example, both the first and second LED structures are conventional green LED structures (i.e., LED structures known to emit green light when an electrical bias is applied). However, in the present invention, the porous region causes a wavelength shift, so the first LED structure in the three-color LED device favorably emits red light when an electrical bias is applied, and the second LED structure emits green light as expected.

[0151] The third exposed region of the n-doped connecting layer is preferably formed above the non-porous region of the group III nitride material. For this reason, the third LED structure is preferably grown above or on the non-porous region of the template, rather than on the porous region.

[0152] The third LED structure is a conventional LED structure configured to emit light at a known wavelength when an electrical bias is applied. Preferably, the third LED structure is a blue LED. Particularly preferably, the third LED structure is a blue LED formed by the process described in WO2019 / 145728. For example, a blue LED is formed by electrochemically porousizing the luminescent quantum well layer in the as-grown third LED structure. As described in WO2019 / 145728, the porosity of the quantum well layer results in a blue shift in the emission spectrum of the LED structure.

[0153] LED devices Another aspect of the present invention relates to an LED device which is an LED device or microLED device manufactured by the method described above.

[0154] According to a fourth aspect of the present invention, an LED device is provided. This LED device is An n-doped connecting layer of group III nitride material on a porous region of group III nitride material, An electrical insulating mask layer on an n-doped group III nitride layer, A first LED structure configured to emit light at a first emission wavelength, A second LED structure configured to emit light at a second emission wavelength different from the first emission wavelength, The LED structure comprises at least a portion of the first and second LED structures extending through the gap in the electrical insulation mask layer and in contact with the n-doped connection layer.

[0155] The LED device is preferably an LED device manufactured using the method described above in relation to a first aspect of the present invention. Since the LED device includes two LED structures that emit light at different wavelengths, it can be called a multicolor LED, a multicolor LED device, or a multiwavelength LED device.

[0156] As described above, the n-doped connecting layer of the group III nitride material can extend over a continuous porous region of the group III nitride material, or over a porous region of the group III nitride material and a non-porous region of the group III nitride material that are arranged in the same plane as each other.

[0157] Preferably, at least one of the first LED structure and the second LED structure is positioned on a porous region. In some embodiments, both the first LED structure and the second LED structure are positioned on a porous region. In other embodiments, one of the first LED structure and the second LED structure is positioned on a porous region and the other is positioned on a non-porous region. The porous region can be a porous layer, and the LED device includes an n-doped connecting layer of group III nitride material on top of a porous layer of group III nitride material. In some embodiments, the porous region includes a plurality of porous layers and optionally a plurality of non-porous layers. In a preferred embodiment of the present invention, the porous region is a stack of alternating porous and non-porous layers, where the top surface of the stack defines the upper part of the porous region and the bottom surface of the stack defines the lower part of the porous region. An n-doped connecting layer of group III nitride material is formed on top of the porous region, which includes a stack of porous layers of group III nitride material.

[0158] In a preferred embodiment, the n-doped connecting layer of the group III nitride material is positioned on a stack of multiple porous layers of the group III nitride material. Thus, the porous region is not a single porous layer of the group III nitride material, but rather a stack of multiple layers of the group III nitride material in which at least some layers are porous.

[0159] The stack of porous layers is preferably a stack consisting of alternating layers of porous and non-porous layers. Preferably, the stack includes 5 to 50 pairs of porous and non-porous layers stacked on top of each other. The porous layers preferably have a thickness of 10 nm to 200 nm, and the non-porous layers preferably have a thickness of 5 nm to 180 nm.

[0160] Preferably, each porous layer within the porous region or stack has a porosity of 10% to 90% or 20% to 70%.

[0161] The LED device preferably includes a non-porous intermediate layer of a porous region of a group III nitride material between the porous region and an n-doped group III nitride connecting layer. Preferably, the porous region is formed by electrochemical porosity through a non-porous layer of the group III nitride material, which is carried out using the methods of PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728), and the non-porous layer of the group III nitride material usually forms a non-porous intermediate layer on top of the porous region. The non-porous intermediate layer advantageously provides a smooth surface for the growth of the connecting layer during manufacturing.

[0162] In a particularly preferred embodiment, the porous layer stack includes a porous distributed Bragg reflector (DBR) or optical filter, and an n-doped connecting layer of group III nitride material is positioned on top of the porous DBR or optical filter of group III nitride material. The porous DBR or optical filter is formed from a stack of alternating porous / non-porous layers, where differences in porosity between adjacent layers create differences in refractive index between adjacent layers, resulting in differences in transmission and reflectivity properties.

[0163] The LED device includes an intermediate layer of a non-porous group III nitride material positioned between a porous region and a connecting layer. The thickness of the intermediate layer is preferably 1 nm to 3000 nm, more preferably 20 nm to 2000 nm, or 50 nm to 1000 nm.

[0164] The n-doped connecting layer of the group III nitride material preferably has a thickness of 100 nm to 2000 nm or 200 nm to 1000 nm. 17 cm -3 ~5×10 20 cm -3 It has a doping concentration of at least 1 × 10⁻¹⁶. 18 cm -3 It has an n-type charge carrier concentration.

[0165] Preferably, the mask layer extends over the entire surface of the n-doped connecting layer of the group III nitride material, so that the connecting layer is completely covered with dielectric material, except for the first and second LED structures. The mask layer is SiO2, SiN, SiON, AlO x , or can be formed from other suitable dielectric materials.

[0166] The thickness of the mask layer is 20 nm to 2000 nm, preferably 200 nm to 1500 nm, and particularly preferably 400 nm to 1000 nm.

[0167] By patterning and lithographically removing a portion of the mask layer, the footprint of the LED structure can be controlled during manufacturing, allowing the LED structure to have any desired shape. For example, the footprint (plan view) of the LED structure can be circular, square, rectangular, hexagonal, or triangular.

[0168] The LED structure has lateral dimensions that classify it as a "micro-LED". For example, the width and / or length (or diameter if the LED is circular) of the LED structure is 0.05 μm to 100 μm, preferably 0.05 μm to 30 μm, particularly preferably less than 10 μm, for example 0.1 μm to 10 μm or 0.5 μm to 10 μm. In a preferred embodiment, the length, width, or diameter of the LED structure is less than 50 μm, or less than 40 μm, or less than 30 μm, or less than 20 μm, or less than 10 μm. Particularly preferably, the LED structure has a width or diameter of less than 10 μm, so that the LED structure forms a micro-LED pixel of a size of less than 10 μm.

[0169] The first LED structure is, The first n-doped section, The first p-doped section, A first light-emitting region is positioned between the first n-doped portion and the first p-doped portion, Includes.

[0170] The second LED structure is, The second n-doped section, The second p-doped section, A second light-emitting region is positioned between the second n-doped region and the second p-doped region, Includes.

[0171] Preferably, at least a portion of the first LED structure and the second LED structure penetrates the electrical insulating dielectric mask layer, so that each LED structure is in electrical contact with the n-doped connection layer.

[0172] As described above in relation to the first aspect of the present invention, the LED structure can take various forms having multiple layers with different thicknesses, compositions, and charge carrier concentrations.

[0173] The features of the LED structure described above in relation to the first aspect of the present invention also apply equally to the LED device of the third aspect.

[0174] The first and / or second LED structure may include an active layer which can be a quantum well or a quantum layer (e.g., a porous quantum well containing multiple 3D quantum structures). The quantum well can be made of InGaN, AlGaN, InN, InAlN, or AlInGaN, and the quantum barrier surrounding the quantum well layer can be made of GaN, AlN, AlGaN, AlInGaN, or InAlN.

[0175] LED structures have lateral dimensions (length and width) smaller than 100 μm × 100 μm, sometimes tens of nanometers or even smaller. In this context, the "height" of an LED is the dimension in the intended direction of light emission.

[0176] The first light-emitting region is preferably composed of In x Ga 1-x It includes one or more light-emitting layers having N, where 0.10 ≤ x ≤ 0.40, preferably 0.18 ≤ x ≤ 0.30, and particularly preferably 0.22 ≤ x ≤ 0.30.

[0177] The second light-emitting region is preferably composed of In y Ga 1-y It includes one or more light-emitting layers having N, where 0.20 ≤ y ≤ 0.40, preferably 0.26 ≤ y ≤ 0.40, and particularly preferably 0.30 ≤ y ≤ 0.40.

[0178] The first and second emission regions preferably have different atomic indium content and therefore different emission wavelengths.

[0179] The light-emitting region preferably includes one or more InGaN quantum wells, and particularly preferably includes 1 to 7 quantum wells.

[0180] The LED device optionally includes further LED structures configured to emit light at wavelengths different from the first and second wavelengths. For example, the LED device further includes a third LED structure. A portion of the third LED structure extends through a gap in the electrical insulation mask layer and is in contact with the n-doped connection layer.

[0181] LED array According to a fifth aspect of the present invention, an array of LEDs is provided. The array of LEDs is formed on a shared substrate, such as a single semiconductor wafer, and comprises a plurality of LED devices according to a fourth aspect of the present invention.

[0182] This invention provides an array of LEDs. This array of LEDs is An n-doped connecting layer of group III nitride material on a porous region of group III nitride material, An electrical insulating mask layer on an n-doped group III nitride layer, Multiple gaps in the electrical insulation mask layer, A plurality of first LED structures configured to emit light at a first emission wavelength, Multiple second LED structures configured to emit light at a second emission wavelength, Each LED structure is provided with at least a portion of it extending through the gap in the electrical insulation mask layer and in contact with the n-doped connection layer.

[0183] An LED array is a sequence of LEDs arranged in an orderly fashion, for example, a regular arrangement of multiple rows and columns, each containing multiple LEDs.

[0184] The LED array is an LED array manufactured using the method of the second aspect of the present invention.

[0185] Preferably, the array is an array of microLEDs, each of which emits light of two different colors.

[0186] The LED array further includes a plurality of third LED structures configured to emit light at a third emission wavelength different from the first and second emission wavelengths.

[0187] 3-color LED device According to a sixth aspect of the present invention, a three-color LED structure is provided. This three-color LED structure is An n-doped connecting layer of group III nitride material on a porous region of group III nitride material, An electrical insulating mask layer on an n-doped group III nitride layer, A first LED structure configured to emit light at a first emission wavelength, A second LED structure configured to emit light at a second emission wavelength different from the first emission wavelength, A third LED structure configured to emit light at a third emission wavelength different from the first and second emission wavelengths, The first, second, and at least a portion of the LED structure are in contact with the n-doped connection layer.

[0188] Particularly preferred is a three-color LED device, which is a red-green-blue (RGB) LED device, and the first, second, and third LED structures are configured to emit red light, green light, and blue light when an electrical bias is applied.

[0189] As described above, the n-doped connecting layer of the group III nitride material extends over a continuous porous region of the group III nitride material, or extends over a porous region of the group III nitride material and a non-porous region of the group III nitride material that are located in the same plane.

[0190] Preferably, at least one of the first LED structure, the second LED structure, and the third LED structure is positioned on a porous region. In some embodiments, both the first LED structure and the second LED structure are positioned on a porous region. In other embodiments, one of the first LED structure and the second LED structure is positioned on a porous region, and the other is positioned on a non-porous region.

[0191] The first LED structure is preferably positioned on a porous region of a group III nitride material, while the second LED structure is preferably not positioned on a porous region of a group III nitride material.

[0192] In some preferred embodiments, the second LED structure is identical to the first LED structure, and the first and second LED structures emit light at different emission wavelengths due to a porous region located beneath the first LED structure.

[0193] In a preferred embodiment, the first LED structure is an LED structure that emits light at a peak wavelength of 515-540 nm under an applied electrical bias. The porous region of the group III nitride material beneath the first LED structure shifts the emission wavelength of the first emission region of the LED structure to 600-650 nm. As a result, the first LED structure emits red light.

[0194] In a preferred embodiment, the second LED structure is also an LED structure that emits light at a peak wavelength of 515 to 540 nm under an electrical bias applied to it. Preferably, since the second LED structure is not positioned on a porous region, it emits light at a predicted peak wavelength of 515 to 540 nm under an electrical bias. Therefore, the first LED structure can emit green light.

[0195] One or more light-emitting layers in the first LED structure and the second LED structure are composed of In x Ga 1-x N can be such that 0.10 ≤ x ≤ 0.40, preferably 0.18 ≤ x ≤ 0.30, and particularly preferably 0.22 ≤ x ≤ 0.30.

[0196] Preferably, the third LED structure is not positioned on a porous region of the group III nitride material.

[0197] In a particularly preferred embodiment, the third LED structure is configured to emit light at a peak wavelength of 415-500 nm, preferably 430-470 nm, under an electrical bias.

[0198] One or more light-emitting layers in the third LED structure are composed of In z Ga 1-z N can be such that 0.10 ≤ z ≤ 0.30, preferably 0.12 ≤ z ≤ 0.25, and particularly preferably 0.15 ≤ z ≤ 0.20.

[0199] Particularly preferably, the third LED structure includes one or more porous light-emitting layers. As described in WO2019 / 145728, the porosity of the light-emitting layer favorably generates additional quantum confinement, which results in a blue shift of the emission wavelength of the third LED structure, so that the third LED structure emits blue light when an electrical bias is applied.

[0200] In a particularly preferred embodiment, the first, second, and third LED structures are: The first LED structure emits light at a peak wavelength of 560 nm to 750 nm, preferably 600 nm to 650 nm, under electrical bias. The second LED structure emits light at a peak wavelength of 500nm to 560nm, preferably 515 to 550nm, under electrical bias. The third LED structure emits light at a peak wavelength of 400-500 nm, preferably 430-470 nm, under electrical bias. It is structured in this way.

[0201] All of the features described above in relation to any of the first, second, third, fourth, fifth, or sixth aspects of the present invention are equally applicable to the aspects of the present invention. [Brief explanation of the drawing]

[0202] Specific embodiments of the present invention will now be described with reference to the drawings.

[0203] Figure 1 shows a porous template suitable for an LED device or micro-LED array according to the present invention. Figures 2 to 22 are schematic side cross-sectional views illustrating the steps for manufacturing an array of five micro-LEDs according to a preferred embodiment of the present invention. Figures 23 to 44 are schematic side cross-sectional views illustrating the steps for manufacturing a red, green, and blue LED device according to a preferred embodiment of the present invention. Figure 45 is a graph showing the normalized electroluminescence (EL) intensity versus wavelength for InGaN LEDs on a non-porous substrate under various current injection conditions. Figure 46 is a graph showing the normalized electroluminescence (EL) intensity versus wavelength for the same InGaN LED as in Figure 45, grown on a porous region according to a preferred embodiment of the present invention, under various current injection conditions. Figures 47 and 48 show alternative steps for preparing a red-green-blue LED device according to a preferred embodiment of the present invention. [Modes for carrying out the invention]

[0204] Figure 1 shows a porous template suitable for an LED device according to the present invention.

[0205] The porous template includes a porous region of group III nitride material on a substrate, with a non-porous layer of group III nitride material positioned on top of the porous region. Optionally, a further layer of group III nitride material may also exist between the substrate and the porous region.

[0206] As detailed above, a porous region can be provided by epitaxially growing an n-doped region of a group III nitride material, followed by an undoped layer of the same group III nitride material, and then porousizing the n-doped region using a porousization process. The porousization process is described in international patent applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728).

[0207] The porous region comprises one or more layers of one or more group III nitride materials and has a certain range of thickness. In a preferred embodiment, the porous region comprises, for example, GaN and / or InGaN and / or AlGaN.

[0208] In a preferred embodiment, a microLED according to the present invention may include the following layers and is manufactured using the stepwise process described below.

[0209] The following description of the LED structure of microLEDs relates to a top-emission architecture, which is described from bottom to top, but the present invention is equally applicable to a bottom-emission architecture.

[0210] Figure 2. Substrate and Group III nitride layer for porous structure A compatible substrate is used as the starting surface for epitaxial growth. The substrate can be silicon, sapphire, SiC, β-Ga2O3, GaN, glass, or metal. The substrate crystal orientation can be polar, semipolar, or nonpolar. The substrate size is 1 cm². 2The diameters vary from 2 inches, 4 inches, 6 inches, 8 inches, 12 inches, 16 inches, and beyond. The substrate thickness is greater than 1 μm, for example, 1 μm to 15,000 μm. Preferably, the substrate is a semiconductor wafer. An advantage of the present invention is that arrays of micro-LEDs can be manufactured simultaneously on a full-size semiconductor wafer. The illustrated example shows two micro-LEDs being formed on a shared template, but it is also possible to manufacture multiple arrays of micro-LEDs on the same wafer using the same method.

[0211] One or more layers of a group III nitride material are epitaxially grown on a substrate. The group III nitride layer may contain one or more combinations of the elements Al, Ga, and In (a binary, ternary, or quaternary layer).

[0212] The thickness T of the porous group III nitride layer is preferably at least 1 nm, at least 5 nm, at least 10 nm, or at least 50 nm, or at least 100 nm, for example, 10 to 10000 nm, preferably 10 nm to 4000 nm.

[0213] The porous group III nitride layer is 1 × 10 17 cm -3 ~5×10 20 cm -3 It includes a doped region having an n-type doping concentration. The group III nitride layer also includes an undoped layer (not shown) of group III nitride material above the doped region.

[0214] The doped region terminates on the exposed upper surface of the group III nitride layer. In this case, the surface of this layer becomes porous during electrochemical etching.

[0215] Preferably, the doped region of the group III nitride material is covered by an undoped intermediate (or "cap") layer of the group III nitride material, so that the doped region is subsurface of the semiconductor structure. The subsurface starting depth (d) of the doped region is, for example, 1 nm to 3000 nm or 5 nm to 2000 nm.

[0216] In the examples shown in Figures 2 to 22, the group III nitride layer is porousd by known electrochemical porosity techniques to form a single, uniform porous layer of group III nitride material.

[0217] Figure 3 Porous region The n-doped group III nitride layer is deposited on the substrate and then porousd by a wafer-scale porosification process described in international patent applications PCT / GB2017 / 052895 (published as WO2019 / 063957) and PCT / GB2019 / 050213 (published as WO2019 / 145728). During this process, the n-doped group III nitride material becomes porous, while the undoped regions of the group III nitride material remain non-porous. The porosity of the porous layer is controlled by an electrochemical etching process, preferably 10% to 90%, and more preferably 20% to 70%.

[0218] After the porosity-forming step, the structure includes a non-porous intermediate layer superimposed on the porous layer.

[0219] Figure 4 Connecting layer As shown in Figure 3, after porosity preparation, a connecting layer 1 is grown on the wafer. The connecting layer is an n-doped group III nitride (preferably GaN) layer with a thickness of 100-2000 nm (layer 1 in Figure 3), and the n-type charge carrier concentration is 1 × 10⁻⁶. 17 cm -3 ~5×10 20 cm -3 Preferably 1 × 10 18 cm -3 Higher.

[0220] The connecting layer 1 is formed of a group III nitride material and contains one or more combinations of the elements Al, Ga, and In (a binary, ternary, or quaternary layer). The connecting layer is doped with a suitable n-type dopant material such as Si, Ge, C, or O.

[0221] Figure 5 First mask layer Next, an electrical insulating first mask layer 2 is deposited on the wafer surface so as to cover the connecting layer 1. The purpose of the mask layer 2 is to protect a specific area of ​​the wafer as a mask in the next step and to enable selective area epitaxy on this template.

[0222] This mask layer 2 is made of SiO2, SiN, SiON, and AlO x , or any other suitable layer. The thickness of this layer can be 20 nm to 1000 nm, preferably about 100 nm to 700 nm.

[0223] Possible methods for depositing this layer include PECVD, sputtering, ALD, vapor deposition, or in-situ MOCVD.

[0224] Figure 6 First exposed region of the connecting layer Using standard lithography or photolithography techniques, openings are created in the non-conductive first mask layer 2, exposing a first exposed area on the surface of the connecting layer. The openings are created using either wet etching or dry etching methods.

[0225] In the schematic diagram of the drawing, two first exposed regions are formed on the first mask layer 2. In a preferred embodiment, a regular array of multiple first exposed regions is formed on the masked semiconductor wafer.

[0226] In a particularly preferred example, inductively coupled dry etching (ICP-RIE) is used to remove SiO2 from two areas, thereby creating two exposed regions on the surface of the connecting layer 1 that are not covered by the first mask layer 2.

[0227] The size of the first exposed region is 200 nm to 50000 nm, preferably 500 nm to 10000 nm or 1000 nm to 8000 nm.

[0228] The distance between adjacent first exposed regions is preferably greater than the lateral width of the first exposed region, and preferably at least 1.5 times or at least 2 times the lateral width of the first exposed region. The distance between adjacent first exposed regions is selected so that there is space between adjacent first exposed regions for growing further LED structures.

[0229] The distance between the two first exposed regions can be 500 nm to 30000 nm, for example, 1000 nm to 10000 nm or 5000 nm to 8000 nm.

[0230] The shape of the exposed area can be circular, square, rectangular, hexagonal, triangular, etc. The width or diameter of the aperture is preferably less than 100 μm, so that the LED structure formed on the exposed area is classified as a micro-LED. The exposed area preferably has a width of 0.05 μm to 30 μm, and particularly preferably 10 μm or less.

[0231] Subsequently, the first LED structure is grown on all of the first exposed areas of the connection layer 1, so these exposed areas become micro-LED pixels.

[0232] Figure 7. First N-doped region After forming the first exposed region of the connecting layer 1, an n-doped layer 3 of a group III nitride material is deposited on the first exposed region.

[0233] In the specific example shown, the n-doped layer 3 is grown by MOCVD. This growth is performed only within a first exposed region on the surface of the n-doped connecting layer 1. Si is used as the dopant for the n-doped layer 3, and the doping concentration is at least 1 × 10⁻⁶. 19 cm -3 Higher.

[0234] The n-doped layer 3 is a bulk group-III nitride layer containing indium, or a stack of thin group-III nitride layers with or without indium, or a bulk group-III nitride layer or a stack of group-III nitride layers in which the atomic percentage of indium varies within the bulk layer or stack. The atomic percentage of indium varies from 0.5% to 25%. The total thickness of the n-type layer 3 varies between 2 nm and 200 nm, for example between 50 nm and 100 nm. When using a stack, the thickness of each individual layer within the stack varies between 1 and 40 nm. The n-doped layer 3 has an n-doping concentration of 1×10 17 cm -3 ~5×10 20 cm -3 .

[0235] Figure 8 First light-emitting region After growing the first n-type layer 3 in the first exposed region, the first light-emitting region 4 is grown.

[0236] The first light-emitting region 4 includes at least one light-emitting layer. Each light-emitting layer can be a quantum well (QW), preferably an InGaN quantum well (QW). Preferably, the light-emitting region includes 1 to 7 quantum wells. Adjacent quantum wells are separated by a barrier layer of a group-III nitride material having a composition different from that of the quantum wells.

[0237] One or more light-emitting layers can be referred to as "quantum wells" throughout this document, but can take various forms. For example, the light-emitting layer can be a continuous layer of InGaN, or can be continuous, fragmented, intermittent, include gaps, or be nanostructured such that it substantially includes a plurality of 3D nanostructures in which the quantum wells behave as quantum dots.

[0238] The quantum wells and barriers are grown in a temperature range of 600 to 800 °C.

[0239] Each quantum well preferably consists of an InGaN layer having an atomic indium percentage of 18 to 30%, preferably more than 22%, preferably less than 30%.

[0240] The thickness of each quantum well layer is 1.5 to 8 nm, preferably 1.5 nm to 6 nm or 1.5 nm to 4 nm.

[0241] The quantum well may or may not be covered with a thin (0.5-3 nm) group III nitride QW capping layer. This capping layer contains one or more combinations of the elements Al, Ga, and In (quaternary layer, ternary layer).

[0242] The QW capping layer (if present) is a layer added immediately after QW growth and consists of AlN, AlGaN with an Al% of 0.01-99.9%, GaN, and InGaN with an In% of 0.01-30%.

[0243] Group III nitride QW barriers separate the luminescent layer (quantum well) and contain one or more combinations of the elements Al, Ga, and In (quaternary layer, ternary layer).

[0244] Since one or more QW capping layers and QW barriers form part of the light-emitting region 4, these layers are not shown with individual reference numbers in the drawings.

[0245] At the end of growth, the height of the luminescent region 4 is within + / - 200 nm of the height of the first mask layer 2.

[0246] The target emission wavelength of emission region 4 is 515 nm to 540 nm, preferably 530 nm.

[0247] Figure 9 Cap layer and EBL After the quantum well is grown, an undoped cap layer 5 is grown. The undoped cap layer 5 is formed after the growth of the complete luminescence region, for example, after the growth of the stack of QW, QW cap layer, and QW barrier layer, and can therefore be called the luminescence region cap layer.

[0248] The cap layer (light-emitting region cap layer) 5 is a standard layer that is very well known in the growth scheme of Group III nitride LEDs.

[0249] The thickness of the cap layer can be 5 to 30 nm, preferably 5 to 25 nm or 5 to 20 nm.

[0250] Electron Block Layer (EBL) After the cap layer 5, an aluminum-containing group III nitride electron blocking layer 6 (EBL) is grown. The thickness of the EBL can typically be 10-50 nm. The Al% is, for example, 5-25%, but higher Al content is also possible.

[0251] EBL is doped with an appropriate p-type doping material. The doping concentration is 5 × 10⁻¹⁰. 18 cm -3 ~8×10 20 cm -3 That is the case.

[0252] Figure 10 First p-doped layer A first p-doped layer 7 is grown above the electron block layer (EBL) 6.

[0253] The p-type region is preferably doped with Mg, and the p-type doping concentration in the p-type layer is preferably 5 × 10⁻¹⁰ 18 cm -3 ~8×10 20 cm -3 That is the case.

[0254] The p-doped Group III nitride layer contains In and Ga.

[0255] The doping layer is preferably 20-200 nm thick, and particularly preferably 50-100 nm thick. The doping concentration may vary within the p-type layer, and to enable better p-contacts, the last 10-30 nm portion of this layer, closer to the LED surface, has a spike in the doping level.

[0256] To activate the Mg acceptors in the p-doped layer, the structure is annealed in a MOCVD reactor or an annealing oven. The annealing temperature ranges from 700 to 850 °C in an N2 or N2 / O2 atmosphere.

[0257] Since both the EBL and the p-doped layer are p-type doped, these layers are referred to as p-doped regions.

[0258] Figure 11 Removal of the first mask layer Next, the wafer is processed to remove the first mask layer 2 from the surface of the connection layer 1. This can be performed by wet etching using a buffered oxide etching chemical.

[0259] Figure 12 Second mask layer The next step is to deposit a combination of the second mask layer 8 or a passivation layer on the connection layer 1 and the layers 3 - 7 of the first LED structure. The second mask layer is formed from SiO2, SiN, SiON, aluminum, tantalum, or hafnium-containing oxides, or a combination of these layers. The second mask layer 8 is deposited by plasma-enhanced chemical vapor deposition, sputtering, or other suitable techniques (e.g., atomic layer deposition). The thickness of the second mask layer 8 varies between 20 and 2000 nm.

[0260] Figure 13 Openings in the passivation layer The next step is to generate a plurality of second exposed regions of the connection layer 1 by removing a portion of the second mask layer 8. This can be performed by standard photolithography techniques, wet etching, or dry etching. In wet etching, buffered oxide etching, diluted hydrofluoric acid, phosphoric acid, or a mixture of these can be used.

[0261] Figure 13 shows three second exposed regions formed in the second mask layer 8 to expose the surface of the connection layer 1.

[0262] The size of the second exposed region is 200 nm to 50000 nm, preferably 500 nm to 10000 nm, or 1000 nm to 8000 nm.

[0263] The distance between adjacent second exposure regions is preferably greater than the lateral width of the second exposure region, and preferably at least 1.5 times or at least 2 times the lateral width of the second exposure region. The distance between adjacent second exposure regions can be selected such that there is space between adjacent first exposure regions for growing further LED structures.

[0264] The distance between adjacent second exposure regions is 500 nm to 30000 nm, for example, 1000 nm to 10000 nm or 5000 nm to 8000 nm.

[0265] The shape of the exposed area can be circular, square, rectangular, hexagonal, triangular, etc. The width or diameter of the aperture is preferably less than 100 μm, so that the LED structure formed on the exposed area is classified as a micro-LED. The exposed area preferably has a width of 0.05 μm to 30 μm, and particularly preferably 10 μm or less.

[0266] Figure 14 Second n-type section After forming a second exposed region of the connecting layer 1, a second n-doped layer 9 of a group III nitride material is deposited in the second exposed region.

[0267] In the specific example shown, the second n-doped layer 9 is grown by MOCVD. This growth is carried out only within the second exposed region on the surface of the n-doped connecting layer 1. Si is used as the dopant for the n-doped layer 9, and the doping concentration is at least 1 × 10⁻⁶. 19 cm -3 Higher.

[0268] The second n-doped layer 9 includes a bulk group III nitride layer containing indium, or a stack of thin group III nitride layers that may or may not contain indium, or a stack of group III nitride bulk layers or group III nitride layers in which the atomic percentage of indium varies within the layer or stack. The atomic percentage of indium varies between 0.5 and 25%. The total thickness of the n-type layer 9 varies between 2 nm and 200 nm, for example between 50 nm and 100 nm. When a stack is used, the thickness of individual layers within the stack varies between 1 and 40 nm. The second n-doped layer 9 is 1 × 10⁻¹⁶ 17 cm -3 ~5×10 20 cm -3 It has a doping concentration of n.

[0269] Figure 15 Second light-emitting region After growing a second n-type layer 9 in the second exposed region, a second light-emitting region 10 is grown on top of each n-type layer 9.

[0270] The second light-emitting region 10 includes at least one light-emitting layer. Each light-emitting layer is a quantum well (QW), preferably an InGaN quantum well (QW). Preferably, the light-emitting region includes 1 to 7 quantum wells. Adjacent quantum wells are separated by a barrier layer of a group III nitride material having a different composition from the quantum wells.

[0271] One or more light-emitting layers, referred to as "quantum wells" throughout this document, can take various forms. For example, the light-emitting layer may be a continuous layer of InGaN, or a continuous, fragmented, or discontinuous layer, or it may contain gaps, or it may be nanostructured to substantially contain multiple 3D nanostructures in which the quantum well behaves as quantum dots.

[0272] Quantum wells and barriers are grown in a temperature range of 600-800°C.

[0273] Each quantum well consists of an InGaN layer having an atomic indium percentage of 20-40%, preferably more than 26%, and preferably more than 30%.

[0274] The thickness of each quantum well layer is 1.5 to 8 nm, preferably 1.5 nm to 6 nm, or 1.5 nm to 4 nm.

[0275] The quantum well may or may not be covered with a thin (0.5-3 nm) group III nitride QW capping layer. This capping layer contains one or more combinations of the elements Al, Ga, and In (quaternary layer, ternary layer).

[0276] The QW capping layer (if present), which is added immediately after QW growth, can be AlN, AlGaN with an Al% of 0.01 to 99.9%, GaN, or InGaN with an In% of 0.01 to 30%.

[0277] The group III nitride QW barrier that separates the luminescent layer (quantum well) contains one or more combinations of the elements Al, Ga, and In (quaternary layer, ternary layer).

[0278] Since one or more QW capping layers and QW barriers form part of the second light-emitting region 10, these layers are not shown with individual reference numbers in the drawings.

[0279] At the end of growth, the height of the luminescent region 4 is within ±200 nm of the height of the first mask layer 2.

[0280] The target PL emission wavelength of the second emission region 10 is 570 nm to 630 nm, preferably greater than 600 nm. Therefore, the second emission region 10 has a different emission wavelength than the first emission region 4.

[0281] Figure 16 Cap layer and EBL After the quantum well is grown, an undoped cap layer 11 and an electron block group III nitride layer 12 (EBL) are grown. These layers are similar to or identical to the cap layer 5 and EBL 6 described above.

[0282] Figure 17 Second p-doped layer A second p-doped layer 13 is grown above the electron block layer (EBL) 12. The second p-doped layer 13 is similar to or identical to the p-doped layer 7 described above.

[0283] The completed second LED structure, including layers 9 to 13, preferably has a PL emission wavelength of 570 to 630 nm and an EL emission wavelength of 600 to 665 nm.

[0284] Figure 18 Exposure of the first p-doped layer In the next step, we will begin the device processing. The first step is to remove the second mask layer 8 only from the p-doped layer 7 of the first LED structure.

[0285] The removal of the second mask layer can be carried out by a wet or dry etching method. In the case of wet etching, buffer oxide etching is used to remove the passivation layer.

[0286] Figure 19 Transparent conductive layer Next, the exposed first and second p-type layers 7 and 13 are covered with a transparent conductive layer 14 such as a transparent conductive oxide (e.g., ITO, ZnO on other compatible oxides) or a metal layer. This covering can be performed in a single step or in multiple steps. The metal completely or partially covers the pixels. The metals include Ti, Pt, Pd, Rh, Ni, Au, Ag, etc. The thickness of a complete metal stack is 200-2000 nm.

[0287] This structuring is performed using standard semiconductor processing methods, including resist coating, photolithography, and lift-off.

[0288] By combining this with dry or wet structuring, it becomes possible for the conductive metal layer to completely or partially cover the upper surface of the p-doped regions (regions 13 and 7).

[0289] Transparent conductive layers are well known in the art, and any suitable material and thickness can be used.

[0290] Figure 20 p-contact The next step in device manufacturing is to cover the transparent conductive layer 14 on the p-doped layers 7 and 13 with a metal layer that acts as an electrical p-contact 15. This covering can be done in a single step or in multiple steps. The metal completely or partially covers the pixel. In this example, a single step is used for simplicity of detail.

[0291] The metals include Ti, Pt, Pd, Rh, Ni, and Au. The thickness of a complete metal stack is 200-2000 nm.

[0292] Figure 21 Exposure of the connecting layer Using standard photolithography techniques, apertures are created in the second mask layer 8, exposing multiple regions of the connecting layer 1. The size of the apertures varies between 200 nm and 50,000 nm. The distance between apertures is between 500 nm and 30,000 nm. Apertures are created only in areas of the wafer not occupied by the first or second LED structure.

[0293] Using dry etching, the second mask layer 8 is etched using a fluorine-based gas.

[0294] Figure 22 The final step in device manufacturing is to cover the oxide openings with a metal layer that acts as an electrical n-contact 16 in contact with the n-doped connection layer 1. This covering can be performed in a single step or in multiple steps. The metal can completely or partially cover the pixels. In this example, a single step is used for simplicity of detail.

[0295] The metals include Ti, Pt, Pd, Rh, Ni, and Au. The thickness of a complete metal stack is 200-2000 nm.

[0296] The micro-LED arrays shown in Figures 2 to 22 are designed to have two sets of LEDs emitting light at two different emission wavelengths, namely 515–540 nm and 570–630 nm. The illustrated devices are configured to emit light from the p-side of the device (the upper side of the illustrated micro-LED array). The emission wavelengths of both the first and second emission regions can be adjusted to obtain LEDs with a desired color combination. It is also possible to add a third array of a third LED structure to the wafer to provide an array of LEDs emitting at three distinct wavelengths.

[0297] Red, Green, Blue (RGB) LED Figures 23 to 44 are schematic side cross-sectional views illustrating the steps for manufacturing a three-color red, green, and blue LED device according to a preferred embodiment of the present invention.

[0298] Figure 23 shows a semiconductor template suitable for use in the present invention. The template in Figure 23 is similar to that in Figure 3, but in the template in Figure 23, the porous layer is not continuously and uniformly porous across the entire width of the template on the substrate, but rather the porous region is limited to a specific lateral portion of the template. The porous region is provided for about one-third of the width of the substrate, and the remaining two-thirds of the lateral width of the substrate is covered by a non-porous region in the same plane as the porous region. The charge carrier concentration is about 1 × 10⁻⁶ 17 cm -3 Since only the larger n-doped regions become porous during electrochemical etching, the size and shape of the porous and non-porous regions in the group III nitride material can be controlled by controlling the charge carrier concentration in these regions during epitaxial growth.

[0299] The details of the numbered regions (or layers) of the devices shown in Figures 23 to 44 are consistent with those described above for Figures 1 to 22.

[0300] The manufacturing steps shown in Figures 23 to 44 are the same as those described above with respect to Figures 1 to 22.

[0301] Once the template in Figure 23 is prepared by electrochemical porosification of the porous region through a non-porous intermediate layer, an n-doped connection layer 1 is formed on both the porous and non-porous regions. Then, a first electrical insulation mask layer 2 is deposited on the connection layer 1.

[0302] Next, by removing a portion of the mask layer 2, a first exposed region is formed on the porous region, and a second exposed region is formed on the non-porous region.

[0303] Next, two identical LED structures are grown, consisting of layers 3 to 7 (as described above in relation to Figures 2 to 22). The first LED structure is grown on a first exposed region on the porous region, and the second LED structure is grown on a second exposed region on the non-porous region. The quantum well in the light-emitting region 4 is a group III nitride layer of InGaN with an atomic indium percentage of 18 to 30%, preferably more than 22% and less than 30%.

[0304] The electroluminescent emission wavelength of the target in region 4 is 515 nm to 540 nm, preferably 530 nm, under electrical bias. However, as described above, since the first LED structure is positioned on a porous region of the group III nitride material, the emission wavelength of the first LED structure is redshifted relative to the second identical LED structure. As a result, the emission region of the second LED structure emits light at a peak EL wavelength of approximately 515 nm to 540 nm, while the wavelength-shifted first LED structure emits light at a peak EL wavelength of approximately 580 nm to 650 nm.

[0305] Once the first and second LED structures (3-7) have grown, the first mask layer 2 is removed, and the second mask layer 8 is deposited on top of the first and second LED structures and the connecting layer 2. Then, by removing a portion of the second mask layer 8, a third exposed region of the connecting layer 1 is created on top of the non-porous region.

[0306] Next, a third LED structure, consisting of layers 9 to 13, is grown on the third exposed region (as described above). The quantum well in the light-emitting region 10 of the third LED structure preferably consists of a group III nitride layer containing indium with an atomic indium percentage of 10 to 30%, preferably more than 12%, preferably more than 15%, and particularly preferably less than 22%. The target emission wavelength of region 10 is 400 nm to 500 nm, preferably 430 to 470 nm, and preferably more than 450 nm, when an electrical bias is applied to the LED structure.

[0307] Once the third LED structure (9-13) is formed, standard device manufacturing steps are performed. These steps include exposing the p-doped layers 7 and 13 of all three LED structures, etching grooves into the connecting layer 1 between the LED structures, electrically insulating the LED structures from each other by depositing dielectric mask material 8 in the grooves, applying transparent conductive oxide 14 and metal p-contacts 15 to all three LED structures, then creating openings in the second mask layer 8 to expose the n-doped connecting layer 1, and forming metal n-contacts 16 for the connecting layer 1.

[0308] Next, as shown in Figure 43, the substrate is removed from the device. The upper side of the device is bonded to another carrier wafer / substrate / backplane 17 or to a microdriver circuit board to form an array of pixels. The lower side of the device is bonded to a cover glass or transparent material 18.

[0309] As shown in Figure 44, the substrate, as well as porous and non-porous regions, are removed from the device. The upper side of the device is bonded to another carrier wafer / substrate / backplane 17 or to a microdriver circuit board to form an array of pixels. The lower side of the device is bonded to a cover glass or transparent material 18.

[0310] As shown in the figure, the completed structure includes a first LED structure having emission wavelengths of 560-650 nm and 650-750 nm, preferably 600-650 nm. Therefore, the first LED structure is a red LED.

[0311] Furthermore, the completed structure includes a second LED structure having an emission wavelength of 500-560 nm, preferably 520-540 nm. Therefore, the second LED structure is a green LED.

[0312] Furthermore, the completed structure includes a third LED structure having an emission wavelength of 400-500 nm, preferably 430-470 nm. Therefore, the third LED structure is a blue LED.

[0313] By providing an integrated device in which all three LED structures are manufactured on the same substrate, a red, green, and blue LED device can be advantageously provided. In this case, the red, green, and blue LED structures form colored pixels for light emission, and in particular, the red, green, and blue pixels are formed in closer proximity than is possible with conventional manufacturing methods.

[0314] The emission wavelength of individual LED structures can be controlled by changing the composition and layer structure of the LED structure according to known principles of LED construction, as will be understood by those skilled in the art. Therefore, a variety of multicolor LED devices can be provided using the present invention, and naturally, it is also possible to provide color combinations other than red, green, and blue.

[0315] Redshift Figures 45 and 46 compare the luminescence characteristics of an InGaN LED on a non-porous substrate (Figure 45) with those of the same InGaN LED grown on a template containing a porous layer of Group III nitride material. Comparing these two graphs demonstrates that the porous underlayer causes a shift to longer emission wavelengths, indicating that the luminescence of the LED on the porous template is consistently 21 nm to 45 nm longer than that of the same LED on a non-porous template. Therefore, if the first LED structure is grown on a porous region and the second identical LED structure is grown on a non-porous region, the first LED structure will emit light at a longer wavelength than the second LED structure.

[0316] Alternative Embodiments Figures 47 and 48 show an alternative method for preparing a red-green-blue LED device according to a preferred embodiment of the present invention.

[0317] A template is provided in which three porous regions with different porosity levels are positioned in the same plane at three different lateral positions within a semiconductor material layer. An n-doped connecting layer (not shown) covers these three porous regions.

[0318] First, a mask is deposited on porous region 1, leaving the exposed areas of the connecting layer above porous regions 2 and 3 as they are. Next, a green LED structure is formed on the connecting layer above porous regions 2 and 3. Then, the green LED structure is divided into two by a conventional etching process, leaving a first LED structure positioned above porous region 3 and a second LED structure positioned above porous region 2.

[0319] Another mask layer is deposited to cover the first and second LED structures. Then, a portion of the mask layer is removed to expose the area of ​​the connecting layer above the porous region 1. Next, the blue LED structure is formed on the exposed area of ​​the connecting layer above the porous region 1.

[0320] Next, all three LED structures are processed using the same LED processing steps described above to generate the device structure.

[0321] In this embodiment, although the first and second LED structures themselves are identical, the difference in porosity between porous region 1 and porous region 2 generates different first and second emission wavelengths. In the illustrated embodiment, the porosity of porous region 1 causes a wavelength shift, so the first LED structure emits red light when an electrical bias is applied. In this way, green and red LEDs can be formed simultaneously using the same epitaxial growth step.

[0322] In various embodiments, instead of porous regions 1 and 2, a second and / or third LED structure may be formed on a non-porous region of the group III nitride material.

Claims

1. A method for manufacturing an LED device, The steps include forming an n-doped connecting layer of a group III nitride material on a first porous region of a group III nitride material, The steps include forming a first electrical insulation mask layer on the n-doped connection layer, The steps include removing a portion of the first electrical insulation mask layer to expose the first exposed region of the n-doped connection layer, The steps include forming a first LED structure configured to emit light at a first emission wavelength on the first exposed region of the n-doped connection layer, The steps include forming a second electrical insulating mask layer on the first LED structure and the n-doped connection layer, The steps include removing a portion of the second electrical insulation mask layer to expose the second exposed region of the n-doped connection layer, The process includes the step of forming a second LED structure on the second exposed region of the n-doped connection layer, which is configured to emit light at a second emission wavelength different from the first emission wavelength. The n-doped connecting layer of the group III nitride material is formed above a plurality of regions having different porosity, the plurality of regions are arranged to occupy different lateral positions on the same plane on the substrate, and the first porous region of the group III nitride material is one of the plurality of regions having different porosity. A method comprising positioning one of the first LED structure and the second LED structure on the first porous region, while the other is not positioned on the first porous region.

2. The method according to claim 1, The n-doped connecting layer of the group III nitride material is formed on a first porous region and a non-porous region of the group III nitride material, and the first porous region and the non-porous region are arranged in the same plane on the substrate. Alternatively, a method in which one of the first LED structure and the second LED structure is positioned on the first porous region and the other is positioned on the non-porous region.

3. The method according to claim 1, A method comprising forming the first LED structure on a first porous region having a first degree of porosity, and forming the second LED structure on a second porous region having a second degree of porosity.

4. The method according to claim 1, A method comprising the steps of forming the first porous region of a group III nitride material by electrochemical porosification through a non-porous layer of the group III nitride material, the non-porous layer of the group III nitride material forming a non-porous intermediate layer on the first porous region, and then forming the n-doped connecting layer.

5. The method according to claim 1, The first porous region of the group III nitride material comprises a stack of multiple porous layers of the group III nitride material. Alternatively, the stack of porous layers is a stack consisting of alternating layers of porous and non-porous layers.

6. The method according to claim 1, A method in which the first and / or second exposed regions of the n-doped connecting layer are circular, square, rectangular, hexagonal, or triangular in shape.

7. A method for manufacturing a three-color LED device, The steps include forming an n-doped connecting layer of group III nitride material on a first porous region of group III nitride material and on a non-porous region of group III nitride material, The steps include forming a first electrical insulation mask layer on the n-doped connection layer, The steps include removing a portion of the first electrical insulation mask layer to expose the first exposed region of the n-doped connection layer on the first porous region, The steps include removing a portion of the first electrical insulation mask layer to expose a second exposed region of the n-doped connection layer on the non-porous region, The steps include forming a first LED structure configured to emit light at a first emission wavelength on the first exposed region of the n-doped connection layer, The steps include forming a second LED structure configured to emit light at a second emission wavelength on the second exposed region of the n-doped connection layer, The steps include forming a second electrical insulating mask layer on the first LED structure, the second LED structure, and the n-doped connection layer, The steps include removing a portion of the second electrical insulation mask layer to expose the third exposed region of the n-doped connection layer, The step includes forming a third LED structure on the third exposed region of the n-doped connection layer, which is configured to emit light at a third emission wavelength different from the first emission wavelength and the second emission wavelength, A method comprising: the n-doped connecting layer of the group III nitride material being formed above a plurality of regions having different porosity, the plurality of regions being arranged to occupy different lateral positions on the same plane on the substrate, the first porous region of the group III nitride material being one of the plurality of regions having different porosity, and one of the first LED structure and the second LED structure being positioned above the first porous region and the other not being positioned above the first porous region.

8. The method according to claim 7, The second LED structure is identical to the first LED structure, and the first and second LED structures are formed simultaneously.

9. The method according to claim 7, The third exposed region of the n-doped connecting layer is formed above the non-porous region of the group III nitride material.

10. LED device, An n-doped connecting layer of a group III nitride material on a first porous region of a group III nitride material, An electrical insulating mask layer on the n-doped connection layer of a group III nitride material, A first LED structure configured to emit light at a first emission wavelength, The present invention comprises a second LED structure configured to emit light at a second emission wavelength different from the first emission wavelength, At least a portion of the first and second LED structures extends through the gap in the electrical insulation mask layer and contacts the n-doped connection layer. An LED device comprising an n-doped connecting layer of a group III nitride material formed above a plurality of regions having different porosity, the plurality of regions being arranged to occupy different lateral positions on the same plane on the substrate, the first porous region of the group III nitride material being one of the plurality of regions having different porosity, and one of the first LED structure and the second LED structure being positioned above the first porous region and the other not being positioned above the first porous region.

11. The LED device according to claim 10, The n-doped connecting layer of the group III nitride material extends over a first porous region and a non-porous region of the group III nitride material, and the porous region and the non-porous region are arranged in the same plane. An LED device in which one of the first LED structure and the second LED structure is positioned on the porous region and the other is positioned on the non-porous region.

12. An LED device according to claim 10 or 11, An LED device in which the first LED structure is positioned on the first porous region having a first porosity, and the second LED structure is positioned on the second porous region having a second porosity.

13. It is a three-color LED device, An n-doped connecting layer of a group III nitride material on a first porous region of a group III nitride material, and an electrical insulating mask layer on the n-doped connecting layer, A first LED structure configured to emit light at a first emission wavelength, A second LED structure configured to emit light at a second emission wavelength different from the first emission wavelength, The present invention comprises a third LED structure configured to emit light at a third emission wavelength different from the first and second emission wavelengths, At least a portion of the first, second, and third LED structures is in contact with the n-doped connection layer. A three-color LED device comprising a group III nitride material, wherein the n-doped connecting layer is formed above a plurality of regions having different porosity, the plurality of regions are arranged to occupy different lateral positions on the same plane on the substrate, and one of the first LED structure and the second LED structure is positioned above the first porous region, while the other is not positioned above the first porous region.

14. A three-color LED device according to claim 13, The three-color LED device is a red-green-blue (RGB) LED device, and the first, second, and third LED structures are configured to emit red light, green light, and blue light when an electrical bias is applied. The first, second, and third LED structures are as follows: The first LED structure emits light at a peak wavelength of 600-650 nm under electrical bias, The second LED structure emits light at a peak wavelength of 515 to 550 nm under electrical bias. A three-color LED device in which the third LED structure is configured to emit light at a peak wavelength of 400 to 500 nm under an electrical bias.

15. A three-color LED device according to claim 13, A three-color LED device in which the first LED structure is positioned on the first porous region of the group III nitride material, and the second LED structure is not positioned on the first porous region of the group III nitride material.

16. A three-color LED device according to claim 15, The second LED structure is identical to the first LED structure, and the first and second LED structures emit light at different emission wavelengths due to the first porous region located below the first LED structure, resulting in a three-color LED device.

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