Three-dimensional memory, method, and memory system

Abstract

The present disclosure provides a three-dimensional memory and a manufacturing method thereof, a memory system, and an electronic device. The three-dimensional memory includes a stacked structure, a plurality of first stops arranged in a first direction X, a protective layer, and a plurality of contact posts. The stacked structure includes a step structure including a plurality of stair structures arranged in the first direction and having different heights in a second direction. The plurality of first stops are arranged in a plurality of steps of at least one of the stair structures. The protective layer covers the step structure and the first stops, and at least a portion of the protective layer is arranged between the first stops and a step adjacent to the first stops. The contact posts extend through the protective layer and the first stops and are connected to the gate layer at the steps corresponding to the first stops.

Description

Technical Field

[0001] [Cross - reference to Related Applications] This disclosure is filed based on Chinese Patent Application No. 202210273522.3 filed on March 18, 2022 and Chinese Patent Application No. 202210273515.3 filed on March 18, 2022, claims the priority of these two Chinese patent applications, and the entire contents of which are incorporated herein by reference.

[0002] This disclosure relates to the field of semiconductor chip technology, and particularly to three - dimensional memory and its manufacturing method, memory systems, and electronic devices.

Background Art

[0003] As the feature size of memory cells approaches the lower limit of the process, planar processes and manufacturing technologies become difficult and expensive, and as a result, the memory density of 2D or planar NAND flash approaches its upper limit. To overcome the limitations brought by 2D or planar NAND flash, memories with three - dimensional structures (3D NAND) have been developed in the industry, which improve the memory density by arranging memory cells three - dimensionally on a substrate.

[0004] In the actual manufacturing process of three - dimensional memory, in order to implement the electrical connection between the contacts and the gate layer in the stacked structure, contact holes that expose each gate layer in the staircase region need to be formed in the dielectric layer covering the stacked structure, and then a conductive material is filled into the contact holes to form contacts.

[0005] However, the higher the integration degree of three - dimensional memory and the larger the number of stacked layers, the deeper the depth of the contact holes, and in the process of forming the contact holes, the upper gate layer will be etched. In this case, after filling the conductive material for forming contacts in the contact holes, a short - circuit between different gate layers (that is, an electrical connection between word lines of different layers) may occur, which may lead to memory failure. [Overview of the project]

[0006] Examples of this disclosure include three-dimensional memory and methods for manufacturing the same, memory systems, and electronic devices.

[0007] The examples in this disclosure employ the following technical solutions:

[0008] In one embodiment, a three-dimensional memory is provided. The three-dimensional memory includes a stacked structure, a plurality of first stops arranged in a first direction, a protective layer, and a plurality of contact posts. The stacked structure includes alternately arranged gate layers and dielectric layers. The stacked structure includes a stepped structure, which includes a plurality of stepped structures arranged in a first direction and having different heights in a second direction. The stepped structure includes a plurality of steps. The first direction and the second direction are perpendicular to each other. The plurality of first stops arranged in the first direction are arranged in a plurality of steps of at least one stepped structure, and each of the first stops is arranged in one of the steps. The protective layer covers the stepped structure and the first stops, and at least a portion of the protective layer is arranged between the first stops and the steps adjacent to the first stops. The contact posts extend through the protective layer and the first stops and are connected to the gate layer in the steps corresponding to the first stops.

[0009] In some examples, the three-dimensional memory further includes a separation structure that extends through the stacked structure in a first direction. The separation structure divides the stacked structure into multiple memory blocks, each memory block containing a stepped structure. The stepped structure on which the first stop section is located is spaced apart from the separation structure.

[0010] In some examples, in the second direction, the memory block comprises a first staircase structure, a second staircase structure, and a third staircase structure, and the first stopper is arranged on multiple steps of the second staircase structure.

[0011] In some examples, in the second direction, the memory block comprises a first-stage structure and a second-stage structure, the first-stage structure being spaced apart from the isolation structure, and the first stop section being located on multiple stages of the first-stage structure.

[0012] In some examples, each memory block further includes a side wall 16. The isolation structure includes a first isolation structure and a second isolation structure, wherein in the second direction, the first isolation structure is positioned between two adjacent side walls, the second isolation structure is positioned between two adjacent tier structures, and in the second direction, the tier structures in two memory blocks adjacent to the second isolation structure are positioned symmetrically.

[0013] In some examples, in the second direction, along the direction from the first separation structure to the second separation structure, the height of multiple stair structures within the memory block gradually decreases.

[0014] In some examples, in the second direction, the two staircase structures adjacent to each other on either side of the second separation structure have the same height.

[0015] In some examples, the three-dimensional memory further includes a plurality of second stops arranged in a first direction. The plurality of second stops arranged in the first direction are positioned on multiple steps of a stair structure other than the stair structure on which the first stop is located. A protective layer further covers the second stops, and at least a portion of the protective layer is positioned between the second stops and the steps adjacent to the second stops.

[0016] In some examples, the three-dimensional memory further includes a plurality of gate line isolation structures extending in a first direction. These gate line isolation structures are positioned between two adjacent isolation structures, and the gate line isolation structures extend through a second stop and a stacked structure. Each gate line isolation structure includes a plurality of sub-isolation structures separated from each other along the first direction. The material of the second stop is the same as the material of the gate layer.

[0017] In some cases, the material of the second stop is the same as the material of the first stop.

[0018] In some examples, the material of the first stop section contains silicon nitride.

[0019] In some examples, in the third direction, the thickness of the first stop is the same as the thickness of the gate layer of the preceding stage. The preceding stage is adjacent to the stage corresponding to the first stop, is higher than the stage corresponding to the first stop, and the third direction is perpendicular to the laminated structure.

[0020] In another embodiment, a method for manufacturing a three-dimensional memory is provided, and this method is The method involves forming an initial laminated structure, wherein the initial laminated structure includes alternately arranged sacrificial layers and dielectric layers, and the initial laminated structure includes a stepped structure comprising a plurality of stepped structures arranged in a first direction and having different heights in a second direction, the stepped structure comprising a plurality of steps, and the first and second directions being perpendicular to each other. The invention involves forming multiple first stopping sections on at least one set of steps of a staircase structure, wherein the multiple first stopping sections are arranged in a first direction, and each of the first stopping sections is positioned on one of the steps. The method involves forming a protective layer, the protective layer covering the stepped structure and the first stop, and at least a portion of the protective layer being positioned between the first stop and the step adjacent to the first stop. Replacing the sacrificial layer with a gate layer to form a laminated structure, A method comprising forming a plurality of contact posts that extend through a protective layer and a first stop and are electrically connected to the gate layer at a stage corresponding to the first stop.

[0021] In some examples, forming a plurality of first stops on a plurality of steps of the at least one staircase structure involves etching the topmost sacrificial layer and dielectric layer of each step to form the plurality of first stops.

[0022] In some examples, the manufacturing method further includes forming a first slit extending through the initial stacked structure in a first direction. The first slit divides the initial stacked structure into a plurality of initial memory blocks, each containing a stepped structure. Separation structures are formed in the first slit.

[0023] In some examples, the manufacturing method further includes forming a second separation sub - portion extending through the initial stacked structure in a first direction, and forming a first sub - slit, a second sub - slit, and a second slit extending in the first direction through the initial stacked structure. The first sub - slit and the second sub - slit respectively contact both ends in the first direction of the second separation sub - portion, and the second slit is disposed between two adjacent second separation sub - portions in a second direction. A first separation sub - portion is formed in the first sub - slit, a third separation sub - portion is formed in the second sub - slit, and a second separation structure is formed in the second slit. The first separation sub - portion, the third separation sub - portion, and the second separation sub - portion constitute at least a part of the first separation structure.

[0024] In some examples, the manufacturing method further includes forming a plurality of second stop portions on a plurality of steps of other stepped structures other than the stepped structure where the first stop portion is disposed. Each second stop portion is disposed on one step.

[0025] In some examples, the manufacturing method further includes forming a plurality of third slits extending in a first direction. The third slits extend through the second stop portions and the initial stacked structure, and each of the third slits includes a plurality of third sub - slits spaced apart from each other in the first direction. A gate line separation structure is formed in the third slits.

[0026] In some examples, forming the plurality of contact posts includes etching a protective layer to the first stop portion to form a plurality of contact holes, etching the first stop portion exposed by the contact holes, etching a dielectric layer under the first stop portion so that the contact holes expose a gate layer, and forming contact posts in the contact holes.

[0027] In still other aspects, a memory system is provided. The memory system includes a controller and a 3 - D memory of any of the above examples. The controller is coupled to the 3 - D memory and is configured to control the 3 - D memory to store data.

[0028] In still another aspect, an electronic device is provided. The electronic device includes the memory system described in any of the above examples.

Brief Description of the Drawings

[0029] To more clearly illustrate the technical solutions in the present disclosure, the drawings required in some examples of the present disclosure are briefly introduced. Obviously, the drawings in the following description are only for some examples of the present disclosure, and those skilled in the art can obtain other drawings from these drawings. Furthermore, the drawings described below can be regarded as exemplary drawings and do not limit the actual size of the products included in the examples of the present disclosure, the actual flow of the methods, and the actual timing of the signals. [Figure 1] It is a perspective structure diagram of a 3D memory according to some examples. [Figure 2] It is a structure diagram of a contact post and a step in the prior art. [Figure 3] It is another structure diagram of a contact post and a step in the prior art. [Figure 4] It is a structure diagram of a contact post according to some examples. [Figure 5A] It is a top view of a 3D memory according to some examples. [Figure 5B] It is a top view of a 3D memory according to some examples. [Figure 6] It is an enlarged view of the CC region in FIG. 5A. [Figure 7A] It is a cross-sectional view taken along the cutting line D-D' in FIG. 6. [Figure 7B] It is another cross-sectional view taken along the cutting line D-D' in FIG. 6. [Figure 8] It is a cross-sectional view taken along the cutting line E-E' in FIG. 6. [Figure 9] It is another cross-sectional view taken along the cutting line E-E' in FIG. 6. [Figure 10] It is another enlarged view of the CC region in FIG. 5A. [Figure 11] It is a cross-sectional view taken along the cutting line F-F' in FIG. 10. [Figure 12A] This is a structural diagram of a stepped structure, based on some examples. [Figure 12B] This is a structural diagram of another tiered structure, based on some examples. [Figure 13] This is another enlarged view of the CC region in Figure 5A. [Figure 14] This is another enlarged view of the CC region in Figure 5A. [Figure 15] This is a cross-sectional view along the cutting line G-G' in Figure 14. [Figure 16] This is a structure diagram of a memory string, based on some examples. [Figure 17] Figure 16 is an equivalent circuit diagram of the memory string. [Figure 18] This is another enlarged view of the CC region in Figure 5A. [Figure 19A] This is a cross-sectional view along the cutting line H-H' in Figure 18. [Figure 19B] This is another cross-sectional view along the cutting line H-H' in Figure 18. [Figure 20] This is a cross-sectional view along the cutting line I-I' in Figure 18. [Figure 21] This is another cross-sectional view along the cutting line II in Figure 18. [Figure 22] This is another enlarged view of the CC region in Figure 5A. [Figure 23] This is a cross-sectional view along the cutting line J-J' in Figure 22. [Figure 24A] This is a structural diagram of yet another layered structure, based on some examples. [Figure 24B] This is a structural diagram of yet another layered structure, based on some examples. [Figure 25] This is another enlarged view of the CC region in Figure 5A. [Figure 26] This is another enlarged view of the CC region in Figure 5A. [Figure 27] This is a cross-sectional view along the cutting line K-K' in Figure 26. [Figure 28] This is a flowchart of a manufacturing method for 3D memory, based on some implementation examples. [Figure 29A]This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 29B] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 30] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 31] This is a flowchart of a manufacturing method for 3D memory, based on some implementation examples. [Figure 32] This is a flowchart of a manufacturing method for 3D memory, based on some implementation examples. [Figure 33A] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 33B] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 34] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 35A] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 35B] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 36] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 37] This is a flowchart of a manufacturing method for 3D memory, based on some implementation examples. [Figure 38] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 39] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 40] This is a flowchart of a manufacturing method for 3D memory, based on some implementation examples. [Figure 41A] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 41B] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 42] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 43] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 44]This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 45] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 46] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 47] This is a flowchart of a manufacturing method for 3D memory, based on some implementation examples. [Figure 48] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 49] This is a flowchart of a manufacturing method for 3D memory, based on some implementation examples. [Figure 50] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 51] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 52] This is a flowchart of a manufacturing method for 3D memory, based on some implementation examples. [Figure 53] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 54] This is a flowchart of a manufacturing method for 3D memory, based on some implementation examples. [Figure 55] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 56] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 57] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 58] This is a diagram illustrating a manufacturing method for a three-dimensional memory, based on some examples. [Figure 59] This is a flowchart of other 3D memory manufacturing methods, using some examples. [Figure 60] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 61] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 62] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 63] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 64] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 65] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 66] This is a flowchart of other 3D memory manufacturing methods, using some examples. [Figure 67] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 68] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 69] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 70] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 71] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 72] This is a flowchart of other 3D memory manufacturing methods, using some examples. [Figure 73] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 74] This is a flowchart of other 3D memory manufacturing methods, using some examples. [Figure 75] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 76] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 77] This is a flowchart of other 3D memory manufacturing methods, using some examples. [Figure 78] This is a flowchart of other 3D memory manufacturing methods, using some examples. [Figure 79] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 80] This is a flowchart of other 3D memory manufacturing methods, using some examples. [Figure 81]This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 82] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 83] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 84] This is a diagram illustrating some examples of other methods for manufacturing three-dimensional memory. [Figure 85] This is a diagram of the structure of other 3D memory, using some examples. [Figure 86] Here are some other 3D memory structure diagrams, based on some examples. [Figure 87] This is a structural diagram of a memory system, based on some examples. [Figure 88] This is a structural diagram of another memory system, using some examples. [Modes for carrying out the invention]

[0030] Technical solutions in some examples of this disclosure are described below clearly and completely, together with the accompanying drawings. However, it is clear that the examples described are only a selection of the examples of this disclosure, and not all of them. All other examples that can be obtained by those skilled in the art based on the examples provided in this disclosure are included within the scope of this disclosure.

[0031] In the description of this disclosure, terms such as “center,” “top,” “bottom,” “front,” “back,” “left,” “right,” “vertical,” “horizontal,” “top,” “bottom,” “inside,” and “outside” are used solely for the purpose of facilitating and simplifying the description of this disclosure and do not indicate or imply that the devices or elements mentioned must have a particular orientation, but rather refer to orientations or positional relationships based on those shown in the figures, which must be configured and operated in a particular orientation and therefore cannot be considered limiting to this disclosure.

[0032] Unless otherwise specified in the context, the term “include” throughout this specification and the claims shall be interpreted in an open and inclusive sense, i.e., “includes, but not limited to.” In this description, the terms “example,” “partial example,” “exemplary implementation,” “as an example,” or “partial example” are intended to mean that certain features, structures, materials, or properties relating to an example or implementation are included in at least one example or implementation of this disclosure. The exemplary expressions of the above terms do not necessarily refer to the same example or implementation. Furthermore, certain features, structures, materials, or properties may be included in any one or more examples or implementations in any suitable manner.

[0033] In the following, terms such as “first,” “second,” etc., are used solely for descriptive purposes and are not intended to be interpreted as indicating or implying relative importance or implicitly indicating the number of technical features shown. Therefore, a feature defined by “first” or “second” may explicitly or implicitly include one or more instances of the feature. In the descriptions of the examples in this disclosure, “multiple” means two or more unless otherwise specified.

[0034] When describing certain examples, expressions such as “to couple” and “to connect” and their extensions may be used. For example, the term “to connect” may be used when describing certain examples to indicate that two or more components have direct physical or electrical contact. As another example, the term “to couple” may be used when describing certain examples to indicate that two or more components have direct physical or electrical contact. However, the term “to couple” may also indicate that there is no direct contact between two or more components, but they still cooperate or interact with each other. The examples disclosed herein are not necessarily limited to those provided herein.

[0035] "At least one of A, B, and C" and "at least one of A, B, or C" have the same meaning and both include the following combinations of A, B, and C: A only; B only; C only; a combination of A and B; a combination of A and C; a combination of B and C; and a combination of A, B, and C.

[0036] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0037] As used herein, “about,” “generally,” or “approximately” include stated values ​​and mean values ​​within a permissible deviation range for a particular value, the permissible deviation range being determined by a person skilled in the art, taking into account the measurement values ​​under discussion and the errors associated with the measurement of a particular quantity, i.e., the limitations of the measurement system.

[0038] In this disclosure, the meanings of “on,” “over,” and “above” should be interpreted most broadly, with “on” meaning not only “directly on” something, but also “on” something with an intermediate feature or layer in between, and “over” or “above” meaning not only “over” or “above” something, but also “over” or “above” something without an intermediate feature or layer in between (for example, directly on top of something).

[0039] Exemplary configurations are described herein with reference to cross-sectional and / or plan views as ideal illustrative drawings. In the drawings, the thickness of layers and areas is exaggerated for illustrative purposes. Therefore, variations in shape from the drawings can be assumed, for example, due to manufacturing techniques and / or tolerances. Accordingly, the exemplary configurations should not be interpreted as limiting the shapes of the areas shown herein, and include, for example, shape deviations caused by manufacturing. For example, an etched area shown as a rectangle may have curved characteristics. Therefore, the areas shown in the drawings are essentially illustrative, and their shapes are not intended to represent the actual shapes of areas in the device, nor are they intended to limit the scope of the exemplary configurations.

[0040] Referring to Figures 1-3, Figure 1 is a perspective view of the structure of the 3D memory 100, and Figures 2 and 3 are two structural diagrams of a contact post section and a step in the prior art.

[0041] In some examples, as shown in Figure 1, the three-dimensional memory 100 includes a stacked structure having a stepped structure and comprising a plurality of alternately arranged gate layers G and dielectric layers (not shown in Figure 1). Both the gate layers G and dielectric layers extend in a first direction X. In a third direction Z, at least one gate layer G at the bottom of the plurality of gate layers G is configured as a source-end selected gate SGS, at least one gate layer G at the top of the plurality of gate layers G is configured as a drain-end selected gate SGD, and the gate layers G between the source-end selected gate SGS and the drain-end selected gate SGD are configured as a plurality of word lines WL.

[0042] To supply electrical signals to the source end selection gate SGS, the drain end selection gate SGD, and the word line WL, the 3D memory 100 further includes a plurality of contact post CNTs. Of the plurality of contact post CNTs, the contact post CNT electrically connected to the drain end selection gate SGD is configured as a drain end selection gate contact post SGDCNT, the contact post CNT electrically connected to the source end selection gate SGS is configured as a source end selection gate contact post SGSCNT, and the contact post CNT electrically connected to the word line WL is configured as a word line contact post WLCNT.

[0043] Referring to Figure 2, as the integration density increases, the number of stacked gate layers G and dielectric layers in the 3D memory gradually increases, and the difference in depth in the third direction Z between different contact post CNTs becomes increasingly large. Therefore, in the process of forming multiple contact post CNTs, the upper layers are more easily penetrated by the contact holes where the contact post CNTs are placed, which can cause short circuits between different gate layers G after the formation of multiple contact post CNTs, leading to failure of the 3D memory.

[0044] In light of this problem, referring to Figure 3, in the conventional technology, the problem of the gate layer G easily penetrating during the manufacturing of contact post CNTs can be improved by increasing the thickness of the gate layer G in the step. However, in order to prevent the contact hole from penetrating the gate layer G of the step, the thickness of the gate layer G of the step must be increased, which is difficult to form.

[0045] Therefore, in the conventional technique, the thickness of the gate layer G in that stage is made as thick as possible, while the etching rate is reduced to prevent the contact holes from penetrating the gate layer G in that stage. However, as shown in Figure 4, the etching rate is slow and the etching directionality is poor, resulting in poor linearity of the contact holes obtained by etching, and also poor linearity of the contact post CNTs. In particular, in the process of etching the contact holes, the poor etching directionality increases the likelihood of etching the dummy channel structure adjacent to the contact hole. As a result, conductive material is filled into the dummy channel structure after the contact post is formed, causing multiple gate layers to short-circuit, resulting in a poor-performing 3D memory.

[0046] Furthermore, if the gate layer G in a stage is thick, conductive material may remain in the gate line slit during the gate layer replacement process using the gate line slit. This can cause multiple gate layers to short-circuit, potentially leading to failure of the 3D memory after gate layer replacement.

[0047] To address at least one of the above-mentioned problems, referring to Figures 5A to 8, some examples of the present disclosure provide a three-dimensional memory 200.

[0048] As shown in Figures 5A and 5B, the three-dimensional memory 200 includes a core array region AA and a tiered region SS in a first direction X. As shown in Figure 5A, the three-dimensional memory 200 may include two core array regions AA and one tiered region SS positioned between the two core array regions AA. Alternatively, as shown in Figure 5B, the three-dimensional memory 200 may include two tiered regions SS and one core array region AA positioned between the two tiered regions SS.

[0049] The methods for distributing the core array region AA and the layer region SS within the three-dimensional memory 200 provided in some examples of this disclosure are not limited thereto.

[0050] Figure 6 is an enlarged view of the CC region in Figure 5A. Figures 7A and 7B are cross-sectional views along the cutting line D-D' in Figure 6, and Figure 8 is a cross-sectional view along the cutting line E-E' in Figure 6.

[0051] Referring to Figures 6 to 8, the three-dimensional memory 200 includes a stacked structure 10, a plurality of first stop sections 20 arranged in a first direction X, a protective layer 30, and a plurality of contact posts 40.

[0052] In some examples, as shown in Figure 7B, the gate layer 11 may be a multilayer composite structure. In this case, the gate layer 11 may have a high dielectric constant layer 112, a metal compound layer 113, and a conductive layer 111 formed in that order. Examples of materials for the high dielectric constant layer 112 include aluminum oxide (Al2O3) and metal compound layer Examples of material 113 include tantalum nitride or titanium nitride.

[0053] In some examples, referring to Figure 7A, the gate layer 11 may be a single-layer structure. The gate layer 11 includes a conductive layer 111. The material of the conductive layer 111 includes, but is not limited to, tungsten, cobalt, copper, aluminum, or doped crystalline silicon, doped silicon and / or silicide.

[0054] In some examples, as shown in Figure 7B, the gate layer 11 may be a multilayer composite structure. In this case, the gate layer 11 may have a high dielectric constant layer 112, a metal compound layer 113, and a conductive layer 111 formed in that order. Examples of materials for the high dielectric constant layer 112 include aluminum oxide (Al2O3), and examples of materials for the metal compound 113 include tantalum nitride or titanium nitride.

[0055] For example, the dielectric layer 12 can be made of an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0056] It should be noted that in the stacked structure 10, the thicknesses of the multiple gate layers 11 may be approximately the same or different. The thicknesses of the multiple dielectric layers 12 may also be approximately the same or different. The thicknesses of the multiple gate layers 11 and the multiple dielectric layers 12 can be selected according to actual demand. Furthermore, the number of stacks in the stacked structure 10 determines the number of memory cells. The more stacks in the stacked structure 10, the higher the integration density, i.e., the greater the number of memory cells. For example, the number of stacks and the height of the stacked structure 10 can be designed based on actual storage demand, and this is not limited to the present disclosure.

[0057] The laminated structure 10 includes a step structure 13 which includes multiple step structures 14 that are arranged in a first direction X and have different heights in a second direction Y. The step structure 14 includes multiple steps 141. The first direction X is perpendicular to the second direction Y.

[0058] If the step structure 13 is arranged in a first direction X and includes stair structures 14 having different heights in a second direction Y, it is understood that two adjacent stair structures 14 among the multiple stair structures 14 included in the step structure 13 may have different heights, but two stair structures 14 that are spaced apart may have the same height.

[0059] In some examples, referring to Figures 6 and 8, the stair structure 13 may include three stair structures 14 arranged in a second direction Y and having different heights from one another.

[0060] In some other examples, referring to Figures 6 and 9, the stair structure 13 may include three stair structures 14 arranged in a second direction Y, where the two stair structures 14 on either side have different heights than the central stair structure 14, but are the same height as each other.

[0061] Furthermore, in some examples, referring to Figures 10 and 11, the step structure 13 may include two stair structures 14 located in a second direction Y and having different heights from each other.

[0062] Please note that the number of staircase structures 14 in this disclosure is not limited to those described herein.

[0063] Multiple first stop units 20 are arranged in a first direction X and are positioned on multiple steps 141 of at least one staircase structure 14, with each first stop unit 20 positioned on one step 141.

[0064] As shown in Figures 8, 9, and 11, the multiple first stop units may be placed on only a number of steps 141 of one staircase structure 14. It is also possible for multiple first stop units 20 to be placed on multiple steps 141 of multiple staircase structures 14.

[0065] As shown in Figure 8, the stage 141 may include one gate layer 11 and one dielectric layer 12. Alternatively, the stage 141 may include multiple gate layers 11 and multiple dielectric layers 12. This is not limited to the present disclosure.

[0066] As shown in Figure 8, the protective layer 30 covers the stepped structure 13 and the first stop section 20, and at least a portion of the protective layer 30 is positioned between the first stop section 20 and the step 141 adjacent to the first stop section 20.

[0067] It is understood that the "stage 141 adjacent to the first stop section 20" may include not only the stage 141 adjacent to the first stop section 20 in the first direction X, as shown in Figure 7A, but also the stage 141 adjacent to the first stop section 20 in the second direction Y, as shown in Figure 8.

[0068] For example, the protective layer 30 can be made of silicon oxide, including but not limited to tetraethoxysilane (TEOS), siloxane, and silsesquioxane. For example, the protective layer 30 can be formed by chemical vapor deposition (CVD), spin coating, or the like.

[0069] At least a portion of the protective layer 30 is present between the first stop section 20 and the step 141 adjacent to the first stop section 20. Therefore, in the process of forming the gate layer 11, it is possible to separate the sacrificial layer and the first stop section 20 with the protective layer 30, thereby preventing the first stop section from being replaced at the same time as the sacrificial layer is replaced by the gate layer. Otherwise, the contact posts would be electrically connected to multiple gate layers through the replaced first stop section, thereby causing a failure in the 3D memory.

[0070] The contact posts among the multiple contact posts 40 extend through the protective layer 30 and the first stop section 20, and are connected to the gate layer 11 at the stage corresponding to the first stop section 20.

[0071] For example, the contact post 40 can be made of conductive materials including, but not limited to, metals such as tungsten, copper, and aluminum, metal silicides, metal nitrides, and / or doped polysilicon.

[0072] It is understood that the stepped structure 13 described above is located within a stepped region SS. If the stepped region SS is located between two core array regions AA, the topography of the stepped structure 13 may be as shown in Figures 12A and 12B. That is, the stepped structure 13 may include at least one group of steps in which the height of a plurality of steps 141 gradually increases or decreases in the first direction X.

[0073] Exemplary, as shown in Figures 12A and 12B, the stepped structure 13 may include eight stepped groups in a first direction X: the first stepped group 131, the second stepped group 132, the third stepped group 133, the fourth stepped group 134, the fifth stepped group 135, the sixth stepped group 136, the seventh stepped group 137, and the eighth stepped group 138. In the first direction X, the heights of the multiple steps 141 in the first stepped group 131, the third stepped group 133, the fifth stepped group 135, and the seventh stepped group 137 gradually decrease. In the first direction X, the heights of the multiple steps 141 in the second stepped group 132, the fourth stepped group 134, the sixth stepped group 136, and the eighth stepped group 138 gradually increase. Of course, the form of the stepped structure 13 in this disclosure is not limited thereto.

[0074] In the three-dimensional memory 200 provided in some examples of this disclosure, a plurality of first stop portions 20 are arranged on at least one staircase structure 14 within a step structure 13. Therefore, when forming the contact holes 41 in which the contact posts 40 are placed, an etching process such as wet etching can be used to remove a portion of the protective layer on the first stop portion 20, exposing a portion of the first stop portion 20. Then, the etching process can be used to remove the exposed portion of the first stop portion 20 and the dielectric layer 12 between the first stop portion 20 and the gate layer 11 below it, exposing a portion of the gate layer 11.

[0075] In the first etching step, due to the presence of the first stop 20, contact holes 41 having different depths corresponding to steps 141 having different heights may be stopped at each of the first stop 20s on the steps 141. In the second etching step, since the distance between each of the first stop 20s and the gate layer 11 of the step 141 where the first stop 20s are located is approximately the same, in the second etching step, while etching is performed simultaneously, contact holes 41 having different depths corresponding to steps 141 having different heights may be stopped at each of the gate layers 11 on the steps 141.

[0076] Therefore, while forming the contact post 40 within the contact hole 41, the contact post 40 can contact the gate layer 11 of the corresponding stage 141, facilitating the avoidance of short circuits between multiple gate layers by contact posts extending through the gate layers due to the increasing number of layers in the stacked structure, thereby improving the electrical performance and yield of the 3D memory.

[0077] At the same time, because the first stopping section 20 is provided, the etching process can be fast while forming contact holes where contact posts are placed, thereby improving the linearity of the contact holes 41 (or contact posts 40), and subsequently making it more difficult to etch the dielectric layer in the dummy channel structure adjacent to the contact posts 40, thereby improving the yield of the 3D memory 200.

[0078] Referring to Figures 6 to 12B, in some examples, the three-dimensional memory 200 further includes a separation structure 50. The separation structure 50 extends through the stacked structure 10 in a first direction X. The separation structure 50 divides the stacked structure 10 into a plurality of memory blocks 15. Each memory block 15 includes a stepped structure 13. The stepped structure 14 on which the first stop 20 is located is spaced apart from the separation structure 50.

[0079] The statement "The staircase structure 14 on which the first stopping section 20 is located is positioned at a distance from the separation structure 50" means that multiple first stopping sections 20 are positioned at a distance from the separation structure 50.

[0080] In some examples of this disclosure, the stacked structure 10 is divided into a plurality of memory blocks 15 having isolation structures 50, which can further improve the memory density of the three-dimensional memory 200. On the other hand, the stepped structure 14 on which the first stop 20 is located is spaced apart from the isolation structure 50, which also prevents the first stop 20 from being replaced in a subsequent step of forming a gate layer 11 by performing gate replacement using the slits on which the isolation structure 50 is located, thereby preventing contact posts from penetrating the replaced first stop and being electrically connected to the plurality of gate layers, which could lead to a failure of the three-dimensional memory.

[0081] When the separation structure 50 divides the stacked structure 10 into multiple memory blocks 15, it should be noted that the separation structure 50 also divides the gate layer 11 into multiple gate lines, such as source-end selection gates, drain-end selection gates, or word lines. Each memory block 15 includes multiple gate lines spaced apart in the third direction Z.

[0082] For example, the first direction X may be the direction in which the gate lines extend. The second direction Y may be the direction in which the bit lines extend. The third direction Z may be the stacking direction of the stacked structure 10.

[0083] In some examples, referring to Figures 6, 8, and 9, in the second direction Y, the memory block 15 includes a first staircase structure 14A, a second staircase structure 14B, and a third staircase structure 14C, and the first stop section 20 is located on multiple steps 141 of the second staircase structure 14B.

[0084] Therefore, the second step structure 14B has a height difference in the third direction Z from both the first step structure 14A and the third step structure 14C, and is positioned at a distance from the separation structure 50 (i.e., the first step structure 14A and the third step structure 14C are between the second step structure 14B and the separation structure 50), which facilitates etching of subsequent steps and formation of the first stop section 20, and thus prevents replacement of the first stop section, so that there is a gap between the first stop section 20 and the adjacent step 141.

[0085] In some other examples, referring to Figure 11, in the second direction Y, the memory block 15 includes a first staircase structure 14A and a second staircase structure 14B, the first staircase structure 14A being spaced apart from the separation structure 50, and the first stop section 20 being positioned on multiple steps 141 of the first staircase structure 14A.

[0086] Therefore, the first step structure 14A has a height difference with respect to the second step structure 14B in the third direction Z and is positioned at a distance from the separation structure 50, which facilitates etching of subsequent steps and formation of the first stop section 20, and a gap exists between the first stop section 20 and the side surface of the adjacent step 141, thus preventing the first stop section 20 from being replaced.

[0087] In some examples, referring to Figures 6 to 11, each memory block 15 further includes a side wall 16 that functions as a bridge structure for connecting two core array regions AA. In some examples, a gate layer included in the step structure is connected by the bridge structure to at least one gate layer of the two core array regions AA. The isolation structure 50 includes a first isolation structure 51 and a second isolation structure 52. In the second direction Y, the first isolation structure 51 is positioned between two adjacent side walls 16, and the second isolation structure 52 is positioned between two adjacent step structures 13. The side walls 16 are configured to enhance the structural stability of the three-dimensional memory 200.

[0088] In some examples, as shown in Figures 6 and 10, the first separation structure 51 may be an integral structure. That is, when manufacturing the first separation structure 51, a slit in which the first separation structure 51 is placed can be obtained by etching in a single etching step, and the first separation structure 51 can be formed within that slit.

[0089] In some other examples, as shown in Figure 13, the first separation structure 51 may include a first separation sub-part 511, a second separation sub-part 512, and a third separation sub-part 513 connected sequentially in a first direction X. The size of the second separation sub-part 512 in the second direction Y is greater than that of the first separation sub-part 511 and greater than that of the third separation sub-part 513.

[0090] For example, the first separation sub-part 511 has approximately the same size in the second direction Y as the third separation sub-part 513.

[0091] Exemplary, the first separation sub-part 511 and the third separation sub-part 513 are located within the core array region AA, and the second separation sub-part 512 is located within the stepped region SS and is in contact with the side wall 16.

[0092] For example, the second separation sub-part 512 may be manufactured simultaneously with the dummy channel structure and the channel structure. The first separation sub-part 511 and the third separation sub-part 513 may be manufactured after the manufacturing of the channel structure is completed. Accordingly, the material of the second separation sub-part 512 may be the same as the material of the dummy channel structure or the channel structure.

[0093] In some examples of this disclosure, by providing a second separation sub-part 512, it is possible to separate two adjacent memory blocks 15 on the one hand, and to support the stacked structure 10 and prevent the stacked structure 10 from collapsing on the other hand.

[0094] In some examples, referring to Figures 6, 10, and 13, in the second direction Y, the stepped structures 13 within the two memory blocks 15 adjacent to the second separation structure 52 are arranged symmetrically.

[0095] "The stepped structures 13 in the two memory blocks 15 are arranged symmetrically" is understood to mean that the number of stepped structures 14 contained in the stepped structures 13 of the two memory blocks 15 is the same, and that the two stepped structures 14 in the two stepped structures 13 that are at the same distance from the second separation structure 52 have the same height.

[0096] In some examples, referring to Figures 8 and 11, the height of the multiple staircase structures 14 within the memory block 15 gradually decreases along the direction from the first separation structure 51 to the second separation structure 52 in the second direction Y.

[0097] In some other examples, referring to Figure 9, in the second direction Y, along the direction from the first separation structure 51 to the second separation structure 52, the height of the multiple step structures 14 within the memory block 15 first decreases and then increases.

[0098] In some examples, referring to Figures 8 and 9, in the second direction Y, the two staircase structures 14 adjacent to both sides of the second separation structure 52 have the same height.

[0099] In some examples, referring to Figure 11, the three-dimensional memory 200 further includes a plurality of second stop units 60 arranged in a first direction X. The plurality of second stop units 60 are arranged on a plurality of steps 141 of the other stair structures 14 among the plurality of stair structures 14 other than the stair structure 14 on which the first stop unit 20 is located.

[0100] The protective layer 30 further covers the second stop section 60, and at least a portion of the protective layer 30 is positioned between the second stop section 60 and the step 141 adjacent to the second stop section 60.

[0101] For example, referring to Figures 8 and 9, when the first stop 20 is positioned on multiple steps 141 of the second stair structure 14B, the second stop 60 can be positioned on multiple steps 141 of the first stair structure 14A and the third stair structure 14C.

[0102] For example, referring to Figure 11, when the first stop 20 is positioned on multiple steps 141 of the first staircase structure 14A, the second stop 60 may be positioned on multiple steps 141 of the second staircase structure 14B.

[0103] In some examples, the materials of the first stop 20 and the second stop 60 are the same. For example, if the materials of the first stop 20 and the second stop 60 are the same, the materials of the first stop 20 and the second stop 60 may include, for example, carbon-doped silicon nitride. Alternatively, in one example, if the materials of the first stop 20 and the second stop 60 are the same, the materials of the first stop 20 and the second stop 60 may be, for example, silicon nitride.

[0104] For example, the material of the first stop unit 20 may be silicon nitride.

[0105] Thus, the material of the first stop section 20 and the material of the gate layer 11 are different, and the etching selectivity ratio of the first stop section 20 is different from that of the gate layer 11. The first stop section 20 tends to be etched when the contact holes are formed by the etching process. For this reason, when manufacturing the contact holes 411 in which the contact posts are placed, first, the heights of the multiple contact holes 41 corresponding to the step 141 are made different from each other, and the distance between the bottom of each contact hole 41 and the step 141 is made approximately the same, so that they can be stopped by the first stop section 20. Next, the first stop section 20 exposed by the multiple contact holes 41 is etched, and the dielectric layer 12 below the first stop section 20 is etched by the etching process, so that the contact holes 41 expose the gate layer 11 at their corresponding steps 141. Therefore, after filling the contact holes with conductive material to form contact posts, the problem of the contact holes penetrating the upper step and causing a short circuit between the gate layers of adjacent upper steps is avoided, improving the electrical performance and yield of the 3D memory.

[0106] In some examples, as shown in Figures 14 and 15, the three-dimensional memory 200 further includes a plurality of gate line isolation structures 70 extending in a first direction X and positioned between two adjacent isolation structures 50. The gate line isolation structures 70 extend through a second stop section 60 and the stacked structure 10 beneath it. In the first direction X, each gate line isolation structure 70 includes a plurality of sub-isolation structures 71 separated from each other. The material of the second stop section 60 is the same as the material of the gate layer 11.

[0107] The statement "the gate line separation structure 70 extends through the second stop section 60 and the laminated structure 10 below it" means that the slit in which the gate line separation structure 70 is placed extends through the second stop section 60 and the laminated structure 10 below it. Therefore, by performing gate replacement using the slit in which the gate line separation structure 70 is placed, the sacrificial layer in the initial laminated structure 101 can be replaced with the gate layer 11. At the same time, the material of the second stop section can be replaced with the material of the gate layer using the slit in which the gate line separation structure 70 is placed.

[0108] In some examples, the second stop 60 may be the same composite multilayer structure as the gate layer 11. In this case, the second stop 60 may include a high dielectric constant layer 112, a metal compound layer 113, and a conductive layer 111, where the high dielectric constant layer 112 encloses the conductive layer 111, and the metal compound layer 113 is located between the high dielectric constant layer 112 and the conductive layer 111. Examples of materials for the high dielectric constant layer 112 include aluminum oxide (Al2O3) and a metal compound. layer Examples of material 113 include tantalum nitride or titanium nitride.

[0109] In some examples, the second stop 60 may be the same single-layer structure as the gate layer 11. In this case, the second stop 60 also includes the conductive layer 111. The material of the conductive layer 111 includes, but is not limited to, tungsten, cobalt, copper, aluminum, or doped crystalline silicon, doped silicon and / or silicide.

[0110] In some examples, the second stop 60 may be the same composite multilayer structure as the gate layer 11. In this case, the second stop 60 may include a high dielectric constant layer 112, a metal compound layer 113, and a conductive layer 111, where the high dielectric constant layer 112 encloses the conductive layer 111, and the metal compound layer 113 is located between the high dielectric constant layer 112 and the conductive layer 111. Examples of materials for the high dielectric constant layer 112 include aluminum oxide (Al2O3), and examples of materials for the metal compound 113 include tantalum nitride or titanium nitride.

[0111] In some examples, referring to Figures 8, 9, 11, and 15, in the third direction Z, the thickness of the first stop 20 is the same as the thickness of the gate layer 11 of the preceding stage 141. The preceding stage 141 is adjacent to and taller than the stage 141 corresponding to the first stop 20.

[0112] Furthermore, it is possible to manufacture a first stop section 20 having a sacrificial layer for manufacturing the gate layer 11 of the preceding stage 141, thus eliminating the need to separately deposit the first stop section 20, thereby simplifying the manufacturing process of the 3D memory 200 and reducing the manufacturing cost of the 3D memory 200.

[0113] In some examples, the three-dimensional memory 200 includes a plurality of memory cell strings 201 arranged in an array in a core array region AA. Exemplarily, referring to Figure 16, in the third direction Z, the memory cell string 201 comprises, in order, a ground selection line layer 202 (bottom selection gate), a word line layer 203, a string selection line layer 204 (top selection gate), and a bit line 205. The memory cell string 201 further includes an array of channel structures 206 extending through the string selection line layer 204, the word line layer 203, and the ground selection line layer 202 in the third direction Z. The channel structures 206 connect the string selection line layer 204, the word line layer 203, and the ground selection line layer 202 in series to form the memory cell string 201.

[0114] In some examples, referring to Figure 16, the channel structure 206 may include sequentially arranged blocking layers 2061, storage layers 2062, tunnel layers 2063, channel layers 2064, and packing layers 2065.

[0115] Exemplary, the blocking layer 2061 may include a single layer, for example, a silicon dioxide (SiO2) layer. The blocking layer 2061 may also include multiple layers, for example, a laminate of silicon dioxide and aluminum oxide (Al2O3). The memory layer 2062 may include a single layer, such as a silicon nitride (SiN) layer. The memory layer 2062 may also include multiple layers, such as a laminate of silicon nitride, silicon oxynitride (SiON), and silicon nitride. The tunnel layer 2063 may include multiple layers, such as a laminate of silicon monoxide (SiO), silicon oxynitride, and silicon oxide. The material of the channel layer 2064 includes a semiconductor material such as polysilicon and / or single-crystal silicon. The material of the packing layer 2065 may include an insulating material such as silicon dioxide.

[0116] Referring to Figure 17, one end of the memory cell string 201 is connected to the bit line 205 and the other end is connected to the source line SL. The memory cell string 201 includes a plurality of transistors connected in series between the first and second ends, including at least one top-selection transistor Q1, at least one storage transistor M, and at least one bottom-selection transistor Q2. Figure 17 illustrates one top-selection transistor Q1, four storage transistors M, and one bottom-selection transistor Q2. The four storage transistors M are M1, M2, M3, and M4, respectively.

[0117] Referring to Figures 5A, 5B, and 18-21, other examples of parts of this disclosure provide other three-dimensional memory 300.

[0118] Similarly, as shown in Figures 5A and 5B, the three-dimensional memory 300 includes a core array region AA and a tiered region SS in the first direction X. As shown in Figure 5A, the three-dimensional memory 300 may include two core array regions AA and one tiered region SS positioned between the two core array regions AA. Alternatively, as shown in Figure 5B, the three-dimensional memory 300 may include two tiered regions SS and one core array region AA positioned between the two tiered regions SS.

[0119] The methods for distributing the core array region AA and the layer region SS within the three-dimensional memory 300 provided in some examples of this disclosure are not limited thereto.

[0120] Referring to Figure 18, the three-dimensional memory 300 includes a stacked structure 10', a plurality of first stop portions 20' arranged in a first direction X, a separation layer 30', a protective layer 40', and a plurality of contact posts 50'.

[0121] In some other examples, as shown in Figure 19B, the gate layer 11' may be a multilayer composite structure. In this case, the gate layer 11' may include sequentially formed high dielectric constant layers 112', metal compound layers 113', and conductive layers 111'. The material of the high dielectric constant layer 112' may include, for example, aluminum oxide (Al2O3), and metal compound layers. layer The material of 113' may include, for example, tantalum nitride or titanium nitride.

[0122] In some examples, the gate layer 11' may be a single-layer structure, as shown in Figure 19A. In this case, the gate layer 11' includes a conductive layer 111'. The material of the conductive layer 111' includes, but is not limited to, tungsten, cobalt, copper, aluminum, or doped crystalline silicon, doped silicon and / or silicide.

[0123] In some other examples, as shown in Figure 19B, the gate layer 11' may be a multilayer composite structure. In this case, the gate layer 11' may include sequentially formed high dielectric constant layers 112', metal compound layers 113', and conductive layers 111'. The material of the high dielectric constant layer 112' may include, for example, aluminum oxide (Al2O3), and the material of the metal compound 113' may include, for example, tantalum nitride or titanium nitride.

[0124] For example, the dielectric layer 12' can be made of an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0125] It should be noted that in the stacked structure 10', the thicknesses of the multiple gate layers 11' may be approximately the same or different. The thicknesses of the multiple dielectric layers 12' may also be approximately the same or different. The thicknesses of the multiple gate layers 11' and the multiple dielectric layers 12' can be selected according to actual demand. Furthermore, the number of stacks in the stacked structure 10' determines the number of memory cells. The more stacks in the stacked structure 10', the higher the integration density, i.e., the larger the number of memory cells. For example, the number of stacks and the height of the stacked structure 10' can be designed based on actual storage demand, and this is not limited to the present disclosure.

[0126] The stacked structure 10' includes a step structure 13' which is arranged in a first direction X and includes multiple step structures 14' having different heights in a second direction Y. The step structure 14' includes multiple steps 141'. The first direction X is perpendicular to the second direction Y.

[0127] If the step structure 13' includes a stair structure 14' positioned in a first direction X and having different heights in a second direction Y, it is understood that two spaced-apart stair structures 14' can have the same height, as long as it is guaranteed that two adjacent stair structures 14' among the multiple stair structures 14' included in the step structure 13' have different heights.

[0128] Based on this, in some examples, referring to Figure 20, the step structure 13' may include three stair structures 14' arranged in the second direction Y and having different heights from each other.

[0129] In some other examples, referring to Figure 21, the stair structure 13' may include three stair structures 14' arranged in a second direction Y, where the two stair structures 14' on either side have different heights than the central stair structure, but are the same height as each other.

[0130] Furthermore, in some examples, referring to Figures 22 and 23, the step structure 13' may include two stair structures 14' positioned in a second direction Y and having different heights from each other.

[0131] Please note that the number of staircase structures 14' in some examples of this disclosure is not limited thereto.

[0132] Multiple first stop sections 20', arranged in a first direction X, are positioned on multiple steps 141' of at least one staircase structure 14', with each first stop section 20' located on one of the steps 141'.

[0133] As shown in Figures 20, 21, and 23, the multiple first stop units 20' may be placed on only multiple steps 141' of a single staircase structure 14'. Alternatively, the multiple first stop units 20' may be placed on multiple steps 141' of multiple staircase structures 14'.

[0134] As shown in Figures 20, 21, and 23, the step 141' may include one gate layer 11' and one dielectric layer 12'. Alternatively, the step 141' may include multiple gate layers 11' and multiple dielectric layers 12'. This is not limited to the present disclosure.

[0135] The separation layer 30' covers the stepped structure 13' and is positioned between the stepped structure 13' and the first stop section 20'.

[0136] Exemplary examples, the separation layer 30' can be made of an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0137] As shown in Figures 20, 21, and 23, "the separation layer 30' is positioned between the stepped structure 13' and a plurality of first stop sections 20'" means that in the third direction Z, the separation layer 30' is positioned between the first stop section 20' of the stepped structure 13' and the step 141', and in the first direction Z and the second direction Y, the separation layer 30' is positioned between the first stop section 20' and the step 141' adjacent to the first stop section 20'.

[0138] In some examples of this disclosure, by providing an isolation layer 30', it is possible to protect the stepped structure 13' with the isolation layer 30' and the stacked structure 10'. On the other hand, when forming the gate layer 11' of the stepped structure 13', the gate layer 11' of the stepped structure 13' and the first stop 20' can be separated to avoid connecting the first stop 20' and the sacrificial layer and replacing the first stop 20', and it is also possible to avoid the gate layer 11' and the first stop 20' being electrically connected, thereby preventing the 3D memory 300 from failing.

[0139] The protective layer 40' covers the separation layer 30' and the first stop section 20'.

[0140] For example, the protective layer 40' can be made of silicon oxide, including but not limited to tetraethoxysilane (TEOS), siloxane, and silsesquioxane. For example, the protective layer 40' can be formed by chemical vapor deposition (CVD), spin coating, or the like.

[0141] In some examples, referring to Figures 19A and 20, when the protective layer 40' covers the separation layer 30' and the first stop portion 20', in the first direction X, at least a portion of the protective layer 40' is positioned between the side surface of the first stop portion 20' and the separation layer 30', and in the second direction Y, at least a portion of the protective layer 40' is positioned between the side surface of the first stop portion 20' and the separation layer 30'.

[0142] Therefore, it facilitates the separation of the multiple first stop units 20' from each other and avoids electrical connections between the multiple first stop units 20'.

[0143] One of the multiple contact posts 50' extends through the protective layer 40', the first stop section 20', and the separation layer 30', and is connected to the gate layer 11' at a step 141' corresponding to the first stop section 20'.

[0144] Exemplary examples, the contact post 50' may be made of a conductive material including, but not limited to, metals such as tungsten, copper, and aluminum, metal silicides, metal nitrides, and / or doped polysilicon.

[0145] It is understood that the stepped structure 13' described above is located within the stepped region SS. If the stepped region SS is located between two core array regions AA, the topography of the stepped structure 13' may be as shown in Figures 24A and 24B. That is, the stepped structure 13' may include at least one group of steps in which the height of a plurality of steps 141' gradually increases or decreases in the first direction X.

[0146] Exemplary, as shown in Figures 24A and 24B, the stepped structure 13' may include eight stepped groups in a first direction X, namely the first stepped group 131', the second stepped group 132', the third stepped group 133', the fourth stepped group 134', the fifth stepped group 135', the sixth stepped group 136', the seventh stepped group 137', and the eighth stepped group 138'. In the first direction X, the heights of the multiple steps 141' in the first stepped group 131', the third stepped group 133', the fifth stepped group 135', and the seventh stepped group 137' gradually decrease. In the first direction X, the heights of the multiple steps 141' in the second stepped group 132', the fourth stepped group 134', the sixth stepped group 136', and the eighth stepped group 138' gradually increase. Of course, the form of the stepped structure 13' in this disclosure is not limited thereto.

[0147] In the three-dimensional memory 300 provided in some examples of the present disclosure, a plurality of first stop portions 20' are arranged on at least one step structure 14' within a step structure 13'. Therefore, when forming contact holes 51' in which contact posts 50' are placed, it is possible to remove a portion of the protective layer on the first stop portions 20' using an etching process such as wet etching to expose a portion of the first stop portions 20', and then use the etching process to remove the exposed portion of the first stop portions 20' and the dielectric layer 12' between the separation layer 30' and the gate layer 11' below the first stop portions 20' to expose a portion of the gate layer 11'.

[0148] In the first etching step, due to the presence of the first stop 20', contact holes 51' having different depths corresponding to steps 141' having different heights can be stopped at each of the first stop 20' on the steps 141'. In the second etching step, since the distance between each of the first stop 20' and the gate layer 11' of the step 141' where the first stop 20' is located is approximately the same, in the second etching step, while etching simultaneously, contact holes 51' having different depths corresponding to steps 141' having different heights can be stopped at each of the gate layers 11' on the steps 141'.

[0149] Therefore, while forming the contact post 50' within the contact hole 51', the contact post 50' can contact the gate layer 11' of the corresponding step 141', facilitating the avoidance of short circuits between multiple gate layers by contact posts extending through multiple gate layers due to an increase in the number of layers of the stacked structure, thereby improving the electrical performance and yield of the 3D memory.

[0150] At the same time, by providing the first stopping section 20', it is also possible to enable the contact hole 51' to have a faster etching rate and the contact hole 51' (or contact post 50') to have better linearity. As a result, the dielectric layer in the dummy channel structure adjacent to the contact post 50' is less likely to be etched, thereby improving the yield of the 3D memory 300.

[0151] Referring to Figures 18 to 23, in some examples the three-dimensional memory 300 further includes a separation structure 60'. The separation structure 60' extends in a first direction X through the stacked structure 10'. The separation structure 60' divides the stacked structure 10' into a plurality of memory blocks 15'. Each memory block 15' includes a stepped structure 13'. The stepped structure 14' on which the first stop 20' is located is spaced apart from the separation structure 60'.

[0152] It is understood that the separation structure 60' may extend through the laminated structure 10' and also through the separation layer 30'.

[0153] The statement "The staircase structure 14' on which the first stopping section 20' is located is positioned at a distance from the separation structure 60'" means that the first stopping section 20' is positioned at a distance from the separation structure 60'.

[0154] In some examples of this disclosure, the stacked structure 10' is divided into a plurality of memory blocks 15' having a separation structure 60', which can further improve the memory density of the three-dimensional memory 300. On the other hand, the stepped structure 14' in which the first stop 20' is located is spaced apart from the separation structure 60', which also prevents the first stop 20' from being replaced in a subsequent step of forming a gate layer 11' by performing gate replacement using the slit in which the separation structure is located, thereby preventing contact posts from penetrating the replaced first stop and being electrically connected to the plurality of gate layers, thus avoiding failures in the three-dimensional memory.

[0155] In some examples, referring to Figures 20 and 21, in the second direction Y, the memory block 15' includes a first staircase structure 14A', a second staircase structure 14B', and a third staircase structure 14C', and the first stop section 20' is positioned on multiple steps 141' of the second staircase structure 14B'.

[0156] Therefore, the second stair structure 14B' has a height difference in the third direction Z from both the first stair structure 14A' and the third stair structure 14C', and is positioned at a distance from the separation structure 60' (i.e., the first stair structure 14A' and the third stair structure 14C' are between the second stair structure 14B' and the separation structure 60'), which facilitates preventing the first stop section 20' from being replaced.

[0157] In some other examples, referring to Figure 23, in the second direction Y, the memory block 15' includes a first staircase structure 14A' and a second staircase structure 14B', the first staircase structure 14A' is spaced apart from the separation structure 60', and the first stop section 20' is positioned on multiple steps 141' of the first staircase structure 14A'.

[0158] Thus, the first stair structure 14A' has a height difference with respect to the second stair structure 14B' in the third direction Z, and is positioned at a distance from the separation structure 60', making it easier to prevent the replacement of the first stop section 20'.

[0159] In some examples, referring to Figures 20 to 24B, each memory block 15' further includes a side wall 16'. The isolation structure 60' includes a first isolation structure 61' and a second isolation structure 62'. In the second direction Y, the first isolation structure 61' is positioned between two adjacent side walls 16', and the second isolation structure 62' is positioned between two adjacent stepped structures 13'. The side walls 16' are configured to enhance the structural stability of the three-dimensional memory 300.

[0160] In some examples, as shown in Figures 18 and 22, the first separation structure 61' may be a single integrated structure. That is, when manufacturing the first separation structure 61', a slit in which the first separation structure 61' is placed can be obtained by etching in a single etching step, and the first separation structure 61' can be formed within that slit.

[0161] In some other examples, as shown in Figure 25, the first separation structure 61' may include a first separation sub-part 611', a second separation sub-part 612', and a third separation sub-part 613' connected sequentially in a first direction X. The second separation sub-part 612' is larger in size in a second direction Y than the first separation sub-part 611' and larger than the third separation sub-part 613'.

[0162] Exemplary, the first separation sub-part 611' and the third separation sub-part 613' are located within the core array region AA, and the second separation sub-part 612' is located within the stepped region SS and is in contact with the side wall 16'.

[0163] For example, the second separation sub-part 612' may be manufactured simultaneously with the dummy channel structure and the channel structure. The first separation sub-part 611' and the third separation sub-part 613' may be manufactured after the manufacturing of the channel structure is completed. Accordingly, the material of the second separation sub-part 612' may be the same as the material of the dummy channel structure or the channel structure.

[0164] In some examples of this disclosure, by providing a second separation sub-part 612', it is possible to separate two adjacent memory blocks 15' on the one hand, and to support the stacked structure 10' on the other hand, thereby preventing the stacked structure 10' from collapsing.

[0165] In some examples, referring to Figures 22, 25, and 26, in the second direction Y, the stepped structures 13' within the two memory blocks 15' adjacent to the second separated structure 62' are arranged symmetrically.

[0166] It is understood that "the stepped structures 13' within the two memory blocks 15' are arranged symmetrically" may mean that the number of stepped structures 14' contained in the stepped structures 13' of the two memory blocks 15' is the same, and that the two stepped structures 14' within the two stepped structures 13' that are at the same distance from the second separation structure 62' have the same height.

[0167] In some examples, referring to Figures 20 and 23, in the second direction Y, the height of the multiple stair structures 14' within the memory block 15' gradually decreases along the direction from the first separation structure 61' to the second separation structure 62'.

[0168] In some other examples, referring to Figure 21, in the second direction Y, along the direction from the first separation structure 61' to the second separation structure 62', the height of the multiple step structures 14' within the memory block 15' first decreases and then increases.

[0169] In some examples, referring to Figures 20 and 21, in the second direction Y, the two staircase structures 14' adjacent to both sides of the second separation structure 62' have the same height.

[0170] In some examples, referring to Figures 20, 21, and 23, the three-dimensional memory 300 further includes a plurality of second stopping units 70' arranged in a first direction X. The plurality of second stopping units 70' are positioned on multiple steps of the other staircase structures 14' among the plurality of staircase structures 14' other than the staircase structure 14' in which the first stopping units 20' are located.

[0171] The separation layer 30' is similarly positioned between the stepped structure 13' and the second stop 70'. Similarly, as shown in Figure 23, "the separation layer 30' is similarly positioned between the stepped structure 13' and the multiple second stop 70'" is understood to mean that in the third direction Z, the separation layer 30' is positioned between the second stop 70' of the stepped structure 13' and the step 141', and in the first direction X and the second direction Y, the separation layer 30' is positioned between the second stop 70' and the step 141' adjacent to the second stop 70'. The protective layer 40' further covers the second stop 70'.

[0172] Exemplary, when the protective layer 40' further covers the second stop portion 70', in the first direction X, at least a portion of the protective layer 40' is positioned between the side surface of the second stop portion 70' and the separation layer 30', and in the second direction Y, at least a portion of the protective layer 40' is positioned between the side surface of the second stop portion 70' and the separation layer 30'.

[0173] For example, referring to Figures 20 and 21, when the first stop 20' is positioned on multiple steps 141' of the second staircase structure 14B', the second stop 70' may be positioned on multiple steps 141' of the first staircase structure 14A' and the third staircase structure 14C'.

[0174] For example, referring to Figure 23, when the first stop 20' is positioned on multiple steps 141' of the first staircase structure 14A', the second stop 70' may be positioned on multiple steps 141' of the second staircase structure 14B'.

[0175] In some cases, the materials of the first stop section 20' and the second stop section 70' may be the same.

[0176] Based on this, the material of the first stop section 20' and the second stop section 70' may include, for example, carbon-doped silicon nitride or silicon nitride.

[0177] In some examples, the materials of the first stop section 20' and the second stop section 70' may be different.

[0178] For example, the material of the first stop section 20' may be silicon nitride.

[0179] If the material of the first stop 20' includes silicon nitride or carbon-doped silicon nitride, the material of the first stop 20' and the material of the gate layer 11' are different, and the etching selectivity ratios of the first stop 20' and the gate layer 11' are different. The first stop 20' tends to be etched when the contact holes are formed by the etching process. Therefore, when manufacturing the contact holes 51' in which the contact posts 50' are placed, first, multiple contact holes 51' corresponding to the steps 141' can be stopped at the first stop 20' with different heights, so that the distance between the bottom of each contact hole 51' and the step 141' is approximately the same. Next, the first stop 20' exposed by the multiple contact holes 51' is etched, and the contact holes 51' expose the gate layer 11' at their corresponding steps 141' in order to etch the isolation layer 30' and dielectric layer 12' below the first stop 20' using the etching process. Therefore, after filling the contact holes with conductive material to form contact posts, the problem of the contact holes penetrating the upper layers and causing short circuits between the gate layers of adjacent upper layers is avoided, improving the electrical performance and yield of the 3D memory.

[0180] In some examples, as shown in Figures 26 and 27, the three-dimensional memory 300 further includes a plurality of gate line isolation structures 80' extending in a first direction X and positioned between two adjacent isolation structures 60'. The gate line isolation structures 80' extend through a second stop section 70' and a stacked structure 10'. In the first direction X, each gate line isolation structure 80' includes a plurality of sub-isolation structures 81' separated from each other.

[0181] The statement "the gate line separation structure 80' extends through the second stop section 70' and the laminated structure 10'" means that the slit in which the gate line separation structure 80' is placed extends through the second stop section 70' and the laminated structure 10'.

[0182] Providing the gate line separation structure 80' also allows for the release of stress on the 3D memory 300.

[0183] In some cases, the thickness of the second stop section 70' is less than or equal to the thickness of the gate layer 11', and in this case, the material of the second stop section 70' is the same as the material of the gate layer.

[0184] In some other examples, the second stop 70' may be the same composite multilayer structure as the gate layer 11'. In this case, the second stop 70' may include a high dielectric constant layer 112', a metal compound layer 113', and a conductive layer 111', where the high dielectric constant layer 112' encloses the conductive layer 111', and the metal compound layer 113' is between the high dielectric constant layer 112' and the conductive layer 111'. The material of the high dielectric constant layer 112' may include, for example, aluminum oxide (Al2O3), or a metal compound layer The material of 113' may include, for example, tantalum nitride or titanium nitride.

[0185] Based on this, in some examples, the second stop 70' may be the same single-layer structure as the gate layer 11'. In this case, the second stop 70' also includes the conductive layer 111'. The material of the conductive layer 111' includes, but is not limited to, tungsten, cobalt, copper, aluminum, or doped crystalline silicon, doped silicon and / or silicide.

[0186] In some other examples, the second stop 70' may be the same composite multilayer structure as the gate layer 11'. In this case, the second stop 70' may include a high dielectric constant layer 112', a metal compound layer 113', and a conductive layer 111', where the high dielectric constant layer 112' encloses the conductive layer 111', and the metal compound layer 113' is between the high dielectric constant layer 112' and the conductive layer 111'. The material of the high dielectric constant layer 112' may include, for example, aluminum oxide (Al2O3), and the material of the metal compound 113' may include, for example, tantalum nitride or titanium nitride.

[0187] In some other examples, the thickness of the second stop section 70' is greater than the thickness of the gate layer 11', in which case the material of the second stop section 70' is the same as the material of the gate line separation structure 80'.

[0188] Based on this, in some examples, the material of the second stop 70' and the material of the gate line separation structure 80' may both include dielectric materials such as silicon oxide and / or silicon nitride. In some other examples, the second stop 70' and the gate line separation structure 80' may be composite laminated structures. For example, the second stop 70' (or gate line separation structure 80') may include a dielectric material layer and a conductive material layer, such as at least one of tungsten, cobalt, copper, aluminum, or polysilicon, arranged in sequence. In some other examples, the second stop 70' may include a dielectric material and a high dielectric constant layer enclosing the dielectric material. In some other examples, the second stop 70' may further include a composite laminated structure and a high dielectric constant layer enclosing the composite laminated structure.

[0189] To address the technical problem that higher gate layers tend to be penetrated by contact posts, two types of 3D memory are introduced above. The two methods for manufacturing these 3D memory are described below.

[0190] Referring to Figure 28, some examples of this disclosure provide a method for manufacturing a three-dimensional memory 200, including operations S1 to S5.

[0191] Referring to Figures S1, 29A, 29B, and 30, an initial laminated structure 101 is formed. The initial laminated structure 101 includes a sacrificial layer 110 and a dielectric layer 12. The initial laminated structure 101 includes a stepped structure 13 which comprises a plurality of stepped structures 14 having different heights in a first direction X and a second direction Y. Each stepped structure 14 comprises a plurality of steps 141. The first direction X is perpendicular to the second direction Y.

[0192] It should be noted that the sacrificial layer 110 and the dielectric layer 12 can be formed, for example, by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), atomic layer deposition (ALD), or sputtering.

[0193] Exemplary, the sacrificial layer 110 and the dielectric layer 12 have different etching selectivity ratios so that the sacrificial layer 110 is removed in a subsequent step while the dielectric layer 12 remains, thereby forming a gate line gap for forming the gate layer 11. Exemplary, the material of the sacrificial layer 110 may be silicon nitride, and the material of the dielectric layer 12 may be silicon oxide.

[0194] The number of sacrificial layers 110 and dielectric layers 12 in the initial laminated structure 101 can be designed according to actual requirements. Exemplariously, the initial laminated structure 101 may have 16 sacrificial layers 110 and dielectric layers 12, or 32 sacrificial layers 110 and dielectric layers 12. This is not limited to the present disclosure. Note that the number of initial layer pairs in the accompanying drawings provided in this disclosure are illustrative and not limit the present disclosure.

[0195] It should be noted that in the initial laminated structure 101, the thicknesses of the multiple sacrificial layers 110 may be approximately the same or different. The thicknesses of the multiple dielectric layers 12 may also be approximately the same or different. The thicknesses of the multiple sacrificial layers 110 and the multiple dielectric layers 12 can be selected according to actual requirements.

[0196] In some examples, the operation S1 for forming the initial laminated structure 101, as shown in Figure 31, includes the following:

[0197] S11, a pre-configured laminated structure 1011 is formed, which includes alternately arranged sacrificial layers 110 and dielectric layers 12.

[0198] In S12, the pre-set laminated structure 1011 is etched to form a plurality of reference steps 142 arranged in the second direction Y. Each reference step 142 corresponds to one staircase structure 14.

[0199] In S13, a staircase structure 14 is formed by trimming etching and cutting processes, which create a plurality of steps 141 arranged in a first direction X based on a reference step 142. The initial laminated structure 101 includes a plurality of staircase structures 14.

[0200] In some examples, as shown in Figure 32, the operation S12 for etching a pre-configured laminated structure 1011 to form a plurality of reference stages 142 arranged in a second direction Y includes the following:

[0201] As shown in Figures 33A and 33B1, S121, a first mask layer 21 is formed on a pre-configured laminated structure 1011. The first mask layer 21 exposes a first region W1 of the pre-configured laminated structure 1011.

[0202] In step S122, as shown in Figure 34, at least one sacrificial layer 110 and at least one dielectric layer 12 of the first region W1 of the pre-configured laminated structure 1011 are etched.

[0203] As shown in S123, Figures 35A and 35B, the first mask layer 21 is trimmed to expose the second region W2 of the pre-configured laminated structure 1011. The first region W1 is located inside the second region W2. Along the second direction Y, there is a gap between the boundary of the first region W1 and the boundary of the second region W2.

[0204] In S124, as shown in Figure 36, at least one sacrificial layer 110 and at least one dielectric layer 12 of the second region W2 of the pre-set laminated structure 1011 are etched to form three reference stages 142 having different heights in the second direction Y.

[0205] For example, in operation S122, it is possible to etch one sacrificial layer 110 and one dielectric layer 12 of a pre-set first region W1 of the laminated structure 1011, and in operation S124, it is possible to etch one sacrificial layer 110 and one dielectric layer 12 of a pre-set second region W2 of the laminated structure 1011 to form three reference stages 142 having different heights in the second direction Y.

[0206] In operation S122, one sacrificial layer 110 and one dielectric layer 12 of the first region W1 of the pre-set laminated structure 1011 are etched, and in operation S124, one sacrificial layer 110 and one dielectric layer 12 of the second region W2 of the pre-set laminated structure 1011 are etched. In this case, the height difference between two adjacent step structures 14 in the third direction Z is the height corresponding to one sacrificial layer 110 and one dielectric layer 12.

[0207] In some other examples, as shown in Figure 37, the operation S12 for etching a pre-configured laminated structure 1011 to form a plurality of reference stages 142 arranged in a second direction Y includes the following:

[0208] In step S125, as shown in Figure 38, a second mask layer 22 is formed on the pre-configured laminated structure 1011. The second mask layer 22 exposes at least one-third of the W3 region of the pre-configured laminated structure 1011.

[0209] Figure 38 shows an example in which the second mask layer 22 exposes two third regions W3, but the disclosure is not limited thereto.

[0210] In S126, as shown in Figure 39, at least one sacrificial layer 110 and at least one dielectric layer 12 of the third region W3 of the pre-set laminated structure 1011 are etched to form three reference stages 142 whose height decreases first and then increases in two directions Y.

[0211] For example, a pre-configured laminated structure 1011 can be etched using either a wet etching process or a dry etching process.

[0212] The above operation was explained using the formation of three reference stages 142 as an example, but please note that it is also possible to form two or more reference stages 142 in other examples.

[0213] For example, if the step structure 13 includes two stair structures 14, the two stair structures 14 can be obtained simply by operations S121, S122, and S13.

[0214] For example, if the stepped structure 13 includes more than three stair structures 14, the first mask layer 21 can be trimmed multiple times after operations S121 to S124 so that the area of ​​the initial laminated structure exposed by the first mask layer 21 becomes increasingly larger. Each time the first mask layer 21 is trimmed, at least one pair of initial layers 102 of the portion of the initial laminated structure 101 exposed by the first mask layer 21 is etched to form more than three reference steps 142, thereby forming more than three stair structures 14.

[0215] Note that after obtaining multiple staircase structures 14, it is necessary to remove the trimmed first mask layer 21 or second mask layer 22.

[0216] For example, in operation S13, it is also possible to form the side walls 16 while forming a plurality of steps 141 arranged in a first direction X based on a reference step 142 by trimming etching and cutting steps in order to form the staircase structure 14.

[0217] S2, a plurality of first stopping sections 20 are formed on a plurality of steps 141 of at least one staircase structure 14.

[0218] In some examples, as shown in Figure 40, the operation S2 that forms a plurality of first stopping sections 20 on a plurality of steps 141 of at least one staircase structure 14 includes the following:

[0219] In S21, the uppermost sacrificial layer 110 and dielectric layer 12 of each stage 141 are etched to form a plurality of first stop sections 20.

[0220] Referring to Figures 29A, 41A, 29B, and 41B, etching the uppermost sacrificial layer 110 and dielectric layer 12 of each stage 141 may, for example, involve etching a portion 143 of the sacrificial layer 110 and dielectric layer 12 at the junction with the stage 141 in the second direction Y. Referring to Figures 30 and 42, etching the uppermost sacrificial layer 110 and dielectric layer 12 of each stage 141 may, for example, involve etching a portion 144 of the sacrificial layer 110 and dielectric layer 12 at the junction with the stage 141 in the first direction X.

[0221] In this way, by etching the uppermost sacrificial layer 110 and dielectric layer 12 of each stage 141 and removing a portion of the uppermost sacrificial layer 110 and dielectric layer 12 at the junction with the stage 141, it is no longer necessary to separately deposit additional films to form multiple first stop sections 20, thereby reducing the manufacturing process and cost of the 3D memory 200.

[0222] At the same time, since there is a gap between the formed first stop portion 20 and the step, the first stop portion 20 has no tendency to be replaced in the subsequent process of replacing the sacrificial layer 110 with the gate layer 11. Therefore, in the subsequent process of forming the contact hole 41, the contact holes 41 corresponding to different steps 141 can first stop at their corresponding first stop portions 20 after the first etching, and then stop at the gate layer 11 after the second etching, thereby avoiding the problem that the contact hole penetrates the upper layer step and a short circuit occurs between the upper layer steps after the contact post is formed.

[0223] S3. Referring to FIGS. 43 and 44, a protective layer 30 is formed. The protective layer 30 covers the stepped structure 13 and the first stop portion 20, and at least a part of the protective layer 30 is disposed between the first stop portion 20 and the step 141 adjacent to the first stop portion 20.

[0224] The protective layer 30 can be made of silicon oxide including, but not limited to, tetraethoxysilane (TEOS), siloxane, silsesquioxane, etc.

[0225] Exemplarily, the protective layer 30 can be formed by a chemical vapor deposition (CVD) process, a spin coating process, etc.

[0226] Exemplarily, after the protective layer 30 is formed, it can also be planarized by a chemical mechanical polishing (CMP) process.

[0227] S4. Referring to FIGS. 45 and 46, the sacrificial layer 110 is replaced with the gate layer 11 to form the stacked structure 10.

[0228] In some examples, the 3D memory 200 includes a separation structure 50 including a first separation structure 51 and a second separation structure 52 that are both integral structures.

[0229] Based on this, in some examples, as shown in FIG. 47, the manufacturing method further includes the following.

[0230] Exemplarily, the sacrificial layer 110 can be replaced with the gate layer 11 using the first slit 501. Exemplarily, it is possible to introduce an etching solution from the first slit 501 into the initial stacked structure 101 by a wet etching process. At this time, since the etching selectivity between the sacrificial layer 110 and the dielectric layer 12 is different, in the etching process, the sacrificial layer 110 can be etched and the dielectric layer 12 can be left remaining, thereby forming a cavity in the corresponding formed portion.

[0231] Exemplarily, the first slit 501 can be formed by a dry etching process. The first slit 501 extends through the initial stacked structure 101 in the third direction Z.

[0232] Exemplarily, the sacrificial layer 110 can be replaced with the gate layer 11 using the first slit 501. Exemplarily, it is possible to introduce an etching solution from the first slit 501 into the initial stacked structure 101 by a wet etching process. At this time, since the etching selectivity between the sacrificial layer 10 and the dielectric layer 12 is different, in the etching process, the sacrificial layer 110 can be etched and the dielectric layer 12 can be left remaining, thereby forming a cavity in the corresponding formed portion.

[0233] Exemplarily, it is possible to form the gate layer 11 in the cavity using one or more of the processes of CVD, PVD, and ALD.

[0234] The gate layer 11 may be a single-layer structure. For example, the gate layer 11 includes a conductive material including, but not limited to, tungsten, cobalt, copper, aluminum, or doped crystalline silicon. Alternatively, the gate layer 11 may be a multilayer composite structure. For example, the gate layer 11 may include a high dielectric constant layer (such as aluminum oxide Al2O3), a metal compound layer (such as tantalum nitride, titanium nitride), and a conductive layer (such as tungsten) formed sequentially.

[0235] In some examples, as shown in FIG. 47, the manufacturing method further includes the following.

[0236] S42, as shown in Figure 45, a separation structure 50 is formed within the first slit 501.

[0237] Exemplary, the isolation structure 50 may be formed using one or more processes from CVD, PVD, and ALD. The isolation structure 50 may include just one or more dielectric material layers, or it may include one or more dielectric material layers and at least one conductive material layer arranged in sequence.

[0238] The separation structure 50 can divide the stacked structure 10 into multiple memory blocks 15, thereby further improving the memory density of the three-dimensional memory 200.

[0239] In some other examples, as shown in Figure 13, the three-dimensional memory 200 includes an isolation structure 50 which includes a first isolation structure 51 and a second isolation structure 52. The first isolation structure 51 may include a first isolation sub-part 511, a second isolation sub-part 512, and a third isolation sub-part 513 which are sequentially connected in a first direction X.

[0240] In some examples, the manufacturing method may further include the following, as shown in Figure 49:

[0241] S43, referring to Figure 50, a second separation sub-part 512 is formed in the first direction X, extending through the initial laminated structure 101.

[0242] Based on this, the second separation sub-part 512 may, exemplarily, be manufactured simultaneously with the dummy channel structure and the channel structure. For example, the second separation sub-part 512 can be formed after the initial laminated structure 101 is formed and before the protective layer 30 is formed.

[0243] S44, referring to Figure 51, a first sub-slit 502, a second sub-slit 503, and a second slit 504 are formed, extending in a first direction X and through the initial laminated structure 101. In the first direction X, the first sub-slit 502 and the second sub-slit 503 are in contact with both ends of the second separation sub-part 512, respectively. In the second direction Y, the second slit 504 is positioned between two adjacent second separation sub-parts 512.

[0244] In some examples, the manufacturing method may further include the following, as shown in Figure 49:

[0245] In S45, referring to Figure 13, a first separation sub-part 511 is formed in the first sub-slit 502, a third separation sub-part 513 is formed in the second sub-slit 503, and a second separation structure 52 is formed in the second slit 504.

[0246] The first separation sub-part 511, the third separation sub-part 513, and the second separation sub-part 512 constitute at least a portion of the first separation structure 51.

[0247] In some examples, referring to Figures 41A, 41B, and 42, the manufacturing method may further include the following:

[0248] Multiple second stop sections 60 are formed on multiple steps 141 of multiple stair structures 14 other than the stair structure 14 on which the first stop section 20 is located.

[0249] In some examples, referring to Figure 52, the manufacturing method may further include the following:

[0250] Referring to S46 and Figure 53, a third slit 505 is formed extending in the first direction X. The third slit 505 extends through the second stop 60 and the initial laminated structure 101. Each third slit 505 includes a plurality of third sub-slits 506 spaced apart from each other along the first direction X.

[0251] In some examples, referring to Figure 41, the manufacturing method may further include the following:

[0252] S47. Referring to FIG. 45, a gate line separation structure 70 is formed in the third slit 505.

[0253] Exemplarily, in operation S4, after replacing the sacrificial layer 120 with the gate layer 11 to form the stacked structure 10, a plurality of third slits 505 extending in the first direction X can be formed. After operation S4, the gate line separation structure 70 can be formed in the third slit 505.

[0254] In some examples, the third slit 505 may be formed simultaneously with the first slit 501. In some other examples, the third slit 505 may be formed simultaneously with the first sub - slit 502, the second sub - slit 503, and the second slit 504.

[0255] Thereby, in the process of replacing the sacrificial layer 110 with the gate layer 11, the material of the second stop portion can be replaced with the same material as the gate layer 11 by using the plurality of third slits 505.

[0256] S5. Referring to FIGS. 6 - 11, a plurality of contact posts 40 are formed. The contact posts 40 extend through the protective layer 30 and the first stop portion 20 and are electrically connected to the gate layer 11 at the stage 141 corresponding to the first stop portion 20.

[0257] Exemplarily, referring to FIG. 54, S5 of forming a plurality of contact posts 40 includes operations S51 - S53.

[0258] S51. Referring to FIGS. 55 and 56, the protective layer 30 is etched to the first stop portion 20 to form a plurality of contact holes 41.

[0259] Exemplarily, the contact holes 41 can be formed by a wet etching process.

[0260] Because the first stop portion 20 and the gate layer 11 are made of different materials and have different etching selectivity ratios, in the process of forming the contact holes 41, the first stop portion 20 does not tend to be etched like the gate layer 11, and all contact holes 41 corresponding to steps 141 of different heights are stopped at the first stop portion 20 on the corresponding step, thereby exposing the first stop portion 20.

[0261] Referring to S52, Figures 57 and 58, the first stop portion 20 exposed by the contact hole 41 is etched, and the dielectric layer 12 beneath the first stop portion 20 is etched, so that the contact hole 41 exposes the gate layer 11.

[0262] For example, the first stop portion 20 exposed by the contact hole 41 can be etched, and the dielectric layer 12 beneath the first stop portion 20 can be etched using a dry etching process to expose the gate layer 11 through the contact hole 41.

[0263] The first stop portions 20 on different stages 141 are at approximately the same distance from the gate layer 11 within the stage 141. Therefore, it is possible to etch layers of the same thickness on different stages 141 to expose the gate layer 11. Thus, all contact holes 41 formed in the 3D memory can make good contact with the gate layer 11 on their corresponding stages 141 and do not penetrate the gate layer 11 on their corresponding stages, thereby effectively avoiding the case where the gate layer is penetrated and different gate layers are short-circuited after the contact posts 40 are formed, and thus improving the electrical performance and yield of the 3D memory.

[0264] Referring to Figures 6 to 11, S53, a contact post 40 is formed within the contact hole 41.

[0265] Exemplary examples include the formation of the contact post 40 by CVD, PVD, and ALD. The material of the contact post 40 is a conductive material such as at least one of tungsten, cobalt, copper, aluminum, doped crystalline silicon, or silicide.

[0266] Some examples in this disclosure further provide other methods for manufacturing three-dimensional memory 300, and the methods for manufacturing three-dimensional memory 200 provided in the above examples may be referenced to implement similar operation to the above examples.

[0267] Referring to Figure 59, the manufacturing method of the 3D memory 300 includes operations S1' to S6'.

[0268] Referring to Figures 60 and 61, S1' forms an initial laminated structure 101'. The initial laminated structure 101' includes alternately arranged sacrificial layers 110' and dielectric layers 12'. The initial laminated structure 101' includes an initial stepped structure 130' which is arranged in a first direction X and includes a plurality of stepped structures 14' having different heights in a second direction Y. The stepped structure 14' includes a plurality of steps 141'. The first direction X is perpendicular to the second direction Y.

[0269] Similar to the manufacturing method of the 3D memory 200 provided in the previous example, the sacrificial layer 110' and the dielectric layer 12' can be formed by, for example, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDP-CVD), and atomic layer growth (ALD) or sputtering processes.

[0270] The sacrificial layer 110' and the dielectric layer 12' have different etching selectivity ratios, so that the sacrificial layer 110' can be removed in a subsequent step while the dielectric layer 12' remains, thereby forming a gate line gap for forming the gate layer 11'. Exemplarily, the material of the sacrificial layer 110' may be silicon nitride, and the material of the dielectric layer 12' may be silicon oxide.

[0271] The number of sacrificial layers 110' and dielectric layers 12' in the initial laminated structure 101' can be designed according to actual requirements. Exemplariously, the initial laminated structure 101' may have 16 pairs of sacrificial layers 110' and dielectric layers 12', or 32 pairs of sacrificial layers 110' and dielectric layers 12', and this is not limited to the present disclosure. Note that the number of initial layer pairs 102' in the accompanying drawings provided in this disclosure is illustrative and not limiting to the present disclosure.

[0272] Note that in the initial laminated structure 101', the thicknesses of the multiple sacrificial layers 110' may be approximately the same or different. The thicknesses of the multiple dielectric layers 12' may also be approximately the same or different. The thicknesses of the multiple sacrificial layers 110' and the multiple dielectric layers 12' can be selected according to actual requirements.

[0273] For the process of forming the initial stacked structure 101', refer to operations S11 to S13 in the manufacturing method of the three-dimensional memory 200 described above.

[0274] S2', as shown in Figures 62 and 63, forms a separation layer 30' that covers the stepped structure 13'.

[0275] Exemplary examples, the separation layer 30' can be made of an insulating material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0276] Referring to Figures 64 and 65, S3', a plurality of first stop sections 20' are formed on the side of the separation layer 30' away from the step structure 13'. The plurality of first stop sections 20' are arranged in a first direction X and are located on a plurality of steps 141' of at least one step structure 14', with each first stop section 20' located on one step 141'.

[0277] In some examples, referring to Figure 66, the operation S3' which forms a plurality of first stop sections 20' on the side of the separation layer 30' away from the stepped structure 13' may include the following:

[0278] Referring to Figures 67 and 68, a predetermined stop layer 21' is formed on the side of the separation layer 30' that is away from the stepped structure 13'.

[0279] Referring to S32', Figures 64 and 65, a portion 211' of the pre-set stop layer 21' is removed at the joint with the corresponding step 141' to form a plurality of first stop portions 20'.

[0280] In some cases, the material of the pre-set stop layer 21' may be the same as the material of the sacrificial layer 120'.

[0281] In some examples, the material of the pre-set stop layer 21' may be different from the material of the sacrificial layer 120'. In this case, the material of the pre-set stop layer 21' may be carbon-doped silicon nitride.

[0282] Referring to S4', Figures 69 and 70, a protective layer 40' is formed. The protective layer 40' covers the separation layer 30' and the first stop section 20'.

[0283] Referring to Figures 64 and 65, it is understood that after the formation of the multiple first stop portions 20', there is a gap between the sides of the first stop portions 20' and the separation layer 30' in the first direction X and the second direction Y. Therefore, after subsequently forming the protective layer 40', at least a portion of the protective layer 40' falls into the gap between the sides of the first stop portions 20' and the separation layer 30'.

[0284] In S5', referring to Figure 71, the sacrificial layer 110' is replaced with the gate layer 11' to form the laminated structure 10'.

[0285] In some examples, the three-dimensional memory 300 further includes a separation structure 60'. The separation structure 60' includes a first separation structure 61' and a second separation structure 62', both of which are integrated structures.

[0286] Based on this, in some examples, the manufacturing method further includes the following, as shown in Figure 72.

[0287] For example, the sacrificial layer 110' can be replaced with the gate layer 11' using the first slit 601'. For example, the first slit can be replaced with the gate layer 11' using a wet etching process. slit It is possible to introduce the etching solution into the initial laminated structure 101' from 601'. At this time, since the etching selectivity ratios of the sacrificial layer 110' and the dielectric layer 12' are different, the sacrificial layer 110' can be etched during the etching process while the dielectric layer 12' is left intact, thereby forming a cavity in the corresponding formation area.

[0288] For example, the first slit 601' can be formed by a dry etching process. The first slit 601' extends through the initial laminated structure 101' in the third direction Z.

[0289] For example, the sacrificial layer 110' can be replaced with the gate layer 11' using the first slit 601'. For example, an etching solution can be introduced from the first separation section 601' into the initial laminated structure 101' using a wet etching process. In this case, since the sacrificial layer 110' and the dielectric layer 12' have different etching selectivity ratios, the sacrificial layer 110' can be etched during the etching process, leaving the dielectric layer 12', thereby forming a cavity in the corresponding formation area.

[0290] For example, it is possible to form a gate layer 11' in the cavity using one or more processes from CVD, PVD, and ALD.

[0291] In some examples, the manufacturing method may further include the following, as shown in Figure 72:

[0292] Referring to Figure 71, S52', a separation structure 60' is formed within the first slit 601'.

[0293] Exemplary examples, the isolation structure 60' can be formed using one or more processes from CVD, PVD, and ALD. The isolation structure 60' may consist of only one or more dielectric material layers, or it may consist of one or more sequentially arranged dielectric material layers and at least one conductive material layer.

[0294] In some other examples, as shown in Figure 25, the three-dimensional memory 300 includes a separation structure 60' which includes a first separation structure 61' and a second separation structure 62'. The first separation structure 61' may include a first separation sub-part 611', a second separation sub-part 612', and a third separation sub-part 613' which are sequentially connected in a first direction X.

[0295] Based on this, in some examples, the manufacturing method may further include the following, as shown in Figure 74.

[0296] S53', referring to Figure 75, a second separation sub-part 612' is formed in the first direction X, extending through the initial laminated structure 101'.

[0297] Based on this, exemplary, the second separation sub-part 612' may be manufactured simultaneously with the dummy channel structure and the channel structure. For example, it is possible to form the second separation sub-part 612' after forming the initial laminated structure 101' but before forming the protective layer 40'.

[0298] Referring to Figure 76, in S54', a first sub-slit 602', a second sub-slit 603', and a second slit 604' are formed in the first direction X, extending through the initial laminated structure 101'. In the first direction X, the first sub-slit 602' and the second sub-slit 603' are in contact with both ends of the second separation sub-part 612', respectively. In the second direction Y, the second slit 604' is positioned between two adjacent second separation sub-parts 612'.

[0299] In some examples, the manufacturing method may further include the following, as shown in Figure 74:

[0300] Referring to Figure 71, in S55', a first separation sub-part 611' is formed in the first sub-slit 602', a third separation sub-part 613' is formed in the second sub-slit 603', and a second separation structure 62' is formed in the second slit 604'.

[0301] The first separation sub-part 611', the third separation sub-part 613', and the second separation sub-part 612' constitute at least a portion of the first separation structure 61'.

[0302] In some examples, the manufacturing method may further include the following, as shown in Figure 77:

[0303] Referring to Figure 71, S7', a plurality of second stopping sections 70' are formed on the side of the separation layer 30' away from the step structure 13'. The plurality of second stopping sections 70 are arranged in a first direction X and are positioned on multiple steps 141' of the other step structures 14' among the plurality of step structures 14' other than the step structure 14' where the first stopping section 20' is located. Each second stopping section 70' is positioned on one step 141'.

[0304] In some examples, the manufacturing method may further include the following, as shown in Figure 78:

[0305] Referring to Figure 79, S56' forms a third slit 605' extending in the first direction X. The third slit 605' extends through the second stop portion 70' and the initial laminated structure 101'. Each third slit 605' includes a plurality of third sub-slits 606' spaced apart from each other in the first direction X.

[0306] For example, the third slit 605' may be formed simultaneously with the first slit 601', or the third slit 605' may be formed simultaneously with the first sub-slit 602', the second sub-slit 603', and the second slit 604'.

[0307] In some examples, the manufacturing method may further include the following, as shown in Figure 78:

[0308] As a result, in the process of replacing the sacrificial layer 110' with the gate layer 11', multiple third slits are used. 605’ Using this method, the material of the second stop section 70' can be replaced with the same material as the gate layer 11'.

[0309] For example, before replacing the sacrificial layer 120' with the gate layer 11' to form the laminated structure 10' in operation S5', a plurality of third slits 605' extending in the first direction X can be formed. After operation S5', it is possible to form a gate line separation structure 80' within the third slits 605'.

[0310] This allows the material of the second stop section 70' to be replaced with the same material as the gate layer 11' in the process of replacing the sacrificial layer 110' with the gate layer 11' by using multiple third slits 505'.

[0311] S6', a plurality of contact posts 50' are formed. The contact posts 50' extend through the protective layer 40', the first stop section 20', and the separation layer 30', and are connected to the gate layer 11' at a step 141' corresponding to the first stop section 20'.

[0312] For example, referring to Figure 80, S6', which forms multiple contact posts 50', includes operations S61' to S63'.

[0313] Referring to S61', Figures 81 and 82, the protective layer 40' is etched up to the first stop portion 20', thereby forming a plurality of contact holes 51'.

[0314] Referring to S62', Figures 83 and 84, the first stop portion 20' exposed by the contact hole 51' is etched, and the isolation layer 30' and dielectric layer 12' below the first stop portion 20' are etched, so that the contact hole 51' can expose the gate layer 11'.

[0315] Referring to Figure 19A, S63', a contact post 50' is formed within the contact hole 51'.

[0316] In some examples, referring to Figures 85 and 86, the three-dimensional memory 200 (or three-dimensional memory 300) may further include peripheral devices 400.

[0317] For illustrative purposes, referring again to Figures 85 and 86, the peripheral device 400 includes a substrate 401 and a peripheral circuit layer 402.

[0318] There are many types of peripheral circuit layers 402 as described above, and they can be selected according to actual needs. The peripheral circuit layer 402 may include, for example, page buffers, decoders (such as row decoders and column decoders), sense amplifiers, drivers (such as word line drivers), or any active or passive components of circuits such as transistors, diodes, resistors, and capacitors.

[0319] The peripheral circuit layer 402 described above may include, for example, a plurality of transistors. Exemplarily, at least some of the plurality of transistors may be formed in the substrate 401 (e.g., below the upper surface of the substrate 401) and / or directly on the substrate 401.

[0320] Furthermore, the peripheral circuit layer 402 described above may also include any other circuits that support high-level logic processing. Exemplaryly, the peripheral circuit layer 402 may include logic circuits such as a processor and a programmable logic unit, as well as / or memory circuits such as static random access memory.

[0321] As shown in Figure 87, some examples of the present disclosure provide a memory system 1000 including a three-dimensional memory 200 (three-dimensional memory 300) and a controller 2000. The controller 2000 is coupled to the three-dimensional memory 200 (three-dimensional memory 300) and controls the three-dimensional memory 300 to store data.

[0322] The memory system 1000 can be integrated into various types of storage devices, such as being contained in the same package (e.g., Universal Flash Storage (UFS)) or an embedded multimedia card (eMMC) package. In other words, the memory system 1000 can be applied to and packaged in different types of electronic products such as mobile phones (e.g., handsets), desktop computers, tablets, notebook computers, servers, automotive devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices that have internal storage.

[0323] In some examples, as shown in Figure 87, the memory system 1000 includes a controller 2000 and a 3D memory 200 (or 3D memory 300), which can be integrated into a memory card.

[0324] Memory cards include any one of the following: PC Card (PCMCIA, International Association of Personal Computer Memory Cards), CompactFlash® (CF) card, SmartMedia (SM) card, Memory Stick, Multimedia Card (MMC), Secure Digital Memory Card (SD), or UFS.

[0325] In some other examples, referring to Figure 88, the memory system 1000 includes a controller 2000 and multiple 3D memories 200 (or 3D memories 300), which are integrated into a solid-state drive (SSD).

[0326] In some examples of the memory system 1000, the controller 2000 is configured to operate in low duty cycle environments such as SD cards, CF cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones.

[0327] In some other examples, the controller 2000 is configured to operate with high-duty-cycle environment SSDs or eMMCs used as data stores for mobile devices such as smartphones, tablets, and notebook computers, as well as enterprise memory arrays.

[0328] In some examples, the controller 2000 may be configured to manage data stored in the 3D memory 200 (or 3D memory 300) and to communicate with external devices (such as a host). In some examples, the controller 2000 may be configured to control the operation of the 3D memory 200 (or 3D memory 300), such as reading, erasing, and programming. In some examples, the controller 2000 may also be configured to manage various functions related to the data stored in or to be stored in the memory 200 (or 3D memory 300), including at least one of bad block management, garbage collection, logical-physical address translation, and wear leveling. In some examples, the controller 2000 may be further configured to process error correction codes with respect to data read from and written to the 3D memory 200 (or 3D memory 300).

[0329] Of course, the controller 2000 may also perform any other appropriate functions, such as formatting the 3D memory 200 (or 3D memory 300). For example, the controller 2000 may communicate with external devices such as a host via at least one of various interface protocols.

[0330] Note that interface protocols include at least one of the following: USB protocol, MMC protocol, Peripheral Interconnect (PCI) protocol, PCI-express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, and Firewire protocol.

[0331] Some examples of this disclosure provide electronic devices. An electronic device may be any one of the following: a mobile phone, a desktop computer, a tablet, a notebook computer, a server, an in-vehicle device, a wearable device such as a smartwatch, a smart bracelet and smart glasses, a mobile power supply, a game console, or a digital multimedia player.

[0332] The electronic device may include the memory system 1000 as described above, and may further include at least one of a central processing unit and a cache.

[0333] The foregoing describes only some implementations of the present disclosure. However, the scope of the present invention is not limited thereto, and any modifications or substitutions that a person skilled in the art could easily conceive of within the scope disclosed herein should be included within the scope of the present disclosure. Accordingly, the scope of the present disclosure should be determined by the claims.

Claims

1. A laminated structure comprising alternating gate layers and dielectric layers, wherein the laminated structure comprises a stepped structure having a plurality of stepped structures arranged in a first direction and having different heights in a second direction, the stepped structure having a plurality of steps, and the first direction being perpendicular to the second direction, A plurality of first stop units arranged in the first direction and positioned on the plurality of steps of at least one of the staircase structures, wherein each of the plurality of first stop units is positioned on a corresponding step of the plurality of steps, A protective layer covering the stepped structure and the first stop section, Each includes a plurality of contact posts, each extending through the protective layer and the first stop portion, and connected to the gate layer in the stage corresponding to the first stop portion, A separation structure extending through the stacked structure in the first direction, wherein the separation structure divides the stacked structure into a plurality of memory blocks, and each memory block further includes a separation structure which includes the stepped structure, The staircase structure on which the first stop unit is located is positioned at a distance from the separation structure, Each memory block further includes a side wall, The separation structure includes a first separation structure and a second separation structure, A three-dimensional memory in which, in the second direction, the first isolation structure is positioned between two adjacent side walls in different memory blocks, the second isolation structure is positioned between two adjacent tiered structures, and in the second direction, the tiered structures in two memory blocks adjacent to the second isolation structure are positioned symmetrically.

2. In the second direction, the memory block comprises a first staircase structure, a second staircase structure, and a third staircase structure, and the first stop unit is arranged on the plurality of steps of the second staircase structure, as described in claim 1.

3. The three-dimensional memory according to claim 1, wherein in the second direction, the memory block comprises a first staircase structure and a second staircase structure, the first staircase structure is spaced apart from the separation structure, and the first stop section is arranged on the plurality of steps of the first staircase structure.

4. The three-dimensional memory according to claim 1, wherein, in the second direction, the height of the plurality of step structures within the memory block gradually decreases along the direction from the first separation structure to the second separation structure.

5. The three-dimensional memory according to claim 1, wherein in the second direction, two staircase structures adjacent to both sides of the second separation structure have the same height.

6. A laminated structure comprising alternating gate layers and dielectric layers, wherein the laminated structure comprises a step structure comprising a plurality of step structures arranged in a first direction and having different heights in a second direction, the step structure comprising a plurality of steps, and the first direction being perpendicular to the second direction, A plurality of first stop units arranged in the first direction and positioned on the plurality of steps of at least one of the staircase structures, wherein each of the plurality of first stop units is positioned on a corresponding step of the plurality of steps, A protective layer covering the stepped structure and the first stop section, Each includes a plurality of contact posts, each extending through the protective layer and the first stop portion, and connected to the gate layer in the stage corresponding to the first stop portion, A separation structure extending through the stacked structure in the first direction, wherein the separation structure divides the stacked structure into a plurality of memory blocks, and each memory block further includes a separation structure which includes the stepped structure, The staircase structure on which the first stop unit is located is positioned at a distance from the separation structure, It further includes a plurality of second stop units arranged in the first direction and positioned on the plurality of steps of other stair structures among the plurality of stair structures other than the stair structure on which the first stop unit is located, The protective layer further covers the second stop portion, and at least a portion of the protective layer is disposed between the second stop portion and the step adjacent to the second stop portion, in a three-dimensional memory.

7. The memory block comprises a plurality of gate line separation structures, each extending through the second stop portion and the stacked structure, and extending in the first direction, and each gate line separation structure comprises a plurality of sub-separation structures arranged at intervals. The three-dimensional memory according to claim 6, wherein the material of the second stop section is the same as the material of the gate layer.

8. The material of the first stop unit comprises silicon nitride, as described in any one of claims 1 to 7.

9. A laminated structure comprising alternating gate layers and dielectric layers, wherein the laminated structure comprises a step structure comprising a plurality of step structures arranged in a first direction and having different heights in a second direction, the step structure comprising a plurality of steps, and the first direction is perpendicular to the second direction, A plurality of first stop units arranged in the first direction and positioned on the plurality of steps of at least one of the staircase structures, wherein each of the plurality of first stop units is positioned on a corresponding step of the plurality of steps, A protective layer covering the stepped structure and the first stop section, Each includes a plurality of contact posts, each extending through the protective layer and the first stop portion, and connected to the gate layer in the stage corresponding to the first stop portion, In the third direction, the thickness of the first stop portion is the same as the thickness of the gate layer of the preceding stage, and the preceding stage is adjacent to the stage corresponding to the first stop portion and is higher than the stage corresponding to the first stop portion. A three-dimensional memory wherein the third direction is perpendicular to the first and second directions.

10. The three-dimensional memory according to claim 6, wherein the first stopping unit includes carbon-doped silicon nitride.

11. The three-dimensional memory according to claim 10, wherein the material of the second stop unit is the same as the material of the first stop unit.

12. The three-dimensional memory according to claim 6, wherein the thickness of the second stop portion is greater than the thickness of the gate layer, and the second stop portion includes an insulating material.

13. The three-dimensional memory according to claim 1, wherein at least a portion of the protective layer is disposed between the first stop unit and the stage adjacent to the first stop unit.

14. The three-dimensional memory according to claim 1, further comprising a separation layer that covers the stepped structure and is disposed between the stepped structure and the first stop unit.

15. A method for manufacturing three-dimensional memory, The method involves forming an initial laminated structure comprising alternating sacrificial layers and dielectric layers, wherein the initial laminated structure comprises a stepped structure having a plurality of stepped structures arranged in a first direction and having different heights in a second direction, the stepped structure having a plurality of steps, and the first direction being perpendicular to the second direction. The present invention provides for the formation of a plurality of first stopping sections on at least one of the plurality of steps of the staircase structure, wherein the plurality of first stopping sections are arranged in the first direction, and each of the plurality of first stopping sections is located on one of the plurality of steps. A protective layer is formed to cover the stepped structure and the first stop portion, wherein at least a portion of the protective layer is positioned between the first stop portion and the step adjacent to the first stop portion. The aforementioned sacrificial layer is replaced with a gate layer to form a laminated structure, This includes forming a plurality of contact posts, each extending through the protective layer and the first stop portion, and electrically connected to the gate layer in the stage corresponding to the first stop portion, Forming the plurality of first stopping parts on at least one of the plurality of steps of the staircase structure is A method comprising etching the uppermost sacrificial layer and dielectric layer of each stage in order to form the plurality of first stop sections.

16. The first slit is formed extending through the initial stacked structure in the first direction, wherein the first slit divides the initial stacked structure into a plurality of initial memory blocks, and each of the initial memory blocks includes the stepped structure. The method according to claim 15, further comprising forming a separation structure within the first slit.

17. Controller and A three-dimensional memory according to any one of claims 1 to 7, comprising: The controller is coupled to the three-dimensional memory and configured to control the three-dimensional memory to store data, thus forming a memory system.

Images