Dispersed plasma source array

Abstract

The substrate processing system includes a processing chamber including a window. A substrate support is disposed within the processing chamber to support a substrate during plasma processing. A first array including E inductive coils disposed adjacent to and outside the processing chamber, where E is an integer greater than 3. A second array includes D RF direct drive circuits, where D is an integer greater than 3, configured to output RF power to the first array to generate a plasma inside the processing chamber.

Description

Technical Field

[0001] Cross - Reference to Related Applications This disclosure is a PCT international application of U.S. Provisional Patent Application No. 63 / 030,644, filed on May 27, 2020. The entire disclosure of the application referenced above is incorporated herein by reference.

[0002] This disclosure relates to a substrate processing system, and more particularly, to a distributed plasma source array for a substrate processing system.

Background Art

[0003] The background description shows an overview of the content of this disclosure. Within the scope described in this background art section, the research by the inventors named at the present time, as well as aspects of the description that cannot be separately regarded as prior art at the time of filing, are not recognized as prior art against this disclosure, whether explicitly or implicitly.

[0004] A substrate processing system performs processing on a substrate such as a semiconductor wafer. Examples of substrate processing include deposition, ashing, etching, cleaning, and / or other processes. The process gas mixture supplied to the processing chamber processes the exposed surface of the substrate. Plasma can be ignited in the processing chamber to facilitate chemical reactions within the processing chamber.

[0005] For example, a substrate processing system can be used to etch the exposed surface of a substrate such as a semiconductor wafer. Dry etching can be performed using plasma generated by an inductively coupled plasma (ICP). One or more induction coils disposed outside the processing chamber (adjacent to the dielectric window) generate a magnetic field. The supplied RF energy ignites the process gas flowing within the processing chamber to generate plasma. In some applications, RF bias power can also be supplied to an electrode in the substrate support. The induction coils generate changing magnetic fields at different locations within the processing chamber, which leads to process non - uniformity.

[0006] When performing other processes using capacitively coupled plasma (CCP), the upper electrode is located inside the processing chamber, and RF power is supplied to the upper electrode. Another electrode is located on the substrate support. Process gases, such as precursor gas and carrier gas, are supplied to the processing chamber. An electric field is generated between the upper and lower electrodes, generating the plasma. In some cases, a conductive showerhead distributes the process gas and acts as the upper electrode. In other cases, the electrode does not act as a showerhead, and the process gas is supplied to the processing chamber in a different manner. The electrodes generate electric fields that vary at different locations within the processing chamber, which leads to process non-uniformity. [Overview of the project]

[0007] The substrate processing system includes a processing chamber with a window. A substrate support is placed inside the processing chamber to support the substrate during plasma processing. A first array includes E induction coils located adjacent to and outside the processing chamber, where E is an integer greater than 3. A second array includes D RF direct drive circuits configured to output RF power to the first array and generate plasma inside the processing chamber, where D is an integer greater than 3.

[0008] In other features, the distance between the top surface of the substrate support and the bottom surface of the window is in the range of 0.4 inches to 6 inches. The distance between the top surface of the substrate support and the bottom surface of the window is in the range of 1 inch to 3 inches. E induction coils have a circular outer shape. E induction coils have a hexagonal outer shape. E induction coils are arranged in a rectangular array. E induction coils are arranged in a hexagonal array. E induction coils have an outer diameter in the range of 1 inch to 6 inches. E induction coils have an outer diameter in the range of 3 inches to 6 inches.

[0009] In other features, the first array further includes F induction coils, at least one of which is different in size and shape from the E induction coils, where F is an integer greater than 2. Each of the E induction coils includes a first induction coil located inside a second induction coil. Each of the E induction coils includes a first induction coil wound around the second induction coil. The window is made of dielectric material. The window includes a frame portion and defines E cavities. The E induction coils in the first array are located in the E cavities of the frame portion.

[0010] In other features, E windows are located in the substrate-facing openings of E cavities. Dielectric windows are located on the substrate-facing side of the frame portion.

[0011] In other features, each of the D RF direct drive circuits includes a clock generator that generates a clock signal at a first frequency. The gate driver receives the clock signal. The bridge circuit includes a first switch having a control terminal, a first terminal, and a second terminal connected to the gate driver; a second switch having a control terminal connected to the gate driver, a second terminal of the first switch, and a first terminal connected to the output node; and a second terminal. A first DC power supply provides a first voltage potential to the first terminal of the first switch. A second DC power supply provides a second voltage potential to the second terminal of the second switch.

[0012] In other features, the first and second voltage potentials have opposite polarities and are approximately equal in magnitude. The second voltage potential is ground.

[0013] In other features, a current sensor senses the current at the output node and generates a current signal. A voltage sensor senses the voltage at the output node and generates a voltage signal. The controller includes a phase offset calculator that calculates the phase offset between the voltage signal and the current signal. A clock regulator adjusts the first frequency based on the phase offset.

[0014] In other features, the clock regulator increases the first frequency when the current leads the voltage and decreases the first frequency when the voltage leads the current. Each of the D RF direct drive circuits includes a first inductor having a first terminal and a second terminal, a second inductor having a first terminal and a second terminal communicating with the first terminal of the first inductor, a first switch having a first terminal, a second terminal and a control terminal, a second switch having a first terminal, a second terminal and a control terminal, and a first capacitor having a first terminal and a second terminal. The first terminal of the first capacitor communicates with the second terminal of the first inductor and the first terminal of the first switch. The second capacitor has a first terminal and a second terminal. The second terminal of the second capacitor communicates with the second terminal of the second inductor and the second terminal of the second switch. The second terminal of the first switch communicates with the first terminal of the second switch, the second end of the first capacitor, and the first end of the second capacitor.

[0015] In other features, the third capacitor includes a first end communicating with the first end of the first capacitor and a second end communicating with at least one first end of the E induction coils. The fourth capacitor includes a first end communicating with the second end of the second capacitor and a second end communicating with at least one second end of the E induction coils.

[0016] In other features, the voltage source has one end connected to the first end of the first inductor and the first end of the second inductor, and a second end connected to the second terminal of the first switch and the first terminal of the second switch. The voltage source supplies a DC voltage.

[0017] In other features, the induction coil surrounds the first array. The controller is configured to control the second array. S sensors are configured to sense S operating parameters corresponding to the second array, where S is an integer greater than 3.

[0018] In other features, the controller is configured to modify the operation of D RF direct drive circuits based on S operating parameters sensed by S sensors, each of which is located within the processing chamber. The processing chamber includes side walls and further comprises one or more induction coils, each containing one or more turns wound around the top of the side walls. The first array is located in a first plane above the window, and the one or more induction coils are located below the first plane.

[0019] In other features, the third array contains F inductive coils embedded within a window, where F is an integer greater than 3. E inductive coils supply RF energy to F inductive coils. The number of E inductive coils in the first array is greater than the number of F inductive coils in the third array. F is greater than E.

[0020] In other features, the third array includes G electrodes embedded in a substrate support, where G is an integer greater than 3. The fourth array includes H RF direct drive circuits configured to output RF power to the first array, where H is an integer greater than 3.

[0021] In other features, the third array includes G electrodes embedded in a substrate support, where G is an integer greater than 3. The fourth array includes H RF direct drive circuits configured to output RF power to the first array, where H is an integer greater than 3.

[0022] The substrate processing system includes a processing chamber with a non-planar outer surface. A substrate support is placed inside the processing chamber to support the substrate during plasma processing. A first array includes E induction coils located outside the processing chamber adjacent to its outer surface, where E is an integer greater than 3. A second array includes D RF direct drive circuits configured to output RF power to the first array and generate plasma inside the processing chamber, where D is an integer greater than 3.

[0023] In other features, the outer surface of the processing chamber is dome-shaped. The E induction coils have a non-planar side cross-sectional shape that matches the outer surface of the processing chamber.

[0024] In other features, each of the D RF direct drive circuits includes a clock generator that generates a clock signal at a first frequency and a gate driver that receives the clock signal. The bridge circuit includes a first switch having a control terminal connected to the gate driver, a first terminal, and a second terminal. The second switch includes a control terminal connected to the gate driver, a first terminal connected to the second terminal of the first switch and an output node, and a second terminal. The first DC power supply supplies a first voltage potential to the first terminal of the first switch. The second DC power supply supplies a second voltage potential to the second terminal of the second switch.

[0025] In other features, the first voltage potential and the second voltage potential have opposite polarities and are approximately equal in magnitude. The second voltage potential is grounded.

[0026] In other features, the current sensor senses the current at the output node and generates a current signal. The voltage sensor senses the voltage at the output node and generates a voltage signal. The controller includes a phase offset calculator that calculates the phase offset between the voltage signal and the current signal, and a clock adjuster that adjusts the first frequency based on the phase offset.

[0027] In other features, the clock regulator increases the first frequency when the current is ahead of the voltage and decreases the first frequency when the voltage is ahead of the current. Each of the D RF direct drive circuits includes a first inductor including a first end and a second end, a second inductor including a first end and a second end communicating with the first end of the first inductor, a first switch including a first terminal, a second terminal, and a control terminal, a second switch including a first terminal, a second terminal, and a control terminal, and a first capacitor including a first end and a second end. The first end of the first capacitor communicates with the second end of the first inductor and the first terminal of the first switch. The second capacitor includes a first end and a second end. The second end of the second capacitor communicates with the second end of the second inductor and the second terminal of the second switch. The second terminal of the first switch communicates with the first terminal of the second switch, the second end of the first capacitor, and the first end of the second capacitor.

[0028] In other features, the third capacitor includes a first end communicating with the first end of the first capacitor and a second end communicating with at least one first end of the E inductive coils. The fourth capacitor includes a first end communicating with the second end of the second capacitor and a second end communicating with at least one second end of the E inductive coils.

[0029] In other features, the voltage source has one end connected to the first end of the first inductor and the first end of the second inductor, and a second end connected to the second terminal of the first switch and the first terminal of the second switch. The voltage source supplies a DC voltage.

[0030] In other features, the induction coil surrounds the first array. The controller is configured to control the second array. D sensors are configured to sense D operating parameters corresponding to the second array, where D is an integer greater than 3. The controller is configured to modify the operation of D RF direct drive circuits based on the D operating parameters sensed by each of the D sensors.

[0031] The substrate processing system includes a processing chamber, a substrate support disposed within the processing chamber, a first array comprising E electrodes disposed adjacent to and inside the processing chamber on the substrate support, where E is an integer greater than 3, and a second array comprising D RF direct drive circuits configured to output RF power to the first array, where D is an integer greater than 3.

[0032] In other features, E electrodes have a circular shape. E electrodes have a hexagonal shape. E electrodes are arranged in a rectangular array. E electrodes are arranged in a hexagonal array. E electrodes have an outer diameter ranging from 1 inch to 6 inches. The first array further includes F electrodes, at least one of which is different in size and shape from the E electrodes.

[0033] In other features, each of the D RF direct drive circuits includes a clock generator that generates a clock signal at a first frequency and a gate driver that receives the clock signal. The bridge circuit includes a first switch having a control terminal, a first terminal, and a second terminal connected to the gate driver. The second switch includes a control terminal connected to the gate driver, a second terminal of the first switch, and a first terminal connected to the output node, as well as a second terminal. The first DC power supply provides a first voltage potential to the first terminal of the first switch. The second DC power supply provides a second voltage potential to the second terminal of the second switch.

[0034] In other features, the first and second voltage potentials have opposite polarities and are approximately equal in magnitude. The second voltage potential is ground. A current sensor senses the current at the output node and generates a current signal. A voltage sensor senses the voltage at the output node and generates a voltage signal. The controller includes a phase offset calculator that calculates the phase offset between the voltage signal and the current signal, and a clock adjuster that adjusts the first frequency based on the phase offset.

[0035] In other features, the clock regulator increases the first frequency when the current leads the voltage and decreases the first frequency when the voltage leads the current. Each of the D RF direct drive circuits includes a first inductor having a first terminal and a second terminal, a second inductor having a first terminal and a second terminal communicating with the first terminal of the first inductor, a first switch having a first terminal, a second terminal and a control terminal, a second switch having a first terminal, a second terminal and a control terminal, and a first capacitor having a first terminal and a second terminal. The first terminal of the first capacitor communicates with the second terminal of the first inductor and the first terminal of the first switch. The second capacitor has a first terminal and a second terminal. The second terminal of the second capacitor communicates with the second terminal of the second inductor and the second terminal of the second switch. The second terminal of the first switch communicates with the first terminal of the second switch, the second end of the first capacitor, and the first end of the second capacitor.

[0036] In other features, the third capacitor includes a first end communicating with the first end of the first capacitor and a second end communicating with at least one first end of the E electrodes. The fourth capacitor includes a first end communicating with the second end of the second capacitor and a second end communicating with at least one second end of the E electrodes.

[0037] In other features, the voltage source has one end connected to the first end of the first inductor and the first end of the second inductor, and a second end connected to the second terminal of the first switch and the first terminal of the second switch. The voltage source supplies a DC voltage.

[0038] In other features, the controller is configured to control the second array. D sensors are configured to sense D operating parameters corresponding to the second array. The controller is configured to modify the operation of D RF direct drive circuits based on the D operating parameters sensed by each of the D sensors.

[0039] The substrate processing system includes a processing chamber and a substrate support placed within the processing chamber to support the substrate during plasma processing. The upper electrodes are positioned on the substrate support. The first array includes E electrodes positioned on the substrate support, where E is an integer greater than 3. The second array includes D RF direct drive circuits configured to output RF power to the first array, where D is an integer greater than 3.

[0040] In other features, the substrate support includes a base plate and a layer disposed on the base plate and configured to support the substrate. A first array is embedded in the layer. The layer further includes a plurality of electrostatic electrodes. The layer further includes a plurality of heaters. The upper electrodes are connected to a reference potential.

[0041] In other features, the substrate processing system includes an RF source and a matching network. The RF source supplies RF power to the upper electrode via the matching network. The upper electrode includes a showerhead. The upper electrode includes a third array containing P electrodes, where P is an integer greater than 3. A fourth array includes Q RF direct drive circuits configured to supply RF power to the third array containing P electrodes, where Q is an integer greater than 3.

[0042] The substrate processing system includes a processing chamber containing a dielectric window assembly. A substrate support is placed inside the processing chamber to support the substrate. E induction coils are embedded in the dielectric window assembly, where E is an integer greater than 3. D RF direct drive circuits are configured to output RF power to the E induction coils, generating plasma inside the processing chamber, where D is an integer greater than 3.

[0043] In other features, the dielectric window assembly includes a first dielectric window having a first thickness and located on the vacuum side of the processing chamber. A second dielectric window having a second thickness is located on the atmospheric side of the processing chamber. E induction coils are positioned between the first and second dielectric windows. The first thickness is smaller than the second thickness. The first thickness ranges from 1 / 16 inch to 3 / 4 inch, and the second thickness ranges from 1 / 2 inch to 3 inches. Conductors pass through the second dielectric window and directly connect D RF direct drive circuits to the E induction coils.

[0044] In other features, G inductor coils are located on the atmospheric side, and G is an integer greater than zero. The G inductor coils are directly connected to D RF direct drive circuits, and the G inductor coils indirectly supply RF power from the D RF direct drive circuits to E inductor coils through a second dielectric window.

[0045] Each of the D RF direct drive circuits includes a clock generator that generates a clock signal at a first frequency and a gate driver that receives the clock signal. The bridge circuit includes a first switch having a control terminal, a first terminal, and a second terminal connected to the gate driver. The second switch includes a control terminal connected to the gate driver, a second terminal of the first switch, and a first terminal connected to the output node, as well as a second terminal. The first DC power supply provides a first voltage potential to the first terminal of the first switch. The second DC power supply provides a second voltage potential to the second terminal of the second switch.

[0046] In other features, the first and second voltage potentials have opposite polarities and are approximately equal in magnitude. The second voltage potential is ground.

[0047] Other features include a current sensor that senses the current at the output node and generates a current signal, and a voltage sensor that senses the voltage at the output node and generates a voltage signal. The controller includes a phase offset calculator that calculates the phase offset between the voltage signal and the current signal, and a clock adjuster that adjusts a first frequency based on the phase offset.

[0048] In other features, the clock regulator increases the first frequency when the current leads the voltage and decreases the first frequency when the voltage leads the current. Each of the D RF direct drive circuits includes a first inductor having a first terminal and a second terminal, a second inductor having a first terminal and a second terminal communicating with the first terminal of the first inductor, a first switch having a first terminal, a second terminal and a control terminal, a second switch having a first terminal, a second terminal and a control terminal, and a first capacitor having a first terminal and a second terminal. The first terminal of the first capacitor communicates with the second terminal of the first inductor and the first terminal of the first switch. The second capacitor has a first terminal and a second terminal. The second terminal of the second capacitor communicates with the second terminal of the second inductor and the second terminal of the second switch. The second terminal of the first switch communicates with the first terminal of the second switch, the second end of the first capacitor, and the first end of the second capacitor.

[0049] In other features, the third capacitor includes a first end communicating with the first end of the first capacitor and a second end communicating with at least one first end of the E induction coils. The fourth capacitor includes a first end communicating with the second end of the second capacitor and a second end communicating with at least one second end of the E induction coils. The voltage source has one end connected to the first end of the first inductor and the first end of the second inductor, and a second end connected to the second terminal of the first switch and the first terminal of the second switch.

[0050] Other areas to which this disclosure may apply will become apparent from the detailed description, claims, and drawings. The detailed description and specific examples are for illustrative purposes only and are not intended to limit the scope of this disclosure. [Brief explanation of the drawing]

[0051] This disclosure will be better understood from the detailed description and accompanying drawings.

[0052] [Figure 1A] Figure 1A is a functional block diagram of an example of a capacitively coupled plasma (CCP) substrate processing system according to this disclosure.

[0053] [Figure 1B] Figure 1B shows an example of an RF electrode array according to this disclosure. [Figure 1C] Figure 1C shows an example of an RF electrode array according to this disclosure. [Figure 1D] Figure 1D shows an example of an RF electrode array according to this disclosure.

[0054] [Figure 2A] Figure 2A is a functional block diagram of an example of an inductively coupled plasma (ICP) substrate processing system according to this disclosure.

[0055] [Figure 2B]Figure 2B shows an example of a coil that can be used in an RF coil array according to this disclosure. [Figure 2C] Figure 2C shows an example of a coil that can be used in an RF coil array according to this disclosure. [Figure 2D] Figure 2D shows an example of a coil that can be used in an RF coil array according to this disclosure. [Figure 2E] Figure 2E shows an example of a coil that can be used in an RF coil array according to this disclosure. [Figure 2F] Figure 2F shows an example of a coil that can be used in an RF coil array according to this disclosure. [Figure 2G] Figure 2G shows an example of a coil that can be used in an RF coil array according to this disclosure. [Figure 2H] Figure 2H shows an example of a coil that can be used in an RF coil array according to this disclosure. [Figure 2I] Figure 2I shows an example of a coil that can be used in an RF coil array according to this disclosure.

[0056] [Figure 3A] Figure 3A shows an example of an RF coil array according to this disclosure. [Figure 3B] Figure 3B shows an example of an RF coil array according to this disclosure. [Figure 3C] Figure 3C shows an example of an RF coil array according to this disclosure. [Figure 3D] Figure 3D shows an example of an RF coil array according to this disclosure. [Figure 3E] Figure 3E shows an example of an RF coil array according to this disclosure. [Figure 3F] Figure 3F shows an example of an RF coil array according to this disclosure.

[0057] [Figure 4A]Figure 4A shows an exemplary layout of RF coils arranged around a non-planar processing chamber according to the present disclosure.

[0058] [Figure 4B] Figure 4B shows an example of a non-planar induction coil according to the present disclosure. [Figure 4C] Figure 4C shows an example of a non-planar induction coil according to the present disclosure.

[0059] [Figure 5A] Figure 5A shows an example of an array of RF coils arranged in a recess in a window according to this disclosure.

[0060] [Figure 5B] Figure 5B is a cross-sectional view of an example of a window and RF coil array according to this disclosure. [Figure 5C] Figure 5C is a cross-sectional view of an example of a window and RF coil array according to the present disclosure. [Figure 5D] Figure 5D is a cross-sectional view of an example of a window and RF coil array according to this disclosure.

[0061] [Figure 6A] Figure 6A is a plan view showing an array of RF coils surrounded by one or more outer coils according to the present disclosure. [Figure 6B] Figure 6B is a plan view showing an array of RF coils surrounded by one or more outer coils according to the present disclosure.

[0062] [Figure 7] Figure 7 is a functional block diagram of an example of a control system for an array of RF direct drive circuits and an array of RF coils or electrodes according to the present disclosure.

[0063] [Figure 8] Figure 8 shows an example of a direct drive circuit used in a substrate processing system according to this disclosure.

[0064] [Figure 9] Figure 9 shows another example of a direct drive circuit used in a substrate processing system according to this disclosure.

[0065] [Figure 10A] Figure 10A is a perspective view of an example of a coil system, including an array of coils positioned adjacent to a window and other coils wound around the processing chamber.

[0066] [Figure 10B] Figure 10B is a side cross-sectional view of the coil system shown in Figure 10A.

[0067] [Figure 10C] Figure 10C is a side cross-sectional view of another example of the coil system shown in Figure 10A.

[0068] [Figure 11A] Figure 11A is a plan view showing an example of a coil system according to the present disclosure, which includes a first array of coils embedded in a window.

[0069] [Figure 11B] Figure 11B is a side cross-sectional view of the coil system shown in Figure 11A.

[0070] [Figure 11C] Figure 11C is a plan view showing a coil system according to the present disclosure, which includes a first array of coils positioned adjacent to a window that supplies RF power to a second array of coils embedded in the window.

[0071] [Figure 11D] Figure 11D is a side cross-sectional view of the coil system shown in Figure 11C.

[0072] [Figure 12A] Figure 12A is a functional block diagram of an example of an electrode array arranged on a substrate support according to this disclosure.

[0073] [Figure 12B] Figure 12B is a functional block diagram of another example of an array of electrodes driven by an RF direct drive circuit and embedded in a substrate support, according to the present disclosure.

[0074] [Figure 12C] Figure 12C is a plan view of an example of a substrate support having embedded electrodes according to the present disclosure.

[0075] [Figure 12D] Figure 12D is a functional block diagram of another example of a first array of electrodes embedded in a substrate support and a second array of electrodes placed on top of the substrate support, according to the present disclosure.

[0076] [Figure 13A] Figure 13A is a functional block diagram of a processing chamber according to the present disclosure, which includes a substrate support containing an array of coils arranged adjacent to a window and driven by an RF direct drive circuit, and an array of RF electrodes driven by an RF direct drive circuit.

[0077] [Figure 13B] Figure 13B is a functional block diagram of a processing chamber according to the present disclosure, which includes a substrate support containing a coil positioned adjacent to a window and driven by an RF source and a matching network, and an array of RF electrodes driven by an RF direct drive circuit.

[0078] In these drawings, reference numbers may be reused to refer to similar and / or identical elements. [Modes for carrying out the invention]

[0079] Plasma processing systems typically include an RF generator that supplies RF power to loads, such as RF electrodes for capacitively coupled plasma (CCP) applications and / or one or more RF induction coils for inductively coupled plasma (ICP) applications. An RF generator typically includes an RF source, a matching network, and connecting conductors such as coaxial cables. Due to the high power and high frequency used, RF generators typically employ relatively large and expensive separate inductive and capacitive components. Consequently, packaging the RF generator near loads such as electrodes and / or induction coils is challenging, especially when multiple loads need to be driven.

[0080] A matching network matches the output impedance of the RF source to the impedance of the load. RF sources can provide RF power in the range of 1 to 10 kW (or 1 to 5 kW) at frequencies in the range of 20 kHz to 3 GHz, although other power output levels and / or frequencies can also be used.

[0081] Given the large size and high cost of RF generators, typically only one or a few RF generators are used in commercial substrate processing systems. In some cases, controlling process uniformity can be improved by dividing the system input into individually monitored zones and controllers. This approach drives each RF generator (and corresponding induction coils and / or electrodes) individually, allowing for fine-tuning of the plasma in the processing chamber. However, the increased cost and package size of conventional RF generators, matching networks, and transmission lines have prevented this approach from being commercially viable.

[0082] While larger gaps can be used between the top surface of the substrate and the bottom surface of the electrodes in CCP applications (or the bottom surface of the dielectric window (and induction coil) in ICP applications), controlling plasma characteristics is particularly important in challenging applications where the gap is relatively small (e.g., 0.4 inches (10.16 mm) or larger, up to 6 inches (152.4 mm), 5 inches (127 mm), 4 inches (101.6 mm), 3 inches (76.2 mm), or 2 inches (50.8 mm) or smaller).

[0083] The systems and methods described herein use an array of RF direct drive circuits to supply power to an array of induction coils (e.g., in ICP applications) or an array of electrodes (e.g., in CCP applications). The RF direct drive circuit designs described herein can significantly reduce the overall size and cost of RF generators and allow them to be placed closer to the load. In some examples, the RF direct drive circuit includes two or more switches that are driven alternately with a duty cycle of about 50%. In some examples, the RF direct drive circuits described herein generally have low output impedance (typically less than 10 ohms, e.g., about 1 ohm). The RF direct drive circuits described herein generally do not require individual components or a matching network with high-impedance coaxial transmission lines. The RF direct drive circuits can be packaged using integrated circuits and printed circuit boards, thereby reducing overall cost and package size. As a result, plasma control can be improved.

[0084] Referring to Figure 1A, an example of a plasma processing chamber for processing a substrate using capacitively coupled plasma is shown. A specific type of plasma processing chamber is shown for illustrative purposes, but other types of plasma processing chambers can also be used. In Figure 1A, the substrate processing system 110 can be used to perform etching, deposition, or other substrate processing using capacitively coupled plasma (CCP).

[0085] The substrate processing system 110 includes a processing chamber 122 that surrounds other components of the substrate processing system 110 and houses RF plasma. The substrate processing system 110 includes an array 124 of RF electrodes and a substrate support 126 such as an electrostatic chuck (ESC). During operation, the substrate 128 is disposed on the substrate support 126. The array 124 of RF electrodes includes a plurality of RF electrodes.

[0086] The substrate support 126 includes a base plate 130 that acts as a lower electrode. An upper layer 132 is disposed on the base plate 130 and is configured to support the substrate during processing. In some examples, the upper layer 132 may further include a heater that can be disposed in two or more zones, an electrostatic electrode that clamps the substrate, and / or a backside gas channel disposed on the upper surface of the upper layer 132. A bonding and / or thermal resistance layer 134 may be disposed between the upper layer 132 and the base plate 130. The base plate 130 may include one or more channels 136 for flowing a coolant through the base plate 130.

[0087] An array 140 of RF direct drive generators generates a plurality of RF voltages and outputs them to the array 124 of RF electrodes. The base plate 130 can be DC grounded, AC grounded, or floating. In some examples, the array 124 of RF electrodes includes A electrodes, the array 140 of RF direct drive generators includes B RF direct drive generators, and A and B are integers greater than 1. In some examples, B is less than or equal to A and B is greater than 1. In some examples, A is less than or equal to B and A is greater than 1. In some examples, A = B and there is a one-to-one correspondence between the RF direct drive circuit and the RF electrodes. In other examples, B < A and a single direct drive circuit drives two or more electrodes. For example, the electrodes can be disposed in Z zones, where Z is an integer greater than 2, and each RF direct drive circuit drives some or all of the electrodes in a given zone. Each of the Z zones includes one or more electrodes.

[0088] A gas supply system 150 supplies gas mixtures, including process gases, carrier gases, etching gases, precursor gases, inert gases, and mixtures thereof, to the processing chamber. The gas supply system 150 includes one or more gas sources 152-1, 152-2, ..., and 152-N (collectively referred to as gas source 152), where N is an integer greater than zero. The gas sources 152 are connected to a manifold 160 by valves 154-1, 154-2, ..., and 154-N (collectively referred to as valve 154) and MFCs 156-1, 156-2, ..., and 156-N (collectively referred to as MFC 156). Secondary valves may be used between the MFCs 156 and the manifold 160. Although a single gas supply system 150 is shown, two or more gas supply systems may also be used.

[0089] The temperature controller 163 may be connected to a plurality of thermal control elements (TCEs) 164 located on the upper layer 132. The temperature controller 163 can be used to control the plurality of TCEs 164 to control the temperatures of the substrate support 126 and the substrate 128. The temperature controller 163 can communicate with the coolant assembly 166 to control the flow of coolant through the channel 136. For example, the coolant assembly 166 may include a coolant pump, a reservoir, and / or one or more temperature sensors (see, e.g., 168). The temperature controller 163 operates the coolant assembly 166 to selectively flow coolant through the channel 136 to cool the substrate support 126.

[0090] The reactant can be discharged from the processing chamber 122 using the valve 170 and the pump 172. The components of the substrate processing system 110 can be controlled using the system controller 182, as will be further described below.

[0091] Referring here to Figures 1B and 1C, an example of an RF electrode array 124 is shown. The RF electrodes in the RF electrode array 124 can have any suitable shape and can be arranged in an array having different configurations (Cartesian, hexagonal, circular, rectangular, etc.). In Figure 1B, the RF electrode array 124 is arranged in a rectangular array. The RF electrode array 124 includes electrodes 180-1, 180-2, ..., and 180-T, where T is an integer greater than or equal to 2 (collectively referred to as RF electrodes 180). In some examples, the electrodes are rectangular, elliptical, or polygonal in shape, but other regular and / or irregular shapes can also be used. The RF electrode array 124 in Figure 1B contains nine electrodes, but the array can also contain fewer electrodes (e.g., four) or more electrodes (e.g., sixteen, twenty-five).

[0092] In Figure 1C, the RF electrode array 124 is arranged in a hexagonal array. The RF electrode array 124 includes electrodes 184-1, 184-2, ..., and 184-T, where T is an integer (collectively referred to as electrode 184). In some examples, electrode 184 is hexagonal in shape. While the RF electrode array 124 contains seven electrodes in Figure 1B, the array can also contain fewer (e.g., three) or more electrodes (e.g., seventeen).

[0093] Referring here to Figure 1D, the RF electrode array 124 may further include one or more electrodes 194 having different sizes, shapes, materials, and / or thicknesses. In other examples, the gap distance between the bottom surface of the electrode and the top surface of the substrate or substrate support varies. For example, electrode 194 in Figure 1D has a smaller outer diameter compared to RF electrode 180. Electrode 194 allows for further tuning of the plasma. Electrodes 180, 194 may be driven individually by an RF direct drive circuit and / or driven as a group by an RF direct drive circuit.

[0094] Referring here to Figure 2A, another example of the substrate processing system 210 according to the present disclosure is shown. The substrate processing system 210 performs etching using inductively coupled plasma. The substrate processing system 210 includes an array 214 of RF direct drive circuits and an array 216 of induction coils.

[0095] In some examples, a window 224 is positioned along one side of the processing chamber 228. In some examples, the window 224 may be made of a dielectric material that is substantially transparent to the magnetic field generated by the induction coils at the target frequency. An array of induction coils 216 is positioned adjacent to the window 224. The processing chamber 228 further comprises a substrate support (or base) 232. The substrate support 232 may include an electrostatic chuck (ESC), a mechanical chuck, or other types of chucks. A process gas is supplied to the processing chamber 228 and a plasma 240 is generated inside the processing chamber 228. The plasma 240 etches the exposed surface of the substrate 234.

[0096] A gas supply system 256 supplies the process gas mixture to the processing chamber 228. The gas supply system 256 may include a process and inert gas source 257, a gas metering system 258 including valves and a mass flow controller, and a manifold 259. A heater / cooler 264 can be used to heat / cool the substrate support 232 to a predetermined temperature. An exhaust system 265 includes valves 266 and a pump 267 for removing the reactant from the processing chamber 228 by purging or exhaust. A controller 254 can be used to control the etching process. The controller 254 monitors system parameters and controls the supply of the gas mixture, plasma striking, maintenance, and extinction, reactant removal, cooling gas supply, etc.

[0097] Referring here to Figures 2B to 2I, various examples of induction coils that can be used in an array of coils are shown. In some examples, the induction coils in the array have an outer diameter ranging from 1 to 7 inches. In other examples, the induction coils have an outer diameter ranging from 3 to 6 inches. In some examples, the induction coils in the array have a number of turns ranging from 2 to 10. In other examples, the induction coils in the array have a number of turns ranging from 2 to 5. In some examples, the induction coils are formed by traces deposited on a PCB. In other examples, the induction coils include air coil inductors mounted on a printed circuit board (PCB).

[0098] In Figures 2B to 2F, the induction coil has an elliptical / circular outer shape and includes a variable number of turns and a variable gap distance between turns. In Figure 2B, the induction coil has an outer diameter ranging from 3 inches to 6 inches (e.g., 4 inches), two turns, and a gap distance of 0.8 inches (20.32 mm). The induction coil has a uniformity of 69%.

[0099] In Figure 2C, the induction coil has an outer diameter ranging from 4.5 inches (114.3 mm) to 6.5 inches (165.1 mm) (e.g., 5.75 inches (146.05 mm)), 1.5 turns, and a gap distance of 0.5 inches. The induction coil has a uniformity of 38%. In Figure 2D, the induction coil has an outer diameter ranging from 3 inches to 6 inches (e.g., 5.75 inches) and 2 turns. In Figure 2E, the induction coil has an outer diameter ranging from 3 inches to 6 inches (e.g., 5.25 inches (133.35 mm)), 3 turns, and a gap distance of 1.75 inches (44.45 mm). The induction coil has a uniformity of 8.8%. In Figure 2F, the induction coil has an outer diameter ranging from 3 inches to 6 inches (e.g., 5.75 inches), 4 turns, and a gap distance of 1.0 inch. The induction coil has a uniformity of 9.7%.

[0100] In Figures 2G to 2I, the induction coil has a hexagonal shape and contains a variable number of turns. In Figure 2G, the induction coil has an outer diameter ranging from 3 to 6 inches (e.g., 5.25 inches), 4 turns, and a gap distance of 1.175 inches (29.845 mm). The induction coil has a uniformity of 7.6%. In Figure 2H, the induction coil has an outer diameter ranging from 3 to 6 inches (e.g., 5.25 inches), 4 turns, and a gap distance of 2.5 inches. The induction coil has a uniformity of 6.9%. As can be understood, uniformity can be influenced by chamber pressure, number of turns, coil shape, and / or gap distance.

[0101] Referring here to Figures 3A to 3F, additional examples of the induction coil array 216 are shown. The individual coils in the induction coil array 216 can have any suitable shape, and the induction coils can be arranged in different array patterns. In Figure 3A, the induction coil array 216 is arranged in a rectangular array. The induction coil array 216 includes coils 310-1, 310-2, ..., and 310-T, where T is an integer greater than or equal to 3 (collectively referred to as induction coils 310). In some examples, the outer edges of the induction coils 310 are rectangular, elliptical, and / or polygonal in shape, but other regular and / or irregular shapes can also be used.

[0102] In the example in Figure 3A, the induction coils have a circular shape and are arranged in a rectangular array. While the induction coil array 216 in Figure 3A contains nine coils, the array can also contain fewer coils (e.g., four) or more coils (e.g., 16, 25, 36). The orientation of the induction coils 310 can be adjusted relative to the position of each coil.

[0103] As seen in Figure 3B, the induction coils 310 can be arranged in a hexagonal array and may have a hexagonal outline. In some examples, the induction coils 310 are clockwise or rotated by 360° / C around the array of coils (where C is the number of coils along the outside of the array) (for example, C=6 in Figure 3B). The array of induction coils 216 in Figure 3B includes induction coils 314-1, 314-2, ..., and 314-T, where T is an integer (collectively referred to as induction coils 314). The array of RF coils 329 in Figure 3B includes 7 coils, but the array may also include a further number of coils (e.g., 17) as shown in Figure 3C.

[0104] In Figure 3C, the induction coil 314 can be associated with different zones. For example, three zones Z1, Z2, and Z3 are shown, but more or fewer zones can also be used. Each of zones Z1, Z2, and Z3 is associated with one or more RF direct drive circuits. For example, zone Z1 includes one induction coil driven by one RF direct drive circuit. In some examples, zone Z2 includes six coils driven by one to six RF direct drive circuits, and zone Z3 includes twelve coils driven by one to twelve RF direct drive circuits.

[0105] Referring here to Figure 3D, the induction coil array 216 may further include one or more induction coils 320 having different sizes, coil thicknesses, number of turns, and / or shapes. For example, the induction coil 320 in Figure 3D has a smaller outer diameter and more turns compared to the induction coil 310. The induction coil 320 is located in a place where it is not large enough to fit into another induction coil 310. The induction coil 320 allows for further tuning of the plasma. The induction coils 320 may be driven individually by one or more RF direct drive circuits and / or driven in a group by one or more RF direct drive circuits.

[0106] Referring here to Figures 3E and 3F, each inductor coil in the inductor coil array 216 may contain one or more coils. For example in Figure 3E, the inductor coil array 216 is nested and contains two or more coils 340, including an outer coil 342 and an inner coil 346. The outer coil 342 and the inner coil 346 can be driven by the same RF direct drive circuit, one or more RF direct drive circuits, or different RF direct drive circuits. In some examples, the outer coil 342 and the inner coil 346 are driven with current flowing in the same direction, current flowing in different directions, or current flowing alternately between the same and different directions, depending on one or more sensed operating parameters. In some examples, an additional switch is used to switch the direction of the current.

[0107] For example, in Figure 3F, the induction coil array 216 includes two or more coils 350, including induction coils 352 and 354 that are wound around each other. In other words, the turns of induction coils 352 and 354 are wound between each other. Induction coils 352 and 354 can be driven by the same RF direct drive circuit or different RF direct drive circuits. In some examples, the outer induction coil 352 and the inner induction coil 354 are driven by currents flowing in the same direction, currents flowing in different directions, or currents flowing alternately between the same and different directions, depending on one or more sensed operating parameters.

[0108] Referring here to Figures 4A to 4C, another substrate processing system 400 includes a processing chamber 410. In the previously mentioned example, the processing chamber has a rectangular side cross-section, and the coil array is generally positioned along the top surface of the processing chamber in a plane parallel to the substrate during processing. However, the processing chamber 410 in Figure 4A includes a non-planar outer surface 412. In some examples, the chamber is made of a material that is substantially transparent (e.g., has low attenuation) to the magnetic field generated by the induction coil at the operating frequency. In some examples, the non-planar outer surface of the processing chamber 410 is dome-shaped, but other types of surfaces such as cylindrical, conical, or other non-planar surfaces may be used.

[0109] A substrate support 414 is placed in the processing chamber 410 to support the substrate 418 during processing. A gas supply system 430 supplies process gas, etching gas, carrier gas, inert gas, precursor gas, and / or other gases to the processing chamber 410. In some examples, the gas supply system 430 uses a gas injector 432 to deliver the gas mixture to the processing chamber 410.

[0110] The RF direct drive circuit array 440 outputs RF power to an array 442 of induction coils arranged around the outer surface of the non-planar outer surface 412. The process can be controlled using the controller 450. The controller 450 communicates with the gas supply system 430 to determine gas selection, timing, and gas flow. The controller 450 communicates with the RF direct drive circuit array 440 to control RF power, timing, and switch switching. The controller 450 communicates with the temperature controller 452, temperature sensor 453, and coolant assembly 464 to control the substrate temperature. The controller 450 communicates with the valve 462 and pump 454 to control chamber pressure or vacuum and / or control the discharge of reactants from the processing chamber 410.

[0111] In Figures 4B and 4C, the induction coils 444 in the induction coil array 442 may have a shape that matches the non-planar outer surface 412 of the processing chamber 410. For example, the induction coils 444 may have an arc-shaped side cross section in one or two directions, as shown in Figure 4C, allowing the coils to follow the surface of the processing chamber 410 to provide uniform spacing and / or reduce plasma non-uniformity.

[0112] Referring to Figures 5A to 5D, each induction coil generates approximately 1 / G of the total power, and the magnetic field strength is attenuated by the window. Therefore, the magnetic field in the processing chamber can be increased by reducing the thickness of the dielectric window between the array of induction coils and the processing chamber. In Figure 5A, induction coils 314-1, 314-2, ..., and 314-G of the induction coil array 216 can be located in cavities 514-1, 514-2, ..., and 514-G (collectively referred to as cavity 514) formed in the dielectric window 510. In Figure 5B, the dielectric window 510 has a thickness T in the area not containing the cavity and a thickness t in the area containing the cavity. <Tである。

[0113] In Figure 5C, the dielectric window 510 includes a frame portion 570 and dielectric windows 574-1, 574-2, ..., and 574-G (only 574-3, 574-4, and 574-5 are shown) (collectively referred to as dielectric windows 574). In this example, the frame portion 570 can be made of a dielectric material or another suitable material. In some examples, the coefficients of thermal expansion (CTE) of the materials used for the frame portion 570 and the dielectric windows 574 are the same or within 5%, 4%, 3%, 2%, or 1% of each other.

[0114] In Figure 5D, the dielectric window 510 includes a frame portion 580 and a dielectric window 584 mounted on the bottom surface of the frame portion 580. In this example, the frame portion 580 can be made of dielectric material or another suitable material. In some examples, the frame portion 580 may be made of aluminum, anodized aluminum, and / or dielectric material of a lower grade or purity compared to the dielectric window 584. In some examples, the coefficients of thermal expansion (CTE) of the materials used for the frame portion 580 and the dielectric window 584 are the same or within 5%, 4%, 3%, 2%, or 1% of each other. Now referring to Figures 6A and 6B, one or more additional induction coils 614 are arranged around the array of coils 618. In Figure 6A, one or more induction coils 614 include a single circular coil 620 surrounding the array of coils 618. In Figure 6B, one or more inductive coils 614 are wound around each other and include two circular coils 620, 624 surrounding an array of coils 618. Referring now to Figure 7, a drive circuit 710 for driving a load such as an RF coil or RF electrode is shown. A voltage source 714 provides voltage to the array of direct drive circuits 718-1, 718-2, ..., and 718-D (collectively referred to as direct drive circuits 718), where D is an integer greater than 2. Alternatively, each of the RF direct drive circuits may include a separate voltage source, and / or two or more RF direct drive circuits may share a single voltage source. The array of direct drive circuits 718-1, 718-2, ..., and 718-D drives loads 732-1, 732-2, ..., and 732-E, respectively (where E is an integer greater than 2). A one-to-one correspondence is shown between D and E, but D can be greater than or less than E. In other words, the outputs of multiple RF direct drive circuits can be connected in parallel to drive a single electrode or a group of electrodes, such as those located in the same zone.

[0115] The controller 722 generates drive signals for the control terminals or gates of the switches in the direct drive circuit 718. In some examples, one or more sensors 724-1, 724-2, ..., and 724-S (where S is an integer greater than zero) (collectively referred to as sensors 724) sense operating parameters. In some examples, S is equal to D and / or S is equal to E. In other examples, S is not equal to D and / or S is not equal to E. Sensors 724 sense operating parameters such as voltage, current, phase offset, or other measurable or estimated operating parameters that indicate plasma conditions specific to one of the RF direct drive circuits and / or general plasma conditions.

[0116] Referring here to Figure 8, an example of an RF direct drive circuit 800 for supplying RF plasma power is shown. The RF direct drive circuit 800 includes a clock 820 operating at one or more selected RF frequencies. The clock signal output by the clock 820 is input to a gate driver circuit 822. In some examples, the gate driver circuit 822 includes an amplifier 844 and an inverting amplifier 846, each having an input connected to the clock 820.

[0117] The output of the gate driver circuit 822 is input to the bridge circuit 838. In some examples, the bridge circuit 838 is a half-bridge, but a full-bridge can also be used. In some examples, the bridge is balanced, but an unbalanced bridge can also be used. In some examples, the bridge circuit 838 includes a first switch 840 and a second switch 842. In some examples, the first switch 840 and the second switch 842 include metal oxide semiconductor field-effect transistors (MOSFETs). The first switch 840 and the second switch 842 each include a control terminal and first and second terminals. The output of the amplifier 844 of the gate driver circuit 822 is input to the control terminal of the first switch 840. The output of the inverting amplifier 846 of the gate driver circuit 822 is input to the control terminal of the second switch 842.

[0118] Output node 830 is connected to the second terminal of the first switch 840 and the first terminal of the second switch 842. The first terminal of the first switch 840 is connected to the first DC power supply 870. The second terminal of the second switch 842 is connected to a reference potential such as earth.

[0119] The output node 830 is connected to the cathode 834 by an inductor 832. In some examples, a resistor R p and capacitance C in series p Using this, the impedances observed by the RF direct drive circuit 800 (e.g., plasma capacitance and resistance, capacitance and resistance of electrodes (or other components) in the substrate support, and / or other stray or parasitic capacitance and resistance) can be modeled.

[0120] In some examples, instead of using the first DC power supply 870 and ground, the RF direct drive circuit uses +V, respectively. DC / 2 and -V DC This may include first and second DC power supplies operating at half the voltage of a single DC power supply, as shown in Figure 8. To achieve the same output RF power, both the first and second DC power supplies operate at half the voltage of a single DC power supply. In some examples, the first and second DC power supplies operate at approximately the same magnitude and opposite polarity. As used herein, approximately the same means that the difference in the magnitude of the DC voltage output by the first DC power supply 870 compared to the second DC power supply 880 is less than 20%, 5%, or 2%. The first DC power supply is connected to the first terminal of the first switch 840. The second DC power supply is connected to the second terminal of the second switch 842.

[0121] In some examples, current sensor 882 and voltage sensor 884 sense the current and voltage at output node 830. Phase offset calculator 890 receives the sensed current and voltage signals and generates a phase offset signal output to clock frequency regulator 892. Clock frequency regulator 892 generates a clock adjustment signal based on the phase offset signal. In other features, clock frequency regulator 892 increases the frequency of clock 820 when the current leads the voltage and decreases the frequency of clock 820 when the voltage leads the current. Additional details relating to the direct drive circuit described in Figure 8 can be found in U.S. Patent No. 10,515,781, issued December 24, 2019, entitled "Direct Drive RF Circuit for Substrate Processing Systems," assigned to a common assignee, the above application is incorporated herein by reference in its entirety.

[0122] Referring here to Figure 9, another example of an RF direct drive circuit 910 is shown. The RF direct drive circuit 910 includes a voltage source 920 that supplies voltage. In some examples, the voltage source 920 provides a DC voltage, but other types of voltage sources can also be used. In some examples, two or more RF direct drive circuits 910 may be supplied by the voltage source 920. Alternatively, each of the RF direct drive circuits or subgroups of RF direct drive circuits may be connected to a voltage bus.

[0123] Inductor L1 has one terminal connected to the first terminal of the voltage source 920 and another terminal connected to the first terminal of switch S1 and the first terminals of capacitors C1 and C3. Inductor L2 has one terminal connected to the first terminal of the voltage source 920 and another terminal connected to the second terminal of switch S2 and the first terminals of capacitors C2 and C4. The second terminal of switch S1 is connected to the node between the first terminal of the second switch S2, the second terminal of the voltage source 920, and capacitors C1 and C2.

[0124] The controller 722 in Figure 7 outputs the drive signal to the control terminals of switches S1 and S2 in each of the RF direct drive circuits. The second terminals of capacitors C3 and C4 are connected to the load 928. The load 928 may include RF electrodes or induction coils or arrays as described herein.

[0125] In some examples, switches S1 and S2 are implemented as semiconductor devices that act as switches. Each switch may be implemented by two or more switches connected in parallel. In some examples, switches S1 and S2 are implemented as high electron mobility transistors, metal oxide semiconductor field-effect transistors (MOSFETs), bipolar junction transistors (BJTs), silicon carbide (SiC) or gallium nitride (GaN) FETs, insulated gate BJTs (IGBJTs), diodes, silicon-controlled rectifiers, and / or combinations thereof.

[0126] In some examples, switches S1 and S2 are driven with a 180-degree phase shift at a desired operating frequency. In other words, the duty cycle of the switches is generally about 50%. However, the controller 722 can receive feedback from one of the sensors 724 associated with one or more of the RF direct drive circuits. Based on the feedback, the controller 722 can adjust the operation of one or more of the RF direct drive circuits by changing the duty cycle and / or frequency, thereby changing the plasma characteristics associated with the corresponding RF direct drive circuits.

[0127] Further details relating to the direct drive circuit shown in Figure 9 can be found in U.S. Patent Publication No. US2019 / 0007004, published on January 3, 2019, which is incorporated herein by reference. In some examples, inductors L1 and L2 can be air-core inductors or mounted using a PCB with metal traces.

[0128] Referring here to Figures 10A to 10C, an array of coils and an additional coil system including one or more other coils are shown. In Figure 10A, the substrate processing system includes a coil system 1010, which includes an array of coils 1024 positioned adjacent to the dielectric window 1020 in a first plane on the atmospheric side. The coil system 1010 further includes one or more coils 1030 wound (one or more times) around the top of the side wall 1040 of the processing chamber 1050 on the atmospheric side below the first plane, as shown. A single coil 1032 is shown having two turns, but a further number of coils, and / or a further or fewer number of turns per coil, may also be used. In this example, the top of the side wall 1040 is made of dielectric material, which allows the magnetic field generated by one or more coils 1030 to pass through.

[0129] In Figure 10B, the coil array 1024 is driven using an array of RF direct drive circuits described herein. One or more coils 1030 can be driven by an RF source and matching network, or by one or more RF direct drive circuits. In the example of Figure 10C, the window 1070 has a "C"-shaped cross-section having a central portion 1071 and side portions 1072 extending therefrom. The central portion 1071 is cylindrical, and the side portions 1072 extend downward from the radial outer edge of the central portion 1071 toward the side wall 1080 of the processing chamber 1050.

[0130] As will be further explained below, a number of smaller coils can be used to improve plasma uniformity and / or tuning flexibility. For example, 19 smaller coils, each about 1 to 3 inches in diameter, can be used with a thinner dielectric window on the vacuum side. In some examples, the coils are embedded in a dielectric window having a thickness of 1 / 16 inch (1.5875 mm) to 3 / 4 inch (19.05 mm) (e.g., 1 / 4 inch (6.35 mm)) from the vacuum side. Thinner dielectric windows can be joined to thicker dielectric windows with the coils in between. The total thickness of the dielectric windows is selected to withstand atmospheric pressure and / or the risk of implosion. In some examples, the coils are energized by a wire passing through the dielectric window on the atmospheric side.

[0131] In other examples, smaller coils are indirectly powered by another set of coils located on the atmospheric side of the dielectric window. For example, the atmospheric-side coils can be made larger (e.g., 3 to 7 inches (177.8 mm)). Power is wirelessly coupled from the atmospheric-side coils to the embedded coils, supplying RF power to ignite and support the plasma.

[0132] Referring here to Figures 11A and 11B, an additional coil system including an array of coils is shown. In Figure 11A, the coil system 1102 includes a first array 1106 containing P coils 1108 embedded in a dielectric window assembly including a dielectric window 1104. In Figure 11B, the dielectric window 1104 includes a bottom surface defining a plurality of cavities. Another dielectric window 1110 is positioned adjacent to the first array 1106 on the vacuum side. In other examples, cavities can be defined on the dielectric window 1110, or dielectric windows 1104 and 1110 can have a rectangular cross-section, and instead of defining cavities in either dielectric window, spacers can be used between the P coils 1108 of the first array 1106 to reduce costs. The array 1114 of the RF direct drive circuit is directly connected to the P coils 1108 of the first array 1106 by a conductor 1116 passing through the dielectric window 1104. The dielectric window 1110 has a thickness t1, the dielectric window 1104 has a thickness t2, and the coil has a thickness t3. In some examples, t1 is less than t2.

[0133] Referring here to Figures 11C and 11D, the embedded coil array can be powered remotely rather than directly. Figure 11C shows the top of the substrate processing system. The substrate processing system includes a coil system 1120 having a first array 1124 containing a plurality of coils 1128 positioned adjacent to the dielectric window assembly 1122 on the atmospheric side outside the processing chamber. The dielectric window assembly 1122 may be similar to that in Figure 11B, without holes for the conductor 1116. The coil system 1120 further includes a second array 1134 containing a plurality of coils 1136 embedded within the dielectric window assembly 1122.

[0134] In Figure 11D, the coils 1128 of the first array 1124 are generally located in a first plane parallel to and above a second plane containing the upper surface of the dielectric window assembly 1122. The coils 1136 of the second array 1134 are located in a third plane below the second plane. When powered by an RF direct drive circuit (or RF source and matching network), the coils 1128 of the first array 1124 couple with the coils 1136 of the second array 1134 to generate a magnetic field that delivers RF energy. The coils 1136 of the second array 1134 then deliver the RF energy to the process gas inside the chamber, igniting and maintaining the plasma.

[0135] In some examples, multiple coils 1128 have larger external dimensions than multiple coils 1136 embedded in the dielectric window assembly 1122. In some examples, the first array 1124 contains fewer coils than the second array 1134. Just as an example, the first array 1124 contains seven coils with external dimensions of 4 feet (1000 mm) to 7 inches (e.g., 6 inches), and the second array 1134 contains 19 coils with external dimensions of 1 inch to 3 inches (e.g., 2 inches), but other diameters, shapes, and numbers of coils can also be used. Note that in Figure 11B, two of the multiple coils 1128 that would normally appear behind coil 1128 have been omitted from the cross-section for clarity. In yet another example, an additional set of coils can be wound around the top of the processing chamber, as shown in Figures 10A–10C, to supply RF energy to the second array 1134.

[0136] Referring here to Figure 12A, the substrate support includes a base plate 1230 supporting a layer 1232 which may correspond to a ceramic multizone heating layer. A bonding layer 1234 may be placed between the layer 1232 and the base plate 1230. The base plate 1230 may include one or more channels 1236 for flowing a coolant through the base plate 1230.

[0137] The array 1250 of electrodes 1252 can be located in layer 1232. The array 1250 of electrodes 1252 is driven by an array 1270 of RF direct drive circuits, which provides an RF bias to the substrate. The upper electrode 1260, located on the substrate support 1226, may not be powered. If not powered, the upper electrode 1260 may be connected to a reference potential such as ground (as shown). The array 1270 of RF direct drive circuits supplies RF power to the array 1250 of electrodes 1252 as described herein, providing an RF bias to the substrate. Heaters and / or electrostatic electrodes, generally identified by 1264, can be located in layer 1232 above or below the array 1250 of electrodes 1252.

[0138] Referring here to Figure 12B, power can also be supplied to the upper electrodes. The substrate processing system includes a showerhead 1265 (having an internal plenum and gas through-holes (not shown)) supplied by a gas supply system 1266. The showerhead 1265 can be made of a conductive material (or a non-conductive material with embedded conductive electrodes). RF power is supplied to the showerhead 1265 by an RF source 1268 and a matching network 1267 (or by one or more RF direct drive circuits). In Figure 12C, a layer 1232 of the substrate support 1226 is shown together with an array of an array 1250 of electrodes 1252 embedded inside.

[0139] Referring here to Figure 12D, the upper electrode may include a second array 1270 of electrodes 1272 driven by an array 1280 of direct drive circuits. An array 1250 of electrodes 1252 is driven by an RF direct drive circuit 1284 to provide an RF bias to the substrate.

[0140] Referring here to Figure 13A, the substrate processing system includes an array of coils positioned adjacent to the dielectric window and an array of electrodes embedded in the substrate support and driven by an RF direct drive circuit. The substrate processing system includes an array 1320 containing a plurality of coils 1324 positioned adjacent to the dielectric window 1310 of the processing chamber. Array 1 320 Multiple coils 1324 are driven by the RF direct drive circuit 1340 described herein, supplying RF energy to ignite the process gas in the substrate processing chamber. The array 1250 of electrodes 1252 described above generates an RF substrate bias during processing.

[0141] Referring here to Figure 13B, the substrate processing system includes a coil 1360 positioned adjacent to the dielectric window 1310. The coil 1360 can be driven by one or more RF sources and matching networks and / or one or more RF direct drive circuits. The substrate processing system further includes an array 1250 having a plurality of electrodes 1252 embedded in the substrate support and driven by an array 1270 of RF direct drive circuits. The coil 1360 may include one or more coils, each having one or more turns. In the example in Figure 13B, the coil 1360 includes an outer coil 1364 and an inner coil 1366 positioned within the outer coil 1364. In some examples, the outer coil 1364 and / or the inner coil 1366 include two or more coils wound around each other as described above.

[0142] The foregoing description is purely illustrative and is not intended to limit the Disclosure, its application, or its use in any way. The broad teachings of this Disclosure can be implemented in various forms. Thus, while this Disclosure includes specific examples, the true scope of this Disclosure should not be limited to such examples, as other modifications will become apparent when considering the drawings, specification, and the claims below. It should be understood that one or more steps in a method may be performed in a different order (or simultaneously) without altering the principles of this Disclosure. Furthermore, while each embodiment is described above as having specific features, it is possible to implement one or more of these features described in relation to any embodiment of this Disclosure in other embodiments and / or combine them with any feature of any other embodiment (even if such combinations are not explicitly described). In other words, the described embodiments are not mutually exclusive, and substituting one or more embodiments with one or more is within the scope of this Disclosure.

[0143] The spatial and functional relationships between elements (e.g., modules, circuit elements, semiconductor layers, etc.) are described using a variety of terms, including “connected,” “engaged,” “joined,” “adjacent,” “next to,” “above,” “upwards,” “below,” and “located.” Furthermore, when a relationship between a first element and a second element is described in the above disclosure, unless it is explicitly described as “direct,” the relationship may be a direct relationship in which no other intervening elements exist between the first and second elements, or it may be an indirect relationship in which one or more intervening elements exist (spatially or functionally) between the first and second elements. As used herein, the expression “at least one of A, B, and C” should be interpreted as logic using non-exclusive logic OR (A or B or C) and not as “at least one of A, at least one of B, and at least one of C.”

[0144] In some embodiments, the controller is part of a system, and such a system may be part of the examples described above. Such a system may comprise semiconductor processing equipment including one or more processing tools, one or more chambers, one or more processing platforms, and / or specific processing components (such as wafer pedestals, gas flow systems, etc.). These systems may be integrated with electronic equipment for controlling system operation before, during, and after processing of semiconductor wafers or substrates. Such electronic equipment may be referred to as a “controller” and may control various components or sub-components of one or more systems. Depending on the processing requirements and / or the type of system, the controller may be programmed to control any of the processes disclosed herein. Such processes include supplying processing gases, setting temperature (e.g., heating and / or cooling), setting pressure, setting vacuum, setting power, setting radio frequency (RF) generator settings, setting RF matching circuit settings, setting frequency, setting flow rate, setting fluid supply, setting position and operation, loading and unloading wafers to and from tools, and loading and unloading wafers to and from other transport tools and / or load locks connected to or interlocked with a particular system.

[0145] In a broad sense, a controller may be defined as an electronic device having various integrated circuits, logic, memory, and / or software that receive and issue instructions, control operations, enable cleaning operations, enable endpoint measurements, etc. Integrated circuits may include chips in the form of firmware that store program instructions, chips defined as digital signal processors (DSPs), application-specific integrated circuits (ASICs), and / or one or more microprocessors, i.e., microcontrollers that execute program instructions (e.g., software). Program instructions are instructions communicated to the controller in the form of various individual settings (or program files) that may define operating parameters for performing a particular process on or for a semiconductor wafer or for a system. In some embodiments, the operating parameters may be part of a recipe defined by a process engineer to realize one or more processing steps in the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or wafer dies.

[0146] In some embodiments, the controller may be part of a computer integrated with or coupled to the system, or otherwise networked to the system, or coupled to such a computer, or a combination thereof. For example, the controller may be in the “cloud” or may be all or part of the fab host computer system. This enables remote access to wafer processing. The computer may enable remote access to the system to monitor the current progress of fabrication operations, review the history of past fabrication operations, review trends or performance criteria from multiple fabrication operations, modify parameters of the current process, set processing steps following the current process, or start a new process. In some examples, a remote computer (e.g., a server) can provide process recipes to the system over a network. Such a network may include a local network or the internet. The remote computer may include a user interface that enables entry or programming of parameters and / or settings, which are then communicated from the remote computer to the system. In some examples, the controller receives instructions in the form of data. Such data identifies parameters for each processing step performed during one or more operations. It should be understood that the parameters may be specific to the type of process being performed and the type of tools to which the controller is configured to interact or control. Therefore, as described above, the controller may be distributed, for example, by comprising one or more separate controllers that are networked together and cooperate toward a common purpose (such as the processes and controls described herein). An example of a distributed controller for such a purpose would be one or more integrated circuits on a chamber that communicate with one or more integrated circuits that are remotely located (e.g., at the platform level or as part of a remote computer) and combined to control the processes in the chamber.

[0147] Exemplary systems may include, but are not limited to, plasma etching chambers or modules, deposition chambers or modules, spin rinse chambers or modules, metal plating chambers or modules, cleaning chambers or modules, bevel edge etching chambers or modules, physical vapor deposition (PVD) chambers or modules, chemical vapor deposition (CVD) chambers or modules, atomic layer deposition (ALD) chambers or modules, atomic layer etching (ALE) chambers or modules, ion implantation chambers or modules, tracking chambers or modules, and any other semiconductor processing systems that may be used in connection with or for the fabrication and / or manufacture of semiconductor wafers.

[0148] As described above, depending on one or more process steps performed by the tool, the controller may communicate with one or more other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, nearby tools, tools located throughout the factory, a main computer, another controller, or tools used for material handling to load and unload wafer containers to and from tool locations and / or load ports within the semiconductor manufacturing plant.

Claims

1. A substrate processing system, A processing chamber including a window, A substrate support is provided within the processing chamber to support the substrate during plasma processing, A first array comprising E induction coils, located adjacent to and outside the processing chamber, wherein E is an integer greater than 3, A second array includes D RF direct drive circuits configured to output RF power to the first array and generate plasma inside the processing chamber, where D is an integer greater than 3. A controller configured to control the second array, The system comprises S sensors, each configured to sense S operating parameters corresponding to the second array, where S is an integer greater than 3. A substrate processing system in which the controller is configured to change the operation of the D RF direct drive circuits based on the S operating parameters sensed by the S sensors.

2. A substrate processing system according to claim 1, A substrate processing system in which the distance between the upper surface of the substrate support and the bottom surface of the window is in the range of 0.4 inches to 6 inches (10.16 mm to 152.4 mm).

3. A substrate processing system according to claim 1, A substrate processing system in which the distance between the upper surface of the substrate support and the bottom surface of the window is in the range of 1 inch to 3 inches (25.4 mm to 76.2 mm).

4. A substrate processing system according to claim 1, A substrate processing system in which the E induction coils have either a circular or hexagonal outer shape.

5. A substrate processing system according to claim 1, A substrate processing system in which the E induction coils are arranged in one of a rectangular array and a hexagonal array.

6. A substrate processing system according to claim 1, The aforementioned E induction coils have an outer diameter ranging from 1 inch to 6 inches, and are part of a substrate processing system.

7. A substrate processing system according to claim 1, The aforementioned E induction coils have an outer diameter ranging from 3 inches to 6 inches, forming a substrate processing system.

8. A substrate processing system according to claim 1, A substrate processing system in which the first array further includes F induction coils, the F induction coils having at least one of different sizes and shapes from the E induction coils, and F is an integer greater than 2.

9. A substrate processing system according to claim 1, A substrate processing system in which each of the E induction coils includes a first induction coil located inside a second induction coil.

10. A substrate processing system, A processing chamber including a window, A substrate support is provided within the processing chamber to support the substrate during plasma processing, A first array comprising E induction coils, located adjacent to and outside the processing chamber, wherein E is an integer greater than 3, A second array comprising D RF direct drive circuits configured to output RF power to the first array and generate plasma inside the processing chamber, wherein D is an integer greater than 3, A substrate processing system in which each of the E induction coils includes a first induction coil wound around a second induction coil.

11. A substrate processing system according to claim 10, further, A controller configured to control the second array, The system comprises S sensors, each configured to sense S operating parameters corresponding to the second array, where S is an integer greater than 3. A substrate processing system in which the controller is configured to change the operation of the D RF direct drive circuits based on the S operating parameters sensed by the S sensors.

12. A substrate processing system according to claim 1, The aforementioned window is made of a dielectric material and is part of a substrate processing system.

13. A substrate processing system according to claim 1, A substrate processing system wherein the window includes a frame portion, the frame portion defines E cavities, and the E induction coils in the first array are arranged in the E cavities of the frame portion.

14. A substrate processing system according to claim 13, A substrate processing system further comprising E windows positioned in the openings of the E cavities facing the substrate.

15. A substrate processing system according to claim 13, A substrate processing system further comprising a dielectric window located on the side of the frame portion facing the substrate.

16. A substrate processing system according to claim 1, wherein each of the D RF direct drive circuits is A clock generator that generates a clock signal at a first frequency, A gate driver that receives the aforementioned clock signal, A first switch having a control terminal, a first terminal, and a second terminal connected to the gate driver, A control terminal connected to the gate driver, a first terminal connected to the second terminal and output node of the first switch, and a second switch having the second terminal. A bridge circuit including, A first DC power supply that supplies a first voltage potential to the first terminal of the first switch, A second DC power supply that supplies a second voltage potential to the second terminal of the second switch, A substrate processing system including this.

17. A substrate processing system according to claim 16, A substrate processing system in which the first voltage potential and the second voltage potential have opposite polarities and are approximately equal in magnitude.

18. A substrate processing system according to claim 16, The second voltage potential is ground in the substrate processing system.

19. A substrate processing system according to claim 16, A current sensor that senses the current at the output node and generates a current signal, A voltage sensor that senses the voltage at the output node and generates a voltage signal, A phase offset calculator that calculates the phase offset between the voltage signal and the current signal. A clock adjuster that adjusts the first frequency based on the phase offset, Controllers including A substrate processing system that also includes additional features.

20. A substrate processing system according to claim 19, A circuit board processing system wherein the clock regulator increases the first frequency when the current leads the voltage and decreases the first frequency when the voltage leads the current.

21. A substrate processing system according to claim 1, wherein each of the D RF direct drive circuits is A first inductor including a first end and a second end, A second inductor including a first end and a second end that communicate with the first end of the first inductor, A first switch including a first terminal, a second terminal, and a control terminal, A second switch including a first terminal, a second terminal, and a control terminal, A first capacitor including a first end and a second end, the first end of the first capacitor communicating with the second end of the first inductor and the first terminal of the first switch, A second capacitor including a first end and a second end, wherein the second end of the second capacitor communicates with the second end of the second inductor and the second terminal of the second switch. Includes, The second terminal of the first switch communicates with the first terminal of the second switch, the second end of the first capacitor, and the first end of the second capacitor. PCB processing system.

22. A substrate processing system according to claim 21, A third capacitor including a first end communicating with the first end of the first capacitor, and a second end communicating with at least one first end of the E induction coils, A fourth capacitor including a first end communicating with the second end of the second capacitor, and a second end communicating with at least one second end of the E induction coils. A substrate processing system that also includes additional features.

23. A substrate processing system according to claim 21, A substrate processing system further comprising a voltage source having one end connected to the first end of the first inductor and the first end of the second inductor, and a second end connected to the second terminal of the first switch and the first terminal of the second switch.

24. A substrate processing system according to claim 1, A substrate processing system further comprising induction coils surrounding the first array.

25. A substrate processing system according to claim 1, The processing chamber further comprises one or more induction coils, each including one or more turns wound around the upper part of the side wall, The first array is arranged in a first plane above the window, and the one or more induction coils are arranged below the first plane. PCB processing system.

26. A substrate processing system according to claim 1, A substrate processing system further comprising a third array including F induction coils embedded in the window, where F is an integer greater than 3, and the E induction coils supply RF energy to the F induction coils.

27. A substrate processing system according to claim 26, A substrate processing system in which the E induction coils of the first array are larger than the F induction coils of the third array.

28. A substrate processing system according to claim 27, F is a substrate processing system that is larger than E.

29. A substrate processing system according to claim 27, further, A fourth array comprising G electrodes embedded in the substrate support, where G is an integer greater than 3, A substrate processing system comprising a fifth array including H RF direct drive circuits configured to output RF power to the fourth array, where H is an integer greater than 3.

30. A substrate processing system, A processing chamber including a window, A substrate support is provided within the processing chamber to support the substrate during plasma processing, A first array comprising E induction coils, located adjacent to and outside the processing chamber, wherein E is an integer greater than 3, A second array includes D RF direct drive circuits configured to output RF power to the first array and generate plasma inside the processing chamber, where D is an integer greater than 3. A third array comprising F induction coils embedded in the window, where F is an integer greater than 3, and the E induction coils supply RF energy to the F induction coils. A substrate processing system in which the E induction coils of the first array are larger than the F induction coils of the third array.

31. A substrate processing system according to claim 30, further, A controller configured to control the second array, The system comprises S sensors, each configured to sense S operating parameters corresponding to the second array, where S is an integer greater than 3. A substrate processing system in which the controller is configured to change the operation of the D RF direct drive circuits based on the S operating parameters sensed by the S sensors.

32. A substrate processing system according to claim 30, A substrate processing system in which each of the E induction coils includes a first induction coil wound around a second induction coil.

33. A substrate processing system according to claim 30, F is a substrate processing system that is larger than E.

34. A substrate processing system according to claim 30, further, A fourth array comprising G electrodes embedded in the substrate support, where G is an integer greater than 3, A substrate processing system comprising a fifth array including H RF direct drive circuits configured to output RF power to the fourth array, where H is an integer greater than 3.

35. A substrate processing system, A processing chamber including a window, A substrate support is provided within the processing chamber to support the substrate during plasma processing, A first array comprising E induction coils, located adjacent to and outside the processing chamber, wherein E is an integer greater than 3, A second array includes D RF direct drive circuits configured to output RF power to the first array and generate plasma inside the processing chamber, where D is an integer greater than 3. A third array comprising F induction coils embedded in the window, where F is an integer greater than 3, and the E induction coils supply RF energy to the F induction coils. The E induction coils of the first array are larger than the F induction coils of the third array. F is a substrate processing system that is larger than E.

36. A substrate processing system according to claim 35, further, A controller configured to control the second array, The system comprises S sensors, each configured to sense S operating parameters corresponding to the second array, where S is an integer greater than 3. A substrate processing system in which the controller is configured to change the operation of the D RF direct drive circuits based on the S operating parameters sensed by the S sensors.

37. A substrate processing system according to claim 35, A substrate processing system in which each of the E induction coils includes a first induction coil wound around a second induction coil.

38. A substrate processing system according to claim 35, further, A fourth array comprising G electrodes embedded in the substrate support, where G is an integer greater than 3, A substrate processing system comprising a fifth array including H RF direct drive circuits configured to output RF power to the fourth array, where H is an integer greater than 3.

39. A substrate processing system, A processing chamber including a window, A substrate support is provided within the processing chamber to support the substrate during plasma processing, A first array comprising E induction coils, located adjacent to and outside the processing chamber, wherein E is an integer greater than 3, A second array includes D RF direct drive circuits configured to output RF power to the first array and generate plasma inside the processing chamber, where D is an integer greater than 3. A third array containing F induction coils embedded in the window, where F is an integer greater than 3, and the E induction coils supply RF energy to the F induction coils. A fourth array comprising G electrodes embedded in the substrate support, where G is an integer greater than 3, A fifth array comprising H RF direct drive circuits configured to output RF power to the fourth array, where H is an integer greater than 3, A substrate processing system in which the E induction coils of the first array are larger than the F induction coils of the third array.

40. A substrate processing system according to claim 38, further, A controller configured to control the second array, The system comprises S sensors, each configured to sense S operating parameters corresponding to the second array, where S is an integer greater than 3. A substrate processing system in which the controller is configured to change the operation of the D RF direct drive circuits based on the S operating parameters sensed by the S sensors.

41. A substrate processing system according to claim 39, A substrate processing system in which each of the E induction coils includes a first induction coil wound around a second induction coil.

42. A substrate processing system according to claim 39, A substrate processing system in which the E induction coils of the first array are larger than the F induction coils of the third array.

43. A substrate processing system according to claim 42, F is a substrate processing system that is larger than E.

44. A substrate processing system, A processing chamber including a window, A substrate support is provided within the processing chamber to support the substrate during plasma processing, A first array comprising E induction coils, located adjacent to and outside the processing chamber, wherein E is an integer greater than 3, A second array includes D RF direct drive circuits configured to output RF power to the first array and generate plasma inside the processing chamber, where D is an integer greater than 3. A third array comprising G electrodes embedded in the substrate support, where G is an integer greater than 3, A substrate processing system comprising: a fourth array including H RF direct drive circuits configured to output RF power to the third array, where H is an integer greater than 3.

45. A substrate processing system according to claim 44, further, A controller configured to control the second array, The system comprises S sensors, each configured to sense S operating parameters corresponding to the second array, where S is an integer greater than 3. A substrate processing system in which the controller is configured to change the operation of the D RF direct drive circuits based on the S operating parameters sensed by the S sensors.

46. A substrate processing system according to claim 44, A substrate processing system in which each of the E induction coils includes a first induction coil wound around a second induction coil.

47. A substrate processing system according to claim 44, A substrate processing system further comprising a fifth array including F induction coils embedded in the window, where F is an integer greater than 3, and the E induction coils supply RF energy to the F induction coils.

48. A substrate processing system according to claim 47, A substrate processing system in which the E induction coils of the first array are larger than the F induction coils of the fifth array.

49. A substrate processing system according to claim 48, F is a substrate processing system that is larger than E.

50. A substrate processing system according to claim 1, A substrate processing system in which each of the E induction coils includes a first induction coil wound around a second induction coil.

51. A substrate processing system according to claim 10, A substrate processing system further comprising a third array including F induction coils embedded in the window, where F is an integer greater than 3, and the E induction coils supply RF energy to the F induction coils.

52. A substrate processing system according to claim 51, A substrate processing system in which the E induction coils of the first array are larger than the F induction coils of the third array.

53. A substrate processing system according to claim 52, F is a substrate processing system that is larger than E.

54. A substrate processing system according to claim 52, further, A fourth array comprising G electrodes embedded in the substrate support, where G is an integer greater than 3, A substrate processing system comprising a fifth array including H RF direct drive circuits configured to output RF power to the fourth array, where H is an integer greater than 3.

55. A substrate processing system according to claim 10, further, A third array comprising G electrodes embedded in the substrate support, where G is an integer greater than 3, A substrate processing system comprising a fourth array including H RF direct drive circuits configured to output RF power to the third array, where H is an integer greater than 3.

56. A substrate processing system according to claim 1, further, A third array comprising G electrodes embedded in the substrate support, where G is an integer greater than 3, A substrate processing system comprising a fourth array including H RF direct drive circuits configured to output RF power to the third array, where H is an integer greater than 3.

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