Indication device

Abstract

To provide a display device capable of controlling a viewing angle.SOLUTION: A display device comprises: a display panel including a display area in which a plurality of sub-pixels is arranged and a non-display area surrounding the display area; and a plurality of level shifts arranged in the display area and that transmits a mode signal so as to drive the plurality of sub-pixels in either a first mode or a second mode. Each of the plurality of sub-pixels includes: a first light-emitting element; a first optical member that refracts light from the first light-emitting element; a second light-emitting element; and a second optical member that refracts light from the second light-emitting element and has a different shape from the first optical member. As a result, a bezel area can be reduced by embedding the level shift for generating the mode signal in the display area.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] This specification relates to a display device, and more particularly to a display device capable of controlling a viewing angle.

Background Art

[0002] As technology in modern society develops, display devices are widely used to provide information to users. Display devices include not only electro-optical panels that simply transmit visual information in one direction, but also various electronic devices that require higher technologies to confirm user input and provide information corresponding to the confirmed input.

[0003] For example, a display device can be included in a vehicle to provide various information to the driver and passengers of the vehicle. However, the display device in the vehicle needs to appropriately display content so as not to interfere with the operation of the vehicle. For example, the display device needs to limit the display of content that can reduce the concentration on driving during the operation of the vehicle.

Summary of the Invention

Problems to be Solved by the Invention

[0004] The problem to be solved by this specification is to provide a display device capable of generating a mode signal using a low-voltage signal without a separate high-voltage IC.

[0005] Another problem to be solved by this specification is to provide a display device capable of selectively controlling the viewing angle in both the row and column directions for multiple regions.

[0006] Another problem to be solved by this specification is to provide a display device with a minimized bezel.

[0007] The problems of this specification are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

Means for Solving the Problems

[0008] A display device according to one embodiment of this specification includes a display panel including a display area on which a plurality of subpixels are arranged and a non-display area surrounding the display area, and a plurality of level shifts arranged in the display area and transmitting mode signals so that the plurality of subpixels are driven in either a first mode or a second mode, each of which includes a first light-emitting element, a first optical element that refracts light from the first light-emitting element, a second light-emitting element, and a second optical element that refracts light from the second light-emitting element and has a different shape from the first optical element.Therefore, the bezel area can be reduced by integrating the level shifts for generating the mode signals into the display area.

[0009] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0010] According to the embodiments described herein, mode signals can be generated using level shifts that use the same control signals as those used to drive the sub-pixel circuits, without using a separate IC for generating mode signals, thereby reducing manufacturing costs.

[0011] According to the embodiments described herein, the bezel area can be reduced by integrating a level shift for generating the mode signal into the display area.

[0012] According to the embodiments of this specification, the viewing angle can be selectively controlled in either the row or column direction by arranging level shifts in multiple regions.

[0013] According to the embodiments of this specification, the level shift can share sub-pixel circuits and signal wiring, minimizing further wiring required to drive the level shift, thereby preventing complexity in the wiring design.

[0014] The effects described herein are not limited to those exemplified above, and a wider variety of effects are included within this specification. [Brief explanation of the drawing]

[0015] [Figure 1] This is a block diagram of a display device according to one embodiment of this specification. [Figure 2] This is a circuit diagram of a subpixel of a display device according to one embodiment of this specification. [Figure 3a] This is a waveform diagram illustrating the sub-pixel circuit of a display device according to one embodiment of this specification. [Figure 3b] This is a waveform diagram illustrating the sub-pixel circuit of a display device according to one embodiment of this specification. [Figure 4a] This is a cross-sectional view of a display device according to one embodiment of this specification. [Figure 4b] This is a cross-sectional view of a display device according to one embodiment of this specification. [Figure 5] This is a plan view of a display device according to one embodiment of this specification. [Figure 6] This is a schematic enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. [Figure 7] This is a circuit diagram of the first level shift of a display device according to one embodiment of this specification. [Figure 8] This is a waveform diagram illustrating the first level shift circuit of a display device according to one embodiment of this specification. [Figure 9a] This is a circuit diagram of the first level shift of a display device according to one embodiment of the present invention during a first period in wide-view mode. [Figure 9b] This is a circuit diagram of the first level shift of a display device according to one embodiment of the present invention during the second period in wide-view mode. [Figure 9c] This is a circuit diagram of the first level shift of a display device according to one embodiment of the present invention during the third period in wide-view mode. [Figure 10] This is a circuit diagram of the second level shift of a display device according to one embodiment of this specification. [Figure 11]This is a waveform diagram for explaining a second-level shift circuit of a display device according to an embodiment of this specification. [Figure 12a] This is a circuit diagram of a second-level shift of a display device according to an embodiment of the present invention during a first period in a narrow viewing angle mode. [Figure 12b] This is a circuit diagram of a second-level shift of a display device according to an embodiment of the present invention during a second period in a narrow viewing angle mode. [Figure 12c] This is a circuit diagram of a second-level shift of a display device according to an embodiment of the present invention during a third period in a narrow viewing angle mode.

Embodiments for Carrying Out the Invention

[0016] The advantages, features, and the methods for achieving them of this specification will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, this specification is not limited to the embodiments disclosed below, and is embodied in various different forms. Merely, these embodiments are provided so that the disclosure of this specification becomes complete and to fully inform those with ordinary knowledge in the technical field to which this specification pertains of the scope of this specification.

[0017] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of this specification are exemplary, so this specification is not limited to the matters illustrated. Throughout this specification, the same reference signs refer to the same components. Also, when explaining this specification, if it is determined that a detailed explanation of related known technologies may muddy the gist of this specification, that detailed explanation will be omitted. When terms such as "including", "having", "being made" as mentioned in this specification are used, other parts can be added as long as "only" is not used. When a component is expressed in the singular, it includes the case of including a plurality unless there are specific descriptions to the contrary.

[0018] When interpreting components, it is interpreted as including an error range even without separate explicit descriptions.

[0019] When describing a spatial relationship, for example, when describing the positional relationship between two parts using phrases like "on top," "above," "below," or "next to," it is acceptable for one or more other parts to be located between the two parts, as long as "immediately" or "directly" is not used.

[0020] When an element or layer is referred to as "on" another element or layer, this includes cases where another layer or other element is interposed immediately above or between the other element.

[0021] Furthermore, while terms such as "first," "second," etc., are used to describe a variety of components, these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0022] Throughout the specification, the same reference numeral refers to the same component.

[0023] The area and thickness of each component shown in the drawings are provided for illustrative purposes only, and this specification is not necessarily limited to the area and thickness of the components shown.

[0024] The features of each of the various embodiments described herein can be combined or combined with one another, either partially or as a whole, enabling a variety of technically diverse interoperability and drive, and each embodiment may be implemented independently of the others or together in relation to one another.

[0025] In the following, this specification will be described with reference to the drawings.

[0026] Figure 1 is a block diagram of a display device according to one embodiment of this specification.

[0027] An electroluminescent display device 100 according to one embodiment of this specification may be an electroluminescent display device. The electroluminescent display device may be an organic light-emitting diode display device, a quantum-dot light-emitting diode display device, or an inorganic light-emitting diode display device.

[0028] Referring to Figure 1, the display device 100 can include a display panel PN, a data drive circuit DD, a gate drive circuit GD, and a timing controller TC.

[0029] The display panel PN can generate an image to be presented to the user. For example, the display panel PN can generate and display an image presented to the user through a pixel PX in which multiple sub-pixel circuits are arranged.

[0030] The data drive circuit DD, gate drive circuit GD, and timing controller TC can provide signals for the operation of each pixel PX through signal wiring. The signal wiring may include, for example, data wiring DL and gate wiring GL.

[0031] Data routing DL may be arranged in the column direction and include multiple routings connected to pixels PX arranged in one column direction, and gate routing GL may be arranged in the row direction and include multiple routings connected to pixels PX arranged in one row direction.

[0032] In some cases, the display device 100 may further include a power supply unit. In such cases, signals for the operation of the pixels PX may be provided through power wiring connecting the power supply unit and the display panel PN. In some embodiments, the power supply unit can supply power to a data drive circuit DD and a gate drive circuit GD. The data drive circuit DD and the gate drive circuit GD can be driven based on the power supplied from the power supply unit.

[0033] For example, the data drive circuit DD can apply a data signal to each pixel PX through the data wiring DL, the gate drive circuit GD can apply a gate signal to each pixel PX through the gate wiring GL, and the power supply unit can supply a power voltage to each pixel PX through the power supply voltage wiring.

[0034] The timing controller TC can control the data drive circuit DD and the gate drive circuit GD. For example, the timing controller TC can realign digital video data input from an external source to match the resolution of the display panel PN and supply it to the data drive circuit DD.

[0035] The data drive circuit DD can convert digital video data input from the timing controller TC into analog data voltages based on data control signals and supply them to numerous data wirings DL.

[0036] The gate drive circuit GD can generate scan signals and light emission signals (or light emission control signals) based on gate control signals. The gate drive circuit GD may include a scan drive unit and a light emission signal drive unit. The scan drive unit can generate scan signals in a row-by-row manner and supply them to scan wiring to drive at least one scan wiring connected for each row of pixels. The light emission signal drive unit can generate light emission signals in a row-by-row manner and supply them to light emission signal wiring to drive at least one light emission signal wiring connected for each row of pixels.

[0037] Depending on the embodiment, the gate driver circuit GD may be arranged on the display panel PN in a GIP (Gate-driver In Panel) configuration. For example, the gate driver circuit GD may be divided into multiple units and arranged on at least two sides of the display panel PN.

[0038] The display panel PN may include a display area and a non-display area surrounding the display area.

[0039] The display area of ​​the display panel PN may include multiple pixels PX arranged in the row and column directions. Pixels PX may be located in areas where numerous data lines and numerous gate lines intersect.

[0040] A single pixel PX can contain multiple subpixels that emit different colors from each other. For example, a pixel PX can use three subpixels to embody blue, red, and green. However, it is not limited to this, and a pixel PX may, in some cases, contain additional subpixels to further embody a specific color (e.g., white).

[0041] In a pixel PX, the area that embodies blue can be called a blue subpixel, the area that embodies red can be called a red subpixel, and the area that embodies green can be called a green subpixel.

[0042] Each of the multiple subpixels includes a first light-emitting element and a second light-emitting element, and may include a first lens that refracts light from the first light-emitting element in a specific direction and a second lens that refracts light from the second light-emitting element in a specific direction. Thus, the first and second lenses can limit the field of view of each of the multiple subpixels.

[0043] A detailed explanation of the first and second lenses will be provided later with reference to Figures 4a and 4b.

[0044] A non-display area may be located around the display area. Various components for driving multiple subpixels located on a pixel PX may be located within the non-display area. For example, at least a portion of a gate drive circuit GD may be located within the non-display area. The non-display area may be referred to as a bezel area.

[0045] Figure 2 is a circuit diagram of a subpixel of a display device according to one embodiment of this specification. A plurality of pixels PX may include a plurality of subpixels SP that each exhibit a different color from each other, and a subpixel circuit SPC corresponding to each of the plurality of subpixels SP.

[0046] Referring to Figure 2, each of the multiple subpixels SP includes multiple light-emitting elements ED1, ED2, a drive transistor DT, first to eighth transistors T1 to T8, and a storage capacitor Cst.

[0047] Multiple transistors DT, T1-T8 may include at least one of amorphous silicon, polycrystalline silicon, and oxide semiconductors such as IGZO. The first or second electrode of a transistor may be the source electrode or the drain electrode. For example, the first electrode may be the source electrode and the second electrode may be the drain electrode. Another example is that the first electrode may be the drain electrode and the second electrode may be the source electrode.

[0048] At least some of the transistors included in the sub-pixel circuit (SPC) may be n-type or p-type transistors. In the case of p-type transistors, the low-level voltage of each drive signal may represent the voltage that turns the TFT on, and the high-level voltage of each drive signal may represent the voltage that turns the transistor off.

[0049] Here, the low-level voltage may correspond to a predetermined voltage lower than the high-level voltage. For example, the low-level voltage may include voltages within the range of -8V to -12V. The high-level voltage may correspond to a predetermined voltage higher than the low-level voltage. For example, the high-level voltage may include voltages within the range of 12V to 16V. Depending on the embodiment, the low-level voltage may be referred to as the first voltage and the high-level voltage as the second voltage. In such a case, the first voltage may be lower than the second voltage.

[0050] In the following discussion, the first or second electrode of a transistor may refer to the source or drain electrode. However, the terms "first electrode" and "second electrode" are merely distinguishing terms and do not limit what each electrode corresponds to. Furthermore, the first electrode may not refer to the same electrode for each transistor. For example, the first electrode of the first transistor T1 may refer to the source electrode of the first transistor T1, and the first electrode of the eighth transistor T8 may refer to the drain electrode of the eighth transistor T8.

[0051] The drive transistor DT can control the drive current applied to multiple light-emitting elements by the source-gate voltage Vsg. The drive transistor DT includes a source electrode connected to a high-potential drive voltage wiring supplied with a high-potential drive voltage VDD, a gate electrode connected to a second node N2, and a drain electrode connected to a third node N3.

[0052] The first transistor T1 can apply a data voltage Vdata to the first node N1 from the data trace DL. The first transistor T1 includes a source electrode connected to the data trace, a drain electrode connected to the first node N1, and a gate electrode connected to the first scan signal trace to which the first scan signal SCAN1 is applied. The first transistor T1 can be turned on or turned off by the first scan signal SCAN1. Thus, the first transistor T1 can apply a data voltage Vdata to the first node N1 from the data trace DL in response to a low-level first scan signal SCAN1, which is the turn-on level.

[0053] The second transistor T2 can diode-connect the gate electrode and drain electrode of the drive transistor DT. The second transistor T2 includes a drain electrode connected to the second node N2, a source electrode connected to the third node N3, and a gate electrode connected to the second scan signal wiring to which the second scan signal SCAN2 is applied. The second transistor T2 can be turned on or turned off by the second scan signal SCAN2. Thus, the second transistor T2 can diode-connect the gate electrode and drain electrode of the drive transistor DT in response to a low-level second scan signal SCAN2, which is the turn-on level.

[0054] The third transistor T3 can apply a reference voltage Vref to the first node N1. The third transistor T3 includes a source electrode connected to a reference wiring that transmits the reference voltage Vref, a drain electrode connected to the first node N1, and a gate electrode connected to a light emission signal wiring. The third transistor T3 can be turned on or turned off by a light emission signal EM. Thus, the third transistor T3 can transmit the reference voltage Vref to the first node N1 in response to a low-level light emission signal EM, which is the turn-on level.

[0055] The fourth transistor T4 can form a current path between the drive transistor DT and the first light-emitting element ED1 when driven in the first mode, which is the wide-field mode. The fourth transistor T4 includes a source electrode connected to the fourth node N4, a drain electrode connected to the anode electrode of the first light-emitting element ED1, and a gate electrode connected to the first mode control wiring to which the first mode signal MS1 is applied. The fourth transistor T4 can be turned on or turned off by the first mode signal MS1. Thus, in response to a low-level first mode signal MS1, which is the turn-on level, the fourth transistor T4 forms a current path between the fourth node N4, which is the source electrode of the fourth transistor T4, and the first light-emitting element ED1. In other words, the fourth transistor T4 forms a current path between the drive transistor DT and the first light-emitting element ED1 in response to a low-level first mode signal MS1. Thus, the fourth transistor T4 can also be referred to as the first light-emitting control transistor that controls the light emission of the first light-emitting element ED1.

[0056] Here, the first mode signal MS1 is provided by the first level shift LS1, which will be described later, and can control the drive (or emission) of the first light-emitting element ED1 on which the first lens is located.

[0057] The fifth transistor T5 can apply a reference voltage Vref to the anode electrode of the first light-emitting element ED1. The fifth transistor T5 includes a source electrode connected to a reference wiring that transmits the reference voltage Vref, a drain electrode connected to the anode electrode of the first light-emitting element ED1, and a gate electrode connected to a second scan signal wiring to which the second scan signal SCAN2 is applied. The fifth transistor T5 can be turned on or turned off by the second scan signal SCAN2. Thus, the fifth transistor T5 can apply the reference voltage Vref to the anode electrode of the first light-emitting element ED1 in response to a low-level second scan signal SCAN2, which is the turn-on level.

[0058] The sixth transistor T6 can apply a reference voltage Vref to the anode electrode of the second light-emitting element ED2. The sixth transistor T6 includes a source electrode connected to a reference wiring that transmits the reference voltage Vref, a drain electrode connected to the anode electrode of the second light-emitting element ED2, and a gate electrode connected to a second scan signal wiring to which the second scan signal SCAN2 is applied. The sixth transistor T6 can be turned on or turned off by the second scan signal SCAN2. Thus, the sixth transistor T6 can apply the reference voltage Vref to the anode electrode of the second light-emitting element ED2 in response to a low-level second scan signal SCAN2, which is the turn-on level.

[0059] The seventh transistor T7 can form a current path between the drive transistor DT and the second light-emitting element ED2 when driven in the second mode, which is the narrow field mode. The seventh transistor T7 includes a source electrode connected to the fourth node N4, a drain electrode connected to the anode electrode of the second light-emitting element ED2, and a gate electrode connected to the second mode control wiring to which the second mode signal MS2 is applied. The seventh transistor T7 can be turned on or turned off by the second mode signal MS2. Thus, in response to a low-level second mode signal MS2, which is the turn-on level, the seventh transistor T7 forms a current path between the fourth node N4, which is the source electrode of the seventh transistor T7, and the second light-emitting element ED2. In other words, the seventh transistor T7 forms a current path between the drive transistor DT and the second light-emitting element ED2 in response to a low-level second mode signal MS2. Thus, the seventh transistor T7 can also be referred to as a second light-emitting control transistor that controls the light emission of the second light-emitting element ED2.

[0060] Here, the second mode signal MS2 is provided by the second level shift LS2, which will be described later, and can control the drive (or emission) of the second light-emitting element ED2 on which the second lens is located.

[0061] The eighth transistor T8 can apply the drive current of the drive transistor DT to the fourth node N4. The eighth transistor T8 includes a source electrode connected to the third node N3, a drain electrode connected to the fourth node N4, and a gate electrode connected to a light emission signal wiring that transmits the light emission signal EM. The eighth transistor T8 can be turned on or turned off by the light emission signal EM. Thus, the eighth transistor T8 can transmit a drive current to the fourth node N4 in response to a low level light emission signal EM, which is the turn-on level.

[0062] The storage capacitor Cst includes a first electrode connected to the first node N1 and a second electrode connected to the second node N2. That is, one electrode of the storage capacitor Cst is connected to the gate electrode of the drive transistor DT, and the other electrode of the storage capacitor Cst is connected to the first transistor T1. The storage capacitor Cst can store a constant voltage and maintain a constant voltage at the gate electrode of the drive transistor DT while the light-emitting element is emitting light.

[0063] The first light-emitting element ED1 may be connected to a fourth transistor T4, which is turned on or off by a first mode signal MS1. The second light-emitting element ED2 may be connected to a seventh transistor T7, which is turned on or off by a second mode signal MS2.

[0064] In such cases, the first light-emitting element ED1 or the second light-emitting element ED2 may be coupled to other components of the sub-pixel circuit SPC, such as the drive transistor DT, depending on the mode. The mode may be determined by user input or by satisfying pre-specified conditions. For example, if a pre-specified first condition is met, the first light-emitting element ED1 can emit light based on the supply of a first mode signal MS1. If a pre-specified second condition is met, the second light-emitting element ED2 can emit light based on the supply of a second mode signal MS2. The first condition may include pre-specified conditions for driving in the first mode. The second condition may include pre-specified conditions for driving in the second mode.

[0065] The first mode signal MS1 can be configured to operate the sub-pixel circuit in first mode when input at a low value. The second mode signal MS2 can be configured to operate the sub-pixel circuit in second mode when input at a low value. In this case, the first mode may be a wide field mode, and the second mode may be a narrow field mode.

[0066] Specifically, the first light-emitting element ED1 emits light in a first mode, which is a wide-field mode. As will be described later, a semi-cylindrical first lens 161 is placed on the first light-emitting element ED1 to realize the wide-field mode. The first light-emitting element ED1 includes an anode electrode connected to a fourth transistor T4 and a cathode electrode connected to a low-potential power supply wiring to which a low-potential power supply VSS is applied. The first light-emitting element ED1 receives the drive current of the drive transistor DT through the fourth transistor T4, which is turned on when in wide-field mode. Therefore, when driven in wide-field mode, the first light-emitting element ED1 can emit light by receiving the drive current.

[0067] The second light-emitting element ED2 emits light in a narrow field of view mode. A hemispherical second lens 162 is positioned on the second light-emitting element ED2 to realize the narrow field of view mode. The second light-emitting element ED2 includes an anode electrode connected to the seventh transistor T7 and a cathode electrode connected to a low-potential power supply wiring. The second light-emitting element ED2 receives the drive current of the drive transistor DT through the seventh transistor T7, which is turned on when in narrow field of view mode. Therefore, when driven in narrow field of view mode, the second light-emitting element ED2 can emit light by receiving the drive current.

[0068] Figures 3a and 3b are waveform diagrams illustrating the sub-pixel circuits of a display device according to one embodiment of this specification. Specifically, Figure 3a is a waveform diagram illustrating the sub-pixel circuit for the implementation of the first mode, the wide-field mode, and Figure 3b is a waveform diagram illustrating the sub-pixel circuit for the implementation of the second mode, the narrow-field mode.

[0069] Referring to Figures 2 through 3b, in wide-field mode only the first light-emitting element ED1 can emit light, and in narrow-field mode only the second light-emitting element ED2 can emit light. In wide-field mode, the second mode signal MS2 that controls the emission of the second light-emitting element ED2 can be output only at a high level, which is the turn-off level, so that only the first light-emitting element ED1 emits light. In narrow-field mode, the first mode signal MS1 that controls the emission of the first light-emitting element ED1 can be output only at a high level, which is the turn-off level, so that only the second light-emitting element ED2 emits light.

[0070] Specifically, referring to Figures 2 and 3a, when considering the wide-field mode, a low-level second scan signal SCAN2, a low-level first mode signal MS1, and a low-level light emission signal EM are output during the initial period Ti. The low-level second scan signal SCAN2 can turn on the second transistor T2, the fifth transistor T5, and the sixth transistor T6; the low-level first mode signal MS1 can turn on the fourth transistor T4; and the low-level light emission signal EM can turn on the third transistor T3 and the eighth transistor T8.

[0071] Through the turned-on third transistor T3, the first node N1 can be initialized to the reference voltage Vref. Through the turned-on fifth transistor T5, the voltage at the anode electrode of the first light-emitting element ED1 can be initialized to the reference voltage Vref, and through the turned-on sixth transistor T6, the voltage at the anode electrode of the second light-emitting element ED2 can be initialized to the reference voltage Vref. Then, through the turned-on second transistor T2, the drive transistor DT is diode-connected, and the gate electrode and drain electrode of the drive transistor DT are shorted, causing the drive transistor DT to operate like a diode. Then, the reference voltage Vref transmitted to the anode electrode side of the first light-emitting element ED1 through the turned-on fifth transistor T5 is transmitted to the third node N3 and the second node N2 through the turned-on fourth transistor T4 and eighth transistor T8, so that the fourth node N4, the third node N3 and the second node N2 can also be initialized to the reference voltage Vref.

[0072] Next, during the sampling period Ts, a low-level first scan signal SCAN1 and a low-level second scan signal SCAN2 are output, and the first mode signal MS1 may be output at a high level. When a high-level light emission signal EM is output, the third transistor T3 is turned off, and at the same time, the first transistor T1 is turned on by the low-level first scan signal SCAN1, and the data voltage Vdata may be transmitted to the first node N1. Then, the drive transistor DT is diode-connected by the turned-on second transistor T2, and the difference voltage between the high-potential power supply voltage and the threshold voltage may be sampled and supplied to the second node N2.

[0073] During the holding period Th, the first scan signal SCAN1 and the second scan signal SCAN2 are output at a high level, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may all be turned off. However, even if the first transistor T1 is turned off, the data voltage Vdata input during the previous sampling period Ts may be maintained by the storage capacitor Cst.

[0074] Finally, during the emission period Te, a low-level first-mode signal MS1 and a light emission signal EM are output, and a high-level second-mode signal MS2 is output. A reference voltage Vref is applied to the first node N1 through a third transistor T3 that is turned on by the low-level light emission signal EM, and the voltage at the first node N1 can become the difference voltage between the reference voltage Vref and the data voltage Vdata, and such voltage fluctuations can also be reflected at the second node N2. The drive current can be controlled by setting the gate-source voltage Vgs of the drive transistor DT to a value obtained by subtracting the reference voltage Vref from the data voltage Vdata and adding the data voltage Vdata (Vdata - Vref + Vth).

[0075] Then, the drive current is supplied from the drive transistor DT to the first light-emitting element ED1 through the turned-on fourth transistor T4 and the eighth transistor T8, allowing the first light-emitting element ED1 to emit light. However, the second mode signal MS2 is output at a high level, causing the seventh transistor T7 to turn off, so the drive current cannot be transmitted from the drive transistor DT to the second light-emitting element ED2. Therefore, in wide-field mode, the drive current is applied only to the first light-emitting element ED1, and only the first light-emitting element ED1 can emit light.

[0076] Referring to Figures 2 and 3b, when considering the narrow field mode, the sub-pixel circuit SPC can be driven in substantially the same manner as in the wide field mode, except that the first mode signal MS1 and the second mode signal MS2 are output in opposite directions. That is, the first mode signal MS1 can be output only at a high level, which is the turn-off level, and the second mode signal MS2 can be output at a low level, which is the turn-on level, during the emission period Te in which the second light-emitting element ED2 emits light.

[0077] Specifically, during the initial period Ti, the first scan signal SCAN1 is output at a high level, and the second scan signal SCAN2 is output at a low level. The first mode signal MS1 is output at a high level, and the second mode signal MS2 and the light emission signal EM are output at low levels. Thus, the second scan signal SCAN2 can turn on the second transistor T2, the fifth transistor T5, and the sixth transistor T6; the second mode signal MS2 can turn on the seventh transistor T7; and the light emission signal EM can turn on the third transistor T3 and the eighth transistor T8.

[0078] The first node N1 is initialized to the reference voltage Vref through the third transistor T3, which is turned on by the light emission signal EM, and the anode electrodes of the first light-emitting element ED1 and the second light-emitting element ED2 can be initialized to the reference voltage Vref by the fifth transistor T5 and the sixth transistor T6, which are turned on by the second scan signal SCAN2, respectively. Then, the drive transistor DT is diode-connected through the second transistor T2, which is turned on, and operates like a diode. Finally, the reference voltage Vref transmitted to the anode electrode side of the second light-emitting element ED2 through the sixth transistor T6, which is turned on, is transmitted to the fourth node N4, the third node N3, and the second node N2 through the seventh transistor T7, which is turned on, and the third node N3 and the second node N2 can also be initialized to the reference voltage Vref.

[0079] Next, a low-level first scan signal SCAN1 and a low-level second scan signal SCAN2 are output during the sampling period Ts, and the second mode signal MS2 and the light emission signal EM can be output from low to high levels. When the high-level light emission signal EM is output, the third transistor T3 is turned off, and the low-level first scan signal SCAN1 turns on the first transistor T1, and the data voltage Vdata can be transmitted to the first node N1. Then, the second transistor T2, which has been turned on, diode-connects the drive transistor DT, and the difference voltage between the high-potential power supply voltage and the threshold voltage can be sampled and supplied to the second node N2.

[0080] During the holding period Th, the first scan signal SCAN1 and the second scan signal SCAN2 are output at a high level, and the first transistor T1, the second transistor T2, the fifth transistor T5, and the sixth transistor T6 may all be turned off. However, even if the first transistor T1 is turned off, the data voltage Vdata input during the previous sampling period Ts may be maintained by the storage capacitor Cst.

[0081] Finally, during the emission period Te, a low-level second-mode signal MS2 and a light emission signal EM are output, and a high-level first-mode signal MS1 is output. A reference voltage Vref is applied to the first node N1 through the third transistor T3, which is turned on by the low-level light emission signal EM. The voltage at the first node N1 can become the difference voltage between the reference voltage Vref and the data voltage Vdata, and such voltage fluctuations can also be reflected in the second node N2. The drive current can be controlled by setting the gate-source voltage Vgs of the drive transistor DT to a value obtained by subtracting the reference voltage Vref from the data voltage Vdata and adding the data voltage Vdata (Vdata - Vref + Vth).

[0082] Then, the drive current is supplied from the drive transistor DT to the second light-emitting element ED2 through the turned-on seventh transistor T7, allowing the second light-emitting element ED2 to emit light. However, the first mode signal MS1 is output at a high level, causing the fourth transistor T4 to turn off, so the drive current cannot be transmitted from the drive transistor DT to the first light-emitting element ED1. Therefore, in the narrow field mode, the drive current is applied only to the second light-emitting element ED2, and only the second light-emitting element ED2 can emit light.

[0083] Figures 4a and 4b are cross-sectional views of a display device according to one embodiment of this specification. Specifically, Figure 4a shows a subpixel on which the first lens 161 is located, and Figure 4b shows a subpixel on which the second lens 162 is located.

[0084] Referring to Figures 4a and 4b, the display device 100 according to the embodiment of this specification may include a substrate 110, a buffer film 111, a gate insulating film 112, an interlayer insulating film 113, a lower protective film 114, an overcoat layer 115, a first transistor T1, a second transistor T2, a first light-emitting element ED1, a second light-emitting element ED2, a first lens 161, a second lens 162, a lens protective film 170, and a sealing member 180.

[0085] The substrate 110 may contain an insulating material. The substrate 110 may contain a transparent material. For example, the substrate 110 may contain glass or plastic.

[0086] A buffer film 111 may be placed on the substrate 110. The buffer film 111 may contain an insulating material. For example, the buffer film 111 may contain an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The buffer film 111 may have a multilayer structure. For example, the buffer film 111 may have a laminated structure of a film made of silicon nitride (SiNx) and a film made of silicon oxide (SiOx).

[0087] The buffer film 111 may be located between the substrate 110 and the drive portion of each pixel PX. The buffer film 111 can prevent contamination by the substrate 110 during the formation process of the drive portion. For example, the upper surface of the substrate 110 facing the drive portion of each pixel PX may be covered by the buffer film 111. The drive portion of each pixel PX may be located on the buffer film 111.

[0088] A gate insulating film 112 may be placed on the buffer film 111. The gate insulating film 112 may contain an insulating material. For example, the gate insulating film 112 may contain inorganic insulating materials such as silicon oxide (SiOx) and silicon nitride (SiNx). The gate insulating film 112 may contain a material having a high dielectric constant. For example, the gate insulating film 112 may contain a high-K material such as hafnium oxide (HfO). The gate insulating film 112 may have a multilayer structure.

[0089] The gate insulating film 112 may extend between the semiconductor layers 121, 131 of transistors Tr1, Tr2 and the gate electrodes 122, 132. For example, the gate electrodes of the drive transistor DT and the switching transistor ST may be insulated from the semiconductor layers of the drive transistor DT and the switching transistor ST by the gate insulating film 112. The gate insulating film 112 may cover the semiconductor layer of each pixel PX. The gate electrodes of the drive transistor DT and the switching transistor ST may be located on the gate insulating film 112.

[0090] An interlayer insulating film 113 may be placed on the gate insulating film 112. The interlayer insulating film 113 may contain an insulating material. For example, the interlayer insulating film 113 may contain an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The interlayer insulating film 113 may extend between the gate electrode and source electrode, and between the gate electrode and drain electrode, of the drive transistor DT and the switching transistor, respectively. For example, the source electrode and drain electrode, of the drive transistor DT and the switching transistor, respectively, may be insulated from the gate electrode by the interlayer insulating film 113. The interlayer insulating film 113 may cover the gate electrode, of the drive transistor DT and the switching transistor, respectively. The source electrode and drain electrode of each pixel PX may be located on the interlayer insulating film 113. The gate insulating film 112 and the interlayer insulating film 113 may expose the source region and drain region of each semiconductor pattern located within each pixel PX.

[0091] A lower protective film 114 may be placed on the interlayer insulating film 113. The lower protective film 114 may contain an insulating material. For example, the lower protective film 114 may contain an inorganic insulating material such as silicon oxide (SiOx) and silicon nitride (SiNx). The lower protective film 114 can prevent damage to the drive parts due to external moisture and shock. The lower protective film 114 may extend along the surface of the drive transistor DT and switching transistor ST facing the substrate 110. The lower protective film 114 may be in contact with the interlayer insulating film 113 outside the drive parts located within each pixel PX.

[0092] An overcoat layer 115 may be placed on the lower protective film 114. The overcoat layer 115 may contain an insulating material. The overcoat layer 115 may contain a different material from the lower protective film 114. For example, the overcoat layer 115 may contain an organic insulating material. The overcoat layer 115 can eliminate the steps caused by the drive parts of each pixel PX. For example, the upper surface of the overcoat layer 115 facing the substrate 110 may be a flat surface.

[0093] A first transistor Tr1 and a second transistor Tr2 may be arranged on the substrate 110. The first transistor Tr1 may be electrically connected between the drain electrode of the drive transistor DT and the first lower electrode 141 of the first light-emitting element ED1. The second transistor Tr2 may be electrically connected between the drain electrode of the drive transistor DT and the second lower electrode 151 of the second light-emitting element ED2.

[0094] The first transistor Tr1 may include a first semiconductor layer 121, a first gate electrode 122, a first source electrode 123, and a first drain electrode 124. The first transistor T1 may have the same structure as a switching transistor and a drive transistor DT. For example, the first semiconductor layer 121 may be located between a buffer film 111 and a gate insulating film 112, and the first gate electrode 122 may be located between the gate insulating film 112 and an interlayer insulating film 113. The first source electrode 123 and the first drain electrode 124 may be located between the interlayer insulating film 113 and a lower protective film 114. The first gate electrode 122 may be superimposed on the channel region of the first semiconductor layer 121. The first source electrode 123 may be electrically connected to the source region of the first semiconductor layer 121. The first drain electrode 124 may be electrically connected to the drain region of the first semiconductor layer 121.

[0095] The second transistor T2 may include a second semiconductor layer 131, a second gate electrode 132, a second source electrode 133, and a second drain electrode 134. For example, the second semiconductor layer 131 may be located in the same layer as the first semiconductor layer 121, the second gate electrode 132 may be located in the same layer as the first gate electrode 122, and the second source electrode 133 and the second drain electrode 134 may be located in the same layer as the first source electrode 123 and the first drain electrode 124.

[0096] The first light-emitting element ED1 and the second light-emitting element ED2 of each pixel PX may be arranged on the overcoat layer 115 of the corresponding pixel PX.

[0097] The first light-emitting element ED1 can emit light of a specific color. For example, the first light-emitting element ED1 may include a first lower electrode 141, a first light-emitting layer 142, and a first upper electrode 143 stacked in order on the substrate 110.

[0098] The first lower electrode 141 may include a conductive material. The first lower electrode 141 may include a material having high reflectivity. For example, the first lower electrode 141 may include metals such as aluminum (Al) and silver (Ag). The first lower electrode 141 may have a multilayer structure. For example, the first lower electrode 141 may have a structure in which a reflective electrode made of metal is positioned between transparent electrodes made of transparent conductive materials such as ITO and IZO. The first lower electrode 141 may be electrically connected to the first drain electrode 124 (or first source electrode 123) of the first transistor T1 through contact holes penetrating the lower protective film 114 and the overcoat layer 115.

[0099] The first light-emitting layer 142 can generate light with a brightness corresponding to the voltage difference between the first lower electrode 141 and the first upper electrode 143. For example, the first light-emitting layer 142 may include an Emission Material Layer (EML) containing a light-emitting material. The light-emitting material may be an organic material, an inorganic material, or a hybrid material.

[0100] The first light-emitting layer 142 may have a multilayer structure. For example, the first light-emitting layer 142 may further include at least one of the following: a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL).

[0101] The first upper electrode 143 may contain a conductive material. The first upper electrode 143 may contain a different material from the first lower electrode 141. The transmittance of the first upper electrode 143 may be higher than that of the first lower electrode 141. For example, the first upper electrode 143 may be a transparent electrode made of a transparent conductive material such as ITO and IZO. As a result, in the display device according to the embodiments of this specification, light generated by the first light-emitting layer 142 can be emitted through the first upper electrode 143.

[0102] The second light-emitting element ED2 may have the same structure as the first light-emitting element ED1. For example, the second light-emitting element ED2 may include a second lower electrode 151, a second light-emitting layer 152, and a second upper electrode 153 that are sequentially stacked on the substrate 110.

[0103] The second lower electrode 151 may correspond to the first lower electrode 141, the second light-emitting layer 152 may correspond to the first light-emitting layer 142, and the second upper electrode 153 may correspond to the first upper electrode 143. For example, the second lower electrode 151 may be formed on the second light-emitting element ED2 with the same structure as the first lower electrode 141, and the same applies to the second light-emitting layer 152 and the second upper electrode 153. For example, the first light-emitting element ED1 and the second light-emitting element ED2 may be formed to have the same structure. However, this is not limited to this, and in some cases, at least some of the configurations of the first light-emitting element ED1 and the second light-emitting element ED2 may be formed to be different.

[0104] In the embodiment, the second light-emitting layer 152 can be separated from the first light-emitting layer 142. This prevents light emission due to leakage current in the display device according to the embodiment of this specification.

[0105] In the embodiments of this specification, in the display device, light can be generated in only one of the first light-emitting layer 142 and the second light-emitting layer 152, depending on the user's selection or pre-specified conditions.

[0106] The second lower electrode 151 of each pixel PX may be separated from the first lower electrode 141 of the corresponding pixel PX. For example, a bank insulating film 116 may be placed between the first lower electrode 141 and the second lower electrode 151 of each pixel PX. The bank insulating film 116 may include an insulating material. For example, the bank insulating film 116 may include an organic insulating material. The bank insulating film 116 may include a different material from the overcoat layer 115.

[0107] The second lower electrode 151 of each pixel PX can be insulated from the first lower electrode 141 of the corresponding pixel PX by a bank insulating film 116. For example, the bank insulating film 116 can cover the edges of the first lower electrode 141 and the second lower electrode 151 located within each pixel PX. As a result, the display device can provide the user with an image from the first lens region of each pixel PX where the first light-emitting element ED1 is located, or an image from the second lens region of each pixel PX where the second light-emitting element ED2 is located.

[0108] The first light-emitting layer 142 and first upper electrode 143 of the first light-emitting element ED1 located within each pixel PX can be stacked on a portion of the corresponding first lower electrode 141 exposed by the bank insulating film 116. The second light-emitting layer 152 and second upper electrode 153 of the second light-emitting element ED2 located within each pixel PX can be stacked on a portion of the corresponding second lower electrode 151 exposed by the bank insulating film 116. For example, the bank insulating film 116 can divide each pixel PX into a first light-emitting region where light from the first light-emitting element ED1 is emitted and a second light-emitting region where light from the second light-emitting element ED2 is emitted. The size of the second light-emitting region divided within each pixel PX may be smaller than the size of the first light-emitting region.

[0109] The second upper electrode 153 of each pixel PX can be electrically connected to the first upper electrode 143 of the corresponding pixel PX. For example, the voltage applied to the second upper electrode 153 of the second light-emitting element ED2 located within each pixel PX may be the same as the voltage applied to the first upper electrode 143 of the first light-emitting element ED1 located within the corresponding pixel PX. The second upper electrode 153 of each pixel PX may contain the same material as the first upper electrode 143 of the corresponding pixel PX. For example, the second upper electrode 153 of each pixel PX may be formed simultaneously with the first upper electrode 143 of the corresponding pixel PX. The second upper electrode 153 of each pixel PX may extend onto the bank insulating film 116 and directly contact the first upper electrode 143 of the corresponding pixel PX. The brightness of the first lens region and the brightness of the second lens region located within each pixel PX can be controlled by the drive current generated in the corresponding pixel PX.

[0110] A sealing member 180 may be positioned on the first light-emitting element ED1 and the second light-emitting element ED2 of each pixel PX. The sealing member 180 can prevent damage to the light-emitting elements ED1 and ED2 from external moisture and impact. The sealing member 180 may have a multilayer structure. For example, the sealing member 180 may include, but is not limited to, a first sealing layer 181, a second sealing layer 182, and a third sealing layer 183 stacked in order. The first sealing layer 181, the second sealing layer 182, and the third sealing layer 183 may contain insulating materials. The second sealing layer 182 may contain a different material from the first sealing layer 181 and the third sealing layer 183. For example, the first sealing layer 181 and the third sealing layer 183 may be inorganic sealing layers containing an inorganic insulating material, and the second sealing layer 182 may be an organic sealing layer containing an organic insulating material. This allows the light-emitting elements ED1 and ED2 of the display device to be more effectively protected from damage from external moisture and impact.

[0111] A first lens 161 and a second lens 162 may be located on the sealing member 180 of each pixel PX. On the other hand, the term "lens" as used herein is used for convenience of explanation and may also be defined as "optical element" instead of "lens".

[0112] The first lens 161 may be positioned on the first light-emitting element ED1. Light generated by the first light-emitting element ED1 of each pixel PX may be emitted through the first lens 161 of the corresponding pixel PX. The first lens 161 may have a shape that does not restrict light in at least one direction. For example, the planar shape of the first lens 161 located within each pixel PX may have a bar shape extending in a first direction.

[0113] In such cases, the direction of light emitted from the first lens area of ​​the pixel PX does not need to be restricted to the first direction. For example, content (or images) provided through the first lens area of ​​the pixel PX can be shared with the user and people in the surrounding area adjacent to them in the first direction. When content is provided through the first lens area, the mode in which content is provided in a first field of view range that is wider than the second field of view range provided by the second lens area may be called a wide-field mode, which is the first mode.

[0114] The second lens 162 may be positioned on the second light-emitting element ED2. Light generated by the second light-emitting element ED2 of each pixel PX may be emitted through the second lens 162 of the corresponding pixel PX. The second lens 162 may restrict the direction of light propagation to a first direction and / or a second direction. For example, the planar shape of the second lens 162 located within the pixel PX may be circular. In such a case, the direction of light propagation emitted in the second lens region of the pixel PX may be restricted to a first direction and a second direction. For example, content provided by the second lens region of the pixel PX does not need to be shared with people around the user. When content is provided through the second lens region, this may be referred to as a narrow-field mode, which is a second mode in which content is provided in a second field of view range that is narrower than the first field of view range provided by the first lens region.

[0115] The first light-emitting region of each pixel PX may have a shape corresponding to the first lens 161 of that pixel PX. For example, the planar shape of the first light-emitting region of each pixel PX may have a bar shape extending in a first direction. The first lens 161 may be larger than the first light-emitting region of that pixel PX. This may improve the efficiency of the light emitted from the first light-emitting region of the pixel PX.

[0116] The second light-emitting region of each pixel PX may have a shape corresponding to the second lens 162 of that pixel PX. For example, the planar shape of the second light-emitting region of each pixel PX may be circular. The second lens 162 may be larger than the second light-emitting region of that pixel PX. This may improve the efficiency of the light emitted from the second light-emitting region of the pixel PX.

[0117] In the embodiment, a lens protective film 170 may be located on the first lens 161 and the second lens 162 of the pixel PX. The lens protective film 170 may contain an insulating material. For example, the lens protective film 170 may contain an organic insulating material. The refractive index of the lens protective film 170 may be smaller than the refractive index of the first lens 161 and the second lens 162 located within each pixel PX. This prevents light passing through the first lens 161 and the second lens 162 of each pixel PX from being reflected towards the substrate 110 due to the refractive index difference with the lens protective film 170.

[0118] Figure 5 is a plan view of a display device according to one embodiment of this specification. In Figure 5, for the sake of explanation, only the display panel PN, multiple flexible films COF, and multiple printed circuit boards PCBs are shown among the various components of the display device 100.

[0119] Referring to Figure 5, the display device 100 includes multiple flexible films (COF), multiple printed circuit boards (PCB), and a display panel (PN).

[0120] Multiple flexible film COFs can be arranged at one end of a display panel PN. Each flexible film COF has various components arranged on a ductile base film and is a film for supplying signals to multiple pixels PX and drive circuits, and can be electrically connected to the display panel PN. For example, multiple flexible film COFs can supply power voltage, data voltage Vdata, etc., to multiple pixels PX and drive circuits.

[0121] On the other hand, multiple flexible film COFs may contain drive ICs, such as data driver ICs. These drive ICs are components that process data for displaying images and drive signals for processing that data. Depending on the mounting method, the drive ICs may be implemented in chip-on-glass (COG), chip-on-film (COF), or tape carrier packages (TCP). However, for the sake of explanation, it has been described as a chip-on-film configuration where the drive ICs are mounted on multiple flexible film COFs, but the system is not limited to this configuration. Furthermore, the drive ICs may be integrated with a timing controller and placed on a single chip.

[0122] On the other hand, the drive IC may be equipped with multiple mode control units that control the driving of the wide-field mode and the narrow-field mode. The mode control units can provide signals to control the modes of multiple sub-pixels SP to the multiple sub-pixels SP. The multiple mode control units can provide a first mode selection signal to control the first mode through a first mode selection signal wiring MCSL1. They can also provide a second mode selection signal to control the second mode through a second mode selection signal wiring MCSL2. The mode control units may be defined as components included in the timing controller TC, or as components separate from the timing controller TC.

[0123] Each of the multiple printed circuit boards (PCBs) is electrically connected to multiple flexible film (COFs). The multiple PCBs are components that supply signals to the drive ICs. The multiple PCBs may contain various components for supplying diverse signals, such as drive signals and data signals, to the drive ICs.

[0124] The display panel PN may include a display area AA and a non-display area NA surrounding the display area AA. The display area AA of the display panel PN includes multiple areas a divided in the row direction. These multiple areas a may be areas of pixels PX to which the same mode signal is applied. On the other hand, in Figure 5, the display area AA is shown to be divided into 12 areas a extending in the column direction, but it is not limited to this.

[0125] The display panel PN may include a first mode selection signal wiring MCSL1 and a second mode selection signal wiring MCSL2 that extend in rows or columns across multiple regions a. The first mode selection signal wiring MCSL1 and the second mode selection signal wiring MCSL2 are each connected to a mode control unit and can transmit the first mode selection signal and the second mode selection signal to multiple regions a. The first mode selection signal transmitted by the first mode selection signal wiring MCSL1 and the second mode selection signal transmitted by the second mode selection signal wiring MCSL2 can each be output as a first mode signal MS1 and a second mode signal MS2, respectively, after their voltages are changed by a level shift described later. Therefore, the first mode selection signal wiring MCSL1 may also be called a wide-field mode selection signal wiring, and the second mode selection signal wiring MCSL2 may also be called a narrow-field mode selection signal wiring. On the other hand, although Figure 5 shows multiple first mode selection signal wirings MCSL1 and multiple second mode selection signal wirings MCSL2 extending in columns across multiple regions a, it is not limited to this and can extend in rows.

[0126] Figure 6 is a schematic enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. In Figure 6, a portion of one of the multiple areas a in Figure 5 is shown, for example, an area corresponding to a total of 12 pixels PX.

[0127] Referring to Figure 6, the display area AA is arranged to provide mode signals to multiple sub-pixels SP. The level shift LS can provide mode signals MS1 and MS2 to the multiple sub-pixels SP, which control the drive mode of the display panel PN so that the multiple sub-pixels SP are driven in either a first mode or a second mode. Specifically, the level shift LS can change the output voltages of the first mode selection signal and the second mode selection signal. For example, the level shift LS can change a low voltage output by the mode control unit, such as a logic voltage of 1.8V or 3.3V, to a higher voltage, such as a value within the range of VGL (-9.0V) to VGH (15.0V). That is, the level shift LS can provide a first mode signal or a second mode signal by changing the output voltages of the first mode selection signal and the second mode selection signal provided by the mode control unit. For example, the level shift LS includes a first level shift LS1 that provides the first mode signal MS1 and a second level shift LS2 that provides the second mode signal MS2. Therefore, the first level shift LS1 is called a wide-field mode level shift because it provides a first mode signal MS1 that controls the drive mode to a wide-field mode, and the second level shift LS2 is called a narrow-field mode level shift because it provides a second mode signal MS2 that controls the drive mode to a narrow-field mode.

[0128] The first level shift LS1 and the second level shift LS2 can each be placed one at a time in each of the multiple regions a. That is, the first level shift LS1 and the second level shift LS2 can each transmit mode signals separately for each of the multiple regions a. For example, the first level shift LS1 and the second level shift LS2 can each consist of the same number as the multiple regions a, and one can be placed in each of the multiple regions a.

[0129] Multiple regions a include pixel PX and non-pixel regions NPX. Pixel PX includes multiple sub-pixels SP. Non-pixel regions NPX can be located between adjacent pixel PX. Non-pixel regions NPX can refer to regions where no sub-pixels SP are located.

[0130] The first level shift LS1 and the second level shift LS2 are placed between adjacent pixels PX. For example, if a region a contains 12 pixels PX, the first level shift LS1 and the second level shift LS2 may be placed with 6 pixels PX spaced apart. On the other hand, in Figure 6, three pixels PX are shown in the same row and two pixels PX are shown in the same column, but this is only illustrative and not limiting.

[0131] On the other hand, the first level shift LS1 and the second level shift LS2 may be placed in the non-pixel area NPX between pixels PX, respectively. However, this is not limited to this, and if a single area a contains three or more pixels PX, the first level shift LS1 and the second level shift LS2 may be placed in two locations between multiple adjacent pixels PX, respectively.

[0132] Figure 7 is a circuit diagram of the first level shift of a display device according to one embodiment of this specification.

[0133] Referring to Figure 7, the first level shift LS1 includes the 11th transistor T11, the 12th transistor T12, the 13th transistor T13, the 14th transistor T14, the 15th transistor T15, the 16th transistor T16, the 17th transistor T17, the 11th capacitor C11, and the 12th capacitor C12.

[0134] On the other hand, as mentioned above, the first level shift LS1 is located within the display area AA, so it can share signal wiring with multiple sub-pixel circuits SPC. That is, the first level shift LS1 can share the first scan signal wiring, the second scan signal wiring, and the light emission signal wiring with the sub-pixel circuits SPC.

[0135] The 11th transistor T11 through the 17th transistor T17 may be p-type thin-film transistors. In the case of p-type thin-film transistors, the low-level voltage of each drive signal may represent the voltage that turns the TFT on, and the high-level voltage of each drive signal may represent the voltage that turns the TFT off.

[0136] The 11th transistor T11 includes a gate electrode connected to the first scan signal wiring, a source electrode connected to the second mode selection signal wiring, and a drain electrode connected to the 11th node N11, which is the first electrode of the 11th capacitor C11. Thus, the 11th transistor T11 can be turned on or turned off by the first scan signal SCAN1 and can transmit the second mode selection signal MCS2 to the 11th node N11, which is the first electrode of the 11th capacitor C11.

[0137] The 12th transistor T12 includes a gate electrode connected to the first scan signal wiring, a source electrode connected to the first mode selection signal wiring, and a drain electrode connected to the 12th node N12, which is the second electrode of the 11th capacitor C11. Thus, the 12th transistor T12 can be turned on or turned off by the first scan signal SCAN1 and can transmit the first mode selection signal MCS1 to the 12th node N12, which is the second electrode of the 11th capacitor C11.

[0138] The 13th transistor T13 includes a gate electrode connected to the second scan signal wiring, a source electrode connected to the second mode selection signal wiring, and a drain electrode connected to the 13th node N13, which is the first electrode of the 12th capacitor C12. Thus, the 13th transistor T13 can be turned on or turned off by the second scan signal SCAN2 and can transmit the second mode selection signal MCS2 to the 13th node N13, which is the first electrode of the 12th capacitor C12.

[0139] The 14th transistor T14 includes a gate electrode connected to the first scan signal wiring, a source electrode connected to the first mode selection signal wiring, and a drain electrode connected to the 14th node N14, which is the second electrode of the 12th capacitor C12. Thus, the 14th transistor T14 can be turned on or turned off by the first scan signal SCAN1 and can transmit the first mode selection signal MCS1 to the 14th node N14, which is the second electrode of the 12th capacitor C12.

[0140] The 15th transistor T15 includes a gate electrode connected to the second scan signal wiring, a source electrode connected to the first mode selection signal wiring, and a drain electrode connected to the 15th node N15. Thus, the 15th transistor T15 can be turned on or turned off by the second scan signal SCAN2 and can transmit the first mode selection signal MCS1 to the 14th node N14, which is the second electrode of the 12th capacitor C12.

[0141] The 16th transistor T16 includes a gate electrode connected to the light-emitting signal wiring, a source electrode connected to the reference wiring that transmits the reference voltage Vref, and a drain electrode connected to the 15th node N15. Thus, the 16th transistor T16 can be turned on or turned off by the light-emitting signal EM and can transmit the reference voltage Vref to the 14th node N14, which is the second electrode of the 12th capacitor C12.

[0142] The 17th transistor T17 includes a gate electrode connected to the light-emitting signal wiring, a source electrode connected to the 11th node N11, which is the first electrode of the 11th capacitor C11, and a drain electrode connected to a plurality of sub-pixels SP. Thus, the 17th transistor T17 can be turned on or turned off by the light-emitting signal EM and can transmit the first mode signal MS1 to the plurality of sub-pixels SP.

[0143] The 11th capacitor C11 includes a first electrode connected to the 11th node N11 and a second electrode connected to the 12th node N12. The 12th capacitor C12 includes a first electrode connected to the 13th node N13 and a second electrode connected to the 14th node N14. On the other hand, the 11th capacitor C11 and the 12th capacitor C12 may be connected in series.

[0144] Figure 8 is a waveform diagram illustrating the first level shift circuit of a display device according to one embodiment of this specification. Figure 9a is a circuit diagram of the first level shift of a display device according to one embodiment of the present invention during a first period in wide-view mode. Figure 9b is a circuit diagram of the first level shift of a display device according to one embodiment of the present invention during a second period in wide-view mode. Figure 9c is a circuit diagram of the first level shift of a display device according to one embodiment of the present invention during a third period in wide-view mode. Hereinafter, the voltage value corresponding to the first mode selection signal MCS1 may be referred to as the first voltage "V1", and the voltage value corresponding to the second mode selection signal MCS2 may be referred to as the second voltage "V2".

[0145] Referring to both Figure 8 and Figure 9a, in wide-field mode, a low-level first scan signal SCAN1 and a low-level second mode selection signal MCS2 may be output during the first period TP1. Thus, the low-level first scan signal SCAN1 can turn on the 11th transistor T11, the 12th transistor T12, and the 14th transistor T14.

[0146] A second voltage, "V2", can be applied to the 11th node N11 by the 11th transistor T11 being turned on. A first voltage, "V1", can be applied to the 12th node N12 by the 12th transistor T12 being turned on. A first voltage, "V1", can be applied to the 14th node N14 by the 14th transistor T14 being turned on.

[0147] Therefore, during the first period TP1, the voltage at the 11th node N11 may be "V2", and the voltages at the 12th node N12 and the 13th node N13 may be "V1". In addition, the 11th capacitor C11 can store the voltage difference between its two electrodes, i.e., the voltage difference between the 11th node N11 and the 12th node N12, which is "V2-V1".

[0148] Next, referring to both Figure 8 and Figure 9b, a low-level second scan signal SCAN2 and a low-level second mode selection signal MCS2 may be output during the second period TP2. Thus, the low-level second scan signal SCAN2 can turn on the 13th transistor T13 and the 15th transistor T15.

[0149] A second voltage, "V2", can be applied to the 13th node N13 by turning on the 13th transistor T13. A first voltage, "V1", can be applied to the 15th node N15 by turning on the 15th transistor T15.

[0150] At this point, the 12th node N12 and the 13th node N13 will have the same voltage, so the voltage at the 12th node N12 may be "V2". Also, the voltage at the 11th node N11 is the sum of the voltage at the 12th node N12, "V2", and the voltage stored in the 11th capacitor C11, "V2-V1", so the voltage at the 11th node N11 may be "V2+(V2-V1)". Also, the voltages at the 14th node N14 and the 15th node N15 will have the same voltage, so the voltage at the 14th node N14 may be "V1". Furthermore, the 12th capacitor C12 can store the voltage difference between its two electrodes, i.e., the voltage difference between the 13th node N13 and the 14th node N14, which is "V2-V1".

[0151] Finally, referring to both Figure 8 and Figure 9c, a low-level light emission signal EM and a low-level first mode selection signal MCS1 may be output during the third period T3. Thus, the low-level light emission signal EM can turn on the 16th transistor T16 and the 17th transistor T17.

[0152] A reference voltage Vref can be applied to the 15th node N15 by the 16th transistor T16 which is turned on. A first-mode signal MS1 can be output to multiple sub-pixels SP by the 17th transistor T17 which is turned on.

[0153] At this point, the 14th node N14 and the 15th node N15 will have the same voltage, so the voltage at the 14th node N14 may be "Vref". Also, the voltage at the 13th node N13 is the sum of the voltage at the 14th node N14, "Vref", and the voltage stored in the 12th capacitor C12, "V2-V1", so the voltage at the 13th node N13 may be "V2+(Vref-V1)". Also, the voltages at the 12th node N12 and the 13th node N13 will have the same voltage, so the voltage at the 12th node N12 may be "V2+(Vref-V1)". Furthermore, since the voltage at the 11th node N11 is the sum of the voltage at the 12th node N12, "V2 + (Vref - V1)", and the voltage stored in the 11th capacitor C11, "V2 - V1", the voltage at the 11th node N11 may be "V2 + (V2 - V1) + (Vref - V1)".

[0154] At this time, the first mode signal MS1 can be output through the 17th transistor T17 connected to the 11th node N11. That is, the voltage at the 11th node N11, "V2 + (V2 - V1) + (Vref - V1)", may be the voltage value of the first mode signal MS1, and since the low-level first mode signal MS1 is a turn-on signal, the second voltage value "V2" can be set to be smaller than the first voltage value "V1".

[0155] Figure 10 is a circuit diagram of the second level shift of a display device according to one embodiment of this specification.

[0156] Referring to Figure 10, the second level shift LS2 includes the 21st transistor T21, the 22nd transistor T22, the 23rd transistor T23, the 24th transistor T24, the 25th transistor T25, the 26th transistor T26, the 27th transistor T27, the 21st capacitor C21, and the 22nd capacitor C22.

[0157] On the other hand, since the second level shift LS2 is located within the display area, it can share signal wiring with multiple sub-pixel circuits SPC. That is, the second level shift LS2 can share the first scan signal wiring, second scan signal wiring, and light emission signal wiring of the display panel with the sub-pixel circuits SPC.

[0158] The 21st transistor T21 through the 27th transistor T27 may be p-type thin-film transistors. In the case of p-type thin-film transistors, the low-level voltage of each drive signal may represent the voltage that turns the TFT on, and the high-level voltage of each drive signal may represent the voltage that turns the TFT off.

[0159] The 21st transistor T21 includes a gate electrode connected to the first scan signal wiring, a source electrode connected to the first mode selection signal wiring, and a drain electrode connected to the 21st node N21, which is the first electrode of the 21st capacitor C21. Thus, the 21st transistor T21 can be turned on or turned off by the first scan signal SCAN1 and can transmit the first mode selection signal MCS1 to the 21st node N21, which is the first electrode of the 21st capacitor C21.

[0160] The 22nd transistor T22 includes a gate electrode connected to the first scan signal wiring, a source electrode connected to the second mode selection signal wiring, and a drain electrode connected to the 22nd node N22, which is the second electrode of the 21st capacitor C21. Thus, the 22nd transistor T22 can be turned on or turned off by the first scan signal SCAN1 and can transmit the second mode selection signal MCS2 to the 22nd node N22, which is the second electrode of the 21st capacitor C21.

[0161] The 23rd transistor T23 includes a gate electrode connected to the second scan signal wiring, a source electrode connected to the first mode selection signal wiring, and a drain electrode connected to the 23rd node N23, which is the first electrode of the 22nd capacitor C22. Thus, the 23rd transistor T23 can be turned on or turned off by the second scan signal SCAN2 and can transmit the first mode selection signal MCS1 to the 23rd node N23, which is the first electrode of the 22nd capacitor C22.

[0162] The 24th transistor T24 includes a gate electrode connected to the first scan signal wiring, a source electrode connected to the second mode selection signal wiring, and a drain electrode connected to the 24th node N24, which is the second electrode of the 22nd capacitor C22. Thus, the 24th transistor T24 can be turned on or turned off by the first scan signal SCAN1 and can transmit the second mode selection signal MCS2 to the 24th node N24, which is the second electrode of the 22nd capacitor C22.

[0163] The 25th transistor T25 includes a gate electrode connected to the second scan signal wiring, a source electrode connected to the second mode selection signal wiring, and a drain electrode connected to the 25th node N25. Thus, the 25th transistor T25 can be turned on or turned off by the second scan signal SCAN2 and can transmit the second mode selection signal MCS2 to the 24th node N24, which is the second electrode of the 22nd capacitor C22.

[0164] The 26th transistor T26 includes a gate electrode connected to the light-emitting signal wiring, a source electrode connected to the reference wiring that transmits the reference voltage Vref, and a drain electrode connected to the 25th node N25. Thus, the 26th transistor T26 can be turned on or turned off by the light-emitting signal EM and can transmit the reference voltage Vref to the 24th node N24, which is the second electrode of the 22nd capacitor C22.

[0165] The 27th transistor T27 includes a gate electrode connected to the light-emitting signal wiring, a source electrode connected to the 21st node N21, and a drain electrode connected to a plurality of sub-pixels SP. Thus, the 27th transistor T27 can be turned on or turned off by the light-emitting signal EM and can transmit the second mode signal MS2 to the plurality of sub-pixels SP.

[0166] The 21st capacitor C21 includes a first electrode connected to the 21st node N21 and a second electrode connected to the 22nd node N22. The 22nd capacitor C22 includes a first electrode connected to the 23rd node N23 and a second electrode connected to the 24th node N24. On the other hand, the 21st capacitor C21 and the 22nd capacitor C22 may be connected in series.

[0167] Figure 11 is a waveform diagram illustrating the second level shift circuit of a display device according to one embodiment of this specification. Figure 12a is a circuit diagram of the second level shift of a display device according to one embodiment of the present invention during the first period in narrow field of view mode. Figure 12b is a circuit diagram of the second level shift of a display device according to one embodiment of the present invention during the second period in narrow field of view mode. Figure 12c is a circuit diagram of the second level shift of a display device according to one embodiment of the present invention during the third period in narrow field of view mode. Hereinafter, the voltage value corresponding to the first mode selection signal MCS1 may be referred to as the first voltage "V1", and the voltage value corresponding to the second mode selection signal MCS2 may be referred to as the second voltage "V2".

[0168] Referring to Figures 11 and 12a, in narrow field mode, a low-level first scan signal SCAN1 and a low-level first mode selection signal MCS1 may be output during the first period TP1. Thus, the low-level first scan signal SCAN1 can turn on the 21st transistor T21, the 22nd transistor T22, and the 24th transistor T24.

[0169] A first voltage, "V1", can be applied to the 21st node N21 by the 21st transistor T21 when it is turned on. A second voltage, "V2", can be applied to the 22nd node N22 by the 22nd transistor T22 when it is turned on. A second voltage, "V2", can be applied to the 24th node N24 by the 24th transistor T24 when it is turned on.

[0170] Next, referring to Figures 11 and 12b, a low-level second scan signal SCAN2 and a low-level first mode selection signal MCS1 may be output during the second period TP2. Thus, the low-level second scan signal SCAN2 can turn on the 23rd transistor T23 and the 25th transistor T25.

[0171] A first voltage, "V1", can be applied to the 23rd node N23 by the 23rd transistor T23 being turned on. A second voltage, "V2", can be applied to the 25th node N25 by the 25th transistor T25 being turned on.

[0172] At this point, the 22nd node N22 and the 23rd node N23 will have the same voltage, so the voltage at the 22nd node N22 may be "V1". Also, the voltage at the 21st node N21 is the sum of the voltage at the 22nd node N22, "V1", and the voltage stored in the 21st capacitor C21, "V1-V2", so the voltage at the 21st node N21 may be "V1+(V1-V2)". Also, the voltages at the 24th node N24 and the 25th node N25 will have the same voltage, so the voltage at the 24th node N24 may be "V2". Furthermore, the 22nd capacitor C22 can store the voltage difference between its two electrodes, i.e., the voltage difference between the 23rd node N23 and the 24th node N24, which is "V1-V2".

[0173] Finally, referring to Figures 11 and 12c, a low-level light emission signal EM and a low-level second mode selection signal MCS2 may be output during the third period TP3. Thus, the low-level light emission signal EM can turn on the 26th transistor T26 and the 27th transistor T27.

[0174] A reference voltage Vref can be applied to the 25th node N25 by the turned-on 26th transistor T26. A second-mode signal MS2 can be output by the turned-on 27th transistor T27.

[0175] At this point, the 24th node N24 and the 25th node N25 will have the same voltage, so the voltage at the 24th node N24 may be "Vref". Also, the voltage at the 23rd node N23 is the sum of the voltage at the 24th node N24, "Vref", and the voltage stored in the 22nd capacitor C22, "V1-V2", so the voltage at the 23rd node N23 may be "V1+(Vref-V2)". Also, the voltages at the 22nd node N22 and the 23rd node N23 will have the same voltage, so the voltage at the 22nd node N22 may be "V1+(Vref-V2)". Furthermore, since the voltage at the 21st node N21 is the sum of the voltage at the 22nd node N22, "V1 + (Vref - V2)", and the voltage stored in the 21st capacitor C21, "V1 - V2", the voltage at the 21st node N21 may be "V1 + (V1 - V2) + (Vref - V2)".

[0176] At this time, the second mode signal MS2 can be output through the 27th transistor T27 connected to the 21st node N21. That is, the voltage at the 21st node N21, "V1 + (V1 - V2) + (Vref - V2)", may be the voltage value of the second mode signal MS2, and since the low-level second mode signal MS2 is a turn-on signal, the first voltage value "V1" may be set to be smaller than the second voltage value "V2".

[0177] On the other hand, to achieve diverse viewing angles, the display device can be driven in either a wide-view mode or a narrow-view mode depending on the region. Generally, a control signal is output from a mode control unit that controls the wide-view mode or narrow-view mode drive, and this signal can be transmitted to the display panel after being changed to the desired voltage through a level shifter. This is because the voltage output from the mode control unit is usually a low voltage of about 1.8V or 3.3V, while the voltage of the control signal used for the display panel is a high voltage, such as a VGH voltage of 10.0V or higher and a VGL voltage of -9.0V or lower. In other words, since there is a difference between the voltage output from the mode control unit and the voltage used for the display panel, a separate level shift IC is required to change the low control voltage to a high control voltage. In this case, the use of a separate IC increases manufacturing costs, or the bezel increases in order to secure space for the level shift IC. Also, since the output channel of a single level shift IC is limited, one or more level shift ICs may be required to achieve diverse viewing angles. In this case, there is a problem of increased complexity in wiring routing due to further wiring connections.

[0178] Therefore, in the display device 100 according to one embodiment of this specification, the level shift LS is arranged in the display area AA. That is, since there is no need to arrange a separate level shift IC in the flexible film COF, manufacturing costs can be reduced. In addition, since there is no need to reserve space in the non-display area NA for wiring to connect the separate IC and the display panel PN, the area of ​​the non-display area NA can be minimized. That is, a narrow bezel can be realized.

[0179] Furthermore, in the display device 100 according to one embodiment of this specification, the level shift LS can share the first scan signal wiring, second scan signal wiring, and light emission signal wiring located on the display panel PN with the sub-pixel circuit SPC. This minimizes the increase in bezel due to further wiring arrangements and minimizes the complexity of the design due to further wiring arrangements. In addition, the number of level shift LS located within the display area AA and the wiring added to drive the level shift LS can be minimized, and the area that must be reserved within the display area AA as the level shift LS is located within the display area AA can also be minimized.

[0180] Furthermore, in the display device 100 according to one embodiment of this specification, the level shift LS includes a first level shift LS1 that transmits a first mode signal MS1 and a second level shift LS2 that transmits a second mode signal MS2. In this case, the first level shift LS1 and the second level shift LS2 are arranged for each of the multiple divided regions a of the display region AA. Thus, in the display device 100 according to one embodiment of this specification, the wide-view mode and the narrow-view mode can be controlled independently for each of the multiple regions a. That is, in the display device 100 according to one embodiment of this specification, the level shift LS are arranged for each region of the subpixel SP, and the viewing angle can be freely and selectively limited for each of the multiple regions. That is, in the display device 100 according to one embodiment of this specification, only a specific region of the screen can be selectively switched to either the wide-view mode or the narrow-view mode to selectively limit the viewing angle, and the regions driven in the wide-view mode and the narrow-view mode can be varied.

[0181] The various embodiments of this specification may be described as follows.

[0182] A display device according to one embodiment of this specification includes a display panel including a display area on which a plurality of subpixels are arranged and a non-display area surrounding the display area, and a plurality of level shifts arranged in the display area and transmitting mode signals so that the plurality of subpixels are driven in either a first mode or a second mode, each of the plurality of subpixels including a first light-emitting element, a first optical member that refracts light from the first light-emitting element, a second light-emitting element, and a second optical member that refracts light from the second light-emitting element and has a different shape from the first optical member.

[0183] According to other features of this specification, the multiple level shifts include a multiple first level shifts that transmit a first mode signal and a multiple second level shifts that transmit a second mode signal, the display area includes a multiple area divided in the row or column direction, and the multiple first level shifts and the multiple second level shifts may each be arranged one by one in the multiple area.

[0184] According to other features of this specification, multiple level shifts can transmit mode signals in multiple regions.

[0185] According to other features of this specification, a plurality of subpixels may include a plurality of subpixel circuits, and the first level shift and the second level shift may share signal wiring with the plurality of subpixel circuits.

[0186] According to other features of this specification, the display panel includes a first scan signal wiring, a second scan signal wiring, and an emission signal wiring, and the plurality of subpixel circuits may include a drive transistor, a first transistor for applying a data voltage to a capacitor, a second transistor for diode-connecting the gate electrode and drain electrode of the drive transistor, a third transistor for applying a reference voltage to a capacitor, a fourth transistor for forming a current path between the drive transistor and the first light-emitting element, a fifth transistor for applying a reference voltage to the anode electrode of the first light-emitting element, a sixth transistor for applying a reference voltage to the anode electrode of the second light-emitting element, a seventh transistor for forming a current path between the drive transistor and the second light-emitting element, and an eighth transistor for connecting the drive transistor to the fourth and seventh transistors.

[0187] According to other features of this specification, in the first mode, the fourth transistor may be turned on and the seventh transistor may be turned off, and in the second mode, the fourth transistor may be turned off and the seventh transistor may be turned on.

[0188] According to other features of this specification, the first level shift circuit may include a first capacitor, a second capacitor connected in series with the first capacitor, a first transistor connected to a first scan signal wiring and transmitting a second mode selection signal to the first electrode of the first capacitor, a second transistor connected to the first scan signal wiring and transmitting a first mode selection signal to the second electrode of the first capacitor, a third transistor connected to the second scan signal wiring and transmitting a second mode selection signal to the first electrode of the second capacitor, a fourth transistor connected to the first scan signal wiring and transmitting a first mode selection signal to the second electrode of the second capacitor, a fifth transistor connected to the second scan signal wiring and transmitting a first mode selection signal to the second electrode of the second capacitor, a sixth transistor connected to a light emission signal wiring and transmitting a reference voltage to the second electrode of the second capacitor, and a seventh transistor connected to a light emission signal wiring and outputting a first mode signal.

[0189] According to other features of this specification, the first level shift circuit is driven in a divided first, second, and third period, during the first period the first scan signal and the second mode selection signal are turn-on signals, during the second period the second scan signal and the second mode selection signal are turn-on signals, and during the third period the light emission signal and the first mode selection signal are turn-on signals.

[0190] According to other features of this specification, the second level shift circuit may include a first transistor connected to a first scan signal wiring and transmitting a first mode selection signal to the first electrode of a first capacitor; a second transistor connected to the first scan signal wiring and transmitting a second mode selection signal to the second electrode of a first capacitor; a third transistor connected to the second scan signal wiring and transmitting a first mode selection signal to the first electrode of a second capacitor; a fourth transistor connected to the first scan signal wiring and transmitting a second mode selection signal to the second electrode of a second capacitor; a fifth transistor connected to the second scan signal wiring and transmitting a second mode selection signal to the second electrode of a second capacitor; a sixth transistor connected to a light emission signal wiring and transmitting a reference voltage to the second electrode of a second capacitor; and a seventh transistor connected to a light emission signal wiring and outputting a second mode signal.

[0191] According to other features of this specification, the second level shift circuit is driven in a divided first, second, and third period, during the first period the first scan signal and the first mode selection signal are turn-on signals, during the second period the second scan signal and the first mode selection signal are turn-on signals, and during the third period the light emission signal and the second mode selection signal are turn-on signals.

[0192] According to other features of this specification, the display panel further includes a plurality of mode control units located in a non-display area, The system may further include a first mode selection signal wiring that extends in the row or column direction across multiple regions, is connected to a mode control unit, and transmits a first mode selection signal to multiple subpixels, and a second mode selection signal wiring that extends in the row or column direction across multiple regions, is connected to a mode control unit, and transmits a second mode selection signal to multiple subpixels.

[0193] According to other features of this specification, the display panel includes a drive transistor and first to eighth transistors, and each of the multiple subpixels is driven in an initial period, a sampling period, a holding period and an emission period, during the initial period the voltage of the gate electrode of the drive transistor is initialized, during the sampling period the threshold voltage of the drive transistor is sampled and the anode electrode of the first light-emitting element and the anode electrode of the second light-emitting element are initialized, respectively, during the holding period the first to eighth transistors are turned off, and during the emission period a drive current is applied to the first light-emitting element and the second light-emitting element, respectively, so that the first light-emitting element and the second light-emitting element, respectively, can emit light.

[0194] According to other features of this specification, in a first mode, the first light-emitting element emits light, and the light from the first light-emitting element is output with its viewing angle limited in a first direction and a second direction by the first optical member, and in a second mode, the second light-emitting element emits light, and the light from the second light-emitting element is output with its viewing angle limited only in the first direction by the second optical member.

[0195] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to these embodiments and can be modified and implemented in various ways within the scope of the technical concept of this specification. Accordingly, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

Claims

1. A display panel including a display area in which multiple subpixels are arranged and a non-display area surrounding the display area, A first level shift circuit is arranged in the display area and transmits a first mode signal so that the plurality of subpixels are driven in the first mode, The display area includes a second level shift circuit that transmits a second mode signal so that the plurality of subpixels are driven in the second mode, Each of the aforementioned subpixels is A first light-emitting element that is selected and emits light by the first level shift circuit, A first optical member that refracts light from the first light-emitting element, A second light-emitting element that is selected and emits light by the aforementioned second level shift circuit, The light from the second light-emitting element is refracted, and the second optical element has a different shape from the first optical element. In the first mode, the first light-emitting element emits light, and the light from the first light-emitting element is output with its viewing angle limited in the first and second directions by the first optical member. A display device in which, in the second mode, the second light-emitting element emits light, and the light from the second light-emitting element is output with its viewing angle limited only in the first direction by the second optical member.

2. The aforementioned display device is Multiple first level shift circuits, It includes multiple second level shift circuits, The aforementioned display area includes a plurality of areas divided in the row or column direction, The display device according to claim 1, wherein each of the plurality of first level shift circuits and the plurality of second level shift circuits is arranged one in each of the plurality of regions.

3. The plurality of first level shift circuits transmit the first mode signal to each of the plurality of regions. The display device according to claim 2, wherein the plurality of second level shift circuits transmit the second mode signal to each of the plurality of regions.

4. The plurality of subpixels include a plurality of subpixel circuits, The display device according to claim 2, wherein the first level shift circuit and the second level shift circuit share signal wiring with the plurality of sub-pixel circuits.

5. The display panel includes a first scan signal wiring, a second scan signal wiring, and an illumination signal wiring. The plurality of sub-pixel circuits are, The drive transistor and A first transistor is connected to the first scan signal wiring by a gate electrode, and is connected to the first electrode of the capacitor with one of the source electrode and drain electrode, and applies a data voltage to the capacitor. A second transistor is connected to the second scan signal wiring by its gate electrode, connected to the second electrode of the capacitor by one of its source electrode and drain electrode, and connected to the drain electrode of the drive transistor by the other, thereby diode-connecting the gate electrode and drain electrode of the drive transistor, A third transistor is connected to the light-emitting signal wiring by a gate electrode, and is connected to the first electrode of the capacitor with one of its source electrode and drain electrode, and applies a reference voltage to the capacitor. A fourth transistor is connected to the first level shift circuit by a gate electrode, with one of its source and drain electrodes connected to the drain electrode of the drive transistor and the other connected to the anode electrode of the first light-emitting element. A fifth transistor is connected to the second scan signal wiring by a gate electrode, and one of its source electrode and drain electrode is connected to the anode electrode of the first light-emitting element, and the reference voltage is applied to the anode electrode of the first light-emitting element. A sixth transistor is connected to the second scan signal wiring by a gate electrode, and one of its source electrode and drain electrode is connected to the anode electrode of the second light-emitting element, and the reference voltage is applied to the anode electrode of the second light-emitting element. A seventh transistor is connected to the second level shift circuit by a gate electrode, one of its source electrode and drain electrode is connected to the drain electrode of the drive transistor, and the source electrode is connected to the anode electrode of the second light-emitting element, The display device according to claim 4, comprising an eighth transistor connected to the light-emitting signal wiring by a gate electrode, with one of its source electrodes and drain electrode connected to the drain electrode of the drive transistor, and the other connected to the one of the source electrodes or drain electrodes of the fourth transistor and the one of the source electrodes or drain electrode of the seventh transistor.

6. In the first mode, the fourth transistor is turned on, and the seventh transistor is turned off. The display device according to claim 5, wherein in the second mode, the fourth transistor is turned off and the seventh transistor is turned on.

7. The display panel includes a first scan signal wiring, a second scan signal wiring, and an illumination signal wiring. The first level shift circuit is, First capacitor and, A second capacitor connected in series with the first capacitor, A first transistor connected to the first scan signal wiring transmits a second mode selection signal to the first electrode of the first capacitor, A second transistor is connected to the first scan signal wiring and transmits the first mode selection signal to the second electrode of the first capacitor, A third transistor is connected to the second scan signal wiring and transmits the second mode selection signal to the first electrode of the second capacitor, A fourth transistor is connected to the first scan signal wiring and transmits the first mode selection signal to the second electrode of the second capacitor, A fifth transistor is connected to the second scan signal wiring and transmits the first mode selection signal to the second electrode of the second capacitor, A sixth transistor is connected to the aforementioned light-emitting signal wiring and transmits a reference voltage to the second electrode of the second capacitor, The display device according to claim 4, further comprising a seventh transistor connected to the light-emitting signal wiring and outputting the first mode signal.

8. The first level shift circuit is driven in a divided manner, divided into a first period, a second period, and a third period. During the first period, the first scan signal and the second mode selection signal are turn-on signals. During the second period, the second scan signal and the second mode selection signal are turn-on signals. The display device according to claim 7, wherein during the third period, the light emission signal and the first mode selection signal are turn-on signals.

9. The display panel includes a first scan signal wiring, a second scan signal wiring, and an illumination signal wiring. The second level shift circuit is, A first transistor is connected to the first scan signal wiring and transmits the first mode selection signal to the first electrode of the first capacitor, A second transistor is connected to the first scan signal wiring and transmits a second mode selection signal to the second electrode of the first capacitor, A third transistor is connected to the second scan signal wiring and transmits the first mode selection signal to the first electrode of the second capacitor, A fourth transistor is connected to the first scan signal wiring and transmits the second mode selection signal to the second electrode of the second capacitor, A fifth transistor is connected to the second scan signal wiring and transmits the second mode selection signal to the second electrode of the second capacitor, A sixth transistor is connected to the aforementioned light-emitting signal wiring and transmits a reference voltage to the second electrode of the second capacitor, The display device according to claim 4, further comprising a seventh transistor connected to the light-emitting signal wiring and outputting the second mode signal.

10. The second level shift circuit is driven in a divided manner, divided into a first period, a second period, and a third period. During the first period, the first scan signal and the first mode selection signal are turn-on signals. During the second period, the second scan signal and the first mode selection signal are turn-on signals. The display device according to claim 9, wherein during the third period, the light emission signal and the second mode selection signal are turn-on signals.

11. The system further includes a plurality of mode control units arranged in the non-display area, The aforementioned display panel is A first mode selection signal wiring that extends in the row or column direction in the plurality of regions, is connected to the mode control unit, and transmits a first mode selection signal to the plurality of subpixels; and The display device according to claim 2, further comprising a second mode selection signal wiring that extends in the row or column direction in the plurality of regions, is connected to the mode control unit, and transmits a second mode selection signal to the plurality of subpixels.

12. Each of the aforementioned subpixels is driven in an initial period, a sampling period, a holding period, and an emission period. During the aforementioned initial period, the voltage of the gate electrode of the drive transistor is initialized. During the sampling period, the threshold voltage of the drive transistor is sampled. The anode electrode of the first light-emitting element and the anode electrode of the second light-emitting element are initialized, During the holding period, the first to eighth transistors are turned off. The display device according to claim 5, wherein during the emission period, a drive current is applied to the first light-emitting element and the second light-emitting element, and the first light-emitting element and the second light-emitting element each emit light.

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