Multilayer FET standard cell architecture

Abstract

A cell layout for implementing stacked transistors is disclosed. The cell layout utilizes both topside metal routing and bottomside metal routing. Various connection routes can be formed between the transistor components (e.g., gate, source, and drain) and either the topside metal routing or the bottomside metal routing. The specific connection routes can be determined based on the desired device structure. Thus, the disclosed cell layout allows various devices to be built based on the basic cell structure.

Description

Technical Field

[0001] The embodiments described in this specification relate to power routing and signal routing for semiconductor devices. More specifically, the embodiments described in this specification relate to power routing and signal routing through both an upper layer and a back layer for an integrated circuit cell having a plurality of transistors.

Background Art

[0002] A standard cell is a group of transistors, passive structures, and interconnect structures that can provide logical functions, memory functions, and the like. The current trend in the standard cell methodology is to reduce the size of the standard cell while increasing the complexity within the standard cell (e.g., circuit density and the number of components or transistors). However, as the standard cell design becomes smaller, it becomes more difficult to provide access (e.g., connection) to the components within the standard cell within the design / manufacturing constraints of the standard cell.

Summary of the Invention

[0003] The features and advantages of the methods and apparatuses of the embodiments described in this disclosure will be more fully understood by reference to the following detailed description of presently preferred but exemplary embodiments according to the embodiments described in this disclosure, in conjunction with the accompanying drawings.

Brief Description of the Drawings

[0004] [Figure 1] Shows a top plan view of a standard cell according to some embodiments.

[0005] [Figure 2] Shows a back plan view of a standard cell according to some embodiments.

[0006] [Figure 3] Shows a cross-sectional view of a standard cell along line 3-3 shown in FIG. 1.

[0007] [Figure 4] Figure 2 shows a cross-sectional view of a standard cell along line 4-4.

[0008] [Figure 5] Figures 1 and 2 both show a cross-sectional view of a standard cell along line 5-5.

[0009] [Figure 6] Figures 1 and 2 both show a cross-sectional view of a standard cell along line 6-6.

[0010] [Figure 7] The upper plan view of a cell with alternative vias along the boundary, according to several embodiments, is shown.

[0011] [Figure 8] This is a cross-sectional view of a cell showing a connection to the source region according to several embodiments.

[0012] [Figure 9] This is a cross-sectional view of a cell showing a connection to the drain region according to several embodiments.

[0013] [Figure 10] The diagrams show cross-sectional views of the multilayer transistor control signal connections within a cell that mounts via pillars, according to several embodiments.

[0014] [Figure 11] Cross-sectional views of multilayer transistor control signal connections with a common gate configuration, according to several embodiments, are shown.

[0015] [Figure 12] Cross-sectional views of multilayer transistor control signal connections with cross-coupled gate configurations according to several embodiments are shown.

[0016] [Figure 13] The images show upper plan views of NAND cells according to several embodiments.

[0017] [Figure 14] A back-side plan view of a NAND cell according to some embodiments is shown.

[0018] [Figure 15] A cross-sectional view of a NAND cell along line A-A' shown in FIGS. 13 and 14 is shown.

[0019] [Figure 16] A cross-sectional view of a NAND cell along line B-B' shown in FIGS. 13 and 14 is shown.

[0020] [Figure 17] A cross-sectional view of a NAND cell along line C-C' shown in FIGS. 13 and 14 is shown.

[0021] [Figure 18] A cross-sectional view of a NAND cell along line D-D' shown in FIGS. 13 and 14 is shown.

[0022] [Figure 19] A schematic diagram of a memory cell is shown.

[0023] [Figure 20] An upper-side plan view of a memory cell having a stacked transistor according to some embodiments is shown.

[0024] [Figure 21] A back-side plan view of a memory cell having a stacked transistor according to some embodiments is shown.

[0025] [Figure 22] A cross-sectional view of a memory cell along line A-A' shown in both FIGS. 和図21 is shown.

[0026] [Figure 23] A cross-sectional view of a memory cell along line B-B' shown in both FIGS. 20 and 21 is shown.

[0027] [Figure 24] Figures 20 and 21 both show cross-sectional views of a memory cell along the line C-C'.

[0028] [Figure 25] The following are illustrative block diagrams of memory devices according to several embodiments.

[0029] [Figure 26] The image shows an upper plan view of a region having a dummy cell according to several embodiments.

[0030] [Figure 27] The rear plan view of a region having a dummy cell according to several embodiments is shown.

[0031] [Figure 28] Figures 26 and 27 both show a cross-sectional view of the region containing a dummy cell along line A-A'.

[0032] [Figure 29] Figures 26 and 27 both show a cross-sectional view of the region containing a dummy cell along line B-B'.

[0033] [Figure 30] The image shows an upper plan view of a region having a dummy cell according to several embodiments.

[0034] [Figure 31] The rear plan view of a region having a dummy cell according to several embodiments is shown.

[0035] [Figure 32] Figures 30 and 31 both show a cross-sectional view of the region containing a dummy cell along line A-A'.

[0036] [Figure 33] Figures 30 and 31 both show a cross-sectional view of the region containing a dummy cell along line B-B'.

[0037] [Figure 34] Schematic diagrams of column I / O cells according to several embodiments are shown.

[0038] [Figure 35] The layout of the column I / O cells in several embodiments is shown.

[0039] [Figure 36] Perspective views of a planned vertical transistor device according to several embodiments are shown.

[0040] [Figure 37] Perspective views of another intended vertical transistor device according to several embodiments are shown.

[0041] [Figure 38] Perspective views of inverter cell structures according to several embodiments are shown.

[0042] [Figure 39] The upper plan view of an inverter cell structure according to several embodiments is shown.

[0043] [Figure 40] The rear plan view of the inverter cell structure according to several embodiments is shown.

[0044] [Figure 41] Figure 39 shows a cross-sectional view of an inverter cell structure along line 41-41 according to several embodiments.

[0045] [Figure 42] Figure 39 shows a cross-sectional view of an inverter cell structure along line 42-42 according to several embodiments.

[0046] [Figure 43] Perspective views of NAND cell structures according to several embodiments are shown.

[0047] [Figure 44] The images show upper plan views of NAND cell structures according to several embodiments.

[0048] [Figure 45] The following are rear-side plan views of NAND cell structures according to several embodiments.

[0049] [Figure 46] Figure 44 shows cross-sectional views of NAND cell structures along lines 46-46 according to several embodiments.

[0050] [Figure 47] Figure 44 shows cross-sectional views of NAND cell structures along lines 47-47 according to several embodiments.

[0051] [Figure 48] Perspective views of MUX cell structures according to several embodiments are shown.

[0052] [Figure 49] The image shows an upper plan view of a MUX cell structure according to several embodiments.

[0053] [Figure 50] The following are rear-side plan views of MUX cell structures according to several embodiments.

[0054] [Figure 51] Figure 49 shows a cross-sectional view of a MUX cell structure along line 51-51 according to several embodiments.

[0055] [Figure 52] Figure 49 shows a cross-sectional view of a MUX cell structure along line 52-52 according to several embodiments.

[0056] [Figure 53] Perspective views of the device according to several embodiments are shown.

[0057] [Figure 54] Figure 53 shows a cross-sectional view of the device along line 54-54 according to several embodiments.

[0058] [Figure 55] This is a block diagram of one embodiment of an exemplary system. [Modes for carrying out the invention]

[0059] The embodiments disclosed herein are open to various modifications and alternative forms, but specific embodiments are shown in the drawings and described in detail herein for illustrative purposes. However, it should be understood that the drawings and their detailed description are not intended to limit the invention to any particular form disclosed in the claims. On the contrary, this application is intended to cover all modifications, equivalents, and alternatives that fall within the spirit and scope of the disclosure of this application, as set forth in the appended claims.

[0060] As used herein, the term “standard cell” refers to a group of transistor structures, passive structures, and interconnect structures formed on a substrate to provide logic or memory functions that are standard for various implementations. For example, an individual standard cell may be one cell in a library of multiple cells from which various suitable cells can be selected to implement a particular cell design. Integrated circuit cells may also include custom circuit design cells that are individually designed for a particular implementation. Embodiments of circuit design cells described herein may be implemented in various implementations of logic integrated circuits or memory integrated circuits.

[0061] Many current cell designs provide connections and routing for power or signals to transistors or other structures in an area above the transistor. For example, connections and routing for power or signals may be provided in the upper layers of the device. As used herein, the term “upper” refers to an area within the device that is vertically above the active layer of the device (e.g., above the transistor region of the device when viewed in a typical cross-sectional view). For example, “upper” may refer to components such as contacts or layers that are vertically above the transistor region, as shown in the drawings and described herein. In some cases, the term “front” may be used interchangeably with the term “upper.”

[0062] Some recent advances in standard cell design involve moving power connections and routing to a metal layer beneath the transistor. For example, power connections and routing may be located within the back layer of the device. As used herein, the term “back” refers to an area within the device that lies vertically below the active layer of the device (e.g., below the transistor region of the device when viewed in a typical cross-sectional view). For example, the back may refer to components such as contacts or layers that are vertically below the transistor region, as shown in the drawings and described herein. As used herein, it should be noted that back elements located below the active layer may be above, inside, or below the silicon substrate on which the active layer is manufactured. That is, as used herein, “back” refers to the active layer, not the silicon substrate.

[0063] This disclosure covers various mounting configurations of stacked transistors or vertical transistors within integrated circuit cells (e.g., standard cells) that utilize connections to both the upper and lower metal layers. The inventors have recognized that utilizing the upper and lower layers in a particular manner can provide technical advantages and space-saving advantages to cell layouts for mounting stacked transistors or vertical transistors. The disclosed embodiments utilize the upper and lower metal layers to provide advantageous cell layouts and routing (e.g., paths) for control signals or power signals within the cell layout. Standard Cell Design of Multilayer Transistors

[0064] Multilayer transistors (for example, those in which two transistor active regions are stacked vertically above the substrate) can offer various technical and space-saving advantages due to the proximity of the devices within the transistor. However, implementing multilayer transistors in standard cells is difficult due to the design and manufacturing constraints associated with the standard cell structure. For example, in a standard cell that utilizes only top routing, there is typically not enough routing to both transistors without increasing the size of the standard cell. A standard cell limited to top routing for control signals and back routing for power signals may also lack the necessary routing and connectivity availability for two multilayer transistors without changing the size of the standard cell.

[0065] This disclosure envisions various techniques for implementing routing in both the upper and lower metal layers, enabling the placement of two multilayer transistors within a standard cell. Various embodiments of the standard cell configuration are disclosed, providing basic building blocks for many different types of devices, from simple devices (e.g., inverters and NAND devices) to more complex devices (e.g., complex FETs). The disclosed embodiments provide a compact standard cell structure that enables the implementation of multilayer transistors in various circuit logic schemes.

[0066] Specific embodiments disclosed herein have four broad elements: 1) a first metal layer (e.g., an upper metal layer) located above the transistor region of the integrated circuit cell structure; 2) a second metal layer (e.g., a back metal layer) located below the transistor region; 3) a pair of vertically stacked transistors within the transistor region; and 4) various possible connection paths for both control signals and power signals between either the first or second metal layer and the first and second transistors. In specific embodiments, the pair of vertically stacked transistors include heterogeneous transistors (e.g., complementary transistor types such as PMOS and NMOS transistors). In some embodiments, the pair of vertically stacked transistors include homogeneous transistors (e.g., the transistors are of the same type).

[0067] In various embodiments, control signal and power signal connections are formed to implement logic associated with a particular integrated circuit device having multiple transistors for a standard cell structure described herein. For example, an example of an inverter device or NAND gate device that can be implemented based on a standard cell configuration is described below. Various possible configurations of control signal and voltage signals to multilayer transistors within a standard cell structure are also described. Those skilled in the art will understand that many different desired circuits can be generated by implementing various possible combinations of these connections based on a multilayer transistor structure within a standard cell configuration.

[0068] In summary, the inventors have recognized that by providing various routing paths within a standard cell structure, it is possible to implement connections to both the upper and lower metal layers for control and power signals from multilayer transistors placed within the standard cell structure. The routing paths described herein enable the use of the standard cell configuration when generating a variety of simple and complex integrated circuit logic devices based on the multilayer transistors in the cell. In addition, the standard cell structure with multilayer transistors described herein provides a scalable template that can be implemented in devices having multiple integrated circuit cells. The standard cell structure with multilayer transistors in this disclosure further enables cell structures that can be implemented within current manufacturing constraints and without changing the size or parameters of current standard cells. As used herein, the term “routing” refers to any combination of metal vias, metal wires, metal traces, etc., that provide a path / route between two structures. Additional embodiments may be contemplated in which the metal in the “routing” is replaced with an alternative conductive material. For example, the metal in the “routing” may be replaced with a superconducting material, a semiconductor material, or a non-metallic conductor.

[0069] Figures 1 to 6 show diagrams of a standard cell having a multilayer transistor and both an upper layer connection and a back layer connection, according to several embodiments. Figure 1 shows an upper plan view of a standard cell 100 according to several embodiments. Figure 2 shows a back plan view of a standard cell 100 according to several embodiments. Figure 3 shows a cross-sectional view of a standard cell 100 along line 3-3 shown in Figure 1. Figure 4 shows a cross-sectional view of a standard cell 100 along line 4-4 shown in Figure 2. Figure 5 shows a cross-sectional view of a standard cell 100 along line 5-5 shown in both Figures 1 and 2. Figure 6 shows a cross-sectional view of a standard cell 100 along line 6-6 shown in both Figures 1 and 2.

[0070] For the sake of simplicity in the drawings, the representations of the cells disclosed herein show only the components relevant to this disclosure. Those skilled in the art will understand that additional components may be present in any of the cells shown herein. For example, in Figure 1, various connections (such as vias or contacts as described herein) may be visible in some depictions. In addition, for a better understanding of the disclosed embodiments, some transparency of the materials is provided to allow visibility of the underlying components in the top and back plan views. For example, in Figures 1 and 2, the substrate 102 has some transparency to provide visibility of the gate and active region of the underlying transistor, and the top metal layer 112 and the back metal layer 120 have some transparency to provide visibility of the contact 114 and the back via 122, respectively.

[0071] In various embodiments, the standard cell 100 includes a substrate 102, as shown in Figures 1 to 6. In certain embodiments, the substrate 102 is a silicon substrate, but other semiconductor substrates may also be intended. The substrate 102 may include additional components or features to be mounted within the cell 100. For example, the substrate 102 may include one or more insulating layers (e.g., oxide layers), diffusion (e.g., oxide diffusion) regions, or doped regions to be mounted within the cell 100. For the sake of simplicity in the drawings, the substrate 102 is shown as the material that fills the volume of the standard cell 100.

[0072] In various embodiments, a first active region 104 and a second active region 106 are formed within the substrate 102. In certain embodiments, within a cell 100, active region 104 is positioned vertically above active region 106. For example, active region 104 may be positioned at the top of cell 100, and active region 106 may be positioned at the bottom of the cell. It should be noted that active regions 104 and 106 are not necessarily positioned directly above / below each other. For example, a portion of active region 104 or active region 106 may lie outside the boundary of the other active region. Therefore, when it is stated that active region 104 is above active region 106, it may mean that at least a portion of active region 104 is above at least a portion of active region 106, and vice versa.

[0073] In certain embodiments, active region 104 is the active region of a first transistor in cell 100, and active region 106 is the active region of a second transistor in cell 100. For example, in one intended embodiment, active region 104 is the active region of an NMOS transistor having one or more NMOS gates, and active region 106 is the active region of a PMOS transistor having one or more PMOS gates. Alternatively, active region 104 may be the active region of a PMOS transistor, while active region 106 is the active region of an NMOS transistor. Transistor stacks having these complementary transistor types (e.g., heterogeneous transistors) are described with reference to Figures 1 to 6, but it should be understood that additional embodiments may be intended where both transistors are of the same type (e.g., homogeneous transistors). In addition, although the disclosed embodiments describe silicon-based transistors such as NMOS and PMOS transistors, other types of semiconductor-based transistors may be intended without departing from the scope of this disclosure. Furthermore, any type of transistor structure may be intended. For example, the transistor formed may include, but is not limited to, a FinFET, a nanosheet FET (NSH), or a GAAFET ("gate-all-around" FET).

[0074] In various embodiments, a transistor having an active region 104 includes an upper gate 108 and a source / drain region 124, while a transistor having an active region 106 includes a lower gate 116 and a source / drain region 124. The transistors may be arranged between insulated gates 110, as shown in Figures 1 to 4. The cell 100 may also include contacts 126 that provide connections for the source / drain region 124. The cell 100 includes two upper gates 108A to B, two lower gates 116A to B, six source / drain regions 124A to F (three source / drain regions 124A to C in the upper transistor and three source / drain regions 124D to F in the lower transistor), and six contacts 126A to F arranged between the insulated gates 110 within the cell 100, as shown in Figures 1 to 6. However, the embodiments of the cell 100 shown in Figures 1 to 6 are examples of possible structures of the transistor components within the cell. For example, it should be understood that cell 100 may include any number of transistor components that fit within the boundaries of the cell in accordance with the design and manufacturing constraints of the cell (e.g., the design and manufacturing constraints of a standard cell), without departing from the scope of this disclosure.

[0075] The upper gate 108 and lower gate 116 may be, for example, a polyline (e.g., a polysilicon layer) or a high-k / metal gate. In certain embodiments, the upper gate 108 and lower gate 116 include a gate spacer (not shown for simplification of the drawings). For example, the gate spacer may be located between the gate 108 / 116 and the source / drain region 124. In various embodiments, the gate spacer is formed as part of the gate 108 / 116 (e.g., the gate and spacer are formed in the same process flow). The source / drain region 124 may be, for example, a fin or nanosheet stack or an epitaxial layer grown on any 2D (two-dimensional) channel material. Various embodiments may also be conceived in which the source / drain region 124 is at least partially located within the substrate 102.

[0076] In addition to the transistor components described above, various connections to the gate and / or source / drain regions may be made within the cell 100. These connections may include, for example, contacts or vias that provide connections between the transistor components within the cell 100 and the upper metal layer 112 or the back metal layer 120. Contact 114 (shown in Figures 1, 3, and 5) is an example of a gate contact that provides a connection between the upper gate 108A and the upper metal layer 112B. Back via 122 (shown in Figures 2, 4, and 6) is an example of a via that provides a connection between the source / drain region 124F and the back metal layer 120B.

[0077] In various embodiments, contact 114 is an upper via providing connections from various parts of the transistor (e.g., source / drain region, gate, etc.) to the upper metal layer 112, while back via 122 provides connections from various parts of the transistor to the back metal layer. Contact 114 and back via 122 are provided as non-limiting examples of possible connections in cell 100. For example, any number or combination of contacts or vias (along with any horizontal routing) can be implemented in cell 100 to provide connections between various upper and back metal layers and transistor components within the cell (e.g., upper gate 108, lower gate 116, and source / drain region 124). Connections may also be made depending on whether control signals or power signals are intended for components within the transistor in cell 100. For example, in the embodiments shown in Figures 1 to 6, contact 114 may provide a control signal connection to the upper gate 108A, while back via 122 provides a power signal connection to the source / drain region 124F. The number, type, and positioning of contacts and vias can be determined based on the desired device constructed using the structure of the components within cell 100. For example, an inverter device has different connections than a NAND device (shown as an example in Figures 13-18).

[0078] As shown in Figures 1 to 6, cell 100 includes four upper metal tracks (upper metal layers 112A to D) and three back metal tracks (back metal layers 120A to C). It should be understood that cell 100 may include any number of upper and back metal tracks, depending on the design and manufacturing constraints of the cell. For example, the number of metal tracks may be more or less, depending on the design and manufacturing constraints of the cell, such as height, pitch, and width. In addition, the upper and back metal tracks do not have to be aligned with each other. For example, as clearly shown in Figures 5 to 6, the upper metal layer 112 is not aligned with the back metal layer 120. However, embodiments having aligned upper and back metal layers may be contemplated.

[0079] In various embodiments, as shown in Figure 4, the back metal layer 120 is formed on or near the bottom surface of the substrate 102. In certain embodiments, the back metal layer 120 includes one or more back layers of the active layer within the cell 100 (e.g., the back metal layer is located vertically below the active region 106). In some embodiments, the back metal layer 120 includes one or more embedded layers within the substrate 102 (e.g., the metal layer is embedded or embedded beneath the bottom surface of the substrate). In some embodiments, the back metal layer 120 is embedded beneath a carrier substrate layer (e.g., a silicon carrier substrate). Additional embodiments may be conceived in which the back metal layer 120 is not located within the substrate 102.

[0080] The metal tracks may also be selected to be used as control signal tracks (e.g., control signal rails) or power signal tracks (e.g., power signal rails) depending on the desired device application of cell 100. Control signal tracks can provide input or output signal connections to transistor components within cell 100, while power signal tracks can provide power routing to and from Vdd (e.g., supply voltage) and Vss (e.g., ground), as well as other intended power connections. The selection of a track to be used as a control signal track or a power signal track may also determine the connections made to the metal tracks. For example, in the illustrated embodiment of cell 100, the upper metal layer 112B is a control signal track connected to the upper gate 108A by contacts 114, while the back metal layer 120B is a power signal track connected to the source / drain region 124F by back vias 122. It should be noted that in various intended embodiments, any of the back metal layers 120A-C may be used as power signal tracks. The remaining upper metal tracks (e.g., upper metal layers 112A, 112C, 112D) may be used for either additional upper control signal tracks or upper power signal tracks. Similarly, the remaining back metal tracks (e.g., back metal layers 120A and 120C) may be used for either additional back power signal tracks or back control signal tracks. For example, in one intended embodiment, one of the upper metal layers 112A, 112C, 112D may be an upper power signal track having contacts to a source / drain region (e.g., one of source / drain regions 124A-C) in the upper portion of cell 100 to provide a power signal connection to an upper transistor having an active region 104. In addition, one of the back metal layers 120A and 120C may be a back control signal track having contacts to a lower gate 116B (e.g., the lower gate in a split-gate configuration) in the lower portion of cell 100 to provide a control signal connection to a lower transistor having an active region 106.

[0081] In various intended embodiments, when a metal track is used as a power rail (e.g., a power signal track), one or more upper metal tracks (e.g., upper metal layers 112A-D) may be merged. For example, in some embodiments, when a metal track along a cell edge (e.g., upper metal layer 112A or upper metal layer 112D) is used as a power rail, the metal track may be merged with a metal cell track from an adjacent cell. For example, as shown in Figure 1, the upper metal layer 112D' may be in an adjacent cell in the cell height direction (above cell 100 in the depiction of Figure 1). Then, a power rail merge layer 109 (dashed box) may be implemented to merge the upper metal layer 112A in cell 100 with the upper metal layer 112D' in the adjacent cell above. In various embodiments, the power rail merge layer 109 is a metal layer connecting the upper metal layer 112A and the upper metal layer 112D'. In some intended embodiments, the upper metal layer 112A, the upper metal layer 112D', and the power rail merge layer 109 may be a single metal track formed within cell 100 and adjacent cells.

[0082] In other intended embodiments of merging metal tracks, metal tracks used as power rails, located at or near the center of a cell, may be merged. For example, as shown in Figure 1, when upper metal layers 112B and 112C are used as power rails, a power rail merging layer 111 (dashed box) may be implemented to merge these layers. The power rail merging layer 111 may be, for example, a metal connecting upper metal layer 112B and upper metal layer 112C. In some cases, upper metal layer 112B, upper metal layer 112C, and power rail merging layer 111 may be a single metal track within cell 100.

[0083] In the embodiments of cell 100 shown in Figures 1 to 6, it should be understood that various connections can be made between the illustrated metal tracks and the transistor components within the cell. It should be noted that additional contacts for control signals and power signals are not shown for the sake of simplification of the drawings. For example, any of the metal tracks (e.g., one of the upper metal layers 112A, 112C, or 112D, or one of the back metal layers 120A and 120C) may be connected to any of the gates (e.g., upper gate 108 or lower gate 116) or source / drain regions 124 within cell 100, as required by the desired device structure. Thus, the illustrated structure of cell 100 in Figures 1 to 6, having components (e.g., gates 108 / 116 and source / drain regions 124) and metal tracks (e.g., upper metal layer 112 and back metal layer 120), provides a basic building block structure that allows for different variations in the connections between the components and the metal tracks to generate many different types of devices.

[0084] As shown in Figures 1 to 6, the upper gate 108 and lower gate 116 can be formed within the cell 100 having different gate-to-gate relationships within the multilayer transistor structure. Two possible embodiments of the gate relationship are shown in Figures 3 and 4. In the first intended embodiment, the upper gate 108A is merged with the lower gate 116A to establish gate-to-gate connectivity. The connectivity established by the gate merging allows a single control signal to be provided to both gates. For example, as shown in Figures 3 and 4, the gate-to-gate connectivity allows a control signal supplied from the upper metal layer 112B to the upper gate 108A via the contact 114 to be passed through and used as a control signal for the lower gate 116A. It should be noted that the merged gate configuration is also shown in the cross-sectional view of Figure 5. The second intended embodiment includes an upper gate 108B that is separated (e.g., split) from the lower gate 116B. By separating the upper gate 108B and the lower gate 116B, the gates are kept electrically disconnected. Therefore, because the control signal cannot pass between the gates due to the separation / splitting between them, the upper gate 108B and the lower gate 116B require separate control signals.

[0085] Although not shown in Figures 1-6, in various embodiments, the source / drain region 124 may also be merged between the upper and lower transistors. Examples of merged source / drain regions are shown in Figures 13-16, which are described below. Merging the source / drain region 124 may allow a single power signal to power both the upper and lower transistors, or a single control signal (e.g., a single output signal from the drain) to be connected to both the upper and lower transistors. Similar to gate splitting, if the source / drain region 124 is split (as shown in Figures 1-6), separate connections are required for the split source / drain regions.

[0086] In certain embodiments, power routing for transistors within cell 100 (e.g., upper and lower transistors) is divided between the upper metal layer 112 and the back metal layer 120. For example, as shown in Figures 2, 4, and 6, the back metal layer 120B is connected to the source / drain region 124F via the back via 122. Thus, in certain embodiments, power to the lower gate 116B in the lower transistor (e.g., a transistor with an active region 206) is routed from the back metal layer 120B. To divide the power, power to the upper gate 108B may be routed from one of the upper metal layers not used for control signals (e.g., upper metal layer 112C). Thus, the upper gate 108B and the lower gate 116B will have separate power rails supplying power to the gate / transistor. Dividing power routing between the upper metal layer 112 and the back metal layer 120 can result in more efficient power routing within cell 100.

[0087] Additional embodiments may be contemplated in which power routing is provided from either the upper metal layer 112 or the back metal layer 120, but not from both layers. For example, as described above, the source / drain regions can be merged, and a single power signal from either the upper or back can be supplied to the merged region. In another contemplated embodiment, power can be supplied into the cell 100 through the back metal layer (e.g., back metal layer 120A), and vias can route power from the back metal layer to one of the upper metal layers, which then connects to the source / drain region in the upper transistor. Vias may be located between the upper and back metal layers within an open channel in the cell 100. An example of a via is shown in Figure 6, where via 600 (dashed line) is optionally routed between the upper metal layer 112A and the back metal layer 120A in the space outside the source / drain regions 124C / 124F (e.g., a channel). Next, the upper metal layer 112A can be connected (directly or via another upper metal layer) to the source / drain region 124C to supply power to the upper transistor. Note that vias 600, as shown in Figure 6, can also be used to route signals between the upper and back metal layers.

[0088] Another alternative for routing power from the back layer to the top may involve extending the source / drain region 124C to intersect and connect with via 600, as shown by the dotted line extending from the source / drain region 124C in Figure 6. This extension establishes a direct connection between via 600 and the source / drain region 124C. Other examples of extensions (both gate and source / drain regions) are provided below with reference to Figures 7–12, which illustrate implementations of via pillars within a cell (e.g., on the outer perimeter of the cell).

[0089] As described above, the embodiments of cell 100 shown in Figures 1 to 6 provide the basis for a compact standard cell structure that implements two vertically stacked transistors. The transistors can be heterogeneous (e.g., two different types of transistors) or homogeneous (e.g., the same type of transistor). Cell 100 implements the availability of connections from either the upper metal layer or the back metal layer to any of the various transistor components, including the gate and source / drain regions. The adaptability in connections for both control signals and power for the transistor components makes it possible to adapt the basic structure of cell 100 to a wide range of logic schemes for implementing different integrated circuit devices using stacked transistors. The compactness of cell 100 makes it possible to implement cells with stacked transistors within current standard cell design and manufacturing constraints.

[0090] In some cases, placing cell 100 next to an adjacent cell can cause manufacturing problems due to routing tracks along the cell boundary. When routing tracks run along the boundary, vias from the routing tracks can cause spacing issues between adjacent cells. One possible solution to this boundary problem is to replace the routing tracks along the edge with via tracks, in which case the vias are used alternately by the current cell and by the adjacent cell.

[0091] Figure 7 shows an upper plan view of a cell with alternative vias along the boundary according to several embodiments. In cell 700, three upper metal layers 112A, 112B, and 112C are arranged between via tracks 705A and 705B. Via tracks 705A and 705B are arranged along the boundary (e.g., edge) of cell 700. Via tracks 705A and 705B include via pillars 710. In certain embodiments, for via pillars 710A and 710B, via pillar 710A belongs to cell 700, while via pillar 710B belongs to an adjacent cell. In various embodiments, via pillars 710 arranged on the outer perimeter of the cell are used to route either control signals or power signals into the cell 700. It should be noted that adjacent cells may have a mirror image configuration with respect to cell 700 to correspond to alternating via pillar arrangements.

[0092] Various embodiments can be conceived for connecting to the via pillar 710A within cell 700 shown in Figure 7. Embodiments may include routing connections to gate or source / drain regions within cell 700. Figures 8 and 9 show cross-sectional views of source and drain connections within a cell implementing a via pillar, according to several embodiments. Figure 8 is a cross-sectional view of cell 800 showing connections to source regions 124A and 124B, and Figure 9 is a cross-sectional view of cell 800 showing connections to drain regions 124C and 124D.

[0093] In various embodiments, as shown in Figure 8, source regions 124A and 124B are directly connected by contacts 114 to the upper metal layer 112B and the back metal layer 120A, respectively. The upper metal layer 112B and the back metal layer 120A can then be routed to a power source (e.g., Vdd) or ground (e.g., Vss) for power connections to source regions 124A and 124B. For drain regions 124C and 124D, as shown in Figure 9, contacts 114 are routed horizontally to via pillars 710A. The via pillars 710A can then be routed to the upper metal layer 112 or the back metal layer 120 for signal connections. In some embodiments, contacts 114 for drain regions 124C and 124D can be replaced by extending the drain regions 124C and 124D horizontally and connecting them to via pillars 710A.

[0094] Figure 10 shows a cross-sectional view of a multilayer transistor control signal connection within a cell mounting via pillars according to several embodiments. In Figure 10, cell 1000 includes source / drain regions 124A and 124B connected to the upper metal layer 112C and the back metal layer 120B, respectively, by contacts 114. The upper metal layer 112C and the back metal layer 120B may be routing for control signals provided to the source / drain regions 124A and 124B.

[0095] The via pillar 710A can also provide routing for control signals from the gates in various embodiments of the multilayer transistor. The gates can be coupled, for example, as a common gate or a split gate (such as those used in transmission gates). Figure 11 shows a cross-sectional view of a multilayer transistor control signal connection in a common gate configuration according to several embodiments. In cell 1100, the upper gate 108A and the lower gate 116A are extended and cross-connected to the via pillar 710A for a common connection to the gates. Figure 12 shows a cross-sectional view of a multilayer transistor control signal connection in a split gate configuration according to several embodiments. In cell 1200, the upper gate 108A is connected to the upper metal layer 112C by contact 114, and the lower gate 116A is extended and cross-connected to the via pillar 710A. The upper metal layer 112C and the via pillar 710A can then be cross-coupled to cross-couple the upper gate 108A and the lower gate 116A. Assimilation NAND cell with stacked transistors

[0096] Figures 13 to 18 show exemplary NAND cells according to several embodiments. Figure 13 shows an upper plan view of a NAND cell 1300 according to several embodiments. Figure 14 shows a rear plan view of a NAND cell 1300 according to several embodiments. Figure 15 shows a cross-sectional view of a NAND cell 1300 along the line A-A' shown in Figures 13 and 14. Figure 16 shows a cross-sectional view of a NAND cell 1300 along the line B-B' shown in Figures 13 and 14. Figure 17 shows a cross-sectional view of a NAND cell 1300 along the line C-C' shown in Figures 13 and 14. Figure 18 shows a cross-sectional view of a NAND cell 1300 along the line D-D' shown in Figures 13 and 14.

[0097] In certain embodiments, Figure 13 shows (from above) the structure associated with the active region 104 (e.g., NMOS active region) of the upper transistor in a vertical stacked transistor, and Figure 14 shows (from the back) the structure associated with the active region 106 (e.g., PMOS active region) of the lower transistor. In the illustrated embodiments, the upper metal layer 112D is the ground rail (e.g., VSS rail), and the back metal layer 120B is the power rail (e.g., VDD rail). The remaining upper metal layers (e.g., upper metal layers 112A, 112B, 112C) and back metal layers (e.g., back metal layers 120A, 120C) may be used for signal routing and / or internal routing within the NAND cell 1300, as described below.

[0098] In the illustrated embodiment, as shown in Figure 13, the NAND cell 1300 includes upper gates 108A and 108B, which are active NMOS gates located within the cell. Insulated gates 110A and 110B (e.g., dummy gates) are located at both ends of the cell 1300 in the gate pitch direction, with upper contact 126A located between insulated gate 110A and upper gate 108A, upper contact 126B located between upper gate 108A and upper gate 108B, and upper contact 126C located between upper gate 108B and insulated gate 110B, similarly located in the gate pitch direction. Furthermore, in the illustrated embodiment, as shown in Figure 14, the NAND cell 1300 includes lower gates 116A and 116B, which are active PMOS gates located within the cell. The lower contact 126D is located between the insulated gate 110A and the lower gate 116A in the gate pitch direction, the lower contact 126E is located between the lower gate 116A and the lower gate 116B, and the lower contact 126F is located between the lower gate 116B and the insulated gate 110B.

[0099] In various embodiments, as shown in Figures 13 and 15, contact 114A provides a connection between contact 126A and the upper metal layer 112D (e.g., the grounding rail). Contact 126A is also connected to the source / drain region 124A of the upper gate 108A. Figures 15 to 18 show the six source / drain regions 124A to F within the NAND cell 1300, noting that source / drain regions 124A to C are the upper source / drain regions, and source / drain regions 124D to F are the lower source / drain regions. In the NAND cell 1300, the upper source / drain regions 124A to C are separated from the lower source / drain regions 124D to F. In addition, the upper source / drain regions 124A-C and upper gates 108A and 108B include the upper channel 1304, while the lower source / drain regions 124D-F and lower gates 116A and 116B include the lower channel 1306.

[0100] The contact 114B shown in Figures 13 and 16 provides a connection between the upper gate 108A and the upper metal layer 112B, which may be a route for input signals to the device of the NAND cell 1300. The NAND cell 1300 further includes a contact 114D (shown in Figures 13 and 18) connecting contact 126C to the upper metal layer 112A, which may be a route for output signals from the device of the NAND cell 1300.

[0101] In the intended embodiment of the NAND cell 1300, the upper gate and the lower gate are merged. For example, as shown in Figure 16, the upper gate 108A is merged with the lower gate 116A. Thus, contact 114B provides a connection (e.g., an input signal route) between the merged upper gate 108A and lower gate 116A and the upper metal layer 112B. The upper gate 108B and lower gate 116B may also be merged (as shown in Figure 13) and connected to contact 114C, which then provides a connection to the upper metal layer 112C, which may be a second route for input signals to the device of the NAND cell 1300.

[0102] In various embodiments, the NAND cell 1300 includes back vias 122A and 122C, as shown in Figures 14, 15, 17, and 18. Back via 122A provides a connection between the lower contact 126D and the back metal layer 120C, as shown in Figures 14 and 15. The back metal layer 120C is also connected to the lower contact 126F by back via 122C, as shown in Figures 14 and 18. Thus, the back metal layer 120C provides an internal (to the cell) route between the lower contact 126D (connected to the lower source / drain region 124D of the lower gate 116A) and the lower contact 126F (connected to the lower source / drain region 124F of the lower gate 116B).

[0103] In certain embodiments, the NAND cell 1300 includes vias 1302A and 1302B. Vias 1302A and 1302B are top-to-back vias connecting the upper contact 126C to the lower contact 126F, as shown in Figures 13, 14, and 18. Thus, vias 1302A and 1302B provide a connection between the upper source / drain region 124C of the upper gate 108B and the lower source / drain region 124F of the lower gate 116B. Note that in the depictions in Figures 13 and 14, vias 1302A and 1302B may be partially obscured from view by contact 114D and back via 122C, respectively.

[0104] The NAND cell 1300 further includes a back via 122B, as shown in Figures 14 and 17. The back via 122B provides a power connection to the lower source / drain region 124E (from the back metal layer 120B, which is a power rail). The lower source / drain region 124E is shared by the lower gates 116A and 116B within the lower active region 106. Thus, power is supplied to all active gates via the back via 122B, as the lower gates 116A and 116B are merged into the upper gates 108A and 108B, respectively. Complementary FET SRAM cell

[0105] In various embodiments, stacked transistors as described herein can be implemented in memory cells such as SRAM cells. Figure 19 shows a schematic diagram of a memory cell. Cell 1700 is, for example, a 6T SRAM memory cell. Cell 1700 includes two inverters 1710A and 1710B, which are cross-coupled and have inputs supplied to outputs at nodes 1712 and 1714. Node 1712 is coupled to the output of pass gate 1720, and node 1714 is coupled to the output of pass gate 1722. Pass gates 1720 and 1722 are sometimes called “access gates” or “transmission gates”. Word line 1730 is coupled to pass gates 1720 and 1722 to supply control signals to the pass gates. Bit line 1740 is coupled to pass gate 1720 to read / write data from the pass gate. A bit line 1742, complementary to bit line 1740, is connected to the pass gate 1722 to read / write data from the pass gate.

[0106] Cell 1700 includes six transistors (two for each inverter and one for each pass gate) using inverters 1710A, 1710B, pass gate 1720, and pass gate 1722. In a particular embodiment, inverter 1710 includes two complementary transistors, for example, each inverter includes an NMOS transistor and a PMOS transistor. Pass gates 1720 and 1722 may be transistors of the same type. In one embodiment, both pass gates are NMOS transistors. Thus, in various embodiments, cell 1700 includes four NMOS transistors and two PMOS transistors.

[0107] This disclosure envisions various techniques for implementing multilayer transistors within memory cells. For example, the multilayer transistor described above can be implemented within a 6T SRAM memory cell shown in Figure 19. Utilizing the disclosed embodiments of the multilayer transistor within a memory cell provides the ability to minimize spacing between multiple transistors within the memory cell. Thus, the disclosed embodiments of the memory cell include multiple transistors with a small scale factor.

[0108] Specific embodiments disclosed herein include five broad elements: 1) a first transistor region having parallel first and second active regions; 2) a second transistor region having parallel third and fourth active regions and positioned vertically below the first transistor region; 3) a first inverter formed by the transistors in the first active region and the transistor in the third active region; 4) a second inverter formed by the transistors in the second active region and the transistor in the fourth active region; and 5) a cross coupling between the first inverter and the second inverter. In specific embodiments, the source / drain regions within the inverters are merged. For example, the source / drain regions on the opposing sides of the gates of two transistors within the first inverter may be merged. In certain embodiments, cross coupling is achieved by coupling the horizontally extending portion of the transistor gate in the third active region with the source / drain region of the transistor in the fourth active region, and by coupling the horizontally extending portion of the transistor gate in the fourth active region with the source / drain region of the transistor in the third active region.

[0109] In various embodiments, the horizontally extending portion of the gate for the cross-connection portion extends toward and possibly into other active regions (for example, the gate of a transistor in a third active region has a portion extending into a fourth active region). By extending the gate as described herein, it becomes possible to make a cross-connection in an area of ​​the cell vertically below the active region of the memory cell. The cross-connection may also be located vertically above any back layer routing. This area is available for cross-connection by removing the material from the inert portions of the third and fourth active regions.

[0110] In summary, the inventors have recognized that by mounting multilayer transistors within a memory cell and removing the inert material from the active region, cross-coupling of inverters formed by the transistors within the memory cell is possible. Cross-coupling of inverters in the area intended for the inert region provides a memory cell structure that maintains current design principles while also reducing the cell height compared to a typical memory cell. By utilizing cross-coupling in the area below the active region, the active regions can be positioned more closely together vertically, thus reducing the cell height. Therefore, by minimizing the vertical spacing between active regions, the overall height of the memory cell can be reduced.

[0111] Figure 20 shows an upper plan view of a memory cell 1800 having a stacked transistor according to several embodiments. Figure 21 shows a rear plan view of a memory cell 1800 having a stacked transistor according to several embodiments. Figure 22 shows a cross-sectional view of the memory cell 1800 along line A-A' shown in both Figures 20 and 21. Figure 23 shows a cross-sectional view of the memory cell 1800 along line B-B' shown in both Figures 20 and 21. Figure 24 shows a cross-sectional view of the memory cell 1800 along line C-C' shown in both Figures 20 and 21.

[0112] For the sake of simplicity in the drawings, the representations of cells disclosed herein show only the components relevant to this disclosure. Those skilled in the art will understand that additional components may be present in any of the cells shown herein. For example, in some depictions in Figures 20 and 21, various connections (such as vias or contacts as described herein) may be visible. In addition, for a better understanding of the disclosed embodiments, some transparency of the materials is provided to allow visibility of the underlying components in the upper and back plan views. For example, in Figures 20 and 21, the gate (e.g., polyline) and source / drain regions have some transparency to provide visibility of the vias / contacts and the active region in the area beneath the transistor, and in Figures 20 and 21, the upper and back metal layers have transparency to provide visibility of the transistor which would be hidden in the plan view. In the cross-sectional views of Figures 22–24, the depth of various components is more clearly visible. It should be noted that in the cross-sectional views of Figures 22–24, the upper metal layer is not shown for the sake of further simplification of the drawings.

[0113] In the illustrated embodiment, cell 1800 includes two upper active regions 1810, 1820 (shown in Figure 20) and two lower active regions 1830, 1840 (shown in Figure 21). In certain embodiments, the upper active regions 1810, 1820 are active regions for NMOS transistors, and the lower active regions 1830, 1840 are active regions for PMOS transistors. The lower active regions 1830, 1840 may include inert portions 1833, 1842 (indicated by the gradient fill pattern in the active region of Figure 21). The inert portions 1833, 1842 can be formed by not providing diffusing material to the portion (for example, by removing the diffusing material or not depositing diffusing material to the portion), or by cutting the diffusing material from the active portion of the lower active regions 1830, 1840 (for example, by a separation structure or separation mechanism).

[0114] The upper active region 1810 is separated from the upper active region 1820 by a diffusion interval distance of 1815. Similarly, the lower active region 1830 is separated from the lower active region 1840 by a diffusion interval distance of 1835. In some embodiments, distances 1815 and 1835 are substantially the same.

[0115] In the illustrated embodiment, the upper active region 1810 includes the upper gate 1812 between the source / drain region 1814A and the source / drain region 1814B, and the upper gate 1816 between the source / drain region 1814B and the source / drain region 1814C. The upper active region 1820 includes the upper gate 1822 between the source / drain region 1824A and the source / drain region 1824B, and the upper gate 1826 between the source / drain region 1824B and the source / drain region 1824C. The upper gates 1812, 1816, 1822, and 1826 may be polygates or other types of gates for the FET transistor device. In one embodiment, the upper gates 1812, 1816, 1822, and 1826 are NMOS gates.

[0116] In certain embodiments, the upper gate 1812 is isolated from the upper gate 1822, and the upper gate 1816 is isolated from the upper gate 1826. For example, the poly for upper gate 1812 is not connected to the poly for upper gate 1822. Similarly, the poly for upper gate 1816 is not connected to the poly for upper gate 1826. The upper gates can be isolated by either cutting the poly between the upper gates (e.g., cutting the poly between upper active region 1810 and upper active region 1820), or by forming the upper gates from separate poly layers within upper active region 1810 and upper active region 1820. The isolation of the upper gates between upper active region 1810 and upper active region 1820 provides distinction between the transistors formed by these upper gates, enabling the upper gates to form transistors for inverters and pass gates, as described herein.

[0117] In the illustrated embodiment, the lower active region 1830 includes a lower gate 1832 between the source / drain region 1834A and the source / drain region 1834B. The lower active region 1840 includes a lower gate 1846 between the source / drain region 1844B and the source / drain region 1844C. It should be noted that the lower active regions 1830 and 1840 have only two gate regions, which is due to the presence of inactive regions 1833 and 1842, and because only two transistors are needed in combination with the four transistors in the upper active region to form a memory cell device. The lower gates 1832 and 1846 may be polygates or other types of gates for FET transistor devices. In one embodiment, the lower gates 1832 and 1846 are PMOS gates.

[0118] In certain embodiments, as shown in Figure 21, portions of the lower gates 1832 and 1846 extend across the separation distance 1835 between the lower active region 1830 and the lower active region 1840. The portions of the lower gates 1832 and 1846 extend across the separation distance and are also visible in the gap between the upper active region 1810 and the upper active region 1820 in the depiction in Figure 20. In some embodiments, portions of the lower gates 1832 and 1846 extend across the separation distance 1835 and extend below the transistor region of the other lower active region. For example, as shown in Figures 20 and 21, the lower gate 1832 extends into the transistor region around the lower active region 1840, which is below the transistor region around the upper active region 1820. Similarly, the lower gate 1846 extends into the transistor region around the lower active region 1830, which is below the transistor region around the upper active region 1810. In some embodiments, portions of the lower gates 1832 and 1846 extend below the transistor region defining the pass gate within the upper active region, as will be described in more detail below. The extensions of the lower gates 1832 and 1846 that cross the active region provide the capability for cross-coupled connections within the cell 1800, as will also be described in more detail below.

[0119] Here, an exemplary embodiment of a 6T (6-transistor) SRAM memory cell that may be implemented within cell 1800 is described in relation to the various connections made within the cell to implement six transistors (e.g., four NMOS transistors and two PMOS transistors) arranged as inverters and pass gates. It should be understood that various additional embodiments of the memory cell may be contemplated based on the disclosed structure of cell 1800. As shown in Figure 19, the 6T SRAM memory cell includes two NMOS transistors and two PMOS transistors arranged to form two inverters, which are then cross-coupled. The two NMOS transistors are then arranged to form pass gates connected to the inverters.

[0120] Returning to cell 1800, the upper gate 1812 shown in Figure 20, together with source / drain regions 1814A and 1814B, can form the first NMOS transistor 1850 of inverter 1710A. Next, as shown in Figure 21, the lower gate 1832, together with source / drain regions 1834A and 1834B, can form the first PMOS transistor 1852 of inverter 1710A. To form inverter 1710A using transistors 1850 and 1852, source / drain region 1814A is merged with source / drain region 1834A by S / D merge 1860A. S / D merge 1860A may be, for example, a via or other substantially vertical connection formed between source / drain region 1814A and source / drain region 1834A. By merging source / drain region 1814A and source / drain region 1834A, the power connections between transistor 1850 and transistor 1852 are merged.

[0121] In addition, for transistors 1850 and 1852, the source / drain region 1814B is merged into the source / drain region 1834B by the S / D merge 1860B (as shown in Figure 22). The merging of the source / drain region 1814B and the source / drain region 1834B merges the outputs of transistors 1850 and 1852. The inputs of transistors 1850 and 1852 can be merged by merging the upper gate 1812 with the lower gate 1832 using the gate merge 1862A. The gate merge 1862A may be a via or other substantially vertical connection formed between the upper gate 1812 and the lower gate 1832, as shown in Figure 23. When the inputs and outputs of transistors 1850 and 1852 are merged, these transistors form an inverter 1710A.

[0122] The inverter 1710B shown in Figure 19 can similarly be formed by a second NMOS transistor 1854 and a second PMOS transistor 1856, as shown in Figures 20 and 21. Transistor 1854 can be formed by combining an upper gate 1826 with source / drain regions 1824B and 1824C, as shown in Figure 20. Transistor 1856 can be formed by combining a lower gate 1846 with source / drain regions 1844B and 1844C, as shown in Figure 21. Source / drain region 1814A is merged into source / drain region 1834A by S / D merger 1860A.

[0123] To form inverter 1710B using transistors 1854 and 1856, the source / drain region 1824B is merged into the source / drain region 1844B by S / D merger 1860C (also shown in Figure 22), and the source / drain region 1824C is merged into the source / drain region 1844C by S / D merger 1860D (also shown in Figure 24). The merging of source / drain region 1824B and source / drain region 1844B merges the outputs of transistors 1854 and 1856, while the merging of source / drain region 1824C and source / drain region 1844C merges the power connection between transistors 1854 and 1856. The inputs of transistors 1854 and 1856 are then merged by merging the upper gate 1826 with the lower gate 1846 using gate merger 1862B. When the inputs and outputs of transistors 1854 and 1856 are merged, these transistors form inverter 1710B.

[0124] In various embodiments, cell 1800 provides utility for forming pass gates 1720 and 1722 in addition to inverters 1710A and 1710B. For example, as shown in Figure 20, a third NMOS transistor 1858 can be used to form pass gate 1720, and a fourth NMOS transistor 1859 can be used to form pass gate 1722. It should be noted that both transistors 1858 and 1859 are formed without the underlying PMOS transistors (e.g., above the inert portion of the lower active region). In the illustrated embodiment, transistor 1858 is formed by an upper gate 1822 and source / drain regions 1824A and 1824B. Transistor 1859 is formed by an upper gate 1816 and source / drain regions 1814B and 1814C.

[0125] Both upper gates 1816 and 1822 may be coupled to a word line (e.g., word line 1730) for transmitting control signals to the gates. Read / write data connections to the bit line (e.g., bit line 1742) for upper gate 1816 may be provided via the source / drain region 1814C, while read / write data connections to the bit line (e.g., bit line 1740) for upper gate 1822 may be provided via the source / drain region 1824A. The output of transistor 1859 (corresponding to pass gate 1722) is provided via the source / drain region 1814B, which is also the output of transistor 1850 and is merged with the output of transistor 1852 in inverter 1710A. Correspondingly, the output of transistor 1858 (corresponding to pass gate 1720) is provided via the source / drain region 1824B, which is also the output of transistor 1854 and is merged with the output of transistor 1856 in inverter 1710B. Thus, transistors 1858 and 1859 provide pass gate transistors 1720 and 1722 which are coupled to inverters 1710A and 1710B according to the schematic diagram in Figure 19.

[0126] As described above, in certain embodiments, the lower gate 1832 (in transistor 1852 of inverter 1710A) and the lower gate 1846 (in transistor 1856 of inverter 1710B) extend toward the inert portion of the active region of the opposite transistor region. These extensions provide the ability to provide cross coupling between inverters below the active region of cell 1800. For example, as shown in Figure 23, the lower gate 1832 extends downwards to the gate 1822 formed within the active region 1820. The extension of the lower gate 1832 allows for the coupling of a cross coupling portion 1864B between the lower gate 1832 (which is a merged PMOS transistor gate in inverter 1710A) and the source / drain region 1844B (which is a merged PMOS source / drain region in inverter 1710B). Thus, the cross coupling portion 1864B cross-couples the input of inverter 1710A to the output of inverter 1710B. Similarly, the cross-coupler 1864A shown in Figures 20 to 22 can be implemented to cross-couple the input of inverter 1710B (by coupling to the extension of the lower gate 1846) and the output of inverter 1710A (by coupling to the source / drain region 1834B as shown in Figure 22).

[0127] In certain embodiments, the cross-couplers 1864A and 1864B are located below the active region and above the back metal layer 120 within the cell 1800. For example, as shown in Figures 22 and 23, the cross-couplers 1864A and 1864B are coupled to the back side (e.g., the bottom) of the lower gate and source / drain regions within the lower transistor region of the PMOS transistor. The cross-couplers 1864A and 1864B may be located in this area due to the removal of material in the inert portions 1833 and 1842 of the lower active regions 1830 and 1840. The use of the cross-couplers 1864A and 1864B within the cell 1800 reduces the cell height compared to a typical SRAM cell, while maintaining the current design principles for SRAM cells. For example, cross-connections 1864A and 1864B implemented using lower gates 1832 and 1846 provide better area scaling in cell 1800 by allowing both the upper active regions 1810 and 1820 and the lower active regions 1830 and 1840 to be closer to each other. For example, in some embodiments, both the upper active regions 1810 and 1820 and the lower active regions 1830 and 1840 may be arranged with the minimum necessary spacing between diffusion regions within the active regions. By implementing the minimum necessary spacing, the height of cell 1800 can be reduced to about half the typical height of a 6T SRAM cell. Macro SRAM cell

[0128] In various embodiments, the multilayer transistors described herein may be implemented not only within memory cells such as SRAM cells (e.g., SRAM bit cells), but also within peripheral cells associated with SRAM cells. For example, this disclosure envisions various techniques for implementing column input / output logic cells that include multilayer transistors. Implementing multilayer transistors in peripheral cells such as column input / output logic cells may enable the use of both top-side routing and back-side routing in memory devices containing various types of SRAM cells, including various embodiments of SRAM cells described herein.

[0129] Certain embodiments disclosed herein have four broad elements, namely: 1) a plurality of bit cells formed within first and second transistor regions arranged perpendicular to each other; 2) a first metal layer located above the bit cells (e.g., an upper metal layer) and a second metal layer located below the bit cells (e.g., a back metal layer); 3) a first column input / output logic cell coupled to the first array of bit cells; and 4) a second column input / output logic cell coupled to the second array of bit cells, wherein the second array of bit cells is closer to the logic cells than the first array of bit cells. In certain embodiments, the first metal layer includes a first routing that couples the first array of bit cells to the first column input / output logic cell, while the second metal layer includes a second routing that couples the second array of bit cells to the second column input / output logic cell. In some embodiments, the column input / output logic cell implements a multilayer transistor as described herein.

[0130] Therefore, in various embodiments, a first column input / output logic cell provides column I / O logic to bit cells further away from the peripheral region of the device, and a second column input / output logic cell provides column I / O logic to bit cells closer to the peripheral region of the device. Dividing routing between the upper and lower metal layers reduces routing congestion compared to using only upper routing or only lower routing for routing logic within the memory device. In various embodiments, dummy cells may be used for local routing of bit line signals between the upper and lower metal layers. For example, dummy cells may be used for local routing near bit cells in the first array (e.g., bit cells far from logic cells).

[0131] In summary, the inventors have recognized that routing for column I / O logic in both the upper and lower metal layers can be utilized in memory devices to alleviate metal congestion in the memory device. In addition, when both the upper and lower metal layers are used to route logic between bit cells and logic cells, various techniques are implemented to reduce any area penalty associated with forward-to-backward transitions (or vice versa). In some embodiments, various routing paths provide reduced resistance paths for logic within the memory device. The disclosed embodiments of the memory device, through the implementation of various disclosed techniques, may have strong signal connectivity with improved read / write speeds and thus improved performance.

[0132] Figure 25 shows an exemplary block diagram of a memory device according to several embodiments. In the illustrated embodiments, the memory device 2300 includes a memory cell area 2310 and a logic circuit cell area 2320. The memory cell area 2310 includes a plurality of bit cells which may be divided into a far bit cell array 2312A and a near bit cell array 2312B. The bit cells in the array may be, for example, the SRAM cells 1800 described above. As shown in Figure 25, the far bit cell array 2312A includes a plurality of bit cells which are located further away from the logic circuit cell area 2320 than the bit cells in the near bit cell array 2312B.

[0133] In various embodiments, the logic circuit cell area 2320 includes a plurality of column input / output (I / O) logic cells 2322. The column I / O cells 2322 may, for example, manage read / write operations from the bit cell array 2312. The column I / O cells 2322 may also include sense amplifier portions. It should be understood that the logic circuit cell area 2320 may include other logic cells in addition to the column input / output (I / O) logic cells 2322. For example, the logic circuit cell area 2320 may also include power switch logic cells, word line logic circuit cells, local I / O circuit cells, global I / O circuit cells, etc. In some embodiments, the logic circuit cell area 2320 may be referred to as the peripheral area of ​​the memory device 2300.

[0134] In the intended embodiment, the logic circuit cell region 2320 includes individual column I / O logic cells 2322 for each bit cell array in the memory cell region 2310. For example, in the illustrated embodiment, since the memory cell region 2310 has two bit cell arrays 2312A and 2312B, the logic circuit cell region 2320 includes a first column I / O logic cell 2322A and a second column I / O logic cell 2322B.

[0135] In various embodiments, the first column I / O logic cell 2322A provides column I / O logic for the far bit cell array 2312A, and the second column I / O logic cell 2322B provides column I / O logic for the near bit cell array 2312B. Routing in both the upper metal layer 112 and the back metal layer 120 may be utilized in the memory device 2300 to alleviate metal density in the memory device. This disclosure intends a routing method that reduces any front-to-back transition area penalty when utilizing both the upper metal layer 112 and the back metal layer 120 when routing logic between bit cells and logic cells.

[0136] In certain embodiments, the memory device 2300 utilizes both the upper metal layer 112 and the back metal layer 120 for bit line routing within the memory device. For example, the upper metal layer 112 may be used for bit line routing between the near bit cell array 2312B and the second column I / O logic cell 2322B, and the back metal layer 120 may be used for bit line routing between the far bit cell array 2312A and the first column I / O logic cell 2322A. In the illustrated embodiment, bit lines 1740A and 1742A provide bit line routing within the far bit cell array 2312A, and bit lines 1740B and 1742B provide bit line routing within the near bit cell array 2312B. Bit lines 1740 and 1742 may be complementary bit lines, as described herein.

[0137] As shown in Figure 25, bit lines 1740A and 1742A in the far bit cell array 2312A are coupled to bit line outputs 2314A and 2316A, respectively. Then, bit line output 2314A is coupled to back bit line routing 2330, and bit line output 2316A is coupled to back bit line routing 2332. In certain embodiments, bit lines 1740A and 1742A are located in the upper metal layer 112. For example, as shown in Figures 19 and 20, the output of a pass gate transistor is in the upper transistor region and coupled to the upper metal layer 112. Since bit lines 1740A and 1742A are routed in the upper metal layer 112 as shown in Figure 25, a transition is required from the upper metal layer to the back metal layer 120 where back bit line routings 2330 and 2332 are located.

[0138] In certain embodiments, dummy cells 2340A and 2340B are located at or near bit line outputs 2314A and 2316A, respectively. Dummy cell 2340A includes a connection between bit line 1740A in the upper metal layer 112 and back bit line routing 2330 in the back metal layer 120. Dummy cell 2340B includes a connection between bit line 1742A in the upper metal layer 112 and back bit line routing 2332 in the back metal layer 120. Figure 26 shows an upper plan view of a region having dummy cells 2340 according to several embodiments. Figure 27 shows a back plan view of a region having dummy cells 2340 according to several embodiments. Figure 28 shows a cross-sectional view of a region having dummy cells 2340 along line A-A' shown in both Figures 26 and 27. Figure 29 shows a cross-sectional view of the region containing the dummy cell 2340 along the line B-B' shown in both Figures 26 and 27.

[0139] In various embodiments, as shown in Figure 26, the upper metal layer 112 within region 2400 includes routing for the ground signal 2401 and the word line 2402, in addition to the bit lines 1740A and 1742A. In various embodiments, as shown in Figure 27, the back metal layer 120 within region 2400 includes routing for the signal 2500 and the power signal 2502, in addition to the back bit line routing 2330 and the back bit line routing 2332. In certain embodiments, dummy gates 2410 are positioned adjacent to the active gates 2440 on both sides of region 2400. The dummy gates 2410 may be, for example, gate cuts or other gates that isolate areas between dummy gates. Isolation may include, for example, preventing connections to any gate activity in the area between dummy gates 2410.

[0140] In certain embodiments, dummy cells 2340A and 2340B include trench metal 2420 formed between bit line 1740A and back bit line routing 2330, and between bit line 1742A and back bit line routing 2332, as shown in Figures 26 to 29. Bit lines 1740A and 1742A may be coupled to the trench metal 2420 by vias 2430 (shown in Figures 26 and 28 to 29), and back bit line routings 2330 and 2332 may be coupled to the trench metal 2420 by vias 2530 (shown in Figures 27 to 29).

[0141] The use of trench metal 2420 for the connection between bit lines 1740A, 1742A and backside bit line routing 2330, 2332 provides a low electrical resistance path for bit line signals to transition from the upper metal layer 112 to the backside metal layer 120. Dummy cell 2340 provides localized traffic management for bit line signals in or near the far bit cell array 2312A. Although dummy cell 2340 has some area penalty in memory device 2300, the area penalty is small because the dummy cell is localized to a shallow metal layer and is not associated with any global routing.

[0142] Returning to Figure 25, the bit line signals are routed to the back bit line routing 2330 and back bit line routing 2332 in dummy cells 2340A and 2340B, respectively. The back bit line routing then carries the signals to the bit line inputs 2324A and 2326A in the first column I / O cell 2322A, respectively. As will be explained below, the bit line inputs 2324A and 2326A in the first column I / O cell 2322A (and the bit line inputs in the second column I / O cell 2322B) are inputs located in the back metal layer. Therefore, no additional transitions between the upper metal layer 112 and the back metal layer 120 are required for the transmission of bit line signals from the back bit line routing 2330 and back bit line routing 2332 to the bit line inputs 2324A and 2326A in the first column I / O cell 2322A.

[0143] Here, referring to the near-bit cell array 2312B, bit lines 1740B and 1742B are coupled to bit line outputs 2314B and 2316B, respectively. Then, bit line outputs 2314B and 2316B are coupled to upper bit line routings 2334 and 2336, respectively. Since both bit lines 1740B, 1742B, and upper bit line routings 2334 and 2336 are located within the upper metal layer 112, a transition between the upper metal layer and the back metal layer 120 is not required near the near-bit cell array 2312B.

[0144] In the illustrated embodiment, the upper bit line routing 2334 and the upper bit line routing 2336 transport the bit line signals from the near-bit cell array 2312B to the bit line inputs 2324B and 2326B in the second column I / O cell 2322B, respectively. As described above and below, the bit line inputs 2324B and 2326B are located within the back metal layer 120. Therefore, a transition from the upper metal layer 112 to the back metal layer 120 may be required for the bit line inputs 2324B and 2326B.

[0145] In certain embodiments, the dummy cell 2350 is located at or near the bit line inputs 2324B, 2326B. The dummy cell 2350 includes connections between the upper bit line routing 2334 in the upper metal layer 112 and the bit line input 2324B in the back metal layer 120, and between the upper bit line routing 2336 in the upper metal layer 112 and the bit line input 2326B in the back metal layer 120. Figure 30 shows an upper plan view of a region having the dummy cell 2350 according to several embodiments. Figure 31 shows a back plan view of a region having the dummy cell 2350 according to several embodiments. Figure 32 shows a cross-sectional view of a region having the dummy cell 2350 along the line A-A' shown in both Figures 30 and 31. Figure 33 shows a cross-sectional view of a region having the dummy cell 2350 along the line B-B' shown in both Figures 30 and 31.

[0146] In various embodiments, as shown in Figure 30, the upper metal layer 112 within region 2800 includes routing for ground signal 2802 and signal 2804, in addition to upper bit line routing 2334 and upper bit line routing 2336. In various embodiments, as shown in Figure 31, the back metal layer 120 within region 2800 includes routing for signal 2900 and power signal 2902, in addition to bit line input 2324B and bit line input 2326B. In certain embodiments, dummy gates 2810 are located adjacent to the active gates 2840 on both sides of region 2800. The dummy gates 2810 may be, for example, gate cuts or other gates that isolate areas between dummy gates. Isolation may include, for example, preventing connections to any gate activity in the area between dummy gates 2810.

[0147] In certain embodiments, the dummy cell 2350 includes trench metal 2820 formed between the upper bit line routing 2334 and the bit line input 2324B, and between the upper bit line routing 2336 and the bit line input 2326B, as shown in Figures 30 to 33. The upper bit line routings 2334 and 2336 may be coupled to the trench metal 2820 by vias 2830 (shown in Figures 30 and 32 to 33), and the bit line inputs 2324B and 2326B may be coupled to the trench metal 2820 by vias 2930 (shown in Figures 31 to 33).

[0148] Similar to dummy cells 2340, the use of trench metal 2820 for connections between upper bit line routing 2334, 2336 and back bit line inputs 2324B, 2326B provides a low electrical resistance path for bit line signals to transition from the upper metal layer 112 to the back metal layer 120. Dummy cell 2350 provides local traffic management for bit line signals within the logic circuit cell region 2320 (e.g., within the peripheral region).

[0149] Returning to Figure 25, similar to the first column I / O cell 2322A, the bit line inputs 2324B and 2326B in the second column I / O cell 2322B are inputs located in the back metal layer 120. Therefore, after the bit line signals are routed to the bit line inputs 2324B and 2326B by the dummy cell 2350, the second column I / O cell 2322B can receive the bit line signals in the appropriate metal layer. Due to various routings of bit line signals from the memory cell region 2310 to the logic circuit cell region 2320 via the combination of the upper metal layer 112 and the back metal layer, in various embodiments, the column logic I / O cells 2322 in the logic circuit cell region may have unipolar connectivity in a simple manufacturing method.

[0150] In various embodiments, the column I / O cell 2322 may implement stacked transistors to provide connectivity to the various routings described above for the memory device 2300. Figure 34 shows a schematic diagram of the column I / O cell 2322 according to several embodiments. In the illustrated embodiments, the cell 2322 includes five PMOS transistors and two NMOS transistors. The PMOS transistors include PMOS1 transistor 3210, PMOS2 transistor 3220, PMOS3 transistor 3230, PMOS4 transistor 3240, and PMOS5 transistor 3250. The NMOS transistors include NMOS1 transistor 3260 and NMOS2 transistor 3270.

[0151] As shown in Figure 34, various routings and connections for the transistors within cell 2322 are provided by the upper metal layer 112 (solid line) and the back metal layer 120 (dashed line). In a particular embodiment, cell 2322 includes Vdd 3202, Vss 3203, PCH 3204, Rcs 3206, Wcs 3208, word line outputs 3280A, 3280B, and sense outputs 3282A, 3282B. Vdd 3202 provides routing to the power supply for cell 2322, and Vss 3203 provides routing to ground. PCH 3204 couples PMOS1 transistor 3210, PMOS2 transistor 3220, and PMOS3 transistor 3230 to form a pre-charge circuit. Rcs 3206 couples PMOS4 transistor 3240 and PMOS5 transistor 3250 for the read column selection circuit, and Wcs 3208 couples NMOS1 transistor 3260 and NMOS2 transistor 3270 for the write column selection circuit. Word line outputs 3280A and 3280B provide write outputs from cell 2322, and sense outputs 3282A and 3282B provide read outputs from cell 2322.

[0152] In certain embodiments, the transistors within cell 2322 may be formed by multilayer transistors as described herein. For example, PMOS transistors are formed in the lower transistor region, and NMOS transistors are formed in the upper transistor region. Figure 35 shows the layout of cell 2322 according to several embodiments. In Figure 35, the upper figure is an upper plan view of the upper transistor region 3300, and the lower figure is a back plan view of the lower transistor region 3350. The upper transistor region 3300 includes an upper active region 3302, and the lower transistor region 3350 includes a lower active region 3352.

[0153] In the illustrated embodiment of the upper transistor region 3300 in Figure 35, the upper metal layer 112 includes routing for bit line inputs 2324 and 2326, Vss 3203, Wcs 3208, and word line outputs 3280A and 3280B. The NMOS1 transistor 3260 includes gates 3262A, 3262B, and 3262C, and source / drain regions 3264A, 3264B, 3264C, and 3264D. The NMOS2 transistor 3270 includes gates 3272A, 3272B, and 3272C, and source / drain regions 3267A, 3274B, 3274C, and 3274D. A dummy gate 3310 (e.g., gate cut) separates the NMOS1 transistor 3260 from the NMOS2 transistor 3270. Via 3312 connects gates 3262 and 3272 using WCS 3208. Via 3312 also connects source / drain regions 3264A and 3264C to word line output 3280A, and source / drain regions 3274B and 3274D to word line output 3280B. Further vias 3312 connect source / drain regions 3264B and 3264D to bit line input 2324, and source / drain regions 3274A and 3274C to bit line input 2326.

[0154] In the illustrated embodiment of the lower transistor region 3350 in Figure 35, the back metal layer 120 includes routing for bit line input 2324, bit line input 2326, Vdd 3202, PCH 3204, Rcs 3206, and sense outputs 3282A, 3282B. PMOS1 transistor 3210 includes gate 3212 and source / drain regions 3214A, 3214B. PMOS2 transistor 3220 includes gate 3222 and source / drain regions 3214B, 3214C. PMOS2 transistor 3230 includes gate 3232 and source / drain regions 3214C, 3214D. A dummy gate 3320 then isolates source / drain region 3214D and PMOS2 transistor 3230 from source / drain region 3244A in PMOS4 transistor 3240. The PMOS4 transistor 3240 includes a gate 3242 and source / drain regions 3244A and 3244B. Another dummy gate 3320 then isolates the PMOS4 transistor 3240 from the PMOS5 transistor 3250. The PMOS5 transistor 3250 includes a gate 3252 and source / drain regions 3254A and 3254B.

[0155] Via 3322 connects gates 3212, 3222, and 3232 via PCH 3204. Via 3322 also connects gates 3242 and 3252 using Rcs 3206. Further vias 3322 connect source / drain region 3244B to sense output 3282A and source / drain region 3254B to sense output 3282B. Further vias 3322 connect source / drain regions 3214B and 3244A to bit line input 2324 and source / drain regions 3214C ​​and 3254A to bit line input 2326. Vdd is connected to source / drain regions 3214A and 3214D via an additional via 3322.

[0156] In some embodiments, the source / drain region 3214B in the lower transistor region 3350 is merged with the source / drain region 3264B in the upper transistor region 3300 by a source / drain merge 3290A. In addition, the source / drain region 3254A may be merged with the source / drain region 3274C by a source / drain merge 3290B. These source / drain region merges provide the necessary connection between the NMOS transistor and the PMOS transistor.

[0157] Embodiments of the memory device 2300 described herein provide a memory device that can provide strong signal connectivity using current layout techniques without significant area penalty. Routing within the memory device 2300 avoids congestion of metal routing within the device by utilizing bit line routing through the upper and lower metal layers. The memory device 2300 also avoids the typical complexities associated with unipolar device manufacturing by utilizing the various routing and connection paths described herein. The various connection paths described herein can also reduce resistance within the memory device 2300, and thus improve the read / write speed and performance of the memory device. Vertical transistor cell

[0158] A recent development in transistor design is the implementation of vertical transistors, in which the cell has vertical transport through vertically displaced source / drain regions, and the gate is positioned vertically between the source / drain regions. Current vertical transistor designs typically include a wide front (e.g., top) power rail at the cell boundary for power supply. However, these wide power rails result in increased, large standard cell height. Increased standard cell height reduces the area efficiency of the vertical transistor, as well as the available connectivity and performance of the transistor.

[0159] This disclosure envisions various embodiments of utilizing back-side power routing in vertical transistor designs to reduce scaling, provide better connectivity, and offer better transistor performance. Specific embodiments disclosed herein have four broad elements: 1) a pair of vertical transistors in an integrated circuit cell; 2) an upper metal layer above the transistor region of the vertical transistors having signal routing; 3) a back-side metal layer below the transistor region having power routing; and 4) a metal contact layer between the back-side metal layer and the source / drain region of the transistors. In certain embodiments, the transistors are complementary transistors. In some embodiments, vias couple the power routing in the back-side metal layer to the metal contact layer. In some embodiments, a second pair of vertical transistors may be included in the cell. Additional implementations of gate vias, fins, contact vias, and various other connections and routings may also be envisioned in various embodiments.

[0160] In various embodiments, control signal and power signal connections are formed using various contacts or vias to implement logic associated with a particular integrated circuit device having multiple vertical transistors for the cell structure described herein. For example, examples of inverter devices, NAND devices, and MUX devices that can be implemented based on the vertical transistor cell structure are described below. Various expected embodiments of connections for control signal and voltage signals to the vertical transistors within the cell structure are also described. Those skilled in the art will understand that many different desired circuits can be generated by implementing various possible combinations of these connections based on the vertical transistor structure within the cell structure disclosed herein.

[0161] In summary, the inventors have recognized that implementing back-side routing for power connections in combination with vertical transistors provides various opportunities for constructing specific transistor designs with reduced scaling. In addition, various techniques are implemented to provide specific routing for control signals and power routing within cell structures having vertical transistors as described herein. The implementation of various disclosed techniques leads to the creation of vertical transistor cell structures that provide improved performance with a small scale factor.

[0162] Figure 36 shows a perspective view of a planned vertical transistor device according to several embodiments. Figure 37 shows a perspective view of another planned vertical transistor device according to several embodiments. It should be noted that device 3400 shown in Figure 36 and device 3500 shown in Figure 37 are general representations of vertical transistor-based device structures, and the various connections that can be made to these structures are not shown. Exemplary embodiments of connected structures are further disclosed below herein with respect to Figures 38 to 54.

[0163] In the embodiment illustrated in Figure 36, device 3400 includes two vertical transistors 3410 and 3420. In certain embodiments, transistors 3410 and 3420 are complementary transistors. For example, transistor 3410 is a PMOS transistor, and transistor 3420 is an NMOS transistor. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Similarly, transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. In some embodiments, gates 3414 and 3424 are fin-type gates. In various embodiments, gate 3414 includes a gate spacer 3415, and gate 3424 includes a gate spacer 3425. For the sake of simplicity in the drawings, gate spacers 3415 and 3425 are not labeled in the remaining drawings.

[0164] As shown in Figure 36, the lower source / drain region, gate, and upper source / drain region are stacked vertically in the transistor. Furthermore, as shown, transistors 3410 and 3420 are parallel, with a gap (e.g., distance) between them in the horizontal direction (e.g., horizontal direction) of device 3400.

[0165] In certain embodiments, transistor 3410 includes an upper contact 3418 coupled to an upper source / drain region 3416, and transistor 3420 includes an upper contact 3428 coupled to an upper source / drain region 3426. Contacts 3418 and 3428 may be metal contacts for contacting various resources in a first metal layer located above transistors 3410 and 3420. For example, as shown in Figure 36, contact 3418 may be routed to a resource by route 3430 (e.g., a routing shown by a dotted line). Route 3430 may be a metal layer route path in the first metal layer above transistors 3410 and 3420. It should be noted that the dotted line depiction of route 3430 is given as an example of one resource (e.g., a routing) in the metal layer, and the metal layer may contain multiple resources (e.g., multiple routings). Furthermore, only the first metal layer above transistors 3410 and 3420 is shown, and there may be multiple additional metal routings above route 3430.

[0166] In various embodiments, transistor 3410 includes a lower contact 3419 coupled to a lower source / drain region 3412, and transistor 3420 includes a lower contact 3429 coupled to a lower source / drain region 3422. Contacts 3419, 3429 may be, for example, metal contacts. Contacts 3419, 3429 may be used for routing to a back-side power routing layer (for example, back-side power routing 3440A or back-side power routing 3440B as shown in Figure 36 and described herein) or for routing to various other resources within device 3400.

[0167] In certain embodiments, device 3400 includes a back-side power layer. In the embodiment illustrated in Figure 36, the back-side power layer includes back-side power routing 3440A and back-side power routing 3440B. Routing 3440A and routing 3440B may provide routing to and from power (e.g., Vdd) and ground (e.g., Vss) resources for device 3400, for example.

[0168] In various embodiments, gates 3414 and 3424 are interconnected by a gate bridge 3450. The gate bridge 3450 may be formed, for example, by extending the gate material of gates 3414 and 3424 to join the gates together. In some embodiments, the gate bridge 3450 may be formed by a single extension of the gate material extending from either gate 3414 or gate 3424 to the other gate. The gate bridge 3450 may also include an extension of the material for gate spacers. The gate bridge 3450 merges gates 3414 and 3424 for the implementation of transistors 3410 and 3420 in various embodiments of the CMOS device, several examples of which are described herein. Various embodiments in which gates 3414 and / or gate 3424 extend in other directions may also be contemplated. For example, the gate may include an extension that extends toward the outer boundary of the device 3400 (for example, toward the outer boundary of the cell structure, in the opposite direction to the gate bridge 3450).

[0169] In the embodiment illustrated in Figure 37, device 3500 does not have a gate bridge connecting gate 3414 in transistor 3410 and gate 3424 in transistor 3420. Various techniques can be contemplated for connecting transistors 3410 and 3420 without a gate bridge. For example, in one contemplated embodiment, contacts 3418 and 3428 may be connected by a strap 3510. The strap 3510 may be, for example, a metal strap. In some embodiments, contacts 3418, 3428, and strap 3510 may be formed as a single contact (e.g., a single strap connecting upper source / drain regions 3416 and 3426). Various embodiments can also be contemplated in which the strap 3510 extends in a different direction from one of the contacts 3418, 3428. For example, the strap 3510 may extend perpendicular to the illustrated embodiment toward another vertical transistor or resource within device 3500.

[0170] In another intended embodiment, contacts 3419 and 3429 may be connected by a strap 3520. The strap 3520 may also be a metal strap. In some embodiments, the strap 3520 is formed together with contacts 3419 and 3429 as a single contact. For example, the strap 3520, contacts 3419, and contacts 3429 may be portions of a single metal contact plate formed within the contact layer. Various embodiments may also be intended in which contacts 3419 and / or contacts 3429 extend outward from the bottom of transistors 3410, 3420. For example, the contacts may have portions that extend toward the outer boundary of device 3500 (for example, toward the outer boundary of a cell structure).

[0171] While various connection structures are shown separately for device 3400 in Figure 36 and device 3500 in Figure 37, it should be understood that in cell design, embodiments may be conceived in which structures from device 3400 are combined with structures from device 3500. For example, a device may be conceived that includes both a gate bridge 3450 and one or both of straps 3510 and strap 3520. Hereinafter, various exemplary device cell configurations based on device 3400 and / or device 3500 are described as examples. It should be noted that various device cell structures are provided as examples, and various additional device cell structures may be implemented based on the description herein.

[0172] Figures 38 to 42 show diagrams of inverter cell structures according to several embodiments. Figure 38 shows a perspective view of an inverter cell structure according to several embodiments. Figure 39 shows an upper plan view of an inverter cell structure according to several embodiments. Figure 40 shows a rear plan view of an inverter cell structure according to several embodiments. Figure 41 shows a cross-sectional view of an inverter cell structure according to several embodiments along line 41-41 shown in Figure 39 (e.g., along the gate bridge). Figure 42 shows a cross-sectional view of an inverter cell structure according to several embodiments along line 42-42 shown in Figure 39 (e.g., perpendicular to the gate fin of transistor 3410).

[0173] The inverter cell device 3600 can be obtained from the structure of device 3400 shown in Figure 36. In the illustrated embodiments shown in Figures 38 to 42, device 3600 includes vertical transistors 3410 and 3420. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, an upper source / drain region 3416, an upper contact 3418, and a lower contact 3419. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, an upper source / drain region 3426, an upper contact 3428, and a lower contact 3429. In the illustrated embodiments of device 3600, transistor 3410 is a PMOS transistor and transistor 3420 is an NMOS transistor.

[0174] In a particular embodiment, device 3600 includes back-side vias 3610A and 3610B. Back-side via 3610A is coupled to the lower source / drain region 3412 via a lower contact 3419. Back-side via 3610A couples the lower source / drain region 3412 to back-side power routing 3440A. In the case of device 3600, back-side power routing 3440A supplies power (e.g., Vdd) to the lower source / drain region 3412 and transistor 3410. Back-side via 3610B is coupled to the lower source / drain region 3422 via a lower contact 3429. Back-side via 3610B couples the lower source / drain region 3422 to back-side power routing 3440B. In the case of device 3600, back-side power routing 3440B supplies ground (e.g., Vss) to the lower source / drain region 3422 and transistor 3420.

[0175] In various embodiments, device 3600 includes upper vias 3620A and 3620B. Upper via 3620A may be coupled to the upper source / drain region 3416 via upper contact 3418, and upper via 3620B may be coupled to the upper source / drain region 3426 via upper contact 3428. Upper vias 3620A and 3620B may provide connections to signal routing resources (e.g., routes 3430A-E) in the first metal layer above transistors 3410 and 3420. For example, in the illustrated embodiment, upper via 3620A is coupled to route 3430B, and upper via 3620B is coupled to route 3430D. Routes 3430B and 3430D may provide routes for output signals from transistors 3410 and 3420, respectively.

[0176] In certain embodiments, a route for input signals to transistors 3410 and 3420 is provided by route 3430C. As shown in Figures 38 and 39, route 3430C is coupled to gate via 3630, which is coupled to gate bridge 3450. Thus, gate via 3630 provides a connection between route 3430C (e.g., the input signal route) and both gate 3414 of transistor 3410 and gate 3424 of transistor 3420. Connections to the input signal route, output signal route, and power / ground route connect transistors 3410 and 3420 to form an inverter cell device 3600.

[0177] Figures 38 and 39 show five routes 3430A-E within the first metal layer above transistors 3410 and 3420, but it should be noted that the first metal layer may include additional routes. Furthermore, additional metal layers may be located above the first metal layer and provide various connections to either the first metal layer or device 3600. For example, in one embodiment, the metal layer above the first metal layer may include a strap (or other connector) connecting routes 3430B and 3430D so that the outputs of transistors 3410 and 3420 are merged together into a single output. In addition, two back-side power routings (e.g., routing 3440A and routing 3440B) are shown, but the back-side power layer may include additional routing (e.g., routing for other power and signal resources).

[0178] The top and back plan views of device 3600 shown in Figures 39 and 40 further illustrate the gate fins that may be present on the transistor gate. For example, gate fin 3415 is the gate fin for gate 3414, and gate fin 3425 is the gate fin for gate 3424. Gate fins 3415 and 3425 are also shown in the cross-sectional view of device 3600 in Figure 41, and gate fin 3415 is shown in the cross-sectional view of transistor 3410 in Figure 42. Note that the cross-sectional view in Figure 42 is perpendicular to the gate fin of transistor 3410, which is in the direction of route 3430B shown in Figures 38 and 39.

[0179] Figures 43 to 47 show diagrams of NAND cell structures according to several embodiments. Figure 43 shows a perspective view of a NAND cell structure according to several embodiments. Figure 44 shows a top plan view of a NAND cell structure according to several embodiments. Figure 45 shows a back plan view of a NAND cell structure according to several embodiments. Figure 46 shows a cross-sectional view of a NAND cell structure according to several embodiments along line 46-46 shown in Figure 44 (for example, along gate bridge 3450'). Figure 47 shows a cross-sectional view of a NAND cell structure according to several embodiments along line 47-47 shown in Figure 44 (for example, perpendicular to the gate fins of transistors 3410 and 3410').

[0180] The NAND cell device 4100 can be obtained from the structure of device 3400 shown in Figure 36. In the embodiments illustrated in Figures 43 to 47, device 4100 includes vertical transistors 3410, 3420, 3410', and 3420'. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. Transistor 3410' includes a lower source / drain region 3412', a gate 3414', and an upper source / drain region 3416'. Transistor 3420' includes a lower source / drain region 3422', a gate 3424', and an upper source / drain region 3426'. In the illustrated embodiment of device 4100, transistors 3410 and 3410' are PMOS transistors, and transistors 3420 and 3420' are NMOS transistors.

[0181] In certain embodiments, a route for input signals to transistors 3410, 3410', 3420, and 3420' is provided by route 3430C. As shown in Figures 43 and 44, route 3430C is coupled to gate via 3630A coupled to gate bridge 3450 and gate via 3630B coupled to gate bridge 3450'. Thus, gate via 3630A provides a connection between route 3430C (e.g., the input signal route) and both gate 3414 of transistor 3410 and gate 3424 of transistor 3420. Gate via 3630B provides a connection between route 3430C (e.g., the input signal route) and both gate 3414' in transistor 3410' and gate 3424' in transistor 3420'.

[0182] In certain embodiments, the upper source / drain region 3416 of transistor 3410 and the upper source / drain region 3416' of transistor 3410' are connected by contact 3418. Similarly, the upper source / drain region 3426 of transistor 3420 and the upper source / drain region 3426' of transistor 3420' are connected by contact 3428. In various embodiments, device 4100 includes an upper via 3620 connected to contact 3418. The upper via 3620 can provide a connection to route 3430B in the first metal layer above the transistor region of device 4100. In the illustrated embodiment, route 3430B provides a route for output signals from transistors 3410 and 3410'.

[0183] In the illustrated embodiment, only transistors 3410, 3410', and 3420 are connected to the back layer. For example, as shown in Figures 42 and 45, transistor 3410 is connected to the back power routing 3440A by contact 3419 and back via 3610A, transistor 3410' is connected to the back power routing 3440A by contact 3419' and back via 3610A', and transistor 3420 is connected to the back power routing 3440B by contact 3429 and back via 3610B. In various embodiments of device 4100, the back power routing 3440A supplies power (e.g., Vdd) to the lower source / drain region 3412 and transistor 3410, as well as to the lower source / drain region 3412' and transistor 3410', while the back power routing 3440B supplies ground (e.g., Vss) to the lower source / drain region 3422 and transistor 3420.

[0184] In certain embodiments, the lower source / drain region 3422' within transistor 3420' is connected to contact 3429', which is not connected to the back-side power routing layer. Contact 3429' extends toward the cell boundary away from the lower source / drain region 3422', as shown in Figures 43, 45, and 46. Contact 3429' is then coupled to route 3430E by contact via 4110. Route 3430E is a route in the first metal layer above the transistor region. Contact via 4110 is a via belonging to the cell structure of device 4100 and is not shared with any adjacent cells along the cell boundary. In certain embodiments, route 3430E is a signal route in the first metal layer for the signal output from transistor 3420'. Therefore, signals within the NMOS transistors (e.g., transistors 3420 and 3420') are routed from the lower source / drain region 3422 (connected to ground by the rear power routing 3440B) through the transistors and contact via 4110 to route 3430E.

[0185] In the illustrated embodiment, route 3430E provides a route for the output signals from transistors 3420 and 3420'. The output signals routed through route 3430E can be combined with the output signals from route 3430B. For example, a metal layer above the first metal layer may include a strap (or other connector) that connects route 3430B and route 3430E so that the outputs of the transistors are merged together to form a single output.

[0186] The various routings and connections within device 4100 form a NAND cell device. Figures 44 and 45 show gate fins 3415, 3415', 3425, and 3425' within gates 3414, 3414', 3424, and 3424', respectively. Gate fins 3415' and 3425' are also shown in the cross-sectional view of device 4100 in Figure 46, and gate fins 3415 and 3415' are shown in the cross-sectional view of device 4100 in Figure 47. Note that the cross-sectional view in Figure 47 is perpendicular to the gate fins of transistors 3410 and 3410', which is in the direction of route 3430B shown in Figure 44.

[0187] Figures 48 to 52 show diagrams of MUX (multiplexer) cell structures according to several embodiments. Figure 48 shows a perspective view of a MUX cell structure according to several embodiments. Figure 49 shows an upper plan view of a MUX cell structure according to several embodiments. Figure 50 shows a rear plan view of a MUX cell structure according to several embodiments. Figure 51 shows a cross-sectional view of a MUX cell structure according to several embodiments along line 51-51 shown in Figure 49 (e.g., along gate fins 3415' and 3425''). Figure 52 shows a cross-sectional view of a MUX cell structure according to several embodiments along line 52-52 shown in Figure 49 (e.g., perpendicular to the gate fins of transistors 3410 and 3410'').

[0188] The MUX cell device 4600 can be obtained from the structure of device 3500 shown in Figure 37. In the illustrated embodiments shown in Figures 48 to 52, device 4600 includes vertical transistors 3410, 3420, 3410'', and 3420''. Similar to device 3500, gate bridges exist between the gates of the transistors in device 4600, and as a result, there are no common gates between complementary transistors. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. Transistor 3410'' includes a lower source / drain region 3412'', a gate 3414'', and an upper source / drain region 3416''. Transistor 3420'' includes a lower source / drain region 3422'', a gate 3424'', and an upper source / drain region 3426''. In the illustrated embodiment of device 4600, transistors 3410 and 3410'' are PMOS transistors, and transistors 3420 and 3420'' are NMOS transistors.

[0189] Since the MUX cell device 4600 is a transmission device, neither transistor 3410 nor transistor 3410'', nor transistor 3420 nor transistor 3420'' are connected to any power within the MUX cell structure. In various embodiments of the MUX cell device 4600, the lower source / drain regions of the transistors are connected together (e.g., merged together). For example, in the illustrated embodiment, the contact plate 4620 is connected to the lower source / drain region 3412 of transistor 3410, the lower source / drain region 3412'' of transistor 3410'', the lower source / drain region 3422 of transistor 3420, and the lower source / drain region 3422'' of transistor 3420''.

[0190] In certain embodiments, contact via 4630 is coupled to contact plate 4620. Contact via 4630 may be connected to contact plate 4620 at or near the center of the contact plate. Then, contact via 4630 is connected to route 3430C in the first metal layer above the transistor region. In various embodiments, route 3430C provides output routing for the MUX cell device 4600. Thus, contact via 4630 can be referred to as an output pin of the MUX cell device 4600.

[0191] In various embodiments, gates 3414, 3414'', 3424, and 3424'' extend toward the cell boundary, providing a surface for a direct vertical connection from the root in the upper first metal layer to the gate. For example, as shown in Figures 48 to 52, gate 3414 includes a gate extension 4640A that extends toward the cell boundary (e.g., horizontally toward the cell boundary). Similarly, gate 3414'' includes a gate extension 4640B, gate 3424 includes a gate extension 4640C, and gate 3424'' includes a gate extension 4640D. The gate extensions 4640A to D are then connected, respectively, to the root in the upper first metal layer by gate vias 3630A to D. For example, as shown in Figures 48 and 49, gate via 3630A connects gate extension 4640A to route 3430A, gate via 3630B connects gate extension 4640B to route 3430A, gate via 3630C connects gate extension 4640C to route 3430E, and gate via 3630D connects gate extension 4640D to route 3430E. Either or both of routes 3430A and 3430E are located at the cell boundary and are not shared with adjacent cells. Routes 3430A and 3430E may provide input routes to device 4600.

[0192] In a particular embodiment, the upper source / drain region 3416 in transistor 3410 is connected to the upper source / drain region 3426 in transistor 3420 by contact 4610A. This connection merges the upper source / drain region 3416 into the upper source / drain region 3426. Similarly, the upper source / drain region 3416'' in transistor 3410'' is connected to the upper source / drain region 3426'' in transistor 3420'' by contact 4610B. The merging of these upper source / drain regions, along with the common connection between the lower source / drain regions (and a single output via contact via 4630), allows device 4600 to operate as a MUX (multiplexer) with signals input via gate vias 3630A-D and output via contact via 4630.

[0193] Figures 49 and 50 show gate fins 3415, 3415'', 3425, and 3425'' within gates 3414, 3414'', 3424, and 3424'', respectively. Gate fins 3415 and 3425 are also shown in the cross-sectional view of device 4600 in Figure 51, and gate fins 3415 and 3415'' are shown in the cross-sectional view of device 4600 in Figure 52. Note that the cross-sectional view in Figure 52 is perpendicular to the gate fins of transistors 3410 and 3410'', which is in the direction of route 3430B shown in Figure 49.

[0194] Figures 53 and 54 show diagrams of cell devices having dielectric walls according to several embodiments. Figure 53 shows a perspective view of device 5100 according to several embodiments. Figure 54 shows a cross-sectional view of device 5100 along line 54-54 shown in Figure 53 (for example, along gate bridge 3450') according to several embodiments.

[0195] Device 5100 can be obtained from the structure of device 3400 shown in Figure 36. In some embodiments, device 5100 may be similar to the inverter cell device 4100 shown in Figures 43 to 47. In the embodiments illustrated in Figures 53 and 54, device 5100 includes vertical transistors 3410 and 3420. Transistor 3410 includes a lower source / drain region 3412, a gate 3414, and an upper source / drain region 3416. Transistor 3420 includes a lower source / drain region 3422, a gate 3424, and an upper source / drain region 3426. In certain embodiments, transistor 3410 is a PMOS transistor and transistor 3420 is an NMOS transistor.

[0196] In various embodiments, as shown in Figures 53 and 54, wall 5100A may be located on the first side of the cell (e.g., the side of transistor 3410), and wall 5100B may be located on the second side of the cell (e.g., the side of transistor 3420 opposite to transistor 3410). In certain embodiments, walls 5100A and 5100B are dielectric walls. By placing dielectric walls on one or both sides of device 5100, the space required between device 5100 and another adjacent cell can be reduced. Therefore, walls 5100A and 5100B can be implemented when it is necessary to reduce the scaling of the device. Exemplary computer system

[0197] Referring next to Figure 55, a block diagram of one embodiment of system 5300 is shown, which can incorporate and / or utilize the methods and mechanisms described herein. In the illustrated embodiment, system 5300 includes at least one instance of system on chip (SoC) 5306, which may include multiple types of processing units such as a central processing unit (CPU), a graphics processing unit (GPU), or other methods, a communication fabric, and interfaces to memory and input / output devices. In some embodiments, one or more processors within SoC 5306 include multiple execution lanes and instruction issue queues. In various embodiments, SoC 5306 is coupled to external memory 5302, peripherals 5304, and a power supply 5308.

[0198] A power supply 5308 is also provided, which supplies a supply voltage to the SoC 5306 and one or more supply voltages to the memory 5302 and / or peripheral devices 5304. In various embodiments, the power supply 5308 represents a battery (e.g., a rechargeable battery for a smartphone, laptop or tablet computer, or other device). In some embodiments, two or more instances of the SoC 5306 are included (and two or more external memories 5302 are also included).

[0199] Memory 5302 is any type of memory, including dynamic random access memory (DRAM), synchronous DRAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM (including mobile versions of SDRAM such as mDDR3 and / or low-power versions such as LPDDR2), RAMBUS DRAM (RDRAM), and static RAM (SRAM). One or more memory devices are coupled to a circuit board to form memory modules such as single inline memory modules (SIMMs) and dual inline memory modules (DIMMs). Alternatively, the devices are mounted on an SoC or integrated circuit in a chip-on-chip, package-on-package, or multi-chip module configuration.

[0200] The peripheral device 5304 may include any desired circuit configuration depending on the type of system 5300. For example, in one embodiment, the peripheral device 5304 includes devices for various wireless communications such as Wi-Fi, Bluetooth, cellular, and global positioning systems. In some embodiments, the peripheral device 5304 also includes additional storage, including RAM storage, solid-state storage, or disk storage. The peripheral device 5304 includes user interface devices such as a display screen including a touch display screen or a multi-touch display screen, a keyboard or other input devices, a microphone, and a speaker.

[0201] As illustrated, system 5300 is shown to be applicable to a wide area. For example, system 5300 may be used as part of a chip, circuit, or component in a desktop computer 5310, a laptop computer 5320, a tablet computer 5330, a cellular or mobile phone 5340, or a television 5350 (or a set-top box coupled to a television). A smartwatch and a health monitoring device 5360 are also illustrated. In some embodiments, the smartwatch may include a variety of general-purpose computing-related functions. For example, the smartwatch may provide access to email, mobile phone services, a user calendar, etc. In various embodiments, the health monitoring device may be a dedicated medical device or may otherwise include dedicated health-related functions. For example, the health monitoring device may monitor the user's vital signs, track the user's proximity to other users for epidemiological social distancing, perform contact tracing, and provide communication to emergency services in the event of a health crisis. In various embodiments, the smartwatch described above may or may not include some or any of the health monitoring-related functions. Other wearable devices, such as devices worn around the neck, implantable devices in the human body, and glasses designed to provide augmented and / or virtual reality experiences, are also intended.

[0202] System 5300 may be further used as part of one or more cloud-based services 5370. For example, the aforementioned devices and / or other devices may have access to computing resources in the cloud (i.e., remotely located hardware and / or software resources). Furthermore, System 5300 may be used in one or more devices in a home 5380 other than those described above. For example, appliances in a home may monitor and detect conditions of note. For example, various devices in a home (e.g., refrigerators, cooling systems, etc.) may monitor the status of the devices and alert the homeowner (or repair facility) if a particular event is detected. Alternatively, a thermostat may monitor the temperature in the home and automate the adjustment of the heating / cooling system based on the homeowner's response history to various conditions. Figure 55 also shows the application of System 5300 to various modes of transport 5390. For example, System 5300 may be used in control systems and / or entertainment systems for aircraft, trains, buses, rental cars, private cars, ships ranging from privately owned boats to cruise ships, and scooters (rented or owned). In various cases, System 5300 can be used to provide automatic guidance (e.g., autonomous vehicles), general system control, and other methods. Many other embodiments of these are possible and contemplated. Note that the devices and applications illustrated in Figure 55 are illustrative and not intended to be limiting. Other devices are possible and contemplated. ***

[0203] This disclosure includes references to “one embodiment” or a group of “embodiments” (e.g., “several embodiments” or “various embodiments”). Embodiments are different implementations or examples of the disclosed concept. References to “one embodiment,” “one embodiment,” “a particular embodiment,” etc., do not necessarily refer to the same embodiment. Numerous possible embodiments, including those specifically disclosed, and modifications or substitutions within the spirit or scope of this disclosure are intended.

[0204] This disclosure may discuss the potential benefits that may arise from the disclosed embodiments. Not all implementations of these embodiments necessarily demonstrate any or all of the potential benefits. Whether a benefit is realized for a particular implementation depends on many factors, some of which are outside the scope of this disclosure. In fact, there are many reasons why an implementation within the claims may not exhibit some or all of any disclosed benefits. For example, a particular implementation may include other circuits outside the scope of this disclosure that, together with one of the disclosed embodiments, negate or reduce one or more of the disclosed benefits. Furthermore, suboptimal design execution of a particular implementation (e.g., implementation technique or tool) may also negate or reduce the disclosed benefits. Even assuming skilled execution, the realization of benefits may still depend on other factors, such as the environmental conditions in which the implementation is deployed. For example, the inputs supplied to a particular implementation may prevent one or more of the problems addressed in this disclosure from occurring on certain occasions, and as a result, the benefits of the solution may not be realized. Given the existence of possible external factors of this disclosure, it is expressly intended that any potential benefits described herein should not be construed as limitations on claims that must be satisfied to demonstrate infringement. Rather, the identification of such potential benefits is intended to illustrate the type(s) of improvements available to designers who have an interest in this disclosure. The acceptable description of such benefits (e.g., the statement that a particular benefit "may occur") is not intended to convey any doubt as to whether such benefits can actually be realized, but rather to acknowledge the technical reality that the realization of such benefits often depends on additional factors.

[0205] Unless otherwise specified, the embodiments are non-limiting. That is, even if only a single embodiment describes a particular feature, the disclosed embodiments are not intended to limit the scope of claims made based on this disclosure. The disclosed embodiments are intended to be illustrative, not limiting, unless there is a statement to the contrary in this disclosure. The foregoing is intended to enable claims that cover not only the disclosed embodiments but also alternatives, modifications, and equivalents that would be obvious to a person skilled in the art who would benefit from this disclosure.

[0206] For example, the features of this application can be combined in any preferred manner. Therefore, new claims can be formulated for any such combination of features during the examination of this application (or an application claiming priority to this application). In particular, referring to the attached claims, features from dependent claims can be combined with features from other dependent claims, including claims dependent on other independent claims, as appropriate. Similarly, features from each independent claim can be combined as appropriate.

[0207] Accordingly, each of the attached dependent claims may be constructed to depend on a single other claim, but additional dependencies are also contemplated. Any combination of features in the dependent claims that are consistent with the present disclosure is contemplated and may be claimed in this application or another application. In summary, the combinations are not limited to those specifically enumerated in the attached claims.

[0208] Where appropriate, claims prepared in one format or legal type (e.g., apparatus) are intended to also support corresponding claims in another format or legal type (e.g., method). ***

[0209] As this disclosure is a legal document, various terms and phrases may be subject to administrative and judicial interpretation. The following paragraphs, and the definitions provided through this disclosure, are hereby publicly noted as being used in interpreting the claims made pursuant to this disclosure.

[0210] References to singular items (i.e., nouns or noun phrases preceded by "a," "an," or "the") are intended to mean "one or more" unless explicitly stated in the context. Therefore, references to "items" in the claims do not, without context, preclude additional instances of an item. "Multiple" items refer to a set of two or more items.

[0211] In this specification, the word "may" is used in an allowable sense (i.e., possible, feasible) and not in an obligatory sense (i.e., not required).

[0212] The terms and forms "comprising" and "including" are open-ended and mean "to include, but not to limit."

[0213] When the term “or” is used in this disclosure in relation to a list of options, it will generally be understood to be used in an inclusive sense unless otherwise explicitly stated in the context. Thus, the enumeration of “x or y” is equivalent to “x or y, or both,” and therefore includes 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, the phrase “either x or y, but not both” clarifies that “or” is used in an exclusive sense.

[0214] The enumerations "w, x, y, z, or any combination thereof" or "...at least one of w, x, y, and z" are intended to cover all possibilities, including single elements, up to the total number of elements in the set. For example, in the set [w, x, y, z], these expressions cover any single element in the set (e.g., w, but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. Thus, the phrase "...at least one of w, x, y, and z" refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in this list of elements. This phrase should not be interpreted as requiring the existence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0215] In this disclosure, various “labels” may precede nouns or noun phrases. Unless otherwise explicitly stated in the context, the various labels used for features (e.g., “first circuit,” “second circuit,” “specific circuit,” “given circuit,” etc.) refer to different examples of the feature. Furthermore, when applied to features, the labels “first,” “second,” and “third” do not imply any type of order (e.g., spatial, temporal, logical, etc.) unless otherwise specified.

[0216] The phrase "based on" is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the decision; that is, the decision may be based on the specified factor alone, or on the specified factor plus other unspecified factors. Consider the phrase "determine A based on B." This phrase identifies B as a factor used to determine A or that influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover even one embodiment in which A is determined based solely on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0217] The phrases “in response to” and “in response to” describe one or more factors that trigger an effect. This phrase does not preclude the possibility that additional factors may influence, or otherwise trigger, the effect, either in conjunction with or independently of a specific factor. That is, the effect may depend on these factors alone, or on the specified factor and other unspecified factors. Consider the phrase “perform A in response to B.” This phrase indicates that B is a factor that triggers the performance of A, or a specific outcome with respect to A. This phrase does not preclude the performance of A from also being in response to other factors, such as C. This phrase also does not preclude the performance of A from being in response to both B and C. This phrase is intended to include embodiments in which A is performed solely in response to B. As used herein, the phrase “in response to” is synonymous with the phrase “in response to at least partially.” Similarly, the phrase “in response to” is synonymous with the phrase “in at least partially.” ***

[0218] Within this disclosure, various entities (which may be referred to as "units," "circuits," or other components, etc.) may be described or claimed to be “configured” to perform one or more tasks or operations. The expression “configured to perform one or more tasks” is used herein to refer to structures (i.e., physical things). More specifically, the expression is used to indicate that the structure is arranged to perform one or more tasks while in operation. A structure may be said to be “configured” to perform some task even when it is not currently in operation. Thus, entities described or explained as “configured” to perform some task refer to physical things such as devices, circuits, systems having a processor unit and memory storing program instructions executable to perform the task. This phrase is not used herein to refer to intangible things.

[0219] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. Even if not specifically stated, it is understood that those entities are "configured" to perform those tasks / operations.

[0220] The term "configured to" is not intended to mean "configurable to." For example, an unprogrammed FPGA is not considered "configured" to perform a particular function. However, this unprogrammed FPGA may be "configurable" to perform that function. After proper programming, the FPGA can then be said to be "configured" to perform a particular function.

[0221] For the purposes of a U.S. patent application based on this disclosure, to state in the claims that the structure is “configured” to perform one or more tasks is not intended to expressly invoke Section 112(f) of the U.S. Patent Act with respect to that claim. not present If the applicant wishes to invoke Section 112(f) of the U.S. Patent Application under this Disclosure during the examination process, it would use “means for” to perform the function to describe the elements of the claim.

[0222] This disclosure may describe various “circuits.” These circuits or “circuit configurations” constitute hardware that includes various types of circuit elements, such as combinational logic, clock memory devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), and programmable logic arrays. Circuits may be custom designed or obtained from standard libraries. In various implementations, circuit configurations may include digital components, analog components, or a combination of both, as needed. Certain types of circuits may generally be referred to as “units” (e.g., decoding units, arithmetic logic units (ALUs), function units, memory management units (MMUs), etc.). Such units also refer to circuits or circuit configurations.

[0223] The disclosed circuits / units / components and other elements shown in the drawings and described herein include hardware elements such as those described in the preceding paragraphs. Often, the internal arrangement of hardware elements within a particular circuit can be specified by describing the function of that circuit. For example, a particular “decoder unit” may be described as performing the function of “processing the opcode of an instruction and routing the instruction to one or more of several functional units,” meaning that the decoder unit is “configured” to perform this function. The detail of this function is sufficient to imply to a person skilled in the art of computer technology a set of possible structures of the circuit.

[0224] In various embodiments, as described in the previous paragraph, circuits, units, and other elements defined by the functions or operations they are configured to implement. The arrangement of such circuits / units / components relative to each other, and the way they interact, form the microarchitecture definition of the hardware that is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation form of the microarchitecture definition. Thus, a microarchitecture definition is recognized by those skilled in the art as a structure from which many physical implementation forms can be derived, and all of its implementation forms belong to the broader structure described by the microarchitecture definition. That is, a person skilled in the art presented with the microarchitecture definition provided pursuant to this disclosure can implement the structure by coding the circuit / unit / component description in a hardware description language (HDL), such as Verilog or VHDL, using ordinary art without excessive experimentation. The HDL description is often expressed in a form that appears to be functional. However, to those skilled in the art, this HDL description is a method used to translate the structure of a circuit, unit, or component into the next level of implementation detail. Such HDL descriptions can take the form of operation-level code (typically not synthesizable), register transfer language (RTL) code (typically synthesizable, in contrast to operation-level code), or structure code (e.g., a netlist specifying logic gates and their connections). The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technique, modified for timing, power, and other reasons, resulting in a final design database that can be sent to a foundry, generating a mask, and ultimately manufacturing the integrated circuit. Some hardware circuits, or parts thereof, can also be custom-designed in a schematic editor and incorporated into the integrated circuit design along with the synthesized circuits.An integrated circuit may further include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, and inductors), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits connected integrally to realize a hardware circuit, and / or, in some embodiments, separate elements may be used. Alternatively, the HDL design may be integrated into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented on an FPGA. This decoupling between the design of this group of circuits and the subsequent low-level implementation of these circuits generally leads to scenarios where the circuit or logic designer does not specify any particular set of structures for low-level implementation forms other than a description of how the circuit is configured, because this process is performed at different stages of the circuit implementation process.

[0225] The fact that the same specifications of a circuit can be implemented using many different low-level combinations of circuit elements results in a multitude of equivalent structures for that circuit. As mentioned above, these low-level circuit implementation forms can vary depending on changes in manufacturing technology, the foundry chosen to manufacture the integrated circuit, the library of cells provided for a particular project, and so on. Often, the choice made by different design tools or methods to generate these different implementation forms can be arbitrary.

[0226] Furthermore, in a given embodiment, a single implementation of a specific functional specification of a circuit typically involves a large number of devices (e.g., millions of transistors). Therefore, given this sheer volume of information, it is impractical to fully enumerate the low-level structures used to implement a single embodiment, let alone a vast number of equivalent possible implementations. For this reason, this disclosure describes the circuit structure using functional omissions commonly used in the industry.

Claims

1. A first transistor region of an integrated circuit cell structure, comprising a first active region and a second active region parallel to the first active region, having a first distance separating the first active region and the second active region, The second transistor region of the integrated circuit cell structure comprises a third active region and a fourth active region parallel to the third active region, having a second distance separating the third active region and the fourth active region, wherein at least a portion of the second transistor region is located below the first transistor region and perpendicular to the integrated circuit cell structure, and the second transistor region is complementary to the first transistor region. The first inverter, A first transistor having a first gate formed within the first active region, the first gate having a first source / drain region and a second source / drain region on both sides of the first gate, A first inverter includes a second transistor having a second gate formed within the third active region, the second gate having a third source / drain region and a fourth source / drain region on both sides of the second gate, the fourth source / drain region being merged with the second source / drain region, and the portion of the second gate extending below the first transistor region. The second inverter, A third transistor having a third gate formed within the second active region, wherein the third gate has a fifth source / drain region and a sixth source / drain region on both sides of the third gate, A second inverter includes a fourth transistor having a fourth gate formed within the fourth active region, wherein the fourth gate has a seventh source / drain region and an eighth source / drain region on either side of the fourth gate, the seventh source / drain region being merged with the fifth source / drain region, and the portion of the fourth gate extending below the first transistor region. The first inverter is cross-coupled to the second inverter by a first coupling between the portion of the second gate extending below the second active region and the seventh source / drain region, and a second coupling between the portion of the fourth gate extending below the first active region and the fourth source / drain region, wherein the first coupling and the second coupling are arranged vertically below the second transistor region. Memory device.

2. The memory device according to claim 1, further comprising a first pass gate coupled to a word line, formed within the second active region, having a fifth source / drain region and a ninth source / drain region on both sides of the first pass gate, the ninth source / drain region being coupled to a first bit line.

3. The memory device according to claim 2, wherein the portion of the second gate extending below the first transistor region is located below the first pass gate.

4. The memory device according to claim 2, further comprising: a second pass gate coupled to the word line, formed within the first active region, having a second source / drain region and a tenth source / drain region on both sides of the second pass gate, the tenth source / drain region being coupled to a second bit line, and the second bit line being complementary to the first bit line.

5. The memory device according to claim 4, wherein the portion of the fourth gate extending below the first transistor region is located below the second pass gate.

6. The memory device according to claim 1, further comprising a vertically positioned metal layer below the second transistor region, the metal layer including power routing connected to the first inverter and the second inverter.

7. A first back-side via connects the power routing within the metal layer to the third source / drain region, A second back via connects the power routing within the metal layer to the eighth source / drain region, The memory device according to claim 6, further comprising the above.

8. The memory device according to claim 1, further comprising a vertically positioned metal layer above the first transistor region, the metal layer including signal routing connected to the first inverter and the second inverter.

9. The memory device according to claim 1, wherein the first inverter is cross-coupled to the second inverter such that the output of the first inverter is provided as an input to the second inverter, and the output of the second inverter is provided as an input to the first inverter.

10. The memory device according to claim 1, wherein the third active region is located below the first active region, and the fourth active region is located below the second active region.

11. The memory device according to claim 1, wherein the first distance is substantially the same as the second distance.

12. The memory device according to claim 1, wherein the portion of the second gate extending below the first transistor region extends to the inactive portion of the fourth active region.

13. The memory device according to claim 1, wherein the portion of the fourth gate extending below the first transistor region extends to the inactive portion of the third active region.

14. The memory device according to claim 13, wherein the inactive portion of the third active region does not have a diffusion material.

15. A first gate merge via that connects the first gate and the second gate, A second gate merge via that connects the third gate and the fourth gate, The memory device according to claim 1, further comprising the following:

16. A first transistor region of an integrated circuit cell structure, comprising a first active region and a second active region parallel to the first active region, having a first distance separating the first active region and the second active region, The second transistor region of the integrated circuit cell structure comprises a third active region and a fourth active region parallel to the third active region, having a second distance separating the third active region and the fourth active region, wherein at least a portion of the second transistor region is located below the first transistor region and perpendicular to the integrated circuit cell structure, and the second transistor region is complementary to the first transistor region. A first pass gate formed within the second active region, wherein the first pass gate is coupled to a word line, and the source / drain region of the first pass gate is coupled to a first bit line, A second pass gate formed within the first active region, wherein the second pass gate is coupled to the word line, and the source / drain region of the second pass gate is coupled to a second bit line that is complementary to the first bit line, A first inverter formed by a first transistor in the first active region and a second transistor in the third active region, wherein the inputs of the first transistor and the second transistor are merged, the outputs of the first transistor and the second transistor are merged, and the portion of the second transistor extends vertically below the first pass gate, A second inverter formed by a third transistor in the second active region and a fourth transistor in the fourth active region, wherein the inputs of the third transistor and the fourth transistor are merged, the outputs of the third transistor and the fourth transistor are merged, and the portion of the fourth transistor extends vertically below the second pass gate, A first coupling between the portion of the second transistor extending below the first pass gate and the source / drain region of the fourth transistor, wherein the first coupling is positioned vertically below the region of the second transistor, A second coupling between the portion of the fourth transistor extending below the second pass gate and the source / drain region of the second transistor, the second coupling being positioned vertically below the second transistor region, A memory device equipped with the following features.

17. The memory device according to claim 16, wherein the first inverter is cross-coupled to the second inverter by the first coupling and the second coupling.

18. The memory device according to claim 16, further comprising a vertically positioned metal layer below the second transistor region, the metal layer including power routing connected to the first inverter and the second inverter.

19. The memory device according to claim 18, wherein the first coupling and the second coupling are arranged vertically between the metal layer and the second transistor region.

20. The memory device according to claim 16, wherein the outputs of the third transistor and the fourth transistor are provided as inputs to the first transistor and the second transistor, and the outputs of the first transistor and the second transistor are provided as inputs to the third transistor and the fourth transistor.

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