Gate voltage determination device, gate voltage determination method, gate drive circuit, and semiconductor circuit

Abstract

To appropriately set an off-gate voltage of a MOS transistor.SOLUTION: Provided is a gate voltage determination apparatus of a MOS transistor having a gate electrode, a gate insulating film, and a channel region. The gate voltage determination apparatus comprises: a characteristic acquisition unit configured to acquire current-voltage characteristics showing a relationship between a gate current flowing through the gate electrodes and a gate voltage when the gate voltage applied to the gate electrode is changed from a higher voltage side to a lower voltage side; and a voltage determination unit configured to determine, based on a value of the gate voltage at which the gate current shows a peak waveform in the current-voltage characteristics, an off-gate voltage to be applied to the gate electrode when turning off the MOS transistor.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a gate voltage determination device, a gate voltage determination method, a gate drive circuit, and a semiconductor circuit. [Background technology]

[0002] Conventionally, a technique is known in which a negative voltage is applied to the gate electrode when turning off a MOS transistor (see, for example, Patent Document 1). Patent Document 1: Japanese Unexamined Patent Publication No. 2019-161079 [Overview of the project] [Problems that the invention aims to solve]

[0003] Applying a negative voltage to the gate electrode can suppress the MOS transistor from accidentally turning on even when noise is superimposed on the gate voltage. On the other hand, applying a large negative voltage to the gate electrode can trap holes in the traps at the interface between the gate insulating film and the semiconductor substrate, causing the threshold voltage of the MOS transistor to fluctuate. For this reason, it is preferable to appropriately set the off-gate voltage when turning off the MOS transistor. In reality, the optimal value of this off-gate voltage varies depending on the gate electrode material, the concentration in the channel region, the trap density of the oxide film and interface, and the value of the fixed charge, so it is preferable to determine the optimal off-gate voltage according to each design. [Means for solving the problem]

[0004] To solve the above problems, one embodiment of the present invention provides a gate voltage determination device for a MOS transistor having a gate electrode, a gate insulating film, and a channel region. The gate voltage determination device may include a characteristic acquisition unit that acquires a current-voltage characteristic showing the relationship between the gate current flowing through the gate electrode and the gate voltage when the gate voltage applied to the gate electrode is changed from a high voltage side to a low voltage side. The gate voltage determination device may also include a voltage determination unit that determines the off-gate voltage to be applied to the gate electrode when the MOS transistor is turned off, based on the value of the gate voltage at which the gate current shows a peak waveform in the current-voltage characteristic.

[0005] The voltage determination unit may determine the off-gate voltage based on the hole injection start voltage, which is the higher voltage of the gate voltages at both ends of the peak waveform.

[0006] The voltage determination unit may determine the off-gate voltage to be lower than the hole injection start voltage.

[0007] The voltage determination unit determines the effective hole injection start voltage V, which is defined by the following formula. E The off-gate voltage may be set to a higher voltage than that. V E =V S -(V SiC +V SiO2 ) However, V S V is the hole injection initiation voltage, SiC V is the voltage applied to the depletion layer in the channel region when a hole injection initiation voltage is applied to the gate electrode. SiO2 This is the magnitude of the voltage applied to the gate insulating film when the hole injection initiation voltage is applied to the gate electrode.

[0008] The voltage determination unit may set the off-gate voltage to a voltage higher than the effective hole injection start voltage. The effective hole injection start voltage may be a voltage at which the integral by parts obtained by partially integrating the gate current of the peak waveform from the hole injection start voltage to the effective hole injection start voltage is 1 / 4 of the total integral value obtained by integrating the gate current over the entire peak waveform.

[0009] The characteristic acquisition unit may acquire hysteresis characteristics that include the relationship between drain current and gate voltage when the gate voltage is changed from the high voltage side to the low voltage side, and the relationship between drain current and gate voltage when the gate voltage is changed from the low voltage side to the high voltage side, within the gate voltage range of each peak waveform. The voltage determination unit may, when the current-voltage characteristics include multiple peak waveforms, select one of the peak waveforms based on the hysteresis characteristics and determine the off-gate voltage based on the gate voltage value of the selected peak waveform.

[0010] The characteristic acquisition unit may acquire the light emission characteristics of the MOS transistor when the gate voltage applied to the gate electrode is changed from a high voltage to a low voltage. The voltage determination unit may, when the current-voltage characteristics include multiple peak waveforms, select one of the peak waveforms based on the light emission characteristics and determine the off-gate voltage based on the gate voltage value of the selected peak waveform.

[0011] The voltage determination unit may, when the current-voltage characteristic includes multiple peak waveforms, select the peak waveform with the largest amplitude and determine the off-gate voltage based on the gate voltage value of the selected peak waveform.

[0012] The voltage determination unit may, when the current-voltage characteristic includes multiple peak waveforms, select the lowest-voltage peak waveform and determine the off-gate voltage based on the gate voltage value of the selected peak waveform.

[0013] A second embodiment of the present invention provides a method for determining the gate voltage of a MOS transistor having a gate electrode, a gate insulating film, and a channel region. In the gate voltage determination method, a current-voltage characteristic showing the relationship between the gate current flowing through the gate electrode and the gate voltage may be obtained when the gate voltage applied to the gate electrode is changed from a high voltage side to a low voltage side. In the gate voltage determination method, the off-gate voltage to be applied to the gate electrode when turning off the MOS transistor may be determined based on the value of the gate voltage at which the gate current shows a peak waveform in the current-voltage characteristic.

[0014] A third embodiment of the present invention provides a gate drive circuit for applying a gate voltage to a MOS transistor having a gate electrode, a gate insulating film, and a channel region. The gate drive circuit may set the off-gate voltage for turning off the MOS transistor to a voltage lower than the hole injection start voltage on the high-voltage side of the gate voltages across the peak waveform of the gate current in the current-voltage characteristic showing the relationship between the gate current flowing through the gate electrode and the gate voltage when the gate voltage applied to the gate electrode is changed from the high-voltage side to the low-voltage side.

[0015] A fourth embodiment of the present invention provides a semiconductor circuit comprising a MOS transistor and a gate drive circuit according to a third embodiment for applying a gate voltage to the MOS transistor.

[0016] It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0017] [Figure 1] This is a block diagram showing an example of a gate voltage determination device 100 according to one embodiment of the present invention. [Figure 2] This is a cross-sectional view showing an overview of MOS transistor 200. [Figure 3] This figure shows an example of the current-voltage characteristics acquired by the characteristic acquisition unit 104. [Figure 4] This figure shows an example of a gate voltage waveform when measuring current-voltage characteristics. [Figure 5] This diagram illustrates the hole injection initiation voltage VS. [Figure 6] This figure shows an example of the gate voltage applied to the MOS transistor 200. [Figure 7] This diagram illustrates another method for determining the effective hole injection initiation voltage VE. [Figure 8] This diagram illustrates the variation in the threshold voltage Vth. [Figure 9]This diagram illustrates which peak waveform 154 is used to determine the hole injection start voltage when the current-voltage characteristic (first characteristic 152) includes multiple peak waveforms 154. [Figure 10] This flowchart outlines the method for determining the gate voltage of MOS transistor 200. [Figure 11] This is a block diagram illustrating the overview of a semiconductor circuit 300 according to one embodiment of the present invention. [Modes for carrying out the invention]

[0018] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0019] The units used in this specification are the SI units unless otherwise specified. In this specification, terms such as "identical" or "equal" may include cases with errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0020] Figure 1 is a block diagram showing an example of a gate voltage determination device 100 according to one embodiment of the present invention. The gate voltage determination device 100 determines the voltage value to be applied to the gate electrode when the MOS transistor 200 is turned off (referred to as the off-gate voltage in this specification).

[0021] The MOS transistor 200 has a gate electrode, a gate insulating film, and a channel region. The MOS transistor 200 is, as an example, a SiC-MOSFET formed on a silicon carbide (SiC) substrate. The MOS transistor 200 may also be a MOSFET formed on a semiconductor substrate of another composition. The MOS transistor 200 may also be formed on a compound semiconductor substrate such as gallium nitride (GaN).

[0022] The gate voltage determination device 100 includes a characteristic measurement unit 102 and an information processing device 110. The characteristic measurement unit 102 measures the characteristics of a MOS transistor 200. The MOS transistor 200 measured by the characteristic measurement unit 102 may be the same individual MOS transistor for which the off-gate voltage is to be set, or it may be another individual having a similar structure. The characteristic measurement unit 102 may measure the average value of the characteristics of multiple MOS transistors 200 having similar structures.

[0023] The characteristic measurement unit 102 has means for measuring the characteristics of the MOS transistor 200. For example, the characteristic measurement unit 102 has means for applying a gate voltage to the MOS transistor 200, means for measuring the drain current and gate current of the MOS transistor 200, etc. The characteristic measurement unit 102 may also have means for measuring the light emission in the MOS transistor 200. In this example, the characteristic measurement unit 102 measures the current-voltage characteristics, which show the relationship between the gate current flowing through the gate electrode and the gate voltage, when the gate voltage applied to the gate electrode of the MOS transistor 200 is changed from a high voltage side to a low voltage side. Details of the current-voltage characteristics will be described later.

[0024] The information processing device 110 processes the measurement results from the characteristic measurement unit 102. In this example, the gate voltage determination device 100 is equipped with a characteristic measurement unit 102, but the gate voltage determination device 100 may receive measurement results from an external characteristic measurement unit 102. In this case, the gate voltage determination device 100 does not need to be equipped with a characteristic measurement unit 102.

[0025] The information processing device 110 includes a characteristic acquisition unit 104 and a voltage determination unit 106. The characteristic acquisition unit 104 acquires the characteristics of the MOS transistor 200 measured by the characteristic measurement unit 102. The voltage determination unit 106 determines the off-gate voltage of the MOS transistor 200 based on the characteristics of the MOS transistor 200 acquired by the characteristic acquisition unit 104. The method for determining the off-gate voltage will be described later.

[0026] FIG. 2 is a cross-sectional view showing an overview of the MOS transistor 200. The MOS transistor 200 has a semiconductor substrate 202, an interlayer insulating film 208, a source electrode 204, and a drain electrode 206. When the MOS transistor 200 is in the on state, a drain current flows between the source electrode 204 and the drain electrode 206 through the semiconductor substrate 202.

[0027] In this example, the source electrode 204 is provided on the upper surface of the semiconductor substrate 202 via a barrier metal 215, and the drain electrode 206 is provided on the lower surface of the semiconductor substrate 202. The MOS transistor 200 in this example is a vertical device in which a drain current flows between the upper and lower surfaces of the semiconductor substrate 202. In other examples, both the source electrode 204 and the drain electrode 206 may be provided on the upper surface of the semiconductor substrate 202. In this case, the MOS transistor 200 becomes a horizontal device in which a current flows in a direction along the upper surface of the semiconductor substrate 202. The barrier metal 215 is provided to prevent the diffusion of metal atoms from the source electrode 204 toward the gate electrode 212 side.

[0028] The semiconductor substrate 202 is, for example, a SiC substrate. The semiconductor substrate 202 has an N - -type drift region 220 through which a drain current flows. An N ++ -type source region 216 is formed on the upper surface of the semiconductor substrate 202. Also, a P-type channel region 218 and an N-type high-concentration region 209 are formed between the source region 216 and the drift region 220.

[0029] Furthermore, the semiconductor substrate 202 is provided with a gate trench portion 210 that penetrates the source region 216 and the channel region 218 and extends from the top surface to the N-type high-density region 209. The gate trench portion 210 has a gate electrode 212 and a gate insulating film 214. The gate electrode 212 is formed of a conductive material such as polysilicon with impurities added. The gate electrode 212 is insulated from the source electrode 204 by an interlayer insulating film 208. The gate insulating film 214 insulates the gate electrode 212 from the semiconductor substrate 202. The gate insulating film 214 is, for example, a silicon oxide film. The gate insulating film 214 is located at least between the gate electrode 212 and the channel region 218. The interface between the gate insulating film 214 and the channel region 218 is defined as interface 219. On the upper side inside the N-type high-density region 209, there is an upper P + A type subregion 201a is locally provided. Upper P + The mold portion region 201a is provided, for example, between the gate trench portions 210. Also, within the N-type high-concentration region 209, the bottom portion 207 and the upper portion P of the gate trench portion 210 are located. + Lower part P in contact with the bottom of the type subregion 201a + A mold portion region 201b is provided. The lower part P is in contact with the bottom 207 of the gate trench portion 210. + The mold portion region 201b is located opposite the bottom portion 207 in the depth direction. Upper portion P + Type subregion 201a and lower P + The type subregion 201b is combined with P + This becomes the mold portion region 201. Also, within the drift region 220, the lower part P between the gate trench portion 210. + An N-type sub-region 203 with a higher impurity concentration than the drift region 220 may be provided at a position deeper than the type sub-region 201b. Within the upper surface of the channel region 218, P ++ A type contact region 205 is selectively provided. In this example, the MOS transistor 200 is a trench-type device in which the gate electrode 212 and gate insulating film 214 are embedded inside the semiconductor substrate 202, but it may also be a planar-type device in which the gate electrode 212 and gate insulating film 214 are stacked on the upper surface of the semiconductor substrate 202.

[0030] A gate voltage is applied to the gate electrode 212. When an on-gate voltage is applied to the gate electrode 212, an N-type inverted channel is formed in the channel region 218 near the interface 219, and carriers flow between the source region 216 and the drift region 220.

[0031] On the lower surface of the semiconductor substrate 202, N + A drain region 222 of type P+ is provided. When a channel is formed on the surface of the channel region 218, current flows between the source region 216 and the drain region 222. The MOS transistor 200 may also be an IGBT in which a P+ type collector region is provided instead of the drain region 222.

[0032] Figure 3 shows an example of the current-voltage characteristics acquired by the characteristic acquisition unit 104. The current-voltage characteristics are, for example, characteristics measured at room temperature (25°C), but are not limited to this. In Figure 3, the horizontal axis represents the gate voltage, and the vertical axis represents the gate current. The current-voltage characteristics include a first characteristic 152 that shows the relationship between the gate current flowing through the gate electrode and the gate voltage when the gate voltage applied to the gate electrode 212 is changed from the high-voltage side to the low-voltage side. The high-voltage side refers to the side with a larger voltage value, and the low-voltage side refers to the side with a smaller voltage value. Note that even if the absolute value of a negative voltage is large, it is considered to be smaller than that of a positive voltage. For positive voltages, the side with a larger absolute value is considered the high-voltage side, and for negative voltages, the side with a larger absolute value is considered the low-voltage side. In this example, the on-gate voltage of the MOS transistor 200 is set to a higher voltage than the off-gate voltage.

[0033] In the current-voltage characteristic diagram, unless otherwise specified, the right side of the horizontal axis represents the high-voltage side, and the left side represents the low-voltage side. The upper side of the vertical axis represents the high-current side, and the lower side represents the low-current side. The current-voltage characteristic may further include a second characteristic 162, which shows the relationship between the gate current flowing through the gate electrode and the gate voltage when the gate voltage applied to the gate electrode 212 is changed from the low-voltage side to the high-voltage side. The current-voltage characteristic in this example is a typical characteristic when the interface between the channel region 218 and the gate insulating film 214 is the a-plane or the m-plane, but is not limited to this.

[0034] The first characteristic 152 includes one or more peak waveforms 154. A peak waveform refers to a waveform in which the gate current fluctuates from an initial value (e.g., 0A) in response to a sweep of the gate voltage, and then converges back to that initial value. In this example, the first characteristic 152 includes peak waveforms 154-1 and 154-2. When the gate voltage is swept from the high voltage side to the low voltage side, electrons may be excited from shallow electron traps at the interface 219 between the channel region 218 and the gate insulating film 214, causing a gate current to flow. This may result in the observation of peak waveform 154-2. The amplitude of peak waveform 154-2 is usually relatively small.

[0035] Further sweeping the gate voltage to a lower voltage allows holes in channel region 218 to overcome the potential barrier created by the depletion layer, become trapped in the hole trap at interface 219, and recombine with electrons trapped at interface 219. This results in the observation of peak waveform 154-1. Peak waveform 154-1 may have a larger amplitude than peak waveform 154-2. The gate voltage at which holes begin to overcome the potential barrier and become trapped in the hole trap at interface 219, or begin to recombine with electrons in the electron trap at interface 219, is defined as the hole injection start voltage V. S Let's assume the gate voltage V across the peak waveform 154-1. H , V L Of these, the gate voltage V on the high-voltage side H The hole injection start voltage V SThis may be the case. The gate voltage at both ends of the peak waveform is the voltage at which the gate current begins to fluctuate from its initial value, or the voltage at which the gate current converges to its initial value. If the positions of both ends of the peak waveform are unclear, the current value is the peak value I of the peak waveform. P The points where the value is 1 / 10 of the peak value may be used as the endpoints of the peak waveform. Alternatively, the current value may be the peak value I P The points where the value is 1 / 100 may be considered the endpoints of the peak waveform.

[0036] Thus, if the gate voltage is set too low, many holes will be trapped in the hole trap at interface 219. When many holes are trapped at interface 219, the threshold voltage Vth when turning on the MOS transistor 200 will fluctuate.

[0037] The second characteristic 162 also includes one or more peak waveforms 164. In this example, the second characteristic 162 includes peak waveform 164-1 and peak waveform 164-2. When the gate voltage is swept from the low voltage side to the high voltage side, holes may be excited from the shallow hole trap at the interface 219, causing a gate current to flow. As a result, peak waveform 164-1 may be observed. The amplitude of peak waveform 164-1 is relatively small.

[0038] Furthermore, when the gate voltage is swept to a higher voltage, electrons in the inversion layer (channel) of channel region 218 recombine with holes in the hole trap at interface 219 and are also trapped in the electron trap at interface 219. As a result, peak waveform 164-2 is observed. Peak waveform 164-2 may have a larger amplitude than peak waveform 164-1.

[0039] The voltage determination unit 106 determines the off-gate voltage to be applied to the gate electrode 212 when turning off the MOS transistor 200, based on the first characteristic 152 included in the current-voltage characteristic. More specifically, the voltage determination unit 106 determines the value of the gate voltage that shows the peak waveform 154-1 (V in this example). H ~V LThe off-gate voltage is determined based on the value within the voltage range. Since the voltage at which a large number of holes are trapped at the interface 219 can be estimated from the gate voltage of the peak waveform 154-1, an off-gate voltage that suppresses fluctuations in the threshold voltage Vth can be determined. The voltage determination unit 106 determines the hole injection start voltage V S The off-gate voltage may be determined based on this.

[0040] Figure 4 shows an example of a gate voltage waveform when measuring current-voltage characteristics. In this example, the gate voltage is changed in a step-like manner and swept. The first characteristic 152 in Figure 3 is measured during period T1 in Figure 4, and the second characteristic 162 is measured during period T2.

[0041] By changing the gate voltage in steps, a transient gate current flows during each step time (i.e., the time during which a single gate voltage is maintained). The integral of the gate current flowing during each step time is defined as the gate current at that gate voltage. Since the gate current is the integral of the transient current, increasing the step voltage (i.e., the difference in gate voltage between steps) increases the gate current. However, if the step voltage is sufficiently small (e.g., 0.1V or less), the waveform of the current-voltage characteristic hardly changes. Also, increasing the step time increases the gate current. On the other hand, the absolute value of the gate current may change depending on the step time, but the shape of the waveform of the current-voltage characteristic and the hole injection start voltage V S The voltage remains almost constant. By sweeping the gate voltage as shown in Figure 4, the current-voltage characteristics (especially the voltage range of the peak waveform) shown in Figure 3 can be obtained with high accuracy. Note that the current-voltage characteristics shown in Figure 3 can be measured using Keysight Technologies' semiconductor device analyzer "Keysight B1500A," but the measuring device is not limited to this.

[0042] Figure 5 shows the hole injection start voltage V. S This is a diagram illustrating this. In Figure 5, we see the case where the gate voltage is relatively high and the case where the gate voltage is the hole injection start voltage V. SThe energy bands of the gate electrode 212, gate insulating film 214, and channel region 218 are shown in this case.

[0043] When the gate voltage is high, the potential barrier PB formed by the depletion layer becomes high. As a result, holes 254 in the channel region 218 cannot overcome the potential barrier PB and are not trapped in the hole trap 250 at the interface 219.

[0044] When the gate voltage is reduced, the depletion layer shrinks, and the potential barrier PB becomes smaller. As a result, the thermal energy causes holes 254 to overcome the potential barrier PB and begin to be trapped in the hole trap 250, causing gate current to flow. The gate voltage at this time is the hole injection start voltage V. S It corresponds to this.

[0045] When a hole 254 is trapped at interface 219, its charge increases the potential barrier and reduces the gate current. However, further reducing the gate voltage reduces the potential barrier again and allows the gate current to flow. When all hole traps 250 trap a hole 254, no gate current flows even if the gate voltage is further reduced. Therefore, by sweeping the gate voltage as shown in Figure 4, the current-voltage characteristics shown in Figure 3 can be obtained.

[0046] As the temperature rises, thermal energy increases, making it easier for holes 254 to overcome the potential barrier PB. However, as the temperature rises, the threshold voltage Vth decreases, so the hole injection initiation voltage does not change much. For example, even if the temperature changes from 25°C to 102°C, the hole injection initiation voltage changes by only about 0.8V. The voltage determination unit 106 may determine the hole injection initiation voltage based on the current-voltage characteristics at room temperature.

[0047] The voltage determination unit 106 may set the off-gate voltage lower than 0V. This reduces false on-on due to noise, etc. The voltage determination unit 106 may also set the off-gate voltage to the hole injection start voltage V SThe voltage may be set to an even lower voltage. This further suppresses false on-on due to noise, etc. The off-gate voltage is the hole injection start voltage V. S Even if it is lower, the off-gate voltage and the hole injection start voltage V S If the difference is not very large, the number of holes 254 trapped in the hole trap 250 will be small, and the effect on the threshold voltage Vth will be minimal. In this example, the voltage at which the amount of holes 254 trapped in the hole trap 250 becomes substantial enough to affect the threshold voltage Vth is defined as the effective hole injection start voltage V E It is called that.

[0048] The voltage determination unit 106 determines the effective hole injection start voltage V, which is determined by the following formula. E The off-gate voltage may be set to a higher voltage than that. V E =V S -(V SiC +V SiO2 )...Equation (1) However, V S V is the hole injection initiation voltage, SiC The voltage V is the voltage at which hole injection begins into the gate electrode 212. S The voltage applied to the depletion layer of channel region 218 when V is applied is the magnitude of the potential barrier PB in Figure 5, and V SiO2 The voltage V is the voltage at which hole injection begins into the gate electrode 212. S This is the voltage applied to the gate insulating film 214 when a charge is applied, or more precisely, the magnitude of the voltage when no charge is present in the oxide film or at the interface. Note that the effect of charge is included in Vs.

[0049] Hole injection start voltage V S This can be obtained from the current-voltage characteristics shown in Figure 3. V SiC As shown in the references below, the voltage can be set to 0.6V at room temperature. Reference "Slow response in gate current-voltage characteristics of metal-oxide-semiconductor structures on the 4H-SiC(0001 / ) face", Naoki Kumagai et al, 2016 Japanese Journal of Applied Physics 55, 054103)

[0050] The voltage determination unit 106 is V SiO2 This can be determined based on the following formula. V SiO2 =V SiC ·C SiC / C SiO2 ...Equation (2) However, C SiC The voltage V is the voltage at which hole injection begins into the gate electrode 212. S In a MOS transistor 200 to which the voltage is applied, the capacitance (C) of the depletion layer formed near the interface 219 is C. SiO2 This is the capacitance (C) of the gate insulating film 214.

[0051] If E is the electric field in channel region 218, then the following equation holds. dE / dx = ρ / ε SiC However, x is the position perpendicular to the interface 219, and ε SiC ρ is the permittivity of the channel region 218. Note that the permittivity (F / cm) is the value obtained by multiplying the permittivity of vacuum by the relative permittivity. Also, ρ = q·p, where q is the elementary charge (q = 1.602 × 10⁻¹⁸). -19 (C)) p is the doping concentration in channel region 218 ( / cm³). 3 ) Also, V SiC The equation is as follows: V SiC =ρw 2 / 2ε SiC =0.6V...Equation (3) However, w(cm) is the hole injection start voltage V into the gate electrode 212. S This is the width in the x-direction of the depletion layer formed near the interface 219 in a MOS transistor 200 to which the voltage is applied.

[0052] From equation (3), the width of the depletion layer w is given by the following equation. w=(1.2·ε SiC / ρ) 1 / 2 Using the depletion layer width w and the x-thickness d (cm) of the gate insulating film 214, the respective capacities are given by the following equations. C SiC =ε SiC / w=(ρ·ε SiC / 1.2) 1 / 2 C SiO2 =ε SiO2 / d However, ε SiO2 is the dielectric constant of the gate insulating film 214. Therefore, equation (2) can be transformed as shown below. V SiO2 =0.6·d·(ρ·ε SiC / 1.2) 1 / 2 / ε SiO2 The voltage determination unit 106 uses d, ρ, and ε. SiC , ε SiO2 Based on V SiO2 These values ​​may be calculated. These values ​​may be obtained from the datasheet of the MOS transistor 200, or they may be measured directly from the MOS transistor 200. The values ​​for each parameter described in Figure 5 may be those at room temperature (25°C).

[0053] The effective hole injection start voltage V shown in equation (1) E When the following gate voltages are applied, the potential barrier disappears, and the hole trapping rate becomes very fast, determined by the trapping cross-section of the trap, causing holes to be trapped rapidly. On the other hand, V E At the gate voltages above, a potential barrier is formed, so the hole trap rate is limited by the potential barrier and the trap rate slows down. Ecorresponds to the flat-band voltage, which can be calculated from the oxide film thickness, channel concentration, etc. in an ideal case. However, in reality, due to electron traps and fixed charges at the interface, the value is different from the ideal one, so it is determined based on the hole injection start voltage. Note that this flat-band voltage is a transient value before holes are trapped. Therefore, the flat-band voltage obtained from the CV characteristics is different because the flat band shifts negatively due to hole trapping. The voltage determination unit 106 in this example uses the effective hole injection start voltage V E as the off-gate voltage for a voltage greater than this.

[0054] FIG. 6 is a diagram showing an example of the gate voltage applied to the MOS transistor 200. When turning on the MOS transistor 200, the on-gate voltage applied is V on , and when turning it off, the off-gate voltage applied is V off . The voltage determination unit 106 sets the off-gate voltage V off to a voltage higher than the effective hole injection start voltage V E . This can suppress fluctuations in the threshold voltage Vth due to hole trapping. The voltage determination unit 106 may set the off-gate voltage V E to be 0.1 V or more higher than the effective hole injection start voltage V off , and may also set the off-gate voltage V off to be 0.2 V or more higher.

[0055] Also, the voltage determination unit 106 may set the off-gate voltage V off to be lower than 0 V. This can suppress false on due to noise, etc. The voltage determination unit 106 may set the off-gate voltage V S to be lower than the hole injection start voltage V off . The voltage determination unit 106 may set the off-gate voltage V off to be lower than -3 V.

[0056] FIG. 7 is a diagram explaining another method for determining the effective hole injection start voltage V E . In this example, the gate current of the peak waveform 154-1 is from the hole injection start voltage V S to the effective hole injection start voltage V EThe value obtained by partially integrating up to this point is taken as the integral by parts value (the integral value of the shaded area in Figure 7). Also, the entire peak waveform 154-1 (hole injection start voltage V) S From voltage V L The total integral value is the value obtained by integrating the gate current over (up to). The voltage determination unit 106 determines the effective hole injection start voltage V at which the partial integral value is 1 / 4 of the total integral value. E This can be used. Experiments have confirmed that even if holes equivalent to about 1 / 4 of the total integral value of peak waveform 154-1 are trapped, the threshold voltage Vth of MOS transistor 200 does not change much.

[0057] The voltage determination unit 106 determines the effective hole injection start voltage V according to the actual operating frequency of the MOS transistor 200. E This may be corrected. If the operating frequency is high and the off time per cycle is short, the amount of holes trapped will decrease even if a low off-gate voltage is set. The voltage determination unit 106 determines that the effective hole injection start voltage V increases as the operating frequency increases. E You may shift it to the lower voltage side.

[0058] Figure 8 illustrates the variation in the threshold voltage Vth. When the gate voltage is low, holes 254 are trapped in hole traps 250. Subsequently, when the gate voltage is increased to form an inversion layer in the channel region 218, electrons in the inversion layer recombine with holes trapped at the interface 219. This recombination energy (e.g., the light energy of the light emitted due to recombination) excites electrons in the inversion layer, which are then injected into the gate insulating film 214 by the electric field and trapped within the gate insulating film 214. The trapping of electrons within the gate insulating film 214 causes the threshold voltage Vth to shift to the high voltage side.

[0059] Figure 9 illustrates how to determine the hole injection start voltage when the current-voltage characteristic (first characteristic 152) includes multiple peak waveforms 154. In this example, the characteristic acquisition unit 104 determines the gate voltage range of each peak waveform 154 (for example, for peak waveform 154-1, V H ~V LHysteresis characteristics, including characteristics 171 and 172, are obtained in at least a portion of the specified range. Since the vertical axis of the characteristics in Figure 9 is on a logarithmic scale, a flat characteristic indicates the noise level (approximately 10 pA to 100 pA). If the noise level is high, this current level increases and the hysteresis appears smaller, but the presence or absence of hysteresis is sufficient for judgment.

[0060] Characteristic 171 shows the relationship between drain current and gate voltage when the gate voltage is changed from the low voltage side to the high voltage side. Characteristic 172 shows the relationship between drain current and gate voltage when the gate voltage is changed from the high voltage side to the low voltage side. The characteristic acquisition unit 104 in this example acquires characteristic 171, which is obtained by sweeping the gate voltage from the sweep start voltage Va to the aliasing voltage Vb which is greater than voltage Va, and characteristic 172, which is obtained by sweeping the gate voltage from voltage Vb to voltage Va. The sweep start voltage is, for example, the lower voltage voltage of the voltages across each peak waveform (for example, for peak waveform 154-1, V L )

[0061] The sweep start voltage Va is equal to the hole injection start voltage V S If it is greater than, characteristic 171 and characteristic 172 will have almost the same waveform. On the other hand, if the sweep start voltage Va is greater than the hole injection start voltage V S In the following case, holes are trapped at interface 219 for at least a portion of the time, resulting in different waveforms for characteristic 171 and characteristic 172.

[0062] The voltage determination unit 106 may, when the current-voltage characteristic (first characteristic 152) includes multiple peak waveforms 154, select one of the peak waveforms 154 based on the hysteresis characteristics (characteristics 171 and 172) of each peak waveform 154, and determine the off-gate voltage based on the value of the gate voltage (e.g., hole injection start voltage) of the selected peak waveform 154. The voltage determination unit 106 may select the peak waveform 154 with the largest difference between the gate voltage at which the drain current is at its initial value in characteristic 171 and the gate voltage at which the drain current is at its initial value in characteristic 172. This allows for the selection of an appropriate peak waveform 154 and setting the off-gate voltage when multiple peak waveforms 154 exist.

[0063] The characteristic acquisition unit 104 may acquire the emission characteristics showing the emission state of the MOS transistor 200 when the gate voltage applied to the gate electrode 212 is changed from the high voltage side to the low voltage side. The emission characteristics may be measured simultaneously with the current-voltage characteristics. As explained in Figure 5, etc., when the gate voltage becomes lower than the hole injection start voltage and holes overcome the potential barrier, holes are trapped at the interface, and then when an on-gate voltage is applied to the gate, electrons in the inversion layer recombine with the holes trapped at the interface 219 and emit light. On the other hand, in the trench-type MOS transistor 200, the lower part P of the trench bottom in Figure 2 + As in the mold subregion 201b, the gate insulating film 214 has a relatively high concentration of lower P + When the mold subregion 201b is in contact, the lower part P of the trench bottom + A peak waveform 154-2 may be observed in the subregion 201b due to the current when a hole is injected or excited. This peak is located at the bottom P + The higher the concentration of the type subregion 201b, the more it appears on the higher potential side. In this case, the voltage at which a normal inversion layer is formed is very high, and since no electrons are injected, no light emission occurs due to the recombination of holes and electrons.

[0064] The voltage determination unit 106 may, when the current-voltage characteristics include multiple peak waveforms 154, select one of the peak waveforms 154 based on the acquired light emission characteristics and determine the off-gate voltage based on the gate voltage value of the selected peak waveform 154. The voltage determination unit 106 may select the peak waveform 154 in which light emission is occurring. The voltage determination unit 106 may also select the peak waveform 154 with the highest light emission intensity. Alternatively, the hole injection start voltage may be determined directly based on the presence or absence of light emission.

[0065] The voltage determination unit 106 may select the lowest voltage peak waveform 154 when the current-voltage characteristic includes multiple peak waveforms 154. Alternatively, the voltage determination unit 106 may select the peak waveform 154 with the largest gate current amplitude when the current-voltage characteristic includes multiple peak waveforms 154. This allows for the selection of a peak waveform 154 with a simple process.

[0066] Figure 10 is a flowchart illustrating the overview of the gate voltage determination method for the MOS transistor 200. The gate voltage determination method includes a characteristic measurement stage S1002, a characteristic acquisition stage S1004, and a voltage determination stage S1006. The processing in the characteristic measurement stage S1002 is the same as the processing in the characteristic measurement unit 102 described in Figures 1 to 9. The processing in the characteristic acquisition stage S1004 is the same as the processing in the characteristic acquisition unit 104 described in Figures 1 to 9. The processing in the voltage determination stage S1006 is the same as the processing in the voltage determination unit 106 described in Figures 1 to 9.

[0067] Figure 11 is a block diagram illustrating the overview of a semiconductor circuit 300 according to one embodiment of the present invention. The semiconductor circuit 300 comprises a gate drive circuit 310 and a MOS transistor 200. The MOS transistor 200 is, for example, part of an inverter, but is not limited thereto.

[0068] The gate drive circuit 310 drives the MOS transistor 200 by applying a gate voltage to the gate electrode 212 of the MOS transistor 200. The gate drive circuit 310 turns off the MOS transistor 200 using the off-gate voltage determined by the gate voltage determination device 100 described in Figures 1 to 10. The gate drive circuit 310 uses the hole injection start voltage V S The off-gate voltage may be set to a lower voltage.

[0069] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0070] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of symbols]

[0071] 100...Gate voltage determination device, 102...Characteristic measurement unit, 104...Characteristic acquisition unit, 106...Voltage determination unit, 110...Information processing device, 152...First characteristic, 154...Peak waveform, 162...Second characteristic, 164...Peak waveform, 171, 172...Characteristics, 200...MOS transistor, 201...P + Type subregion, 202... Semiconductor substrate, 203... N-type subregion, 204... Source electrode, 205... P ++Type contact region, 206...Drain electrode, 207...Bottom, 208...Interlayer insulating film, 209...N-type high-concentration region, 210...Gate trench region, 212...Gate gate, 214...Gate insulating film, 215...Barrier metal, 216...Source region, 218...Channel region, 219...Interface, 220...Drift region, 222...Drain region, 250...Hole trap, 254...Hole, 300...Semiconductor circuit, 310...Gate drive circuit

Claims

1. An information processing device for determining the gate voltage of a MOS transistor having a gate electrode, a gate insulating film, and a channel region, A characteristic acquisition unit that acquires a current-voltage characteristic showing the relationship between the gate current flowing through the gate electrode and the gate voltage when the gate voltage applied to the gate electrode is changed from a high voltage side to a low voltage side, A voltage determination unit determines the value of the gate voltage at which the gate current exhibits a peak waveform in the current-voltage characteristics, and determines the off-gate voltage to be applied to the gate electrode when the MOS transistor is turned off, based on the determined value of the gate voltage. An information processing device equipped with the following features.

2. The voltage determination unit determines the off-gate voltage based on the hole injection start voltage, which is the higher voltage of the gate voltages at both ends of the peak waveform. The information processing apparatus according to claim 1.

3. The voltage determination unit determines the off-gate voltage to be lower than the hole injection start voltage. The information processing apparatus according to claim 2.

4. The voltage determination unit determines the effective hole injection start voltage V as defined by the following formula. Ｅ Set the off-gate voltage to a voltage higher than the above. V Ｅ =V Ｓ -(V ＳｉＣ +V ＳｉＯ２ ) However, V Ｓ V is the hole injection start voltage, ＳｉＣ V is the voltage applied to the depletion layer in the channel region when the hole injection initiation voltage is applied to the gate electrode, ＳｉＯ２ This is the magnitude of the voltage applied to the gate insulating film when the hole injection initiation voltage is applied to the gate electrode. The information processing apparatus according to claim 3.

5. The voltage determination unit sets the off-gate voltage to a voltage higher than the effective hole injection start voltage. The effective hole injection initiation voltage is the voltage at which the partial integral value obtained by partially integrating the gate current of the peak waveform from the hole injection initiation voltage to the effective hole injection initiation voltage is 1 / 4 of the total integral value obtained by integrating the gate current over the entire peak waveform. The information processing apparatus according to claim 3.

6. The characteristic acquisition unit acquires hysteresis characteristics, including the relationship between the drain current and the gate voltage when the gate voltage is changed from the high voltage side to the low voltage side, and the relationship between the drain current and the gate voltage when the gate voltage is changed from the low voltage side to the high voltage side, within the range of the gate voltage of each peak waveform. The voltage determination unit, when the current-voltage characteristic includes multiple peak waveforms, selects one of the peak waveforms based on the hysteresis characteristic and determines the off-gate voltage based on the gate voltage value of the selected peak waveform. The information processing apparatus according to any one of claims 1 to 5.

7. The characteristic acquisition unit further acquires the light emission characteristics indicating the light emission state of the MOS transistor when the gate voltage applied to the gate electrode is changed from a high voltage side to a low voltage side. The voltage determination unit, when the current-voltage characteristics include a plurality of peak waveforms, selects one of the peak waveforms based on the light emission characteristics and determines the off-gate voltage based on the gate voltage value of the selected peak waveform. The information processing apparatus according to any one of claims 1 to 5.

8. The voltage determination unit, when the current-voltage characteristic includes multiple peak waveforms, selects the peak waveform with the largest amplitude and determines the off-gate voltage based on the gate voltage value of the selected peak waveform. The information processing apparatus according to any one of claims 1 to 5.

9. The voltage determination unit, when the current-voltage characteristic includes multiple peak waveforms, selects the lowest-voltage peak waveform and determines the off-gate voltage based on the gate voltage value of the selected peak waveform. The information processing apparatus according to any one of claims 1 to 5.

10. A method for determining the gate voltage of a MOS transistor having a gate electrode, a gate insulating film, and a channel region, When the gate voltage applied to the gate electrode is changed from a high voltage to a low voltage, a current-voltage characteristic is obtained that shows the relationship between the gate current flowing through the gate electrode and the gate voltage. Based on the value of the gate voltage at which the gate current exhibits a peak waveform in the current-voltage characteristics, the off-gate voltage to be applied to the gate electrode when the MOS transistor is turned off is determined using an information processing device. Method for determining gate voltage.

11. Using the information processing device, the off-gate voltage is determined based on the hole injection start voltage, which is the higher voltage of the gate voltages at both ends of the peak waveform. The gate voltage determination method according to claim 10.

12. Using the information processing device, the off-gate voltage is determined to be lower than the hole injection start voltage. The gate voltage determination method according to claim 11.

13. Using the information processing device, the off-gate voltage is set to a voltage higher than the effective hole injection start voltage V E determined by the following formula. V E =V S -(V SiC +V SiO2) However, V S is the hole injection initiation voltage, V SiC is the voltage applied to the depletion layer in the channel region when the hole injection initiation voltage is applied to the gate electrode, and V SiO2 is the magnitude of the voltage applied to the gate insulating film when the hole injection initiation voltage is applied to the gate electrode. The gate voltage determination method according to claim 12.

14. Using the information processing device, set the off-gate voltage to a voltage higher than the effective hole injection start voltage, The effective hole injection initiation voltage is the voltage at which the partial integral value obtained by partially integrating the gate current of the peak waveform from the hole injection initiation voltage to the effective hole injection initiation voltage is 1 / 4 of the total integral value obtained by integrating the gate current over the entire peak waveform. The gate voltage determination method according to claim 12.

15. A method for manufacturing a gate drive circuit that applies a gate voltage to a MOS transistor having a gate electrode, a gate insulating film, and a channel region, When the gate voltage applied to the gate electrode is changed from a high voltage to a low voltage, a current-voltage characteristic is obtained that shows the relationship between the gate current flowing through the gate electrode and the gate voltage. Based on the value of the gate voltage at which the gate current exhibits a peak waveform in the current-voltage characteristics, the off-gate voltage to be applied to the gate electrode when the MOS transistor is turned off is determined using an information processing device. The off-gate voltage is set to the gate drive circuit. A method for manufacturing a gate drive circuit.

16. A MOS transistor having a gate electrode, a gate insulating film, and a channel region, A gate drive circuit that applies a gate voltage to the MOS transistor and A method for manufacturing a semiconductor circuit comprising: When the gate voltage applied to the gate electrode is changed from a high voltage to a low voltage, a current-voltage characteristic is obtained that shows the relationship between the gate current flowing through the gate electrode and the gate voltage. Based on the value of the gate voltage at which the gate current exhibits a peak waveform in the current-voltage characteristics, the off-gate voltage to be applied to the gate electrode when the MOS transistor is turned off is determined using an information processing device. The off-gate voltage is set to the gate drive circuit. A method for manufacturing semiconductor circuits.

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