Firmware update

Abstract

To update firmware of a device while allowing the device to continue operation without causing the device to shut down.SOLUTION: Examples described herein include a device that, when operating, executes reduced function firmware to maintain operation of the device during an update of firmware for the device, the reduced function firmware provides the device with less functionality than the updated firmware. In some examples, the reduced function firmware comprises verified reduced function firmware. In some examples, the reduced function firmware comprises an updated version of reduced function firmware that overwrites full firmware in a firmware storage.SELECTED DRAWING: Figure 2

Description

Background Art

[0001] Computing devices utilize firmware for hardware initialization, low-level hardware management, and management of the boot process. In addition to platform firmware, computing devices may also include dedicated firmware for controller chips, peripheral devices, or other components. Firmware is typically loaded in relation to booting at runtime, but may be updated in relation to a dedicated firmware update process.

[0002] Runtime firmware patches may be deployed to various central processing unit (CPU) firmware engines to fix bugs, introduce new capabilities, or revert to a previous firmware version. Some firmware patches require a system reset. However, rebooting the CPU can result in system downtime where the CPU cannot execute workloads, or lead to delays in workload completion. CPU downtime can increase the total cost of ownership (TCO) for the owner or operator of a data center, which may not be desirable.

Brief Description of the Drawings

[0003] [Figure 1] An exemplary system is shown.

[0004] [Figure 2] 3]]An exemplary system is shown.

[0005] [Figure 3A] ] An exemplary operation is shown. [Figure 3B] An exemplary operation is shown. <0000)028> [Figure 4A] An exemplary process is shown. [Figure 4B] An exemplary process is shown.

[0007] [Figure 5] An exemplary system is shown.

[0008] [Figure 6] An exemplary system is shown. [Modes for carrying out the invention]

[0009] Some examples provide a method that allows a device to continue operating without shutting down while its firmware is being updated. During a firmware update, two versions of the firmware can be updated: the first version can be a reduced-feature-set firmware, and the second version can be a full-feature-set firmware. The authenticity of the firmware update can be verified before execution. When a firmware update occurs for a device, the operating system (OS) can continue running by executing the first version of the firmware. However, some device functions may not be available until the second version of the firmware is executed. After the second version of the firmware is updated and verified, the device can run the second version. If a firmware update error or power outage occurs during the update of the first or second version of the firmware, the device can revert to a reduced image or a recovery image of the first version and continue operating. Therefore, by avoiding a reset during a firmware update, continuous OS execution and workload execution during the firmware update can be enabled. For example, the firmware includes Microsoft Windows® SPS (server platform services). In some examples, in the event of power loss during or after a firmware update, or an error during the firmware update, the device may have a version of the firmware running.

[0010] Figure 1 shows an exemplary system. The central processing unit (CPU) 102 may include cores 104-0 to 104-n. A core may be an execution core or a computing engine capable of executing instructions. A core may have access to its own cache and ROM (read-only memory), and multiple cores may share the cache or ROM. Cores may be homogeneous and / or heterogeneous devices. Any type of inter-processor communication technology may be used, but is not limited to messaging, IPI (inter-processor interrupts), or inter-processor communication. Cores may be connected in any type of scheme, such as a bus, ring, or mesh, but is not limited to this. The core may support one or more instruction sets, including the instructions described herein (for example, the x86 instruction set (with some extensions added in newer versions), the MIPS instruction set from MIPS Technologies, Sunnyvale, California, or the ARM (Advanced RISC Machines) instruction set from ARM Holdings, Sunnyvale, California (with optional additional extensions such as NEON). In addition to or as an alternative to the use of a CPU, an XPU or xPU may be used. An XPU may include one or more of the following: a graphics processing unit (GPU), a general-purpose GPU (GPGPU), a field-programmable gate array (FPGA), an APU (Accelerated Processing Unit), an accelerator, or another processor.

[0011] One or more of the cores 140-0 to 104-n can run an operating system (OS). In some examples, the OS could be Linux®, Windows® Server or Personal Computer, Android®, macOS®, iOS®, VMware vSphere, or any other operating system. The OS and drivers can run CPUs or processors sold or designed by, among others, Intel®, ARM®, AMD®, Qualcomm®, IBM®, Texas Instruments®, and others.

[0012] The CPU 102 can cause the boot controller 114 to access the firmware code 122 from the storage 120 and copy the firmware code into memory 106 (illustrated as firmware 110) for execution by one or more cores. The boot firmware code or firmware may have a header file that identifies a map of which boot code is copied by the CPU 102. For example, the .h file of the firmware code may have a flash image layout map of which segments of the firmware code are copied. When executed by the processor, the firmware code is executed by the processor to perform hardware initialization during the boot process (e.g., power-on or reboot) and can provide runtime services to the operating system and programs.

[0013] In some examples, the boot controller 114 can access firmware code 122 from storage 120 and copy the firmware code to a memory device for execution by one or more devices 118. In some examples, storage 120 can connect to the boot controller 114 using a fabric or network, and firmware updates can be transmitted using one or more packets via a fabric or network interface (not shown). One or more devices 118 may include one or more of the following: XPU, IPU (infrastructure processing unit), CPU, CPU socket, GPU (graphics processing unit), processor, accelerator device, BMC (Board Management Controller), storage controller, memory controller, display engine, peripheral device, Intel® Management or ME (Manageability Engine), AMD PSP (Platform Security Processor), ARM core with TrustZone extension, network interface device, PCH (Platform Controller Hub), application-specific integrated circuit (ASIC), etc.

[0014] For example, an ME may include one or more processors and enable the power-on, setup, control, or reset of a computer system via communications received using a network interface device. For example, an ME may provide temperature, voltage, current, and fan speed control and monitoring of fan speed sensors. For example, an ME may provide a secure audio and / or video communication path. For example, an ME may provide a secure boot process by requiring the firmware to be verified by its digital signature before booting. A PCH may include a chipset or circuit board that provides data paths and display interfaces, input / output controllers, a clock, and other circuitry.

[0015] In some cases, boot firmware code or firmware can include one or more of the following: BIOS (Basic Input / Output System), VBIOS (video BIOS), GPU BIOS, UEFI (Universal Extensible Firmware Interface), or boot loader. BIOS firmware can be pre-installed on the system board of a personal computer or accessed via an SPI interface from boot storage (e.g., flash memory). In some cases, firmware can include an SPS. In some cases, UEFI (Universal Extensible Firmware Interface) can be used instead of or in addition to BIOS for booting or restarting a core or processor. UEFI is a specification that defines a software interface between an operating system and platform firmware. UEFI can read entries from disk partitions by booting from a specific boot loader at a specific location on a particular disk or storage, as well as booting from disk or storage. UEFI can support remote diagnosis and repair of a computer even if no operating system is installed. A boot loader can be written for UEFI, the boot code firmware can be the executable instructions, and the boot loader boots the operating system. A UEFI bootloader can be a bootloader that can be read from UEFI-type firmware.

[0016] UEFI encapsulation is a method for encapsulating a binary image for firmware code updates. However, in some cases, UEFI encapsulation is used to update the runtime components of firmware code. UEFI encapsulation can contain an updatable binary image in a relocatable PE (Portable Executable) file format for executable or DLL (dynamic linked library) files based on COFF (Common Object File Format). For example, UEFI encapsulation can contain an executable file (*.exe). This UEFI encapsulation can then be deployed to the target platform as an SMM image via existing OS-specific techniques (such as Windows Update for Azure or Linux LVFS).

[0017] The trusted entity 150 may include a BIOS, BMC, or other hardware that can send commands to update firmware, verify firmware, and / or trigger specific reduction or full firmware executions. For example, the trusted entity 150 can send IPMI (Intelligent Platform Management Interface) consistent commands to the ME or other devices to update firmware, verify firmware, and / or trigger specific reduction or full firmware executions.

[0018] The boot controller 114 may be any type of controller (e.g., a microcontroller) or a processor capable of managing the loading and storage of firmware code into memory 106 or other memory. In some examples, the boot controller 114 may be implemented using CPU cores (e.g., any of 104-0 to 104-n) or threads of a multithreaded core. In some examples, the boot controller 114 may be coupled to the storage 120 using interface 130. Interface 130 can provide communication using one or more protocols from among SPI (serial peripheral interface), eSPI (enhanced SPI), SMBus (System Management Bus), I2C, MIPI I3C®, PCIe (Peripheral Component Interconnect Express), and CXL (Compute Express Link). See, for example, Peripheral Component Interconnection Express (PCIe) Base Specification 1.0 (2002), as well as earlier versions, later versions, and their variations. For example, see Compute Express Link (CXL) Specification revision 2.0, version 0.7 (2019), and previous versions, later versions, and their variations.

[0019] As described herein, device 118 can execute firmware code 122 from at least a first or second slot in storage 120. A bootable and verified copy of the firmware may be stored in at least one or the first or second slot in storage 120. The types of executable firmware may include a firmware version (a) for performing services essential to the operation of the server system and preventing access to the PCH SPI after boot, and a firmware version (b) (e.g., full firmware) for services and extension services essential to the operation and management of the server system. For example, power limiting may not be supported by reduced firmware compared to full firmware that supports power limiting. For example, reduced device power management functionality may be supported by reduced firmware compared to full firmware that supports device power management functionality. For example, reduced power management functionality, or the absence of this functionality, may be supported by reduced firmware compared to full firmware that supports full power monitoring functionality. For example, reduced platform telemetry acquisition and reporting, or the absence of this functionality, may be supported by reduced firmware compared to full firmware that supports full platform telemetry acquisition and reporting functionality. For example, reduced input from one or more sensors, or the absence of such input, may be supported by the reduced firmware compared to full firmware that supports input from one or more sensors.

[0020] If a feature not supported by the reduced firmware is requested, an error message may be issued to the OS, but the device with the updated firmware can continue to operate. In some cases, while the device is running version (a) firmware, the device's firmware can be updated while the system is running the OS to maintain system functionality. In some cases, some SPS functionality may be limited in the reduced firmware compared to the full firmware.

[0021] For example, a firmware update operation may include the device whose firmware is being updated running a first reduced firmware version, storing a second reduced firmware version in one of the slots, such as the slot that stored the previous full firmware version, verifying the second reduced firmware version, then the device whose firmware is being updated running the second reduced firmware version, storing the full firmware version in another slot, such as the slot that stored the first reduced firmware version, and finally the device whose firmware is being updated running the full firmware version.

[0022] Figure 2 shows an exemplary manner of storing firmware. For example, using a layout, firmware accessible by a device can be stored. A slot can be a range of addressable memory regions. For example, slot 201 and slot 202 can be addressable memory regions. In some examples, as described herein, slot 201 and slot 202 can store updated reduced firmware before one of slot 201 or slot 202 stores full firmware. Although two slots are illustrated, note that three or more slots can be used to store reduced or full firmware. In some examples, the order of firmware update and execution is to overwrite full firmware with a second reduced firmware, retain a fallback reduced firmware, execute the second reduced firmware while overwriting the reduced firmware with the second full firmware after verification of the second reduced firmware, and then execute the second full firmware.

[0023] Figures 3A and 3B show an exemplary flow of operations. A firmware update can include three stages of firmware update. That is, recovery at the firmware update stage during operation, firmware update stage during recovery, and firmware update stage during operation. One or more firmware updates can be verified, and if a firmware update is not verified, the device can boot from a verified firmware image.

[0024] The firmware update can include updating at least two versions of firmware, namely, a first version that is reduced functionality firmware (reduced firmware) and a second version that is full functionality firmware (firmware or full firmware). In some examples, prior to the firmware update, the first slot can store the reduced firmware and the second slot can store the full firmware. At 302, the trusted entity can send a command to the device whose firmware is being updated to execute the reduced firmware image in the first slot. The device can execute the reduced firmware in the first slot. At 304, the device can indicate to the trusted entity that the device is executing the reduced firmware.

[0025] At 306, the trusted entity can write a second reduced firmware to the second slot of the firmware storage, where the second slot previously stored the full firmware. At 308, the firmware storage controller can indicate to the trusted entity that the second slot stores the second reduced firmware. At 310, the trusted entity can instruct the device to boot from the second reduced firmware in the second slot. If the device fails to boot from the reduced firmware in the second slot, the device can boot using the reduced firmware in the first slot.

[0026] In 312, the device can provide the trusted entity with a status indicating that the device has booted the second reduced firmware from the second slot. The status may indicate the firmware version being run. The trusted entity can check whether the updated second reduced firmware has been correctly activated by verifying that the firmware version matches the updated recovery version. If verification fails, the trusted entity can have the device run a previously verified firmware version, such as the reduced firmware in the first slot, and / or indicate to the administrator that the full firmware version of a particular device has not been verified.

[0027] In 314, the trusted entity can update the first slot with the third reduced firmware. In 316, the firmware storage controller can indicate to the trusted entity that the first slot will store the third reduced firmware. In 318, the trusted entity can instruct the device to run the third reduced firmware image in the first slot. The device can then run the third reduced firmware in the first slot. In some examples, the trusted entity can activate the execution of the third reduced firmware in the first slot by sending a command to force recovery. If booting the third reduced firmware from the first slot fails, the second reduced firmware in the second slot can be executed. In 320, the device can indicate to the trusted entity that the device is running the third reduced firmware. For example, the trusted entity can send a Get FW status command, and the device will respond with a FW status that includes the FW version. The trusted entity can check whether the third reduced firmware in the first slot is correctly activated by verifying that the FW version matches the new recovery version, and the recovery reason is set to be executed by command.

[0028] In 322, the trusted entity can update the first slot with the second full firmware. In 324, the firmware storage controller can indicate to the trusted entity that the second slot will store the second full firmware. In 326, the trusted entity can activate the second full firmware for execution from the second slot by sending a Force ME Recovery command. If the device fails to boot the full firmware from the second slot, the device can boot using the reduced firmware from the second slot. In 328, the device can indicate to the trusted entity that the device is running the updated full firmware. The trusted entity can check whether the updated reduced firmware has been correctly activated by verifying that the firmware version matches the updated recovery version. If verification fails, the trusted entity can have the device run a previously verified firmware version (including the reduced firmware version) and / or indicate to the administrator that the full firmware version for a particular device has not been verified.

[0029] In some cases, steps 314-320 are not executed, the device can continue running the second reduced firmware instead of the third reduced firmware, the second full firmware can be written to the first slot instead of the second slot, and the device can run the second full firmware from the first slot.

[0030] Figures 4A and 4B show examples of processes that may be executed by the boot controller. In 402, a determination may be made if a firmware update is requested. If a firmware update is requested, the process can proceed to 404. If a firmware update is not requested, the process can repeat 402.

[0031] In 404, the device can boot from reduced firmware from the first slot of firmware storage. The firmware storage slot can store reduced or full firmware. In 406, the device can receive the second reduced firmware. The second reduced firmware can be stored in the second slot of firmware storage. In 408, in response to a request to boot the second reduced firmware from the second slot, the device can boot the second reduced firmware from the second slot and present the firmware version to the trusted entity. In some cases, the second reduced firmware is the same firmware as the reduced firmware in the first slot. In some cases, the second reduced firmware is different firmware from the reduced firmware in the first slot.

[0032] In step 410, the boot controller can determine whether it receives an indication to run a specific firmware after the reduction firmware update. For example, the device may receive an indication to run the reduction firmware from the first slot based on the identification that the second reduction firmware in the second slot has not been verified by the trusted entity. If the device receives an indication to run a specific firmware after the reduction firmware update, the process can proceed to step 430. If the device does not receive an indication to run a specific firmware after the reduction firmware update, the process can proceed to step 430.

[0033] In 412, a third reduced firmware can be received. The third reduced firmware may be stored in the first slot. In 414, in response to a request to boot the third reduced firmware from the third slot, the device can boot the third reduced firmware from the third slot and present the firmware version to the trusted entity.

[0034] Referring to Figure 4B, at 416, the boot controller can determine whether it receives an indication to run a specific firmware after the reduction firmware update. For example, the device may receive an indication to run the reduction firmware from the second slot based on the identification that the third reduction firmware in the first slot has not been verified by the trusted entity. If the device receives an indication to run a specific firmware after the reduction firmware update, the process can proceed to 430. If the device does not receive an indication to run a specific firmware after the reduction firmware update, the process can proceed to 418.

[0035] At 418, the device can receive a second full firmware. The second full firmware can be stored in the second slot or another slot. At 420, in response to a request to boot the second full firmware, the device can boot the second full firmware from the second slot and display the firmware version to a trusted entity.

[0036] In step 422, the boot controller can determine whether it receives an indication to run a specific firmware after a firmware update. For example, the device may receive an indication to run a third reduced firmware from the first slot based on the identification that the firmware in the second slot has not been verified by a trusted entity. If the device receives an indication to run a specific firmware after a firmware update, the process can continue to step 430. If the device does not receive an indication to run a specific firmware after a firmware update, the process can terminate or continue with another operation.

[0037] In the 430, the boot controller can execute verified reduced firmware or full firmware stored in the slot that was last updated. For example, after storing a second reduced firmware, it can execute verified reduced firmware. For example, after storing a third reduced firmware, it can execute verified second reduced firmware. For example, after storing full firmware, it can execute verified third reduced firmware.

[0038] Figure 5 shows an exemplary process that can be performed by a trusted entity. In 502, the trusted entity can verify the firmware recently copied to the device's firmware storage. Verification can be performed based on at least the firmware version in at least some examples. If the firmware is verified, the process can terminate. If the firmware is not verified, the process can continue to 504, where the trusted entity can have the device run a previously verified reduced or full firmware and notify the administrator of any specific firmware update that could not be verified.

[0039] Figure 6 shows the system. Various examples may be used by System 600 to update or access updated firmware, as described herein. System 600 includes a processor 610 that provides instruction processing, operation management, and execution for System 600. Processor 610 may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), APU (Accelerated Processing Unit), processing core, or other processing hardware or combination of processors that provides processing for System 600. Processor 610 controls the overall operation of System 600 and may be or include one or more programmable general-purpose or dedicated microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations thereof.

[0040] In one example, system 600 includes an interface 612 coupled to processor 610 that can represent a faster or higher-throughput interface to system components requiring higher bandwidth connections, such as the memory subsystem 620 or the graphics interface 640 or accelerator 642. Interface 612 represents an interface circuit that can be a standalone component or integrated into the processor die. If present, the graphics interface 640 interfaces with a graphics component to provide a visual display to the user of system 600. In one example, the graphics interface 640 can drive a high-definition (HD) display that provides output to the user. High resolution can refer to a display with a pixel density of approximately 100 PPI (pixels per inch) or higher and can include formats such as Full HD (e.g., 1180p), Retina displays, and 6K (Ultra High Definition or UHD). In one example, the display can include a touchscreen display. In one example, the graphics interface 640 generates a display based on data stored in memory 630, or based on operations performed by processor 610, or both. In one example, the graphics interface 640 generates a display based on data stored in memory 630, or based on operations performed by processor 610, or both.

[0041] Accelerator 642 can be a programmable or fixed-function offload engine that can be accessed or used by processor 610. For example, an accelerator within accelerator 642 can provide sequential and speculative decryption operations in the manner described herein, compression (DC) capabilities, cryptographic services such as public-key cryptography (PKE), cipher, hash / authentication capabilities, decryption, or other capabilities or services. In some embodiments, an accelerator within accelerator 642 provides field selection controller capabilities as described herein. In some cases, accelerator 642 may be integrated into a CPU socket (e.g., a connector to a motherboard or circuit board that includes a CPU and provides an electrical interface with the CPU). For example, accelerator 642 may include a single or multi-core processor, a graphics processing unit, a logic execution unit, a single or multi-level cache, a function unit that can be used to independently execute a program or thread, an application-specific integrated circuit (ASIC), a neural network processor (NNP), programmable control logic, and programmable processing elements such as a field-programmable gate array (FPGA). Accelerator 642 can provide multiple neural networks, CPUs, processor cores, general-purpose graphics processing units, or graphics processing units that can be made available by artificial intelligence (AI) or machine learning (ML) models. For example, the AI ​​model may use or include any or a combination of reinforcement learning schemes, Q-learning schemes, deep Q-learning or A3C (Asynchronous Advantage Actor-Critic), combinatorial neural networks, recurrent combinatorial neural networks, or other AI or ML models. Multiple neural networks, processor cores, or graphics processing units can be made available by the AI ​​or ML model. Firmware updates for processor 610 or accelerator 642 can be triggered using the techniques described herein.

[0042] The memory subsystem 620 represents the main memory of the system 600 and provides storage for data values ​​used when executing code or routines run by the processor 610. The memory subsystem 620 may include one or more memory devices 630, such as read-only memory (ROM), flash memory, DRAM, or other types of random access memory (RAM), or a combination of such devices. Memory 630 stores and hosts, among other things, the operating system (OS) 632, which provides a software platform for executing instructions in the system 600. Additionally, applications 634 can run from memory 630 on the software platform of OS 632. An application 634 represents a program with its own operational logic that performs the execution of one or more functions. A process 636 represents an agent or routine that provides auxiliary functions to OS 632, or one or more applications 634, or a combination thereof. OS 632, applications 634, and processes 636 provide software logic that provides functionality to the system 600. In one example, the memory subsystem 620 includes a memory controller 622, which is a memory controller that generates and issues commands to memory 630. It will be understood that the memory controller 622 may be a physical part of the processor 610 or a physical part of interface 612. For example, the memory controller 622 may be an integrated memory controller that is integrated into the circuit having the processor 610.

[0043] Although not specifically illustrated, System 600 will be understood to include one or more buses or bus systems between devices, such as a memory bus, graphics bus, interface bus, or others. Buses or other signal lines can connect components together communicatively or electrically, or can connect components communicatively and electrically. A bus can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuits or combinations. A bus can include, for example, one or more of the following: a system bus, a PCI (Peripheral Component Interconnect) bus, a Hypertransport or ISA (Industry Standard Architecture) bus, a SCSI (Small Computer System Interface), a USB (Universal Serial Bus), or an IEEE (Institute of Electrical and Electronics Engineers) 1394 bus (Firewire).

[0044] In one embodiment, system 600 includes interface 614 which may be coupled to interface 612. In one example, interface 614 represents an interface circuit which may include standalone components and integrated circuits. In one example, multiple user interface components or peripheral components, or both, are coupled to interface 614. Network interface 650 provides system 600 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 650 may include Ethernet adapters, wireless interconnect components, cellular network interconnect components, USB (universal serial bus), or other wired or wireless standard-based or proprietary interfaces. Network interface 650 may transmit data to remote devices which may include transmitting data stored in devices or memory located in the same data center or rack. Network interface 650 may receive data from remote devices which may include storing the received data in memory. Various examples can be used in relation to network interface 650, processor 610, and memory subsystem 620.

[0045] For example, system 600 includes one or more input / output (I / O) interfaces 660. The I / O interfaces 660 may include one or more interface components (e.g., audio, alphanumeric, haptic / touch, or other interfaces) through which the user interacts with system 600. Peripheral interfaces 670 may include any hardware interfaces not specifically described above. Peripherals generally refer to devices that depend on system 600 for connection. Dependent connections are those on which system 600 provides a software platform, hardware platform, or both, through which it operates and the user interacts.

[0046] In one example, system 600 includes a storage subsystem 680 that stores data in a non-volatile manner. In one example, in a particular system implementation, at least certain components of storage 680 may overlap with components of memory subsystem 620. Storage subsystem 680 includes storage 684, which may be or include any conventional medium for storing large amounts of data in a non-volatile manner, e.g., one or more magnetic, solid-state, or optical-based disks, or a combination thereof. Storage 684 holds code or instructions and data 1046 in a persistent state (e.g., values ​​are retained despite power interruption to system 600). Storage 684 can generally be considered “memory,” but memory 630 is typically execution memory or operational memory that provides instructions to processor 610. While storage 684 is non-volatile, memory 630 may include volatile memory (e.g., if power is interrupted to system 600, the values ​​or state of the data are indeterminate). In one example, storage subsystem 680 includes a controller 682 that interfaces with storage 684. For example, the controller 682 may be a physical part of the interface 614 or the processor 610, or it may include circuitry or logic in both the processor 610 and the interface 614.

[0047] Volatile memory is memory whose state (and therefore the data stored in it) is undefined when the device is powered off. Dynamic volatile memory may involve refreshing the data stored in the device to maintain its state. Examples of dynamic volatile memory include DRAM (Dynamic Random Access Memory) or several variants such as SDRAM (Synchronous DRAM). Memory subsystems such as those described herein may be compatible with multiple memory technologies, such as DDR3 (Double Data Rate version 3, originally released by JEDEC (Joint Electronic Device Engineering Council) on June 27, 2007). DDR4 (DDR version 4, initial specification published by JEDEC in September 2012), DDR4E (DDR version 4), LPDDR3 (Low Power DDR version 3, JESD209-3B, published by JEDEC in August 2013), LPDDR4 (LPDDR version 4, JESD209-4, original published by JEDEC in August 2014), WIO2 (Wide Input / output version 2, JESD229-2, original published by JEDEC in August 2014), HBM (High Bandwidth Memory, JESD325, original published by JEDEC in October 2013), LPDDR5 (currently under discussion by JEDEC), HBM2 (HBM version 2, currently under discussion by JEDEC), or other combinations of memory technologies, and technologies based on derivatives or extensions of such specifications.

[0048] Non-volatile memory (NVM) devices are memory devices whose state remains clear even when power is interrupted. In some examples, NVM devices can include block-addressable memory devices such as NAND technology, more specifically, multi-threshold level NAND flash memory (e.g., SLC (Single-Level Cell), MLC (Multi-Level Cell), QLC (Quad-Level Cell), TLC (Tri-Level Cell), or some other NAND). NVM devices may also include byte-addressable write-in-place 3D crosspoint memory devices, or other byte-addressable write-in-place NVMs such as single or multilevel PCM (Phase Change Memory) or PCMS (phase change memory with a switch), NVM devices using chalcogenide phase change materials (e.g., chalcogenide glass), resistive memory including metal oxide-based, oxygen vacancy point-based, and CB-RAM (Conductive Bridge Random Access Memory), nanowire memory, ferroelectric random access memory (FeRAM, FRAM®), magnetoresistive random access memory (MRAM) incorporating memoryr technology, STT (spin transfer torque)-MRAM, spintronic magnetic tunneling junction memory-based devices, MTJ (magnetic tunneling junction)-based devices, DW (Domain Wall) and SOT (Spin Orbit Transfer)-based devices, thyristor-based memory devices, or combinations of the above, or other memories.

[0049] A power source (not shown) provides power to the components of System 600. More specifically, the power source typically interfaces to one or more power sources within System 600 to provide power to the components of System 600. In one example, the power source includes an AC-DC (alternating current-to-direct current) adapter that plugs into a wall outlet. Such AC power can be a renewable energy source (e.g., solar power). In one example, the power source includes a DC power source such as an external AC-DC converter. In one example, the power source or power supply includes wireless charging hardware for charging via proximity to a charging field. In one example, the power source may include an internal battery, an AC power source, a motion-based power source, a solar power supply, or a fuel cell power source.

[0050] For example, System 600 may be implemented using interconnected computing threads of a processor, memory, storage, network interface, and other components. High-speed interconnects may include Ethernet® (IEEE 802.3), RDMA (remote direct memory access), InfiniBand, iWARP (Internet Wide Area RDMA Protocol), QUIC (quick UDP Internet Connections), RoCE (RDMA over Converged Ethernet), PCIe (Peripheral Component Interconnect express), QPI (Intel QuickPath Interconnect), UPI (Intel Ultra Path Interconnect), IOSF (Intel On-Chip System Fabric), Omnipath, CXL (Compute Express Link), HyperTransport, High-Speed ​​Fabric, NVLink, AMBA (Advanced Microcontroller Bus Architecture) interconnect, OpenCAPI, Gen-Z, CCIX (Cache Coherent Interconnect for Accelerators), 3GPP LTE (Long Term Evolution) (4G), 3GPP 5G, and their variations. Data can be copied or stored on virtualized storage nodes using protocols such as NVMe-oF (NVMe over Fabrics) or NVMe.

[0051] The examples herein may be implemented in various types of computing and networking equipment, such as switches, routers, racks, and blade servers used in data center and / or server farm environments. Servers used in data centers and server farms include arrayed server configurations, such as rack-based servers or blade servers. These servers are interconnected by communication through various network configurations, such as partitioning a set of servers into a Local Area Network (LAN) with appropriate switching and routing capabilities between LANs to form a private intranet. For example, cloud hosting functionality may typically utilize a large data center with a large number of servers. A blade comprises a separate computing platform configured to run server-type functionality, i.e., a “server on a card.” Thus, a blade includes components common to conventional servers, including a main printed circuit board (main board) that provides internal wiring (e.g., buses) for coupling appropriate integrated circuits (ICs), and other components mounted on the board.

[0052] Various examples can be used in base stations supporting communications using wired or wireless protocols (e.g., 3GPP LTE (Long Term Evolution) (4G) or 3GPP 5G), on-premises data centers, off-premises data centers, edge network elements, edge servers and switches, fog network elements, and / or hybrid data centers (e.g., data centers that use virtualization, cloud, and software-defined networking to deliver application workloads across physical data centers and distributed multi-cloud environments).

[0053] The examples herein may be implemented in various types of computing and networking equipment, such as switches, routers, racks, and blade servers used in data center and / or server farm environments. Servers used in data centers and server farms include arrayed server configurations, such as rack-based servers or blade servers. These servers are interconnected by communication through various networking configurations, such as partitioning a set of servers into a Local Area Network (LAN) with appropriate switching and routing capabilities between LANs to form a private intranet. For example, cloud hosting functionality may typically utilize a large data center with a large number of servers. A blade comprises a separate computing platform configured to run server-type functionality, i.e., a “server on a card.” Thus, each blade includes components common to conventional servers, including a main printed circuit board (main board) that provides internal wiring (e.g., buses) for coupling appropriate integrated circuits (ICs), and other components mounted on the board.

[0054] In some cases, network interfaces and other examples described herein can be used in connection with base stations (e.g., 3G, 4G, 5G, etc.), macro base stations (e.g., 5G networks), pico stations (e.g., IEEE 802.11 compliant access points), and nano stations (e.g., for PtMP (Point-to-MultiPoint) applications).

[0055] Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. Determining whether an example is implemented using hardware elements and / or software elements may vary according to any number of factors such as desired computing speed, power levels, thermal tolerances, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints, as desired for a given implementation. The processor may be a hardware state machine, a digital control logic, a central processing unit, or any combination of one or more hardware, firmware, and / or software elements.

[0056] Some examples may be implemented using or as manufactured articles or at least one computer-readable medium. The computer-readable medium may include non-temporary storage media for storing logic. In some examples, the non-temporary storage media may include one or more types of computer-readable storage media capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, etc. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0057] According to some examples, computer-readable media may include non-temporary storage media that, when executed by a machine, computing device, or system, stores or maintains instructions causing that machine, computing device, or system to perform methods and / or actions according to the examples described. Instructions may include any preferred type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. Instructions may be implemented according to a predefined computer language, scheme, or syntax for instructing a machine, computing device, or system to perform a given function. Instructions may be implemented using any preferred high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0058] One or more aspects of at least one example may be implemented by representative instructions stored in at least one machine-readable medium representing various logic within a processor, which, when read by a machine, computing device, or system, manufacture to the machine, computing device, or system the logic that performs the techniques described herein. Such representations, known as "IP cores," may be stored on tangible machine-readable medium and supplied to various customers or manufacturing facilities for loading into manufacturing machines that actually manufacture the logic or processor.

[0059] Where the phrases “one example” or “a certain example” appear, they do not necessarily refer to the same example or embodiment. Any aspect described herein can be combined with any other or similar aspect described herein, whether or not the aspect is described in relation to the same figure or element. The division, omission, or inclusion of block features shown in the accompanying drawings does not necessarily imply that hardware components, circuits, software, and / or elements for implementing these features are included in the division, omission, or inclusion in the example.

[0060] Some examples may be written using the expressions “combined” and “connected” along with their derivatives. These terms are not necessarily intended to be synonymous with each other. For example, a description using the terms “connected” and / or “combined” may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term “combined” may also mean that two or more elements are not in direct contact with each other but are cooperating or interacting with each other.

[0061] The terms “first,” “second,” etc., in this specification do not indicate any order, quantity, or importance, but rather are used to distinguish one element from another. The terms “a” and “an” in this specification do not indicate a limit on quantity, but rather indicate the presence of at least one of the referenced items. The term “asserted,” as used herein in reference to a signal, indicates that the signal is active and is a state of the signal that can be achieved by applying any logic level, logic 0 or logic 1, to the signal. The terms “following” or “after” can refer to immediately following or following some other event or a set of events. Other sequences of actions may also be performed by alternative examples. Furthermore, additional actions may be added or removed depending on the particular application. Any combination of modifications may be used, and those skilled in the art who are interested in this disclosure will understand many of these variations, modifications, and alternative examples.

[0062] Separable language, such as the phrase "at least one of X, Y, or Z," is generally understood to mean, unless otherwise specified, in contexts where it is used to indicate that an item, term, etc., can be X, Y, Z, or any combination thereof (e.g., X, Y, and / or Z). Therefore, such separable language is not intended, nor should it be, to imply that a particular example requires at least one of X, at least one of Y, or at least one of Z, each in order to exist. Additionally, associative language, such as the phrase "at least one of X, Y, and Z," should also be understood to mean "X, Y, Z," or any combination thereof, including "X, Y, and / or Z," unless otherwise specified.

[0063] Exemplary examples of devices, systems, and methods disclosed herein are provided below. Examples of devices, systems, and methods may include one or more of the examples described below, or any combination thereof.

[0064] Example 1 includes one or more examples illustrating the behavior of a device during a firmware update to a storage device. 、 Executing the reduction function firmware during the firmware update to the storage device, and booting the firmware from the storage device after the firmware update to the storage device, Maintained by Includes methods.

[0065] Example 2 includes one or more examples, which include storing multiple copies of the reduction function firmware before updating the firmware of the device.

[0066] Example 3 includes one or more examples, wherein the reduction function firmware being executed includes the verified reduction function firmware.

[0067] Example 4 includes one or more examples in which booting the firmware from storage after updating the firmware to storage is based on verified mitigation firmware.

[0068] Example 5 includes one or more examples, which include copying the reduction function firmware to a first area of ​​firmware storage, copying a second reduction function firmware to a second area of ​​firmware storage, and overwriting the first area of ​​firmware storage with the firmware.

[0069] Example 6 includes one or more examples in which overwriting the first area of ​​the firmware storage with the firmware is based on verification of at least the second reduction function firmware.

[0070] Example 7 includes one or more examples, wherein the reduction function firmware is 1 It provides one or more of the following: output reduction measurement from more than one sensor, reduced device power management function, limited power monitoring function, and / or reduced platform telemetry collection and reporting.

[0071] Example 8 includes one or more examples in which the boot controller executes reduction function firmware while updating the firmware to the storage device, and boots the firmware from the storage device after the firmware update to the storage device.

[0072] Example 9 includes one or more examples, including an apparatus including a device, wherein the device runs reduced-function firmware to maintain the operation of the device while it is operating and during a firmware update of the device, wherein the reduced-function firmware provides the device with fewer functions than the firmware being updated.

[0073] Example 10 includes one or more examples, wherein the reduction function firmware includes verified reduction function firmware.

[0074] Example 11 includes one or more examples in which the reduction function firmware includes an updated version of the reduction function firmware that overwrites the full firmware in the firmware storage.

[0075] Example 12 includes one or more examples, wherein the reduction function firmware is 1 It provides one or more of the following: output reduction measurement from more than one sensor, reduced device power management function, limited power monitoring function, and / or reduced platform telemetry collection and reporting.

[0076] Example 13 includes one or more examples in which the firmware provides the operation of the reduction function firmware and provides one or more of the following: measurement of output from one or more sensors, device power management function, power monitoring function, and / or platform telemetry collection and reporting.

[0077] Example 14 includes one or more examples, wherein the device includes one or more of the following: XPU, IPU (infrastructure processing unit), CPU (central processing unit), CPU socket, GPU (graphics processing unit), processor, accelerator device, BMC (Board Management Controller), storage controller, memory controller, display engine, peripheral device, Intel® Management or ME (Manageability Engine), AMD PSP (Platform Security Processor), ARM (Advanced RISC Machines) core with TrustZone extension, network interface device, PCH (Platform Controller Hub), and application-specific integrated circuit (ASIC).

[0078] Example 15 includes one or more examples, including a server that includes the device, wherein, prior to the firmware update, the server instructs the device to perform one or more operations, and maintaining the operation of the device includes performing the one or more operations.

[0079] Example 16 includes one or more examples, including a computer-readable medium on which instructions are stored, wherein, if executed by one or more processors, the instructions cause one or more processors to execute reduced-function firmware in order to maintain the operation of the device during a firmware update of the device, wherein the reduced-function firmware provides the device with fewer functions than the firmware being updated.

[0080] Example 17 includes one or more examples, wherein the reduction function firmware includes verified reduction function firmware.

[0081] Example 18 includes one or more examples in which the reduction function firmware includes an updated version of the reduction function firmware that overwrites the full firmware in the firmware storage.

[0082] Example 19 includes one or more examples, wherein the reduction function firmware is 1 It provides one or more of the following: output reduction measurement from more than one sensor, reduced device power management function, limited power monitoring function, and / or reduced platform telemetry collection and reporting.

[0083] Example 20 includes one or more examples, the device including one or more of the following: XPU, IPU (infrastructure processing unit), CPU (central processing unit), CPU socket, GPU (graphics processing unit), processor, accelerator device, BMC (Board Management Controller), storage controller, memory controller, display engine, peripheral device, Intel® Management or ME (Manageability Engine), AMD PSP (Platform Security Processor), ARM (Advanced RISC Machines) core with TrustZone extension, network interface device, PCH (Platform Controller Hub), and application-specific integrated circuit (ASIC).

Claims

1. A method performed by a boot controller, The device's behavior during firmware updates to storage devices is as follows: The reduction function firmware is executed during the firmware update to the storage device, The method includes maintaining the firmware after updating the firmware on the storage device by booting the firmware from the storage device, and the method is Copying the aforementioned reduction function firmware to the first area of ​​firmware storage, Copying the second reduction function firmware to the second area of ​​the firmware storage, A method comprising overwriting the first area of ​​the firmware storage with the firmware.

2. The method according to claim 1, comprising storing a plurality of copies of the reduction function firmware before updating the firmware of the device.

3. The method according to claim 1, wherein the reduction function firmware to be executed includes verified reduction function firmware.

4. The method according to claim 1, wherein booting the firmware from the storage device after updating the firmware on the storage device is based on the fact that the reduction function firmware has been verified.

5. The method according to claim 1, wherein overwriting the first area of ​​the firmware storage with the firmware is based on verification of at least the second reduction function firmware.

6. The method according to any one of claims 1 to 5, wherein the reduction function firmware provides one or more of the following: reduction measurement of output from one or more sensors, reduction device power management function, limited power monitoring function, and / or reduction platform telemetry collection and reporting.

7. The device includes, and the device, when in operation, During a firmware update of the device, in order to maintain the operation of the device, a reduction function firmware is executed, wherein the reduction function firmware provides the device with fewer functions than the firmware being updated. The device includes an updated version of the reduction function firmware that overwrites the full firmware in the firmware storage.

8. The apparatus according to claim 7, wherein the reduction function firmware to be executed includes verified reduction function firmware.

9. The apparatus according to claim 7, wherein the reduction function firmware provides one or more of the following: reduction measurement of output from one or more sensors, reduction device power management function, limited power monitoring function, and / or reduction platform telemetry collection and reporting.

10. The apparatus according to claim 9, wherein the firmware provides the operation of the reduction function firmware and provides one or more of the following: measurement of output from one or more sensors, device power management function, power monitoring function, and / or platform telemetry collection and reporting.

11. The aforementioned devices include XPU, IPU (infrastructure processing unit), CPU (central processing unit), CPU socket, GPU (graphics processing unit), processor, accelerator device, BMC (Board Management Controller), storage controller, memory controller, display engine, peripheral device, Intel® Management or ME (Manageability Engine), AMD PSP (Platform Security Processor), ARM (Advanced RISC Machines) core with TrustZone extension, network interface device, PCH (Platform Controller) The apparatus according to any one of claims 7 to 10, comprising one or more Hubs and Application-Specific Integrated Circuits (ASICs).

12. Includes a server that includes the aforementioned device, The apparatus according to any one of claims 7 to 11, wherein, prior to the firmware update, the server instructs the device to perform one or more operations, and maintaining the operation of the device includes performing the one or more operations.

13. A computer-readable medium on which instructions are stored, wherein, when the instructions are executed by one or more processors, the instructions are sent to one or more processors. During a device firmware update, in order to maintain the operation of the device, a reduction function firmware is executed, wherein the reduction function firmware provides the device with fewer functions than the firmware being updated. The reduction function firmware is a computer-readable medium containing an updated version of the reduction function firmware that overwrites the full firmware in the firmware storage.

14. The computer-readable medium according to claim 13, wherein the reduction function firmware includes verified reduction function firmware.

15. The computer-readable medium according to any one of claims 13 to 14, wherein the reduction function firmware provides one or more of the following: reduction measurement of output from one or more sensors, reduction device power management function, limited power monitoring function, and / or reduction platform telemetry collection and reporting.

16. The aforementioned devices include XPU, IPU (infrastructure processing unit), CPU (central processing unit), CPU socket, GPU (graphics processing unit), processor, accelerator device, BMC (Board Management Controller), storage controller, memory controller, display engine, peripheral device, Intel® Management or ME (Manageability Engine), AMD PSP (Platform Security Processor), ARM (Advanced RISC Machines) core with TrustZone extension, network interface device, PCH (Platform Controller) A computer-readable medium according to any one of claims 13 to 15, comprising one or more Hubs or Application-Specific Integrated Circuits (ASICs).

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