Trench-type BEOL memory cell

Abstract

To provide an integrated chip including a memory cell within a BEOL metal interconnect structure.SOLUTION: A memory cell may be a FeRAM memory cell. The memory cell is formed over a plurality of openings positioned in a dielectric structure including an inter-level dielectric layer. The plurality of openings may form an array or another two-dimensional pattern. A plurality of layers of the memory cell, is aligned with respect to the plurality of openings so that each of a lower electrode layer, a data storage layer, and an upper electrode layer descends into the openings. The lower electrode layer may pass through an etch stop layer and contact a lower interconnect structure. There may be a plurality of top electrode vias. The top electrode vias may be offset from the opening. The memory cell structure provides a large area, which leads to low threshold voltages.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This disclosure relates to integrated circuits and methods of forming the same.

Background Art

[0002] Many conventional electronic devices include electronic memory. The electronic memory may be volatile or non-volatile. Non-volatile memory can retain stored data even when the power supply is insufficient, while volatile memory cannot retain stored data when the power supply is insufficient. Dynamic random-access memory (DRAM), which requires frequent refreshing, is volatile memory. Non-volatile memory includes, for example, resistive random-access memory (RRAM), magnetoresistive random-access memory (MRAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and the like.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Summary of the Invention

[0004] Some forms of the present disclosure relate to an integrated chip comprising: a substrate; a lower dielectric structure located on the substrate; an interconnection structure located within the lower dielectric structure; an etching stop layer located on the lower dielectric structure; an interlayer dielectric layer located above the etching stop layer; one or more openings extending through the interlayer dielectric layer and the etching stop layer; and a memory cell including a lower electrode, a data storage layer and an upper electrode, the upper electrode being located on or within one or more openings, wherein each of the lower electrode, the data storage layer and the upper electrode extends into one or more openings and is located on one or more interlayer dielectric layers adjacent to the openings.

[0005] Some forms of the present disclosure relate to an integrated chip comprising a substrate, a metal interconnect structure located on the substrate and including a metallized layer, and a dielectric structure located on the metallized layer. Three or more openings, arranged in a two-dimensional manner, are extended to penetrate the dielectric structure. A memory cell includes a lower electrode, a data storage layer, and an upper electrode, the upper electrode being located on the dielectric structure and in each of the three or more openings. Each of the lower electrode, data storage layer, and upper electrode descends into the three or more openings and is located on the adjacent interlayer dielectric layers on the side of the three or more openings.

[0006] Some forms of this disclosure relate to a method for forming an integrated chip, comprising: forming a lower interconnect structure in a lower dielectric structure located on a substrate; forming an etching stop layer on the lower dielectric structure; forming an interlayer dielectric layer on the etching stop layer; etching a plurality of openings so as to penetrate the interlayer dielectric layer; forming a memory cell stack on the interlayer dielectric layer and in the plurality of openings; and etching from the memory cell stack to define memory cells, wherein the upper electrodes of the memory cells descend into each of the openings, and the portion of the memory cell extends from the opening side to the interlayer dielectric layer. [Brief explanation of the drawing]

[0007] By referring to the attached drawings while reading, the following detailed description will best convey the aspects of this disclosure. It should be noted that, according to standard industrial practice, various features are not depicted to scale. In fact, for the sake of clarity, the dimensions of various features may be arbitrarily enlarged or reduced. [Figure 1] This is a cross-sectional side view showing an integrated chip having memory cells according to some embodiments of the present disclosure. [Figure 2] Figure 1 is a top view showing the integrated chip. [Figure 3-9] This is a top view showing an integrated chip having memory cells according to multiple embodiments of the present disclosure. [Figure 10] A cross-sectional side view showing an integrated chip having memory cells according to another embodiment of the present disclosure. [Figure 11-19] Figure 1 is a cross-sectional side view illustrating an example method for forming a series of integrated chips, such as the integrated chip shown in Figure 1. [Figure 20] This flowchart illustrates a method for forming an integrated chip having memory cells according to this disclosure. [Modes for carrying out the invention]

[0008] The following disclosure provides numerous different embodiments or examples for implementing different features of the subject matter provided. For the sake of brevity, specific examples of elements and arrangements are described below. Of course, these are merely examples and not intended to be limiting. For example, a description in which a first feature lies on or is formed above a second feature includes, in addition to embodiments in which the first and second features are formed in direct contact, embodiments in which other features are formed between the first and second features so that they do not come into direct contact. Furthermore, the disclosure may duplicate element codes and / or alphabets in each example. This duplication is done for simplicity and clarity and does not specify relationships between the embodiments and / or arrangements in which it is described.

[0009] Spatial relative terms such as "below," "downward," "bottom," "above," "top," and similar terms may be used to describe and facilitate the description of the relationship between one element or feature and another element or feature as shown herein. These spatial relative terms are intended to include different orientations of the elements in use or operation, in addition to the illustrated orientation. The apparatus may be oriented in other forms (90-degree rotation or other orientations), and the spatial relative terms used herein may be interpreted accordingly.

[0010] This disclosure relates to a plurality of memory cells provided in a back-end-of-line (BEOL) metal interconnect structure of an integrated chip. The BEOL metal interconnect structure includes a plurality of through-hole layers and metallization layers that provide interconnection with a plurality of dielectric structures. The first dielectric structure includes an inter-level dielectric (ILD) layer provided on one of the plurality of metallization layers located in the metal interconnect structure. In some embodiments, the first dielectric layer includes an etching stop layer. In some embodiments, the first dielectric structure includes a buffer layer interposed between the etching stop layer and the ILD layer. The first dielectric layer includes the inner walls of one or more openings defined by the first dielectric structure. The memory cell includes a lower electrode, a data storage layer and an upper electrode, the upper electrode provided on one or more openings so that a first portion of the memory cell is provided laterally in one or more openings and a second portion of the memory cell is provided within one or more openings. Each of the first and second parts includes multiple parts of the lower electrode, data storage layer, and upper electrode.

[0011] In some embodiments, one or more openings include multiple openings. In some embodiments, multiple openings are arranged in two dimensions. In some embodiments, memory cells close to the lower electrode but without a through-hole for the lower electrode include one or more lines in the metallization layer and are in direct contact with an interconnect structure located directly beneath the memory cell.

[0012] The memory cell may be of a non-volatile type. In some embodiments, the memory cell is a resistive random-access memory (RRAM), a magnetoresistive random-access memory (MRAM), a ferroelectric random-access memory (FeRAM), a phase-change memory (PCM), or a similar. The data storage layer may consist of multiple layers, the combination of which is determined by the type of memory. In some embodiments, the memory cell is a ferroelectric random-access memory (FeRAM) cell, and the data storage layer is ferroelectric.

[0013] The memory cells described herein have a large effective cell area. The large effective cell area makes the threshold voltage more predictable and reduces the variation in threshold voltage between cells. The large effective cell area also reduces boundary effects and allows for a simpler structure in the peripheral region of the memory cell edge, thereby minimizing the number of processing steps without wasting chip area. The effective cell area can be enlarged by creating multiple deeper openings. In some embodiments, the depth of one or more openings is greater than the width of each of these openings. Deep openings are created by forming multiple openings in a first dielectric structure including an ILD layer. In some embodiments, the dielectric structure occupies the main space interposed between adjacent metallize layers. The multiple openings are further enlarged by extending to an etching stop layer located below the ILD layer. In some embodiments, the lower electrode is directly connected to the metallize layer located below and does not have a lower electrode through-hole. In some embodiments, the depth of the multiple openings is greater than half or half of the distance from the metallize layer below to the metallize layer located directly above the memory cell. In some embodiments, the lower electrode is connected to multiple lines located below the metallize layer.

[0014] By forming memory cells on multiple openings, the effective cell area can be further increased. Forming memory cells on multiple openings also offers another advantage. When a memory cell is formed on a single opening, the upper electrode may be recessed above the opening. A cover layer or hard shield layer surrounded by a recess may interfere with the connection of the top electrode through-hole. When there are multiple through-holes, each recess is smaller and located in the top electrode through-hole, which is situated on the upper electrode and facilitates better connection. In some embodiments, the memory cell includes multiple top electrode through-holes. Having multiple top electrode through-holes can reduce resistance. In some embodiments, the top electrode through-holes are laterally offset from the multiple openings. In some embodiments, the number of top electrode through-holes differs from the number of multiple openings. Separating the position and number of top electrode through-holes from the position and number of multiple openings allows for design and manufacturing flexibility.

[0015] In the method of this disclosure, the first dielectric structure is formed on a metallized layer. A shield is formed on one or more openings and is used to etch one or more openings through the first dielectric structure. The memory cell stack is formed on multiple openings so that the lower electrode and the data storage layer are aligned with the openings. In some embodiments, these multiple layers are formed by depositing atomic layers. In some embodiments, the upper electrode is also formed by depositing atomic layers. The memory cell stack is then etched to define the memory cells from the memory cell stack. In some embodiments, sidewall spacers are formed to surround the memory cells. In some embodiments, the sidewall spacers are connected to the edges of the lower electrode, the data storage layer and the upper electrode. The sidewall spacers may be located on top of the dielectric structure.

[0016] Figure 1 is a cross-sectional side view showing an integrated chip 100 having a memory cell according to some embodiments of the present disclosure. The integrated chip 100 includes a lower interconnect structure 155 provided on a lower dielectric structure 151 located on a substrate 153. A dielectric structure 181, including an etching stop layer 149, a buffer layer 147, and a first ILD layer 145, is provided on the lower dielectric structure 151. The dielectric structure 181 includes inner walls 181s that define a plurality of openings 111 by the dielectric structure 181. The inner walls 181s include the inner wall 149s of the etching stop layer 149, the inner wall 147s of the buffer layer 147, and the inner wall 145s of the first ILD layer 145.

[0017] The memory cell 101 is arranged on the dielectric structure 181 and extends to penetrate a plurality of openings 111 and is electrically coupled to the lower interconnect structure 155. The memory cell 101 includes a data storage layer 141 interposed between the lower electrode 143 and the upper electrode 139. In the region 175 on the side of the plurality of openings 111, each of the lower electrode 143, data storage layer 141, and upper electrode 139 of the memory cell 101 is located on the dielectric structure 181 and extends substantially horizontally. In region 175, the data storage layer 141 is positioned to be interposed vertically between the lower electrode 143 and the upper electrode 139. In region 171, each of the lower electrode 143, data storage layer 141, and upper electrode 139 extends substantially horizontally into the plurality of openings 111. In region 171, the data storage layer 141 is positioned to be interposed laterally between the lower electrode 143 and the upper electrode 139. The lower electrode 143 is arranged along the upper surface 181u and inner wall 181s of the dielectric structure 181. The data storage layer 141 is arranged along the surface 143u and inner wall 143s of the lower electrode 143. The upper electrode 139 is arranged along the surface 141u and inner wall 141s of the data storage layer 141. Each of the lower electrode 143, the data storage layer 141, and the upper electrode 139 is recessed into a plurality of openings 111.

[0018] In some embodiments, the cover structure 135 includes a dielectric material along the upper electrode 139. The top electrode through hole 123 extends through the cover structure 135 and is coupled to the upper electrode 139 by an upper interconnect structure 121 provided in the upper dielectric structure 133. The top electrode through hole 123 is connected to the upper surface 139u of the upper electrode 139. In some embodiments, the upper surface 139u has a plurality of recesses 139d located over the plurality of openings 111. In some embodiments, at least one top electrode through hole 123 is directly located over one of the recesses 139d. In some embodiments, an island region 125 of the dielectric material from the cover structure 135 is sandwiched between the top electrode through hole 123 located in the recess 139d and the upper electrode 139.

[0019] The sidewall spacer 137 surrounds the memory cell 101. In some embodiments, the sidewall spacer 137 is connected to the edge 139e of the upper electrode 139, the edge 141e of the data storage layer 141, and the edge 143e of the lower electrode 143. In some embodiments, the edges 139e, 141e, and 143e are aligned with each other. In some embodiments, the lower surface 137L of the sidewall spacer 137 is completely restricted over the upper surface 181u of the dielectric structure 181.

[0020] FIG. 2 is a top view showing an integrated chip in FIG. 1 along the cross-sectional line A-A' of FIG. 1. As shown in FIG. 2, the memory cell 101 has a square or rectangular shape and extends at a first distance along a first direction 206 and at a second distance along a second direction 208 perpendicular to the first direction 206. The second distance may be greater than, equal to, or less than the first distance. Alternatively, the integrated chip 100 may be circular, elliptical, hexagonal, or any other shape.

[0021] The multiple openings 111, constrained by the inner walls 181s of the dielectric structure 181, can also be square or rectangular. The multiple openings 111 extend along a first direction 206 by a third distance and along a second direction 208 by a fourth distance. The fourth distance may be greater than, equal to, or less than the third distance. Alternatively, the openings 111 may be circular, elliptical, hexagonal, or any other shape. Figure 3 is a top view showing an integrated chip having a memory cell 101B according to an alternative embodiment of the present disclosure. The memory cell 101B is similar to the memory cell 101 but has multiple circular openings 111B.

[0022] In some embodiments, the multiple openings 111 are elongated ellipses (i.e., rectangular or elliptical) but have a maximum width that is no more than three times the minimum width. In some embodiments, the maximum width is twice the minimum width. The shape of the openings that provide a high surface area is not an elongated ellipse, but rather something close to a square, circle, or hexagon, for example.

[0023] The arrangement of multiple openings 111 in a two-dimensional manner means that these openings do not form a single linear arrangement. As shown in this example, the multiple openings 111 may be arranged in a single array. The multiple openings 111 may be arranged in rows (extending in a second direction 208) and columns (extending in a first direction 206). The array may be 2×2, 2×4, 2×6, 3×3, or other sizes. In the examples of the disclosure, the array is 2×6. The memory cell 101 itself may be one of the memory cell 101 arrays that form a memory cell block.

[0024] Two lines located in the metallized layer Mx-1 of the lower interconnect structure 155 are positioned directly beneath each row. Each line is coupled to the lower electrode 143 by a plurality of openings in the corresponding row. As an alternative example, a broad single line of the lower interconnect structure 155 extends directly beneath one of the plurality of openings 111 in the array and is coupled to the lower electrode 143 by each of the plurality of openings 111. As another alternative example, a plurality of lines extending in a second direction 208 along the rows in the array may use three lines in such a case. In some embodiments, the lower electrode 143 is connected directly to one of the plurality of lines located at the bottom of each opening.

[0025] As shown in Figure 2, each of the openings 111 may have one top electrode through-hole 123. Alternatively, it may have more or fewer top electrode through-holes 123. As shown in Figure 2, the top electrode through-holes 123 may be located directly above the multiple openings 111. Alternatively, some or all of the top electrode through-holes 123 may be offset laterally from the multiple openings 111.

[0026] In some embodiments, the significance of arranging the top electrode through-holes 123 in two dimensions lies in the fact that they include at least three and are not all arranged in a single line. As shown in this example, the top electrode through-holes 123 may be arranged in an array. The top electrode through-holes 123 may be aligned in rows (extending in a second direction 208) and columns (extending in a first direction 206). The array may be 2×2, 2×4, 2×6, 3×3, or other sizes. In the example of disclosure, the array is 2×6. Alternatively, the through-holes do not have to be uniformly arranged on the top electrode 139.

[0027] Two lines located in the metallized layer Mx of the upper interconnect structure 121 are positioned directly above each row. Each line is coupled to a top electrode through-hole 123 in the corresponding row. As an alternative example, a broad single line of the upper interconnect structure 121 extends directly above the top electrode through-hole 123. As another alternative example, multiple lines extending in a second direction 208 along the rows in the array may use three lines in such a case. Each top electrode through-hole 123 is directly connected to one of the multiple lines.

[0028] Figure 4 is a top view 400 showing an alternative embodiment of the integrated chip provided by the present disclosure. The integrated chip in Figure 4 is similar to the integrated chip 100 in Figures 1 and 2, but has two top electrode through-holes 123, both connected to one line of the upper interconnect structure 121. In this embodiment, the top electrode through-holes 123 are offset from the multiple openings 111 to ensure good connection with the upper electrode 139.

[0029] Figure 5 is a top view 500 showing another alternative embodiment providing an integrated chip according to the present disclosure. The integrated chip in Figure 5 is similar to the integrated chip in Figure 4, but has a lower interconnect structure 155 which includes a single broad line extending corresponding to the memory cells 101 under six openings 111 located in the dielectric structure 181.

[0030] Figure 6 is a top view 600 showing another alternative embodiment of the integrated chip provided by the present disclosure. The integrated chip in Figure 6 is similar to the integrated chip in Figure 5, but has four top electrode through-holes 123 located at the outer corners close to the memory cell 101. The upper interconnect structure 121 includes two lines connected to the four top electrode through-holes 123.

[0031] Figure 7 is a top view 700 showing another alternative embodiment of the integrated chip provided by the present disclosure. The integrated chip in Figure 7 is similar to the integrated chip in Figure 6, but has an upper interconnect structure 121 that includes a single broad line connected to any of the four top electrode through-holes 123.

[0032] Figure 8 is a top view 800 showing another alternative embodiment of the integrated chip provided by the present disclosure. The integrated chip in Figure 8 is similar to the integrated chip in Figure 7, except that the top electrode through-holes 123 of the integrated chip in Figure 8 are irregularly arranged on the upper electrodes 139. This embodiment demonstrates the flexibility of positioning the top electrode through-holes 123 provided by the memory cell 101 and formed on a number of small openings.

[0033] Figure 9 is a top view 900 showing some other embodiments of the integrated chip provided by the present disclosure. The integrated chip includes a memory cell 101C similar to the memory cell 101B, but includes seven openings 111B. The seven openings 111B are arranged in three rows. Each of the openings 111B located in each row is arranged alternately with respect to the openings 111B in the adjacent row. Nine top electrode through-holes 123 are arranged in a 3x3 matrix. In this embodiment, the lower interconnect structure 155 includes three lines extending in a second direction 208 to connect to lower electrodes 143 located at the bottom of each of the seven openings 111B. The upper interconnect structure 121 includes three lines extending in a first direction 206. Each of the lines located in the metallized layer Mx connects to the three top electrode through-holes 123.

[0034] Referring to Figures 1 and 2, the opening 111 has a width W1 and a height H1. In some embodiments, the height H1 is greater than or equal to the width W1. In some embodiments, the height H1 is twice or greater than twice the width W1. The height H2 separates the lower interconnect structure 155 and the upper interconnect structure 121. The height H2 is also the distance between the metallization layer Mx-1 located below the direct memory cell 101 and the metallization layer Mx located above the direct memory cell 101. In some embodiments, the height H1 is half or greater than half the height H2. In some embodiments, the height H1 is formed to be between 400 angstroms (Å) and 3200 Å. In some embodiments, the height H1 is formed to be between 700 Å and 2150 Å. In some embodiments, the distance D1 between adjacent openings 111 is less than or equal to the width W1 of the opening 111. In some embodiments, this limitation is satisfied in both directions, the first direction 206 and the second direction 208.

[0035] The integrated chip 100 may include one or more lower interconnection structures 155 provided within the lower dielectric structure 151, and one or more upper interconnection structures 121 provided within the upper dielectric structure 133. The lower interconnection structures 155 and upper interconnection structures 121 may include interconnection lines, interconnection through holes, contact plugs, contact pads, or similar. In some embodiments, the lower interconnection structures 155 and upper interconnection structures 121 may include copper, tungsten, ruthenium, aluminum, a combination thereof, or similar. Each of the lower interconnection structures 155 and upper interconnection structures 121 may include multiple stacked inter-level dielectric (ILD) layers. The ILD layers may be separated from the buffer layers by one or more etching stop layers.

[0036] The first ILD layer 145 and other ILD layers may include silica, carbon-doped silica, borosilicate glass (BSG), phosphorus silicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), un-doped silicate glass (USG), combinations thereof, or similar materials. In some embodiments, the first ILD layer 145 is a low k-value dielectric. In some embodiments, it is an extremely low k-value dielectric. One example of a low k-value dielectric is a low k-value dielectric material that reduces the porosity of the overall dielectric constant. In some embodiments, the first ILD layer 145 is formed to a thickness of 300 Å to 2000 Å, specifically with reference to the portion of height H1 from the first ILD layer 145 to the opening 111. In some embodiments, this portion of the first ILD layer 145 is formed to a thickness of 500 Å to 1500 Å.

[0037] The etching stop layer 149 and other etching stop layers may contain metal nitrides, metal oxides, metal carbides, silicon nitride, silicon oxide, silicon carbide, silicon oxynitride, silicon carbon oxide, combinations thereof, or similar materials. In some embodiments, the etching stop layer 149 contains silicon carbide, silicon nitride, silicon oxynitride, silicon carbon oxide, combinations thereof, or similar materials. In some embodiments, the etching stop layer 149 contains silicon carbide or similar materials. In some embodiments, the etching stop layer 149 is formed to a thickness of 50 Å to 500 Å. In some embodiments, the etching stop layer 149 is formed to a thickness of 150 Å to 350 Å.

[0038] The buffer layer 147 may or may not be formed and may, for example, include promoting adhesion between the first ILD layer 145 and the etching stop layer 149. The buffer layer 147 may be a silicon oxide compound such as silica, silicon-rich silicon oxide, or similar. In some examples, the buffer layer 147 is silicon oxide derived from tetraethyl orthosilicate (TEOS). In some examples, the etching stop layer 149 is formed to a thickness of 30 Å to 700 Å. In some examples, the etching stop layer 149 is formed to a thickness of 50 Å to 300 Å.

[0039] Each of the lower electrode 143 and the upper electrode 139 may be or include one or more metal layers such as tantalum oxide, titanium oxide, ruthenium, platinum, iridium, tungsten, a combination thereof, or similar. In some embodiments, the lower electrode 143 is tantalum oxide, titanium oxide, each of the above layers, or similar, or includes them. In some embodiments, the lower electrode 143 has a thickness in the range of 25 Å to 400 Å. In some embodiments, the lower electrode 143 has a thickness in the range of 50 Å to 200 Å. In some embodiments, the lower electrode 143 forms a layer having these thicknesses. In some embodiments, these thicknesses may be applied to the region 175 on the side of the opening 111.

[0040] In some embodiments, the upper electrode 139 is a layer of tantalum oxide, titanium oxide, or both, or similar, or comprises them. In some embodiments, the upper electrode 139 has a thickness in the range of 25 Å to 1000 Å. In some embodiments, the upper electrode 139 has a thickness in the range of 50 Å to 500 Å. These thicknesses may be applied to the region 175 on the side of the opening 111. The upper electrode 139 in the opening 111 has a thicker thickness by being deposited or grown on the opposing inner wall 141s of the data storage layer 141.

[0041] The data storage layer 141 may include one or more layers formed of any suitable material. In some embodiments, the data storage layer 141 includes a ferroelectric layer. The ferroelectric layer may be, for example, a binary oxide, a ternary oxide, or a quaternary oxide. In some embodiments, the data storage layer 141 includes hafnium silicate (HfSiO x ), hafnium zirconate (HfZrO x ), barium titanate (BaTiO3), lead titanate (PbTiO3), strontium titanate (SrTO3), manganese calcium (CaMnO3), bismuth ferrite (BiFeO3), aluminum scandium nitrate (AlScN), aluminum gallium nitride (AlGaN), aluminum yttrium nitrate, combinations thereof or similar ternary oxides. In some examples, the data storage layer 141 is made of strontium barium titanate (BaSrTiO3), lead titanate (PbTiO3), strontium titanate (SrTO3), strontium barium titanate (BaSrTiO nitrate (SrTO3), strontium nitrate (CaMnO3), bismuth ferrite (BiFeO3), aluminum scandium nitrate (AlScN), aluminum gallium nitride (AlGaN), aluminum yttrium nitrate, or a combination thereof or similar ternary oxides. x ) or a similar quaternary oxide. In some embodiments, the data storage layer 141 has a thickness in the range of 25 Å to 400 Å. In some embodiments, the data storage layer 141 has a thickness in the range of 50 Å to 200 Å.

[0042] The cover structure 135 may include one or more layers formed of any material. In some embodiments, the cover structure 135 includes a hard shield material. The hard shield material may, for example, be silicon oxynitride, titanium nitride, silicon oxide, silicon nitride, silicon carbide nitride, silicon oxynitride, metal oxides, combinations thereof, or similar. The metal oxide may be titanium oxide, aluminum oxide, or similar. In some embodiments, the cover structure 135 has a thickness in the range of 30 Å to 600 Å. In some embodiments, the cover structure 135 has a thickness in the range of 50 Å to 400 Å. The material applied to the cover structure 135 is also applied to the side wall spacer 137.

[0043] Figure 10 is a cross-sectional side view 1000 showing an integrated chip having memory cells 101 according to another embodiment of the present disclosure. The integrated chip includes a first region 1002, which may also be called a memory region, and a second region 1004, which is laterally offset from the first region 1002 and may also be called a logic region. In the first region 1002, one or more lower interconnect structures 155 are arranged in a lower dielectric structure 151 located on a substrate 153. The memory cells 101 are arranged on a dielectric structure 181, which is located on the lower dielectric structure 151. The dielectric structure 181 includes an etching stop layer 149, a buffer layer 147, and a first ILD layer 145. The first ILD layer 145 may be deposited on the side of the memory cells 101, following a second ILD layer 1006 above it. The second ILD layer 1006 is the bottommost part of the upper dielectric structure 133. The upper interconnect structure 121 is arranged within the upper dielectric structure 133. The upper interconnect structure 121 is electrically coupled to the memory cell 101 by the top electrode through-hole 123.

[0044] The memory cell 101 includes a lower electrode 143 and an upper electrode 139 separated from each other by a data storage layer 141. Each of the lower electrode 143, the upper electrode 139, and the data storage layer 141 includes a downward-facing projection that extends into an opening 111 located in the dielectric structure 181. The lower electrode 143 extends downward and contacts one or more lower interconnection structures 155.

[0045] In the second region 1004, one or more additional lower interconnection structures 1012 are provided within the lower dielectric structure 151. One or more additional lower interconnection structures 1012 are coupled to additional interconnection through-holes 1014 that penetrate the dielectric structure 181 and the second ILD layer 1006. An additional upper interconnection structure 1018 is provided within the upper dielectric structure 133. Each of the upper interconnection structure 121 and the additional upper interconnection structure 1018 includes a plurality of lines located in the metallized layer Mx. Each of the lower interconnection structure 155 and the additional lower interconnection structure 1012 includes a plurality of lines located in the metallized layer Mx-1.

[0046] Figures 11 to 19 are cross-sectional side views illustrating several embodiments of a method for forming an integrated chip having a series of memory cells. While Figures 11 to 19 illustrate the method, it should be understood that the structures disclosed in Figures 11 to 19 are not only found in this method but can also exist independently of it.

[0047] In the cross-sectional side view 1100 shown in Figure 11, one or more lower interconnect structures 155 are formed within a lower dielectric structure 151 located on the substrate 153. In various embodiments, the substrate 153 may be any type of semiconductor block material (i.e., silicon, silicon germanium, SOI, etc.), such as a semiconductor wafer and / or a die located on the wafer, or any other type and associated semiconductor and / or epitaxial layer. In some embodiments, one or more lower interconnect structures 155 may include one or more middle-of-line (MOL) interconnect structures, conductive contacts, interconnect lines and / or interconnect through-holes.

[0048] In some embodiments, one or more lower interconnect structures 155 may be formed correspondingly by a damascene process (i.e., a single damascene process or a dual damascene process). In such embodiments, one or more lower interconnect structures 155 may be formed correspondingly by one or more cycles including forming an interlayer dielectric (ILD) layer, selectively etching the ILD layer to define through holes and / or grooves in the ILD layer, forming a conductive material (e.g., copper, aluminum, etc.) in the through holes and / or grooves, and performing a planarization process (e.g., a chemical mechanical planarization (CMP) process) to remove excess conductive material from above the ILD layer.

[0049] In the cross-sectional side view 1200 shown in Figure 12, the dielectric structure 181 includes an etching stop layer 149, a buffer layer 147, and a first ILD layer 145 formed on the lower dielectric structure 151. The etching stop layer 149, buffer layer 147, and first ILD layer 145 may be formed by one or more deposition processes (e.g., physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced CVD (PE-CVD), atomic layer deposition (ALD), or similar).

[0050] In the cross-sectional side view 1300 shown in Figure 13, a shield 1304 is formed and a first etching process 1302 is performed to pattern the dielectric structure 181. The shield 1304 may include a photosensitive material (e.g., a photoresist material), a hard shield, or the like. The first etching process 1302 forms a plurality of side walls 181s that define a plurality of openings 111 that extend through the dielectric structure 181. In some embodiments, the openings 111 are rectangular in plan view. In some embodiments, the openings 111 are circular in plan view. After the completion of the first etching process 1302, the shield 1304 is peelable.

[0051] In the cross-sectional side view 1400 shown in Figure 14, the memory cell stack 1407 is formed on a first ILD layer and located within a plurality of openings 111. The memory cell stack 1407 may be formed by a plurality of deposition processes (e.g., PVD process, CVD process, PE-CVD process, ALD process, or similar). The memory cell stack 1407 includes at least one lower electrode layer 1401, a data storage layer 1403, and an upper electrode layer 1405. In some embodiments, the lower electrode layer 1401 is formed along the inner wall 181s and upper surface 181u of the dielectric structure 181. In some embodiments, the lower electrode layer 1401 is formed by ALD or similar. In some embodiments, the data storage layer 1403 is formed along the inner wall 1401s and upper surface 1401u of the lower electrode layer 1401. In some embodiments, the data storage layer 1403 is formed by ALD or similar. In some embodiments, the upper electrode layer 1405 is formed by the inner wall 1403s and surface 1403u of the data storage layer 1403. In some embodiments, the upper electrode layer 1405 is formed by ALD or similar. Furthermore, in the cross-sectional side view 1400 shown in Figure 14, the cover structure 135 may be formed on the memory cell stack 1407. The cover structure 135 may be formed by one or more deposition processes.

[0052] In the cross-sectional side view 1500 shown in Figure 15, the second shield 1504 may be formed in and used in the second etching process 1502 to define the memory cell 101 from the memory cell stack 1407. The second etching process 1502 defines the lower electrode 143 from the lower electrode layer 1401, the data storage layer 141 from the data storage layer 1403, and the upper electrode 139 from the upper electrode layer 1405. In some embodiments, the second etching process 1502 includes one or more dry etching processes (e.g., reactive ion etching (RIE), plasma etching, a combination thereof, or similar). After completion of the second etching process 1502, the second shield 1504 is removable.

[0053] In the cross-sectional side view 1600 shown in Figure 16, the sidewall spacer 137 may be formed to cover multiple edges 101e of the memory cell 101. The sidewall spacer 137 may be formed by one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, ALD process, or similar) and a subsequent etching process to remove spacer material from multiple horizontal surfaces.

[0054] In the cross-sectional side view 1700 shown in Figure 17, the second ILD layer 1006 may be formed on the memory cell 101 and the first ILD layer 145. The second ILD layer 1006 may be formed by one or more deposition processes (e.g., PVD process, CVD process, PE-CVD process, ALD process, or similar).

[0055] In the cross-sectional side view 1800 shown in Figure 18, a shield 1804 may be formed, and a third etching process 1802 may be performed, thereby forming a plurality of grooves 1806 in the second ILD layer 1006. In the cross-sectional side view 1900 shown in Figure 19, a shield 1904 may be formed, and a fourth etching process 1902 may be performed, thereby forming a plurality of holes 1906 in the plurality of grooves 1806. The plurality of holes 1906 extend through the second ILD layer 1006 and through the cover structure 135 to expose the upper surface 139u of the upper electrode 139. In particular, if the plurality of holes 1906 are formed on a plurality of recesses 139d located directly on the upper surface 139u, the island region 125 of the cover structure 135 may be left at the bottom of the plurality of holes 1906.

[0056] The shield 1904 is peelable, and the multiple holes 1906 and multiple grooves 1806 may be filled with a conductive material and then planarized to produce the structure shown in Figure 1. Filling the multiple holes 1906 with the conductive material provides the top electrode through-hole 123, and filling the multiple grooves 1806 with the conductive material provides multiple lines MX. The conductive material may be formed by a deposition process and / or a planarization process (e.g., electroplating, chemical coating or similar). The planarization process may be, for example, chemical mechanical polishing (CMP).

[0057] Figure 20 is a flowchart illustrating process 2000 for forming an integrated chip having memory cells according to the present disclosure. While process 2000 has been described as a series of actions or events, it should be understood that the order of these actions or events is not restrictive. For example, some actions may occur in a different order than those shown and / or described in these embodiments and / or simultaneously with other actions or events. Furthermore, not all actions shown are necessary to realize one or more states or embodiments described herein. Note that one or more actions described herein may be performed in one or more separate actions and / or events.

[0058] Process 2000 may begin with step 2002, which involves forming a lower interconnect structure within a dielectric structure located on a substrate. A cross-sectional side view 1100 in Figure 11 provides one example. Forming the lower interconnect structure may involve forming a plurality of through-holes and metallized layers to produce a structure of the type shown in the cross-sectional side view 1000 in Figure 10.

[0059] Process 2000 may continue from step 2004, which forms a dielectric structure located on top of the lower dielectric structure. A cross-sectional side view 1200 in Figure 12 provides one example. The dielectric structure includes an ILD layer. In some embodiments, the ILD layer is a low k-value dielectric. In some embodiments, the dielectric structure includes an etching stop layer which is its bottom layer. In some embodiments, the dielectric structure includes a buffer layer located between the etching stop layer and the ILD layer.

[0060] Step 2006 patterns the dielectric structure to form multiple openings. In some embodiments, the lower dielectric structure is exposed by multiple openings. A cross-sectional side view 1300 in Figure 13 provides one example. In some embodiments, the multiple openings are arranged in a two-dimensional pattern, and the multiple openings include at least three openings that are not arranged in a single line. Figures 2 to 9 provide several examples of several possible opening shapes and two-dimensional patterns.

[0061] Step 2008 involves forming a memory cell stack on a dielectric structure and within multiple openings. A cross-sectional side view 1400 in Figure 14 provides one example. The memory cell stack includes at least one lower electrode layer, a data storage layer, and an upper electrode layer. Each of these layers itself may include multiple layers.

[0062] Step 2010 involves forming a cover structure on the memory cell stack. A cross-sectional side view 1400 in Figure 14 provides one example. The cover structure may include one or more layers. The cover structure may provide a hard shield to etch the memory cell stack. The cover structure may provide a buffer layer between the upper electrode located on the memory cell and the second ILD layer. The cover structure may provide an etching stop layer to help the through-holes adhere to the upper electrode.

[0063] Step 2012 patterns the memory cell stack to define the memory cells. A cross-sectional side view 1500 in Figure 15 provides one example. The memory cell includes a protrusion located at each opening.

[0064] Step 2014 forms sidewall spacers surrounding the memory cells. A cross-sectional side view 1600 in Figure 16 provides one example. In some embodiments, the height of the sidewall spacers is equal to the height of the memory cell stack. In some embodiments, multiple edges of various layers of the memory cell stack are aligned with and in contact with adjacent sidewall spacers. Selectively, before forming the sidewall spacers, multiple edges of the memory cells are treated to remove or deactivate contaminants. Selectively, the memory cells include multiple sidewall spacers. Selectively, some sidewall spacers are formed before the patterning of the memory cell stack is completed and selectively do not need to be aligned with multiple edges.

[0065] Step 2016 involves forming a second ILD layer on top of the memory cell. A cross-sectional side view 1700 in Figure 17 provides one example. The second ILD layer may have the same configuration as the first ILD layer, and such two layers may appear as a continuous layer.

[0066] Step 2018 extends to connect the upper electrode and forms a top electrode through-hole that penetrates the second ILD layer. A combination of the cross-sectional side view 1800 in Figure 18, the cross-sectional side view 1900 in Figure 19, and Figure 1 provides one example. In some embodiments, the top electrode through-holes are arranged in a two-dimensional pattern. In some embodiments, the top electrode through-holes are formed above multiple openings. In some embodiments, an island region of the cover structure is sandwiched between one of the top electrode through-holes and the upper electrode. In some embodiments, at least some top electrode through-holes are offset from multiple openings. In some embodiments, the number of top electrode through-holes is greater than the number of multiple openings. In some embodiments, the number of top electrode through-holes is less than the number of multiple openings. Figures 1 to 9 provide several examples of possible arrangement schemes for several top electrode through-holes.

[0067] Some forms of the present disclosure relate to an integrated chip comprising: a substrate; a lower dielectric structure located on the substrate; an interconnect structure located within the lower dielectric structure; an etching stop layer located on the lower dielectric structure; an interlayer dielectric layer located above the etching stop layer; one or more openings extending through the interlayer dielectric layer and the etching stop layer; and a memory cell including a lower electrode, a data storage layer and an upper electrode, the upper electrode being located on or within one or more openings, each of which extends within one or more openings and is located on an adjacent interlayer dielectric layer on the side of one or more openings. In some embodiments, one or more openings include at least three openings arranged in two dimensions. In some embodiments, the array of openings corresponds to a memory cell. In some embodiments, the memory cell is a ferroelectric memory cell. In some embodiments, the lower electrode and the interconnect structure are in direct contact. In some embodiments, the depth of one or more openings is greater than or equal to the width of one or more openings.

[0068] Some embodiments of this disclosure relate to an integrated chip comprising a substrate, a metal interconnect structure located on the substrate and including a metallized layer, and a dielectric structure located on the metallized layer. Three or more openings, arranged in a two-dimensional manner, extend to penetrate the dielectric structure. A memory cell includes a lower electrode, a data storage layer, and an upper electrode, the upper electrode being located on the dielectric structure and within each of the three or more openings. Each of the lower electrode, data storage layer, and upper electrode descends into the three or more openings and is located on the adjacent interlayer dielectric layer on the side of the three or more openings. In some embodiments, the top electrodes and the through-hole upper electrodes are in direct contact. In some embodiments, an island region of dielectric material falls between the top electrode through-hole and the upper electrode of the memory cell. In some embodiments, the top electrode through-hole is horizontally offset from each of the three or more openings. In some embodiments, the three or more openings are located directly above two or more lines in the metallized layer. In some embodiments, the depth of three or more openings is greater than or equal to the distance between the top of the three or more openings and the metallized layer covering them.

[0069] Some embodiments of this disclosure relate to a method for forming an integrated chip, comprising: forming a lower interconnect structure in a lower dielectric structure located on a substrate; forming an etching stop layer on the lower dielectric structure; forming an interlayer dielectric layer on the etching stop layer; etching a plurality of openings so as to penetrate the interlayer dielectric layer; forming a memory cell stack on the interlayer dielectric layer and in the plurality of openings; and etching from the memory cell stack so as to define memory cells, wherein the upper electrodes of the memory cells descend into each of the openings, and the memory cell portions extend from the plurality of openings onto the interlayer dielectric layer. In some embodiments, the openings are extended so as to penetrate the etching stop layer. In some embodiments, the method further comprises forming a plurality of top electrode through-holes, each in contact with a top electrode.

[0070] The preamble outlines several embodiments so that those skilled in the art may easily understand the aspects of this disclosure. Those skilled in the art should understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures to achieve the same objectives and / or the same merits as the embodiments described herein. Those skilled in the art should also be aware that such equivalent structures will not deviate from the spirit and scope of this disclosure, and that various changes, substitutions and modifications can be made to the text without deviating from the spirit and scope of this disclosure. [Explanation of Symbols]

[0071] 100: Integrated chip 101, 101B, 101C: Cell 101e: Edge 111,111B: Opening 121: Upper interconnection structure 123:Top electrode through hole 125: Island Area 133: Upper dielectric structure 135: Cover structure 137: Side wall spacer 137L: Bottom surface 139: Upper electrode 139d: recess 139e: Edge 139u: surface 141: Data storage layer 141e: Edge 141s: Inner wall 141u: surface 143: Lower electrode 143e: Edge 143s:Inner wall 143u: surface 145: First ILD layer 145s: Inner wall 147: Buffer layer 147s:Inner wall 149: Etching stop layer 149s: Inner wall 151: Lower dielectric structure 153: Base material 155: Lower interconnection structure 171: Area 175: Area 181: Dielectric Structure 181s: Inner wall 181u: surface 206: First Direction 208: Second Direction 400, 500, 600, 700, 800, 900: Top view 1000, 1100, 1200, 1300, 1400, 1500, 1600, 1700, 1800, 1900: Cross-sectional side view 1002: First Domain 1004: Second Domain 1006: Second ILD layer 1012: Additional lower interconnection structure 1014: Additional interconnection through hole 1018: Additional upper interconnection structure 1302: First etching process 1304: Shield 1401: Lower electrode layer 1401s: Inner wall 1401u: Upper surface 1403: Data storage layer 1403s: Inner wall 1403u: Upper surface 1405: Upper electrode layer 1407: Memory cell stack 1502: Second etching process 1504: The Second Shield 1802: Third Etching Process 1804: Shield 1806: Groove 1902: The fourth etching process 1904: Shield 1906: Hole 2000: Process 2002,2004,2006,2008,2010,2012,2014,2016,2018:Process A-A': Line D1: Distance H1, H2: Height Mx, Mx-1: Metallized layer MX: Line W1:Width

Claims

1. Substrate and A lower dielectric structure located on the substrate, An interconnection structure located within the lower dielectric structure, An etching stop layer located on the lower dielectric structure, An interlayer dielectric layer located above the etching stop layer, One or more openings extending through the interlayer dielectric layer and the etching stop layer, A memory cell comprising a lower electrode, a data storage layer, and an upper electrode, wherein the upper electrode is provided on and within one or more openings, The upper electrode has a through-hole that is in direct contact with the upper electrode, Equipped with, An integrated chip wherein each of the lower electrode, the data storage layer, and the upper electrode extends into the one or more openings and is located on the interlayer dielectric layer adjacent to the one or more openings, the etching stop layer is thicker than the lower electrode, and the upper surface of the upper electrode has one or more recesses located on each of the one or more openings, and the bottom of the one or more recesses is located above the top of the data storage layer.

2. The integrated chip according to claim 1, wherein the one or more openings include at least three openings arranged in two dimensions.

3. The integrated chip according to claim 1, wherein the depth of the one or more openings is greater than or equal to the width of the one or more openings.

4. Substrate and A metal interconnection structure located on the substrate and including a first metallized layer, A dielectric structure located on the first metallized layer and including an etching stop layer and an interlayer dielectric layer located on top of it, Three or more openings extending through the dielectric structure, A memory cell comprising a lower electrode, a data storage layer, and an upper electrode, wherein the upper electrode is provided on the dielectric structure and in each of the three or more openings, The upper electrode has a through-hole that is in direct contact with the upper electrode, Equipped with, Each of the lower electrode, the data storage layer, and the upper electrode descends into the three or more openings and is located on the dielectric structure adjacent to the three or more openings, the etching stop layer is thicker than the lower electrode, the upper surface of the upper electrode has a recess located on one of the three or more openings, and the bottom of the recess is located above the top of the data storage layer. The three or more openings are arranged in a two-dimensional manner in the integrated chip.

5. The integrated chip according to claim 4, further comprising an island region formed of a dielectric material located only between a part of the bottom surface of the top electrode through hole and the upper electrode.

6. The integrated chip according to claim 4, wherein the top electrode through-hole is horizontally offset from each of the three or more openings.

7. The integrated chip according to claim 4, wherein the metal interconnect structure further comprises a second metallized layer on the top electrode through-hole, and the depth of the three or more openings is greater than or equal to the distance from the top of the three or more openings to the second metallized layer.

8. Forming a lower interconnection structure within a lower dielectric structure located on a substrate, Forming an etching stop layer on the lower dielectric structure, Forming an interlayer dielectric layer on the etching stop layer, Etching multiple openings so as to penetrate the interlayer dielectric layer and the etching stop layer, Forming a memory cell stack on the interlayer dielectric layer and within the plurality of openings, Etching the memory cell stack to define the memory cell, Forming multiple top electrode through-holes on the memory cell, Includes, The memory cell includes a lower electrode, a data storage layer located above the lower electrode, and an upper electrode located above the data storage layer, wherein the upper surface of the upper electrode has a plurality of recesses located above each of the plurality of openings, and the lowest part of each of the plurality of recesses is located above the highest part of the data storage layer. The upper electrode of the memory cell descends into each of the plurality of openings, and the etching stop layer is thicker than the lower electrode of the memory cell. A method for forming an integrated chip in which the memory cell portion extends from the plurality of openings to the interlayer dielectric layer.

9. The method for forming an integrated chip according to claim 8, wherein each of the top electrode through-holes is in contact with the upper electrode.

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