Fuse memory circuit and semiconductor device

Abstract

A first fuse unit 110 and a second fuse unit 120 have the same configuration. A rectifier element 112 is connected in parallel to the fuse element. The drain of a first transistor M11 is connected to a second terminal of the fuse element F11, the source thereof is connected to a second line 104, and the gate thereof is connected to a program terminal PROG1. The source of a second transistor M12 is connected to a second terminal of the fuse element F11, the drain thereof is connected to an output terminal OUT1, and the gate thereof is connected to a test terminal TEST1. The drain of the third transistor M13 is connected to the output terminal, and the source thereof is connected to the second line 104.

Description

[Technical Field]

[0001] This disclosure relates to a fuse memory circuit. [Background technology]

[0002] Trimming is a well-known technique for adjusting characteristics and modifying the configuration of various semiconductor devices after manufacturing. Trimming can be performed continuously (analog) or discretely (digitally), but in recent years, digital trimming, which is more cost-effective, has become preferred.

[0003] The cost advantages include the ease of using area-efficient digital circuits due to miniaturization, and the elimination of extra test flows such as laser trimming.

[0004] Furthermore, because the trimming value is fixed, the ability to switch functions and recover defective products by turning redundant circuits ON / OFF is another reason why digital trimming is preferred.

[0005] The following methods are known for digital cropping: • Non-volatile memory (EEPROM, Flash memory, FeRAM, MRAM, PRAM, etc.) • Fuses (polysilicon fuses, metal wire fuses) • Antifuse (Zener zapping, gate oxide breakdown)

[0006] Each method has its advantages and disadvantages, so the most suitable method is chosen according to the application. However, conventional trimming methods do not always meet all required design specifications, and may have to be used under certain limitations.

[0007] Challenges of non-volatile memory systems This requires the addition of costly processes. Furthermore, exposure of the memory elements themselves or the latch circuit to noise or radiation can cause soft errors, requiring countermeasures such as refresh or error correction circuits. For these reasons, it is unsuitable for analog ICs.

[0008] Furthermore, it may have limited environmental resistance, such as a short memory retention lifespan, low radiation resistance, and susceptibility to data loss due to heat.

[0009] In configurations requiring peripheral circuits such as flash memory, economies of scale are not realized if the memory capacity is small. In other words, it is not suitable for trimming by a few bits to tens of bits.

[0010] Furthermore, because initialization and reading operations are required, it cannot be used in applications where values ​​need to be determined immediately after power-on.

[0011] Therefore, fuse memory circuits using fuses or antifuses (hereinafter collectively referred to as fuse elements) are used in the following applications. • Analog or mixed-signal ICs (Integrated Circuits) without reset / enable functions. • Products requiring fault repair through redundant circuits • Applications where functions are switched on the same die for product development. • Applications that allow for programmable modification of power-on conditions, such as the release voltage of the POR (Power On Reset) circuit or the startup sequence between different power supplies. [Prior art documents] [Patent Documents]

[0012] [Patent Document 1] Japanese Patent Publication No. 2005-85980 [Overview of the project] [Problems that the invention aims to solve]

[0013] The fuse memory circuit is required to have the following characteristics. · No preliminary operation is required. No read operation / initialization operation is required. (= No Power-On reset) · High noise tolerance That is, when data corruption (soft error) occurs due to external interference, it is required to be able to automatically return to the correct state. · Low steady-state current: It is desirable that the steady-state current be reduced substantially to zero (only leakage current) regardless of whether the fuse is cut or not. · Low cost For this purpose, it is desirable to have a small area, a small number of pins, a low test cost, and a small number of layers. · Wide operating voltage range Specifically, it is desirable to be able to operate within an operating voltage range with sufficient margin for the entire operating voltage range of the circuit to be controlled other than the fuse memory circuit. · High portability That is, it is desirable that no peripheral circuits for complex control and testing are required. · Testability It is desirable to be able to perform virtual trimming before programming and fault detection before and after programming. · High reliability Specifically, it is desirable to have semi-permanent data retention characteristics, high environmental resistance characteristics (heat, radiation), and high electrostatic breakdown resistance.

[0014] This disclosure has been made in this context, and one of the exemplary purposes of one of its aspects is to provide a fuse memory circuit that simultaneously satisfies some of the plurality of characteristics required for a fuse memory circuit.

Means for Solving the Problem

[0015] A fuse memory circuit in one aspect of the present disclosure includes a first line which is one of a power line and a ground line, a second line which is the other of a power line and a ground line, a first fuse unit, and a second fuse unit. The first fuse unit and the second fuse unit each include a test terminal, a program terminal, an output terminal, a fuse element whose first end is connected to the first line, a rectifier element connected in parallel with the fuse element, a first transistor whose drain is connected to the second end of the fuse element, whose source is connected to the second line, and whose gate is connected to the program terminal, a second transistor whose source is connected to the second end of the fuse element, whose drain is connected to the output terminal, and whose gate is connected to the test terminal, and a third transistor whose drain is connected to the output terminal, and whose source is connected to the second line. The gate of the third transistor of the first fuse unit is connected to the output terminal of the second fuse unit, and the gate of the third transistor of the second fuse unit is connected to the output terminal of the first fuse unit.

[0016] Furthermore, any combination of the above components, or conversion of the expressions of this disclosure between methods, apparatus, etc., are also valid embodiments of the present invention. [Effects of the Invention]

[0017] According to one aspect of this disclosure, it is possible to simultaneously satisfy several of the multiple characteristics required for a fuse memory circuit. [Brief explanation of the drawing]

[0018] [Figure 1] Figure 1 is a circuit diagram of a fuse memory circuit according to Example 1. [Figure 2] Figure 2 shows the output waveform of the fuse memory circuit in Figure 1 when the power is turned on after programming. [Figure 3] Figure 3 illustrates the soft error correction of the fuse memory circuit shown in Figure 1. [Figure 4]Figure 4 is an equivalent circuit diagram of the fuse memory circuit during electrostatic testing. [Figure 5] Figure 5 is an equivalent circuit diagram of the fuse memory circuit during electrostatic testing. [Figure 6] Figure 6 is a circuit diagram of the fuse memory circuit according to Example 2. [Figure 7] Figure 7 is a circuit diagram of the fuse memory circuit according to Example 3. [Figure 8] Figure 8 is a circuit diagram of the fuse memory circuit according to Example 4. [Figure 9] Figure 9 is a circuit diagram of a semiconductor device equipped with a fuse memory circuit. [Figure 10] Figure 10 is a circuit diagram showing an example of an output buffer configuration. [Figure 11] Figure 11 is a circuit diagram showing an example of a lock circuit configuration. [Figure 12] Figure 12 is a circuit diagram showing another example of a lock circuit configuration. [Figure 13] Figure 13 is a block diagram showing an example of a semiconductor device configuration. [Figure 14] Figure 14 is a block diagram showing an example of a semiconductor device. [Figure 15] Figure 15 shows another example of a semiconductor device. [Figure 16] Figure 16 shows another example of a semiconductor device. [Modes for carrying out the invention]

[0019] (Summary of the embodiment) This section outlines some exemplary embodiments of the present disclosure. This outline is intended to provide a basic understanding of the embodiments and to simplify some concepts of one or more embodiments, serving as a prelude to the more detailed descriptions that follow later, and is not intended to limit the scope of the invention or disclosure. This outline is not a comprehensive overview of all possible embodiments, nor is it intended to identify any or all essential elements of all embodiments, nor to delineate the scope of some or all embodiments. For convenience, “one embodiment” may be used to refer to one embodiment (example or variation) or more embodiments (example or variation) disclosed herein.

[0020] A fuse memory circuit according to one embodiment includes a first line which is one of a power line and a ground line, a second line which is the other of a power line and a ground line, a first fuse unit, and a second fuse unit. The first fuse unit and the second fuse unit each include a test terminal, a program terminal, an output terminal, a fuse element whose first end is connected to the first line, a rectifier element connected in parallel with the fuse element, a first transistor whose drain is connected to the second end of the fuse element, whose source is connected to the second line, and whose gate is connected to the program terminal, a second transistor whose source is connected to the second end of the fuse element, whose drain is connected to the output terminal, and whose gate is connected to the test terminal, and a third transistor whose drain is connected to the output terminal, and whose source is connected to the second line. The gate of the third transistor of the first fuse unit is connected to the output terminal of the second fuse unit, and the gate of the third transistor of the second fuse unit is connected to the output terminal of the first fuse unit.

[0021] This fuse memory circuit employs a configuration that uses two fuse units with identical configurations to perform complementary writing. The third transistor of the first fuse unit and the third transistor of the second fuse unit are cross-coupled, allowing the two third transistors to latch data. Furthermore, even if the data (state) of one of the first or second fuse units is temporarily reversed (data corruption), the undisconnected fuse element and the cross-coupled third transistor pair guarantee that it will return to the correct state.

[0022] Furthermore, the rectifier element prevents current from flowing from the back gate of the first transistor into the fuse element during electrostatic testing where a reverse bias is applied to the power line and ground line, thereby protecting the fuse element.

[0023] In one embodiment, both the second transistors of the first and second fuse units may be turned on before programming (when the fuse is not blown). In this case, current flows through all elements of both the first and second fuse units. By measuring the circuit current at this time, a structural defect can be determined.

[0024] In one embodiment, before programming, the second transistor of one of the first and second fuse units may be turned on, and the second transistor of the other may be turned off. This allows testing whether the output value changes normally without actually programming the fuse element, or allows supplying an arbitrary output to the circuit to be trimmed. Furthermore, by measuring the current in this state, the leakage current (also called quiescent current Iddq) can be evaluated.

[0025] In one embodiment, the rectifier element may include a fourth transistor whose source is connected to the first terminal of the fuse element and whose drain is connected to the second terminal of the fuse element. The body diode of a MOSFET can be used as the rectifier element.

[0026] In one embodiment, the gate of the fourth transistor may be connected to the gate of the third transistor. As a result, the third and fourth transistors form a CMOS inverter, and the CMOS inverters of the first fuse unit and the second fuse unit are cross-coupled. This increases the gain of the latch circuit, enabling correct state determination even when the on / off ratio of the fuse element is small. Additionally, since the amplification speed increases, the noise tolerance is improved.

[0027] In one embodiment, the threshold voltage of the CMOS inverter circuit formed by the third and fourth transistors is V , ,

[0028] , ,

[0030] , ,

[0029] , , ,

[0031] , , , the resistance value of the fuse element before disconnection is R FUSE , the power supply voltage is V DD , the on-resistance of the second transistor is R M12 , the on-resistance of the third transistor is R M13 When this is the case, V DD ×R M13 / (R FUSE +R M12 +R M13 )>V TINV may be satisfied. This enables automatic recovery to the correct state when the state of the fuse memory circuit transitions to a different state than the programmed state due to noise.

[0028] In one embodiment, the first line may be a power supply line and the second line may be a ground line.

[0029] In one embodiment, the first line may be a ground line and the second line may be a power supply line.

[0030] In one embodiment, the fuse element may be a fuse that becomes electrically disconnected when current flows through it. In one embodiment, the fuse element may be an anti-fuse that becomes electrically conductive when current flows through it.

[0031] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing will be denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Furthermore, the embodiments are illustrative and not limiting to the disclosure and invention, and not all features or combinations thereof described in the embodiments are necessarily essential to the disclosure and invention.

[0032] In this specification, "member A connected to member B" includes not only cases where member A and member B are directly connected physically, but also cases where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection or impair the functions or effects produced by their combination.

[0033] Similarly, "the state in which member C is connected (provided) between member A and member B" includes not only cases where member A and member C, or member B and member C, are directly connected, but also cases where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the function or effect produced by their combination.

[0034] (Example 1) Figure 1 is a circuit diagram of the fuse memory circuit 100A according to Embodiment 1. The fuse memory circuit 100A functions as a 1-bit non-volatile memory element capable of holding a binary state.

[0035] The fuse memory circuit 100A includes a first line 102, a second line 104, a first fuse unit 110, and a second fuse unit 120.

[0036] The first line 102 is either the power line VDD or the ground line GND, and the second line 104 is either the power line VDD or the ground line GND. In this embodiment, the first line 102 is the power line VDD, and the second line 104 is the ground line GND.

[0037] The first fuse unit 110 and the second fuse unit 120 are connected between the first line 102 and the second line 104 and are configured similarly.

[0038] The first fuse unit 110 includes a test terminal TEST1, a program terminal PROG1, an output terminal OUT1, a fuse element F11, a rectifier element 112, a first transistor M11, a second transistor M12, and a third transistor M13.

[0039] The first terminal of fuse element F11 is connected to the first line 102 (power line VDD). However, in the following description, it is assumed that fuse element F11 is electrically conductive before current flows and becomes a fuse that trips when a specified current flows.

[0040] The rectifier element 112 is connected in parallel with the fuse element F11. The orientation of the rectifier element 112 is such that it conducts from the ground line GND towards the power line VDD. In this embodiment, the rectifier element 112 includes a P-channel fourth transistor M14. The source of the fourth transistor M14 is connected to the first terminal of the fuse element F11 (i.e., the first line 102), and its drain is connected to the second terminal of the fuse element F11. In other words, the body diode of the fourth transistor M14, which is a MOSFET, is used as the rectifier element.

[0041] The first transistor M11 is a programming transistor. The first transistor M11 is an NMOS transistor, its drain is connected to the second terminal of the fuse element F11, and its source is connected to the second line 104 (ground line GND). The gate of the first transistor M11 is connected to the programming terminal PROG1.

[0042] The second transistor M12 is provided for testing the fuse memory circuit 100A. The second transistor M12 is a PMOS transistor, its source connected to the second terminal of the fuse element F11 and the drain of the first transistor M11, and its gate connected to the test terminal TEST1.

[0043] The third transistor M13 is a latching transistor. The third transistor M13 is an NMOS transistor, with its drain connected to the output terminal OUT1 and its source connected to the second line 104 (ground line GND).

[0044] The above describes the configuration of the first fuse unit 110. The second fuse unit 120 is configured similarly to the first fuse unit 110. Specifically, the second fuse unit 120 includes a test terminal TEST2, a program terminal PROG2, an output terminal OUT2, a fuse element F21, a rectifier element 122, a first transistor M21, a second transistor M22, and a third transistor M23.

[0045] The gate of the third transistor M13 of the first fuse unit 110 is connected to the output terminal OUT2 of the second fuse unit 120. The gate of the third transistor M23 of the second fuse unit 120 is connected to the output terminal OUT1 of the first fuse unit 110.

[0046] The third transistor M13 and the fourth transistor M14 of the first fuse unit 110 constitute a CMOS inverter circuit 114. Similarly, the third transistor M23 and the fourth transistor M24 of the second fuse unit 120 also constitute a CMOS inverter circuit 124. These two CMOS inverter circuits 114 and 124 are cross-coupled and function as latch circuits. Note that the fourth transistor M14 (M24) may be biased to be off, in which case the configuration is equivalent to that in Figure 6.

[0047] The two outputs OUT1 and OUT2 of the fuse memory circuit 100A are supplied to the circuit to be trimmed (not shown). Note that when the fuse memory circuit 100A is functioning correctly, the two outputs OUT1 and OUT2 take mutually exclusive values, so the circuit to be trimmed may refer to only one of the two outputs.

[0048] The above describes the configuration of the fuse memory circuit 100A. Next, its operation will be explained. Note that it is not necessary to perform all of the tests described below on the fuse memory circuit 100A; some of them may be performed.

[0049] 1. First Examination The first test before programming (writing) is described below. In the first test, a low signal is applied to the test terminals TEST1 and TEST2 of the first fuse unit 110 and the second fuse unit 120, respectively, and the second transistors M12 and M22 are turned on.

[0050] In the first fuse unit 110, current is supplied from the power line VDD via the fuse element F11 to the second transistor M12 and the third transistor M13. In the second fuse unit 120, current is supplied from the power line VDD via the fuse element F21 to the second transistor M22 and the third transistor M23. As a result, the outputs OUT1 and OUT2 of the first fuse unit 110 and the second fuse unit 120 are balanced to an intermediate potential.

[0051] When an intermediate potential appears at output OUT1, current will flow through the fourth transistor M24 of the second fuse unit 120. When an intermediate potential appears at output OUT2, current will flow through the fourth transistor M14 of the first fuse unit 110.

[0052] In this state, by measuring the current Ion flowing through the fuse memory circuit 100A, it is possible to test the overall characteristics considering all transistors except the fuse element F11 (F21) and the first transistor M11 (M21), and to detect structural defects. The first test is also called the Ion test.

[0053] 2. Second Examination The second test, performed before programming (writing), is described below. In the second test, the second transistor M12 of the first fuse unit 110 and the second transistor M22 of the second fuse unit 120 are turned on exclusively, one at a time.

[0054] If the first fuse unit 110 and the second fuse unit 120 are functioning correctly, when TEST1=H and TEST2=L, the second transistor M12 turns off and the second transistor M22 turns on. This causes the output OUT1 of the first fuse unit 110 to become L. When output OUT1 becomes L, the output OUT2 of the CMOS inverter circuit 124 on the second fuse unit 120 side becomes H, which is input to the CMOS inverter circuit 114 of the first fuse unit 110, causing it to latch.

[0055] If the first fuse unit 110 and the second fuse unit 120 are functioning correctly, when TEST1=L and TEST2=H, the second transistor M22 turns off and the second transistor M12 turns on. This causes the output OUT2 of the second fuse unit 120 to become L. When output OUT2 becomes L, the output OUT1 of the CMOS inverter circuit 114 on the first fuse unit 110 side becomes H, which is input to the CMOS inverter circuit 124 of the second fuse unit 120, causing a latch to engage.

[0056] These actions are similar to those that occur when either fuse element F11 or F12 is disconnected. This fault detection test allows for the detection of abnormalities in elements other than the first transistors M11 and M21.

[0057] Since all current paths from the power line to the ground line are interrupted, the quiescent current (leakage current Iddq) can be evaluated by measuring the circuit current at this time.

[0058] 3. Virtual trimming Generally, the outputs OUT1 and OUT2 of the fuse memory circuit 100 are referenced by the circuit to be trimmed (not shown), and the operating state (operating mode, operating parameters, and circuit constants) of the circuit to be trimmed is set according to the outputs OUT1 and OUT2. Virtual trimming is a function that provides arbitrary outputs OUT1 and OUT2 from the fuse memory circuit 100A to the circuit to be trimmed before actually programming the fuse memory circuit 100.

[0059] The operation of virtual trimming is the same as in the fault detection test described above. That is, if you want to generate OUT1=L and OUT2=H, you should set TEST1=H and TEST2=L. Conversely, if you want to generate OUT1=H and OUT2=L, you should set TEST1=L and TEST2=H.

[0060] 4. Program (i) To program the system to be in the state of OUT1=H and OUT2=L, input PROG1=H and PROG2=L. When PROG1=H, the first transistor M11 of the first fuse unit 110 turns on, current flows to the fuse element F11, and the fuse element F11 is disconnected.

[0061] (ii) To program the system to be in the state of OUT1=L and OUT2=H, input PROG1=L and PROG2=H. When PROG2=H, the first transistor M21 of the second fuse unit 120 turns on, current flows to the fuse element F21, and the fuse element F21 is disconnected.

[0062] When programming, it is best to turn off the second transistors (M12, M22) on the fuse unit side containing the fuse element to be disconnected, and turn on the second transistor on the other fuse unit side.

[0063] Specifically, if you want to program the system to be in the state of OUT1=H and OUT2=L, you should set TEST1=H and TEST2=L, turning off the second transistor M12 and turning on the second transistor M22. In this case, due to the same operation as the virtual trimming described above, OUT1=L and OUT2=H will occur, and as a result, the fourth transistor M14, which is in parallel with the fuse element F11 that you want to disconnect, will be turned off. Therefore, the current flowing through the first transistor M11 can be concentrated on the fuse element F11.

[0064] Conversely, if you want to program the system to be in the state of OUT1=L and OUT2=H, you should set TEST1=L and TEST2=H, turning on the second transistor M12 and turning off the second transistor M22. In this case, due to the same operation as the virtual trimming described above, OUT1=H and OUT2=L will occur, and as a result, the fourth transistor M24, which is in parallel with the fuse element F21 that you want to disconnect, will be turned off. Therefore, the current flowing through the first transistor M21 can be concentrated on the fuse element F21.

[0065] 5. After the program Once the program has finished, all inputs PROG1, PROG2, TEST1, and TEST2 to the fuse memory circuit 100A are fixed to L. By fixing PROG1 and PROG2 to L, the first transistors M11 and M12 are fixed to OFF, which prevents one of the fuse elements F11 and F12 that is not disconnected from being accidentally disconnected.

[0066] Furthermore, by fixing TEST1 and TEST2 to L, the second transistors M12 and M22 are fixed to ON. After programming to disconnect the fuse element F11 on the first fuse unit 110 side, the fuse element F21 of the second fuse unit 120 and the second transistor M22 cause output OUT2 to the power supply voltage V DD When pulled up, a high (H) appears in output OUT2, and a low (L) appears in output OUT1.

[0067] Conversely, after programming to disconnect fuse element F21 on the second fuse unit 120 side, output OUT1 is switched to the power supply voltage V by fuse element F11 of the first fuse unit 110 and second transistor M12. DD When pulled up, output OUT1 becomes high and output OUT2 becomes low.

[0068] Figure 2 shows the output waveform of the fuse memory circuit 100A shown in Figure 1 when the power is turned on after programming. TH This is the threshold voltage of the transistor.

[0069] This fuse memory circuit 100A can operate from very low voltages because all transistors operate in two states: on and off. This wide-range operation allows the circuit to be trimmed to reference the correct value of the fuse memory circuit 100A immediately after power-on.

[0070] 6. Soft error correction Figure 3 illustrates the soft error correction of the fuse memory circuit 100A shown in Figure 1. This fuse memory circuit 100A is programmed so that OUT1=H and OUT2=L, and Figure 3 shows the equivalent circuit diagram at that time. In this state, suppose noise occurs at output OUT1 or OUT2, and its potential is reversed.

[0071] Focus on the potential of output OUT1. When output OUT2 becomes high due to noise, the third transistor M13 changes from off to on. The resistance value of the now-on third transistor M13 is R. M13 Let's assume that the resistance value of fuse element F11 is R FUSE The resistance value of the second transistor M12 is R M12 The voltage level of output OUT1 is V. N teeth, V N =V DD ×R M13 / (R FUSE +R M12 +R M13 ) It converges to V. Therefore, V N However, the threshold voltage V of the CMOS inverter circuit 124 TINV To make it higher, the resistance value R of the third transistor M13 M13 By designing the MOSFET's W / L ratio (i.e., the output error will automatically return to a normal value).

[0072] 7. Measures against electrostatic discharge After shipping a semiconductor device equipped with a programmed fuse memory circuit 100A, it is necessary to prevent damage to the fuse element on the un-extended side.

[0073] Figure 4 is an equivalent circuit diagram of the fuse memory circuit 100A during electrostatic discharge testing. Figure 4 shows the electrostatic discharge test applied to the power line VDD and the ground line GND in a reverse bias state. In other words, the power line VDD is grounded (VDD common), and electrostatic discharge is applied to the ground line GND.

[0074] This section describes the first fuse unit 110, but the same applies to the second fuse unit 120. When VDD is common and reverse biased, the current flowing through the body diode Db1 between the back gate and drain of the first transistor M11 becomes a problem.

[0075] In the first fuse unit 110A, this current is diverted to the body diode Db4 between the drain and back gate of the fourth transistor M14, which functions as a rectifier element 112, thus preventing the fuse element F11 from being unintentionally disconnected. This current can also flow through the body diode Db2 between the source and back gate of the second transistor M12, suppressing the flow of current to the fuse element F11.

[0076] Figure 5 is an equivalent circuit diagram of the fuse memory circuit 100A during an electrostatic discharge test. Figure 5 shows an electrostatic discharge test applied to the power line VDD and the ground line GND in a forward bias state. That is, the ground line GND side is grounded (GND common), and electrostatic discharge is applied to the power line VDD side. In a forward bias of GND common, the electrostatic discharge energy needs to be released from the power pin or ground pin before the first transistor M11 breaks down. In the fuse memory circuit 100A after programming, where the fuse element F21 is disconnected, the fourth transistor M14 is already ON at the stage when the first transistor M11 begins to break down. Therefore, current flows through the source-drain (channel) of the fourth transistor M14 instead of the fuse element F11, protecting the fuse element F11.

[0077] The above describes the operation of the fuse memory circuit 100A. This fuse memory circuit 100A has the following characteristics.

[0078] This fuse memory circuit 100A generates output based on the program without any preparatory operations after power-on. Therefore, reading and initialization operations are unnecessary.

[0079] Furthermore, as mentioned above, it can automatically recover from data corruption (soft errors) caused by external noise, thus demonstrating high noise immunity.

[0080] Furthermore, regardless of whether the fuse is blown or not, the steady-state current is virtually zero (only leakage current), thus offering the advantage of low steady-state current.

[0081] Furthermore, the 100A fuse memory circuit is cost-effective because it can be constructed with a small area, few pins, low test costs, and few layers.

[0082] In addition, since all transistors in the fuse memory circuit 100A operate in two states, on and off, they can operate from very low voltages, and specifically, they can operate within an operating voltage range that has a sufficient margin over the entire operating voltage range of the controlled circuit.

[0083] Furthermore, as mentioned above, the fuse memory circuit 100A is superior in terms of testability because it allows for virtual trimming before programming and fault detection before and after programming.

[0084] Furthermore, it eliminates the need for complex control and testing peripheral circuits. This point will be discussed later.

[0085] Furthermore, as explained above with reference to Figures 4 and 5, it can be said that it has high static discharge resistance and high reliability even in tests in which electrostatic discharge is applied.

[0086] (Example 2) Figure 6 is a circuit diagram of the fuse memory circuit 100B according to Embodiment 2. This fuse memory circuit 100B replaces the fourth transistor M14 (M24) with a diode D11 (D21). Diode D11 is connected with the high-potential (power line VDD) side as the cathode and the low-potential (ground line GND) side as the anode. The other configurations are the same as in Figure 1.

[0087] The operation of the fuse memory circuit 100B is the same as that of the fuse memory circuit 100A, although the logic levels (H / L) of the signals applied to each terminal PROG1, PROG2, TEST1, and TEST are different in Example 1.

[0088] Furthermore, in Figure 1, the third transistor M13 and the fourth transistor M14 on the first fuse unit 110 side form a CMOS inverter circuit 114, and the third transistor M23 and the fourth transistor M24 on the second fuse unit 120 side form a CMOS inverter circuit 124, with the two CMOS inverter circuits 114 and 124 cross-coupled to form a latch circuit. In contrast, in Figure 6, the latch circuit is formed by the cross-coupled third transistors M13 and M23. Therefore, the gain of the latch circuit is smaller than that of the fuse memory circuit 100A in Figure 1. In other words, compared to Example 2, Example 1 can correctly determine the state even when the on / off ratio of the fuse element is small, and because the amplification speed is high, it can be said to have high noise immunity.

[0089] (Example 3) Figure 7 is a circuit diagram of the fuse memory circuit 100C according to Embodiment 3. This fuse memory circuit 100C has a configuration in which the fuse memory circuit 100A of Figure 1 is inverted vertically and the P channel and N channel are swapped.

[0090] Specifically, in Example 3, the ground line GND becomes the first line 102, and the power line VDD becomes the second line 104.

[0091] This configuration also provides the same effect as the fuse memory circuit 100A in Figure 1.

[0092] (Example 4) Figure 8 is a circuit diagram of the fuse memory circuit 100D according to Embodiment 4. This fuse memory circuit 100D is obtained by replacing the fourth transistors M14 and M24 of the fuse memory circuit 100C in Figure 7 with diodes D11 and D21.

[0093] This configuration also provides the same effect as the fuse memory circuit 100A in Figure 1.

[0094] Next, we will explain the peripheral circuits of the fuse memory circuits 100A to 100D (hereinafter collectively referred to as fuse memory circuit 100).

[0095] (Peripheral circuits) Figure 9 is a circuit diagram of a semiconductor device 300 equipped with a fuse memory circuit 100. The semiconductor device 300 includes a bit circuit 200 and an internal circuit 310. In addition to the fuse memory circuit 100, the bit circuit 200 includes a control circuit 210 and an output buffer 220. The output buffer 220 receives outputs OUT1 and OUT2 from the fuse memory circuit 100. The internal circuit 310 to be trimmed refers to outputs DO and DOB from the output buffer 220. The B at the end of each signal indicates inverted logic.

[0096] Multiple control signals (LOCK signal, WEN write enable signal, WTD write data signal, and TIONB signal) are input to the control circuit 210.

[0097] The LOCK signal is negated (e.g., L) before programming and asserted (e.g., H) after programming.

[0098] The write enable signal WEN is primarily asserted (e.g., high) when programming the fuse memory circuit 100.

[0099] The write data WTD is data that specifies the value to be programmed, or the state of the fuse memory circuit 100 during virtual trimming or fault detection.

[0100] The TIONB signal is asserted (low, as the 'B' at the end represents negative logic) when the first test is performed.

[0101] The outputs OUT1 and OUT2 of the fuse memory circuit 100 are supplied to the internal circuit 310 via the output buffer 220. The internal circuit 310's state is trimmed (set) based on the outputs DO and DOB of the output buffer 220.

[0102] As described above, during the first test, the outputs OUT1 and OUT2 of the fuse memory circuit 100 are balanced to an intermediate potential. If the output buffer 220 is operated in this state, a shoot-through current will flow through the output buffer 220. It is preferable that the output buffer 220 be configured with an enable function, and by disabling the output buffer 220 during the first test, it is possible to prevent a shoot-through current from flowing through the output buffer 220.

[0103] The control circuit 210 generates control signals (PROG1, PROG2, TEST1, TEST2) for the fuse memory circuit 100 and an enable signal EN for the output buffer 220 based on the control signals LOCK, WEN, WTD, and TIONB.

[0104] Regarding the control signals TEST1, TEST2, PROG1, PROG2, and EN, the level at which the transistor receiving each signal turns on is called the on-level, and the level at which it turns off is called the off-level.

[0105] For example, with respect to the control signal TEST1, if the second transistor M12 is a PMOS transistor, the on-level is L and the off-level is H, and if the second transistor M12 is an NMOS transistor, the on-level is H and the off-level is L.

[0106] After the program ends, when the LOCK signal is asserted (H), the control circuit 210 turns on the control signals TEST1 and TEST2, fixing the second transistors M12 and M22 in the ON state. Also, when the LOCK signal is asserted (H), the control circuit 210 turns off the control signals PROG1 and PROG2, fixing the first transistors M11 and M21 in the OFF state.

[0107] Before programming, when the LOCK signal is negated (L), the control circuit 210 changes the control signals TEST1, TEST2, PROG1, and PROG2 according to the WEN signal, WTD signal, and TIONB signal.

[0108] Specifically, the control circuit 210 enters the first test mode when the WTD signal is high, the WEN signal is negated (low), and the TIONB signal is asserted (low). In this mode, both control signals TEST1 and TEST2 are turned on, and the second transistors M12 and M22 are turned on.

[0109] Furthermore, when the WEN signal is negated (L) and the TIONB signal is negated (H), the control circuit 210 sets the outputs OUT1 and OUT2 of the fuse memory circuit 100 according to the WTD signal, and enters virtual trimming or fault detection mode.

[0110] Furthermore, when the WEN signal is asserted (H), the control circuit 210 sets one of the PROG1 and PROG2 signals, corresponding to the WTD signal, to the ON level and the other to the OFF level, and writes this information to the fuse memory circuit 100.

[0111] The control circuit 210 shown in Figure 9 is assumed to be either the fuse memory circuit 100A in Figure 1 or the fuse memory circuit 100B in Figure 6. The control circuit 210 can be constructed as a combinational circuit. However, the control circuit 210 includes four NOR gates NOR1 to NOR4, inverters INV1 and INV2, and a NAND gate NAND1.

[0112] Inverter INV1 inverts the WEN signal. NOR gate NOR1 takes the negated OR of the LOCK signal, the output of inverter INV1, and the WTD signal, and outputs the PROG1 signal.

[0113] The NOR gate NOR2 takes the negated OR of the LOCK signal and the WTD signal and outputs the TEST1 signal.

[0114] NAND gate NAND1 generates a negative logical AND of the WTD signal and the TIONB signal. NOR gate NOR3 takes the negative logical OR of the LOCK signal and the output of NAND gate NAND1 and outputs the TEST2 signal. NOR gate NOR4 takes the negative logical OR of the LOCK signal, the output of inverter INV1, and the output of NAND gate NAND1 and outputs the PROG2 signal.

[0115] Inverter INV2 inverts the TIONB signal and generates the enable signal EN for output buffer 220. Output buffer 220 is disabled when the TIONB signal is asserted (low), i.e., during the first test, and enabled when the TIONB signal is negated (high), i.e., during any other test.

[0116] Furthermore, the configuration of the control circuit 210 is not limited to that shown in Figure 9. Those skilled in the art can design a control circuit capable of providing appropriate control signals to each of the fuse memory circuits 100A to 100D.

[0117] Figure 10 is a circuit diagram showing an example configuration of the output buffer 220. The output buffer 220 is a cross-coupled type and includes PMOS transistors MP11 to MP15 and NMOS transistors MN11 to MN12. An inverting logic enable signal ENB is input to the gate of PMOS transistor MP15. When the enable signal ENB is asserted (L), the output buffer 220 is enabled, and when the enable signal ENB is negated (H), the output buffer 220 is disabled. During the first test, when the input terminals DIN and DINB of the output buffer 220 are at an intermediate voltage, negating the enable signal ENB prevents shoot-through current from the output buffer 220.

[0118] Furthermore, by using a cross-coupled configuration, the output buffer 220 gains hysteresis, which improves noise immunity.

[0119] Figure 11 is a circuit diagram showing an example configuration of the lock circuit 230. The lock circuit 230 is integrated into the semiconductor device 300 together with the fuse memory circuit 100 and the bit circuit 200.

[0120] The lock circuit 230 generates a lock signal LOCK. The lock circuit 230 includes a fuse memory circuit 100E and an output buffer 232. The fuse memory circuit 100E can be configured similarly to the fuse memory circuits 100A (or 100B~100D) in Figure 1.

[0121] In the fuse memory circuit 100E, the nodes corresponding to the test terminals TEST1 and TEST2 in Figure 1 are grounded, and the second transistors M12 and M22 are fixed to ON. Also, the node corresponding to the program terminal PROG1 in Figure 1 is grounded, and the first transistor M11 is fixed to OFF. The node corresponding to the program terminal PROG2 in Figure 1 receives the lock enable signal LOCKEN. The lock enable signal LOCKEN is asserted (H) when the programming of the bit circuit 200 is complete.

[0122] The output buffer 232 receives the outputs OUT1 and OUT2 from the first fuse unit 110E and outputs them as a lock signal LOCK. The output buffer 232 may have the same configuration as the output buffer 220 in Figure 10. In this case, the enable terminal EN in Figure 10 may be grounded to fix transistor MP15 in the ON position. Alternatively, transistor MP15 may be omitted.

[0123] Before programming the fuse memory circuit 100E, both fuse elements F11 and F12 of the first fuse unit 110E are conducting. Therefore, the two outputs OUT1 and OUT2 are at an intermediate potential. At this time, both outputs (OUT and OUTB) of the subsequent output buffer 232 are low. Therefore, the lock signal LOCK is low.

[0124] The manufacturer of the semiconductor device 300 asserts the lock enable signal LOCKEN once the programming of the bit circuit 200 is complete. This disconnects the fuse element F12 of the fuse memory circuit 100E. As a result, the fuse memory circuit 100E outputs OUT1=H and OUT2=L. The lock signal LOCK, which is the output of the output buffer 232, is asserted (H).

[0125] In the lock circuit 230 shown in Figure 11, the steady-state current becomes zero after the fuse element F12 is disconnected (after programming), but a steady-state current flows before programming. Therefore, if the first test (Ion test) of the semiconductor device 300 is performed before programming the semiconductor device 300, the steady-state current of the lock circuit 230 will be included as an error.

[0126] Figure 12 is a circuit diagram showing another configuration example of the lock circuit 230. In Figure 12, the fuse memory circuit 100F includes two CMOS switches SW11 and SW21. CMOS switch SW11 is fixed in the ON state. CMOS switch SW22 can be switched ON or OFF according to the control signal swcnt. When performing the first test, the fuse memory circuit 100F can be interrupted by turning off CMOS switch SW22.

[0127] The control circuit 234 generates the lock enable signal LOCKEN and control signals SW and SWB based on the mode signal MODE. The mode signal MODE is a flag indicating whether the program is before or after completion. The configuration of the control circuit 234 is not particularly limited. The inverted lock enable signal lockenb is an internal signal based on at least the MODE signal. The control circuit 234 includes a NAND gate NAND31, which outputs the negated logical AND of the inverted lock enable signal lockenb and the inverted lock signal lockb as the lock enable signal LOCKEN. After the lock signal lock becomes high, the LOCKEN signal is fixed at high. Also, the NAND gate NAND32 fixes the TIONB signal to high after the lock signal lock becomes high.

[0128] Figure 13 is a block diagram showing an example configuration of the semiconductor device 300. The semiconductor device 300 includes a number of bit circuits 200_1, 200_2 (two in this example) and an internal circuit 310, in addition to a lock circuit 230. The bit circuits 200_1, 200_2 and the lock circuit 230 are referred to as the fuse circuit 400.

[0129] Finally, I will describe some specific examples of semiconductor device 300.

[0130] Figure 14 is a block diagram showing an example of a semiconductor device 300 (300A). The internal circuit 310A is a digital circuit and includes static random access memory (SRAM) 312, 314, a selector 316, and a microprocessor 318. The two SRAMs 312 and 314 are provided for redundancy, and one of them is selected by the selector 316.

[0131] The fuse circuit 400 is controllable via the control register 402, and the fuse circuit 400 is programmable with the control information of the selector 316. The microprocessor 318 can access one of the two SRAMs 312 and 314, depending on the value written to the fuse circuit 400. With this configuration, if an abnormality is detected in one of the two SRAMs 312 and 314 during the inspection process of the semiconductor device 300A, the yield can be improved by selecting the other normal SRAM.

[0132] Figure 15 shows another example (300B) of the semiconductor device 300. The internal circuit 310B includes a linear regulator (LDO: Low Drop Output) 320. The linear regulator 320 comprises a transistor 322, an operational amplifier 324, a reference voltage source 326, and resistors R41 and R42.

[0133] In this example, resistor R42 is a variable resistor, and the fuse circuit 400 is programmed with the set value of the variable resistor. This controls the output voltage V of the linear regulator 320.OUT The target value can be adjusted.

[0134] Figure 16 shows another example (300C) of the semiconductor device 300. The internal circuit 310C includes an interface circuit 330. The interface circuit 330 includes an input buffer 332, a pull-down resistor 336, and a switch 334. The fuse circuit 400 is programmed with the on / off setting of the switch 334. This allows switching between buffered and pull-down input pins for the semiconductor device 300C.

[0135] Those skilled in the art will understand that the embodiments are illustrative, and that various modifications exist for each component and combination of processing steps, and that such modifications are also included in this disclosure and may constitute the scope of the present invention.

[0136] (Note) One aspect of this disclosure can be understood as follows:

[0137] (Item 1) The first line is one of the power line and the ground line, The second line is the other of the aforementioned power line and the aforementioned ground line, First fuse unit and The second fuse unit, Equipped with, The first fuse unit and the second fuse unit are, Test terminals and Program terminal and Output terminals, Its first end is connected to the first line, and it is a fuse element, A rectifier element connected in parallel with the fuse element, The drain of the first transistor is connected to the second terminal of the fuse element, its source is connected to the second line, and its gate is connected to the program terminal. A second transistor whose source is connected to the second terminal of the fuse element, whose drain is connected to the output terminal, and whose gate is connected to the test terminal, The drain of the third transistor is connected to the output terminal, and its source is connected to the second line. Includes, The gate of the third transistor of the first fuse unit is connected to the output terminal of the second fuse unit. A fuse memory circuit in which the gate of the third transistor of the second fuse unit is connected to the output terminal of the first fuse unit.

[0138] (Item 2) The rectifier element is, The fuse memory circuit according to item 1, comprising a fourth transistor whose source is connected to the first terminal of the fuse element and whose drain is connected to the second terminal of the fuse element.

[0139] (Item 3) The fuse memory circuit described in item 2, wherein the gate of the fourth transistor is connected to the gate of the third transistor.

[0140] (Item 4) When the threshold voltage of the CMOS inverter circuit formed by the third transistor and the fourth transistor is VTINV, the resistance value of the fuse element before disconnection is RFUSE, the power supply voltage is VDD, the on-resistance of the second transistor is RM12, and the on-resistance of the third transistor is RM13, VDD×RM13 / (RFUSE+RM12+RM13)>VTINV A fuse memory circuit as described in item 3, which satisfies the requirements.

[0141] (Item 5) The fuse memory circuit described in item 1 includes a diode connected such that the high-potential side is the cathode and the low-potential side is the anode.

[0142] (Item 6) A fuse memory circuit according to any one of items 1 to 5, wherein the first line is the power supply line and the second line is the ground line.

[0143] (Item 7) A fuse memory circuit according to any one of items 1 to 5, wherein the first line is the ground line and the second line is the power supply line.

[0144] (Item 8) The fuse element is a fuse that becomes electrically interrupted when current is passed through it, as described in any of items 1 to 7 of the fuse memory circuit.

[0145] (Item 9) The fuse element is an antifuse that becomes electrically conductive when current is passed through it, as described in any of items 1 to 7 of the fuse memory circuit.

[0146] (Item 10) A semiconductor device comprising a fuse memory circuit as described in any of items 1 to 9. [Industrial applicability]

[0147] This disclosure relates to a fuse memory circuit. [Explanation of symbols]

[0148] 100 Fuse Memory Circuit 102 Line 1 104 Second Line 110 First Fuse Unit 120 Second Fuse Unit OUT1, OUT2 output terminals F11, F21 Fuse elements M11, M21 First Transistor M12, M22 Second Transistor M13, M23 Third Transistor M14, M24 4th transistor D11, D21 diodes 112 Rectifier element 114 CMOS Inverter Circuit 122 Rectifier element 124 CMOS Inverter Circuit 200-bit circuit 210 Control circuits 220 Output buffer 230 Locking Circuit 232 Output buffer 234 Control circuits 232 Output buffer 234 Control circuits 300 semiconductor equipment 310 Internal circuit 312,314 SRAM 316 Selector 318 microprocessors 320 Linear Regulator 322 transistors 324 Op-amps 326 Reference voltage source 330 Interface Circuit 332 Input Buffers 334 switches 336 pull-down resistors 400 Fuse Circuit 402 Control Register

Claims

1. The first line is one of the power line and the ground line, The second line is the other of the power line and the ground line, First fuse unit and The second fuse unit, Equipped with, The first fuse unit and the second fuse unit are, Test terminals and Program terminal and Output terminals, Its first end is connected to the first line, and it is a fuse element, A rectifier element connected in parallel with the fuse element, The drain of the first transistor is connected to the second terminal of the fuse element, its source is connected to the second line, and its gate is connected to the program terminal. A second transistor whose source is connected to the second terminal of the fuse element, whose drain is connected to the output terminal, and whose gate is connected to the test terminal, The drain of the third transistor is connected to the output terminal, and its source is connected to the second line. Includes, The gate of the third transistor of the first fuse unit is connected to the output terminal of the second fuse unit. A fuse memory circuit in which the gate of the third transistor of the second fuse unit is connected to the output terminal of the first fuse unit.

2. The rectifier element is, The fuse memory circuit according to claim 1, further comprising a fourth transistor whose source is connected to the first end of the fuse element and whose drain is connected to the second end of the fuse element.

3. The fuse memory circuit according to claim 2, wherein the gate of the fourth transistor is connected to the gate of the third transistor.

4. The threshold voltage of the CMOS inverter circuit formed by the third transistor and the fourth transistor is V ＴＩＮＶ The resistance value of the fuse element before disconnection is R ＦＵＳＥ , the power supply voltage is V ＤＤ , the on-resistance of the second transistor is R Ｍ１２ The on-resistance of the third transistor is R Ｍ１３ In that case, V ＤＤ ×R Ｍ１３ / (R ＦＵＳＥ +R Ｍ１２ +R Ｍ１３ )>VTINV A fuse memory circuit according to claim 3, satisfying the requirements.

5. The fuse memory circuit according to claim 1, wherein the rectifier element includes a diode connected in such a way that the high-potential side is the cathode and the low-potential side is the anode.

6. The fuse memory circuit according to any one of claims 1 to 5, wherein the first line is the power supply line and the second line is the ground line.

7. The fuse memory circuit according to any one of claims 1 to 5, wherein the first line is the ground line and the second line is the power supply line.

8. The fuse memory circuit according to any one of claims 1 to 5, wherein the fuse element is a fuse that becomes electrically interrupted when current is passed through it.

9. The fuse memory circuit according to any one of claims 1 to 5, wherein the fuse element is an antifuse that becomes electrically conductive when current is passed through it.

10. A semiconductor device comprising a fuse memory circuit according to any one of claims 1 to 5.

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