Display panels and display devices

Abstract

To improve display quality.SOLUTION: A display panel includes pixels in a delta-nabla layout. A pixel circuit column consists of cyclically disposed pixel circuits for three colors. A pixel circuit column pair consists of two adjacent pixel circuit columns. Data lines for three colors are disposed cyclically. Each data line set consists of data lines for a first color, a second color, and a third color disposed consecutively. An additional data line for the first color is disposed outside a plurality of data line sets. A plurality of pixel circuit column pairs is associated with data line sets different from each other. The pixel circuit for the first color in the pixel circuit column pair is supplied with a data signal from a data line closer to the data line for the first color in the associated data line set, and the data line for the first color located adjacent to the data line for the third color in the associated data line set outside the associated data line set.SELECTED DRAWING: Figure 11

Description

Technical Field

[0004] , , , , , , ,

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[0001] The present disclosure relates to a display panel and a display device.

Background Art

[0002] Instead of liquid crystal display devices, OLED (Organic Light-Emitting Diode) display devices have been proposed. Since OLED elements are current-driven self-emitting elements, they do not require a backlight, and have advantages such as low power consumption, a wide viewing angle, and a high contrast ratio, and are expected in the development of flat panel displays.

[0003] The display area of an active matrix color OLED display device is generally composed of red (R), green (G), and blue (B) sub-pixels arranged on the substrate of the display panel. Various arrangements (pixel arrangements) of sub-pixels have been proposed. For example, RGB Straipe arrangement and delta nabla arrangement (also simply called delta arrangement) are known.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0005] In display devices, a demultiplexer circuit (DeMUX) is sometimes used to reduce the number of pins in the driver circuit that outputs data signals. The demultiplexer circuit sequentially selects multiple data lines corresponding to each output pin of the driver circuit and outputs data signals from the output pins. In a configuration where a single data line transmits data signals to the pixel circuits of subpixels of different colors, insufficient writing of data signals to the pixel circuits can become a problem. [Means for solving the problem]

[0006] One aspect of the present disclosure is a display panel in which three-color pixels, consisting of a first color, a second color, and a third color, are arranged in a delta nabla layout. The display panel includes a plurality of pixel circuit arrays and a plurality of data lines. The plurality of pixel circuit arrays extend in a first direction and are arranged in a second direction perpendicular to the first direction. Each pixel circuit array in the plurality of pixel circuit arrays consists of the three-color pixel circuits arranged cyclically. Each pixel circuit in the three-color pixel array controls the light intensity of pixels of the same color as the pixel circuit. The plurality of pixel circuit arrays consists of a plurality of pixel circuit array pairs, each consisting of two adjacent pixel circuit arrays. The plurality of data lines extend in the first direction and are arranged in the second direction. In the plurality of data lines, the three-color data lines are arranged cyclically. Each data line in the plurality of data lines transmits a data signal to a pixel circuit of the same color as the data line. The plurality of data lines includes a plurality of data line sets, each data line set consisting of the first-color data lines, the second-color data lines, and the third-color data lines arranged in a continuous sequence. The plurality of data lines include additional data lines of the first color located outside the plurality of data line sets. The plurality of pixel circuit array pairs are associated with different data line sets. Each pixel circuit of the first color in each of the plurality of pixel circuit array pairs is supplied with a data signal from the closer data line of the first color, which is between the data lines of the first color within the associated data line set and the data lines of the first color outside the associated data line set. [Effects of the Invention]

[0007] One aspect of this disclosure can improve display quality. [Brief explanation of the drawing]

[0008] [Figure 1] A schematic example of the configuration of an OLED display device is shown. [Figure 2A] An example of a pixel circuit is shown. [Figure 2B] An example of a pixel circuit is shown. [Figure 3] This shows the pixel arrangement in a delta nabla panel. [Figure 4] This specification shows a circuit layout according to one embodiment, illustrating an example of the layout of sub-pixels (light-emitting regions), pixel circuits, scan lines, and data lines. [Figure 5] This diagram illustrates the connection point between the data line and the pixel circuit. [Figure 6A] A schematic example of the configuration of a demultiplexer circuit between the data lines and the driver IC shown in Figure 4 is illustrated. [Figure 6B] An example configuration of a 1:4 DeMUX circuit is shown. [Figure 7] Another schematic configuration of the demultiplexer circuit between the data lines and the driver IC shown in Figure 4 is illustrated. [Figure 8] Figure 4 shows an example of a circuit layout near the edge of the display area, corresponding to the configuration example shown. [Figure 9] An example of a circuit layout is shown, where the green pixel circuit occupies a larger area than the red and blue pixel circuits. [Figure 10] Here are some other examples of circuit layouts. [Figure 11] The circuit layout of one embodiment of this specification is shown. [Figure 12] This shows a wider area following the circuit layout shown in Figure 11. [Figure 13] Figure 12 shows an example configuration of a 1:2 demultiplexer circuit that outputs data signals to the data lines shown. [Modes for carrying out the invention]

[0009] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be noted that this embodiment is merely an example for realizing the features of the present disclosure and does not limit the technical scope of the present disclosure. The same reference numerals are assigned to common configurations in each figure.

[0010] In a display device, by using a demultiplexer circuit (DeMUX), the number of pins of a driving circuit that outputs a data signal can be reduced. The demultiplexer circuit sequentially selects a plurality of data lines corresponding to each output pin of the driving circuit and outputs the data signal from the output pin.

[0011] In a configuration (color rotation) in which one data line transmits data signals to pixel circuits of sub-pixels of different colors, it is necessary to prevent incorrect color data signals from being input to the pixel circuits corresponding to each color. Therefore, when performing scanning driving, it is necessary to control so that the data writing timings for the pixel circuits of each color connected to one data line do not overlap. Such control can be achieved by temporally separating the data writing periods for the plurality of pixel circuits connected to one data line. On the other hand, when assuming high definition or high frame rate driving of the display panel, the data writing period becomes short, and insufficient writing of the data signal to the pixel circuit may become a problem.

[0012] So far, in a display device with a delta nabla layout using DeMUX, the supply of data signals by color rotation has been performed. For the supply of data signals by non-color rotation, a complex structure of the lead-out part between the data line and the pixel circuit has been required.

[0013] The inventors have studied the circuit layout of a display panel including a pixel circuit for controlling pixels in a delta nabla layout and data lines. The display panel according to an embodiment of the present specification enables the supply of data signals by using a demultiplexer circuit and non-color rotation while suppressing the influence on the design of the pixel circuit. Thereby, display degradation due to insufficient writing of data signals can be reduced.

[0014] <Embodiment 1> [Configuration of Display Device] Referring to FIG. 1, the overall configuration of the display device according to the present embodiment will be described. For the sake of easy understanding of the description, the dimensions and shapes of the illustrated objects may be exaggerated in some cases. Hereinafter, as an example of the display device, an OLED (Organic Light-Emitting Diode) display device will be described, but the features of the present disclosure can be applied to different types of display devices from the OLED display device. The features of the present disclosure are particularly useful for display devices that display images using self-emitting elements.

[0015] FIG. 1 schematically shows a configuration example of an OLED display device 10. The OLED display device 10 includes an OLED display panel and a control device. The OLED display panel includes a TFT (Thin Film Transistor) substrate 100 on which OLED elements (light-emitting elements) are formed, a sealing substrate 200 for sealing the OLED elements, and a joining portion (glass frit seal portion) 300 for joining the TFT substrate 100 and the sealing substrate 200.

[0016] For example, dry nitrogen or dry air is enclosed between the TFT substrate 100 and the sealing substrate 200 and is sealed by the joining portion 三

[0017] A scanning driver 131, an emission driver 132, a protection circuit 133, a demultiplexer circuit 136 (DeMUX), and a driver IC 134 are arranged around the cathode electrode formation area 114 outside the display area 125 of the TFT substrate 100. These are connected to external equipment via an FPC (Flexible Printed Circuit) 135. The driver IC 134, scanning driver 131, emission driver 132, protection circuit 133, and demultiplexer circuit 136 are included in the control unit.

[0018] The scanning driver 131 drives the scanning lines of the TFT substrate 100. The emission driver 132 drives the emission control lines to control, for example, the light emission period of each subpixel. The protection circuit 133 protects the elements from electrostatic discharge. The driver IC 134 is mounted, for example, using an anisotropic conductive film (ACF).

[0019] The driver IC 134 supplies power and timing signals (control signals) to the scan driver 131 and the emission driver 132. Furthermore, the driver IC 134 supplies power, control signals, and data signals to the demultiplexer circuit 136. The demultiplexer circuit 136 sequentially outputs the output of one pin of the driver IC 134 to d data lines (d is an integer of 2 or more). The demultiplexer circuit 136 drives d times the number of output pins of the driver IC 134 by switching the data line to which the data signal from the driver IC 134 is output d times during the scan period (1:d DeMUX).

[0020] In Figure 1, the axis extending horizontally is called the X-axis, and the axis extending vertically is called the Y-axis. These are orthogonal. Scan lines extend along the X-axis, and data lines extend along the Y-axis. These transmission lines may be straight or partially bent. In the display area 125, pixels or sub-pixels arranged along the X-axis are called pixels or sub-pixel rows. In the display area 125, pixels or sub-pixels arranged along the Y-axis are called pixel columns or sub-pixel columns. The circuit that controls the light emission of sub-pixels is called a pixel circuit. Hereafter, a single light-emitting area, i.e., a sub-pixel, may simply be referred to as a pixel.

[0021] The display area 125 of this embodiment is composed of sub-pixels arranged in a delta nabla pattern on an insulating substrate. The insulating substrate is made of, for example, glass or resin, and is either rigid or flexible. Details of the delta nabla arrangement will be described later. The sub-pixels are light-emitting areas that display one of the following colors: red (R), green (G), or blue (B). The example described below displays an image using the above three-color combination.

[0022] The light-emitting region is contained within the OLED element. An OLED element consists of an anode electrode (the lower electrode), an organic light-emitting film, and a cathode electrode (the upper electrode). In other words, multiple OLED elements are formed by one cathode electrode, multiple anode electrodes, and multiple organic light-emitting films. The region where the organic light-emitting film is in contact with the anode electrode is the light-emitting region, or sub-pixel.

[0023] [Pixel circuit] Multiple pixel circuits are formed on the TFT substrate 100 to control the current supplied to the anode electrodes of multiple sub-pixels. Figure 2A shows an example of the configuration of a pixel circuit. Each pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a retaining capacitor C. The pixel circuit controls the light emission of the OLED element E1, which is a sub-pixel. The transistors are TFTs (Thin Film Transistors). Hereinafter, the first transistor T1 to the third transistor T3 will be abbreviated as transistors T1 to T3, respectively.

[0024] Transistor T2 is a switch for sub-pixel selection. Transistor T2 is a p-channel TFT, and its gate terminal is connected to scan line 106. Its drain terminal is connected to data line 105. Its source terminal is connected to the gate terminal of transistor T1.

[0025] Transistor T1 is a driver transistor (driver TFT) for the OLED element E1. Transistor T1 is a p-channel TFT, and its gate terminal is connected to the source terminal of T2. The source terminal of transistor T1 is connected to power line 108 (VDD). The drain terminal is connected to the source terminal of transistor T3. A retaining capacitance C is formed between the gate terminal and the source terminal of transistor T1.

[0026] Transistor T3 is a switch that controls the supply and cessation of drive current to the OLED element E1. Transistor T3 is a p-channel TFT, and its gate terminal is connected to emission control line 107. The source terminal of transistor T3 is connected to the drain terminal of transistor T1. The drain terminal is connected to the OLED element E1.

[0027] Next, the operation of the pixel circuit will be explained. The scanning driver 131 outputs a selection pulse to the scanning line 106, turning on transistor T2. The data voltage supplied from the driver IC 134 via the data line 105 is stored in the retention capacitor C. The retention capacitor C holds the stored voltage throughout one frame period. The retention voltage causes the conductance of transistor T1 to change analogously, and transistor T1 supplies a forward bias current corresponding to the light emission gradation to the OLED element E1.

[0028] Transistor T3 is located on the drive current supply path. The emission driver 132 outputs a control signal to the emission control line 107 to control the ON / OFF state of transistor T3. When transistor T3 is ON, drive current is supplied to the OLED element E1. When transistor T3 is OFF, this supply is stopped. By controlling the ON / OFF state of transistor T3, the illumination period (duty cycle) within one field period can be controlled.

[0029] Figure 2B shows another example of a pixel circuit configuration according to one embodiment of this specification. The pixel circuit is contained in the k-th (k is an integer) pixel circuit row. The pixel circuit includes six transistors (TFTs) P1 to P6, each having a gate, source, and drain. In this example, all transistors P1 to P6 are P-type TFTs.

[0030] Transistor P1 is a drive transistor that controls the amount of current supplied to the OLED element E1. The source of drive transistor P1 is connected to power line 241, which transmits the positive power supply potential VDD. Drive transistor P1 controls the amount of current supplied to the OLED element E1 from power line 241 according to the voltage held by series-connected retention capacitors C1 and C2. Retention capacitors C1 and C2 hold the written voltage throughout one frame period. The cathode of the OLED element E1 is connected to power line 204, which transmits the negative power supply potential VEE from the cathode power supply.

[0031] Capacitors C1 and C2 are connected in series between the power line 241, which transmits the positive power supply potential VDD, and the gate of the drive transistor P1. Power line 241 is connected to one end of capacitor C1. One end of capacitor C2 is connected to the other end of capacitor C1. The gate of drive transistor P1 is connected to the other end of capacitor C2. The source / drain of transistor P4 and the source / drain of transistor P2 are connected to the intermediate node between capacitors C1 and C2.

[0032] The combined capacitance of the series-retaining capacitance elements C1 and C2 retains the voltage between the gate and source of the drive transistor P1, which is the power supply line 241. The source of the drive transistor P1 is connected to the power supply line 241, and the source potential is the positive power supply potential VDD. Therefore, the retaining capacitance elements C1 and C2 retain the gate-source voltage of the drive transistor P1.

[0033] Transistor P5 is a light emission control switch transistor that controls the supply of drive current to the OLED element E1 and the resulting ON / OFF of light emission. The source of transistor P5 is connected to the drain of drive transistor P1. Transistor P5 switches the current supply to the OLED element E1 connected to its drain ON / OFF. The gate of transistor P5 is connected to control signal line 233 which transmits the light emission control signal Em, and transistor P5 is controlled by the light emission control signal Em from emission driver 132. The light emission control signal is a selection signal that controls the light emission of the OLED element E1.

[0034] Transistor P6 operates to supply the reset potential Vrst to the anode of the OLED element E1. One end of the source / drain of transistor P6 is connected to the power line 242 that transmits the reset potential Vrst, and the other end is connected to the anode of the OLED element E1.

[0035] The gate of transistor P6 is connected to control signal line 231, which transmits selection signal S1, and transistor P6 is controlled by selection signal S1. When transistor P6 is turned ON by selection signal S1 from scan driver 131, it supplies a reset potential Vrst transmitted by power line 242 to the anode of OLED element E1.

[0036] Furthermore, transistors P5 and P6, via transistor P3, supply a reset potential Vrst to the gate of the drive transistor P1 and to one of the electrodes of the retaining capacitor C2. As a result, the charge held in the anode of the OLED element E1 and the retaining capacitors C1 and C2 in the previous frame is discharged via transistor P6, and the gate potential of the drive transistor P1 is reset (initialized).

[0037] Transistor P3 is a switch transistor (threshold compensation transistor) that writes the voltage for threshold correction (threshold compensation) of the drive transistor P1 to the holding capacitance elements C1 and C2, and is a transistor that resets the gate potential of the drive transistor P1. The source and drain of transistor P3 are connected to the gate and drain of the drive transistor P1. Therefore, when transistor P3 is ON, the drive transistor P1 is in a diode connection state.

[0038] Transistor P4 is used to write the voltage for threshold compensation of the drive transistor P1 to the holding capacitance elements C1 and C2. Transistor P4 controls whether or not a reference potential Vref is supplied to the holding capacitance elements C1 and C2. The reference potential Vref may be, for example, the same potential as the positive power supply potential VDD. This allows the transmission line (power line) for the reference potential Vref and the positive power supply potential VDD to be shared. One end of the source / drain of transistor P4 is connected to the power line 202 that transmits the reference potential Vref, and the other end is connected to the intermediate node of the capacitance elements C1 and C2. The gate of transistor P4 is connected to the control signal line 231 that transmits the selection signal S1, and transistor P4 is controlled by the selection signal S1 input to the gate from the scan driver 131.

[0039] Transistors P3, P6, and P4 are controlled by the selection signal S1. Therefore, these transistors P3, P6, and P4 are switched ON / OFF simultaneously. While they are ON, transistor P5 is turned ON to reset the gate potential of the drive transistor P1, and then transistor P5 is turned OFF. When transistors P3 and P4 are ON, transistor P1 constitutes a diode-connected transistor. Based on the positive power supply potential VDD and the reference potential Vref, the threshold compensation voltage of the drive transistor P1 is written to the retaining capacitance elements C1 and C2.

[0040] Transistor P2 is a switch transistor that selects the pixel circuit to supply the data signal and writes the data signal (data signal voltage) Vdata to the retaining capacitance elements C1 and C2. One end of the source / drain of transistor P2 is connected to the retaining capacitance elements C1 and C2 and to the data line 237 that transmits the data signal Vdata.

[0041] The gate of transistor P2 is connected to control signal line 232, which transmits selection signal S2 from scan driver 131. Transistor P2 is controlled by selection signal S2. Selection signal S2 is a different selection signal from selection signal S1. In the pixel circuit, selection signal S2 is a selection signal that controls the supply of data signal Vdatae to retention capacitance elements C1 and C2. When transistor P2 is ON, transistor P2 supplies data signal Vdata, supplied from driver IC 134 via data line 237, to retention capacitance elements C1 and C2.

[0042] [Pixel arrangement in a delta nabla panel] Figure 3 shows the pixel (subpixel) layout in a delta nabla panel. Figure 3 schematically shows a portion of the display area 125. The display area 125 consists of multiple red subpixels 41R, multiple green subpixels 41G, and multiple blue subpixels 41B arranged within the plane. Each subpixel is a single light-emitting region of each color. In Figure 3, one red subpixel, one green subpixel, and one blue subpixel are indicated by their symbols, for example. In Figure 3, squares (with rounded corners) with the same hatching indicate subpixels of the same color. In Figure 3, the shape of the subpixels is square, but the shape of the subpixels is arbitrary and may be, for example, hexagonal or octagonal.

[0043] The display area 125 includes multiple sub-pixel rows 42 arranged in the X direction. In Figure 3, one sub-pixel row is indicated by the symbol 42, for example. In Figure 3, the sub-pixel row 42 consists of sub-pixels arranged along the Y direction. The X direction is the direction from left to right in Figure 3 (along the X-axis), and the Y direction is the direction from top to bottom (along the Y-axis). The X and Y directions are perpendicular within the plane in which the sub-pixels are arranged.

[0044] The subpixel row 42 is composed of red subpixels 41R, green subpixels 41G, and blue subpixels 41B arranged cyclically at a predetermined pitch. In the example in Figure 3, the red subpixels 41R, blue subpixels 41B, and green subpixels 41G are arranged in this order. The subpixel row may be composed of subpixels arranged in a different order of color. The positions of adjacent subpixel rows 42 are offset in the Y direction, and the subpixels of subpixel row 42 are located between the other two colored subpixels of adjacent subpixel rows 42 in the Y direction.

[0045] In the example in Figure 3, adjacent subpixel rows 42 are offset by half a pitch. One pitch is the distance in the Y direction between subpixels of the same color. For example, the green subpixel 41G is located in the Y direction, midway between the red subpixel 41R and the blue subpixel 41B in the adjacent subpixel row 42.

[0046] The display area 125 includes multiple sub-pixel rows 43 arranged in the Y direction. In Figure 3, one green sub-pixel row is indicated by reference numeral 43, for example. Each sub-pixel row 43 consists of sub-pixels arranged at a predetermined pitch along the X direction. In the example in Figure 3, each sub-pixel row 43 consists of sub-pixels of the same color. Each sub-pixel row 43 is sandwiched along the Y axis between two other sub-pixel rows of different colors.

[0047] A subpixel in subpixel row 43 is located in the X direction between two adjacent subpixels in the adjacent subpixel row 43. In the example in Figure 3, adjacent subpixel rows 43 are offset by half a pitch. One pitch is the distance between adjacent subpixels in subpixel row 43. A subpixel is located in the X direction between two adjacent subpixels in the adjacent subpixel row 43.

[0048] In this embodiment, for convenience, sub-pixel lines extending along the X-axis are referred to as sub-pixel rows, and sub-pixel lines extending along the Y-axis are referred to as sub-pixel columns; however, the direction of sub-pixel rows and sub-pixel columns is not limited to these.

[0049] The display area 125 includes two types of principal pixels, a first principal pixel 51 and a second principal pixel 52, arranged in a matrix. In Figure 3, only one first principal pixel is indicated by reference numeral 51, for example. Similarly, only one second principal pixel is indicated by reference numeral 52, for example. One of the first principal pixel and the second principal pixel is a delta pixel in a delta nabla arrangement, and the other is a nabla pixel.

[0050] In Figure 3, several first-class primary pixels 51 are represented by triangles with one vertex on the left and two vertices on the right. Similarly, several second-class primary pixels 52 are represented by triangles with one vertex on the right and two vertices on the left. In Figure 3, the right side is the X-direction, and the left side is the opposite direction. Note that primary pixels 51 may be called second-class primary pixels, and primary pixels 52 may be called first-class primary pixels.

[0051] The first primary pixel 51 and the second primary pixel 52 each consist of one green sub-pixel 41G and, in the sub-pixel row 42 adjacent to the green sub-pixel 41G, the nearest red sub-pixel 41R and blue sub-pixel 41B adjacent to the green sub-pixel 41G.

[0052] In the first primary pixel 51, the red subpixel 41R and the blue subpixel 41 are arranged consecutively in the same subpixel row 42. The subpixel row 42 containing the green subpixel 41G is adjacent to the subpixel row 42 containing the red subpixel 41R and the blue subpixel 41 on the opposite side in the X direction, i.e., to the left in Figure 3. The green subpixel 41G is located along the Y axis between the red subpixel 41R and the blue subpixel 41B, more specifically in the center.

[0053] In the second primary pixel 52, the red subpixel 41R and the blue subpixel 41 are arranged consecutively in the same subpixel row 42. The subpixel row 42 containing the green subpixel 41G is adjacent to the subpixel row 42 containing the red subpixel 41R and the blue subpixel 41 on the X-direction side, i.e., on the right side in Figure 3. The green subpixel 41G is located along the Y-axis between the red subpixel 41R and the blue subpixel 41B, more specifically in the center.

[0054] The display area 125 includes multiple rows of principal pixels (pixel lines extending along the X-axis) that extend along the X-axis and are arranged along the Y-axis. The multiple rows of principal pixels consist of two types of principal pixel rows: first-type principal pixel rows 61 and second-type principal pixel rows 62. In Figure 3, one first-type principal pixel row is indicated by reference numeral 61, for example. Also, one second-type principal pixel row is indicated by reference numeral 62, for example.

[0055] The first row of primary pixels 61 consists of primary pixels 51 arranged in the X direction. The second row of primary pixels 62 consists of primary pixels 52 arranged in the X direction. In the display area 125, the first row of primary pixels 61 and the second row of primary pixels 62 are arranged alternately in the Y direction.

[0056] Display area 125This includes multiple rows of principal pixels (pixel lines extending along the Y axis) 63 that extend along the Y axis and are arranged along the X axis. In Figure 3, one row of principal pixels is indicated by reference numeral 63, for example. Each row of principal pixels 63 consists of first-type principal pixels 51 and second-type principal pixels 52 that are arranged alternately along the Y axis at a predetermined pitch.

[0057] [Data line and pixel circuit layout] Figure 4 shows a portion of the circuit layout pattern according to one embodiment of this specification, illustrating an example of the layout of subpixels (light-emitting regions), pixel circuits (only the element placement area is shown, with individual element patterns omitted), switch transistors for writing data to the pixel circuits, scan lines, and data lines. In Figure 4, multiple subpixels (light-emitting regions) are shown by dashed rectangles. For example, one red subpixel is indicated by code 411R, one green subpixel by code 411G, and one blue subpixel by code 411B.

[0058] Within the dashed rectangle, R, G, and B represent red, green, and blue, respectively. Each subpixel (sometimes simply called a pixel) is an emission region and is the contact region between the anode electrode and the organic light-emitting laminate. As explained with reference to Figure 3, the subpixels are arranged in a delta nabla layout. Similarly, the anode electrode is also arranged in a delta nabla layout.

[0059] The regions containing the pixel circuits that control the light emission of each sub-pixel are each indicated by solid rectangles. Regions defined in this way are called pixel circuit regions or simply pixel circuits. For example, the pixel circuit of one red sub-pixel is indicated by code 431R, the pixel circuit of one green sub-pixel is indicated by code 431G, and the pixel circuit of one blue sub-pixel is indicated by code 431B. R, G, and B within the solid rectangles indicate the colors of the sub-pixels being controlled, respectively.

[0060] Pixel circuits 431R, 431G, and 431B are separate from each other and do not overlap. The portion of one pixel circuit exists outside of all other pixel circuits. In the configuration example in Figure 4, the outline of the pixel circuits is rectangular, but this does not exclude other shapes. Pixel circuits controlling subpixels of the same color have the same shape, while pixel circuits controlling subpixels of different colors may have different shapes.

[0061] Multiple pixel circuits 431R, 431G, and 431B are arranged in a different layout from the sub-pixels. In the example in Figure 4, the multiple pixel circuits 431R, 431G, and 431B are arranged in a matrix. Multiple pixel circuits consist of multiple pixel circuit rows or multiple pixel circuit columns. Each pixel circuit row consists of pixel circuits arranged in the X direction, and multiple pixel circuit rows are arranged in the Y direction. Each pixel circuit column consists of pixel circuits arranged in the Y direction, and multiple pixel circuit columns are arranged in the X direction.

[0062] In the configuration example shown in Figure 4, the shape and occupied area of ​​all pixel circuits 431R, 431G, and 431B are the same. Furthermore, in a row of pixel circuits, the centroid of the pixel circuit lies on a straight line in the X direction, and in a column of pixel circuits, the centroid of the pixel circuit lies on a straight line in the Y direction.

[0063] In Figure 4, the two pixel circuit sequences on the left control the subpixels of the t-th primary pixel sequence 461t, and the two pixel circuit sequences on the right control the subpixels of the t+1-th primary pixel sequence 461t+1, where t is an integer. As explained with reference to Figure 3, one primary pixel sequence consists of two adjacent subpixel sequences. A primary pixel consists of three subpixels of different colors located in the 3rd row and 2nd column of the subpixels. Thus, multiple pixel circuit sequences contain multiple pairs of pixel circuit sequences, each corresponding to a different primary pixel sequence.

[0064] In each pixel circuit sequence, three colored pixel circuits are arranged cyclically. In the example in Figure 4, red, green, and blue pixel circuits are arranged repeatedly from top to bottom in that order. The arrangement of adjacent pixel circuit sequences is shifted by one pixel circuit. Therefore, within adjacent pixel circuit sequences, two pixel circuits in the same row will have different colors. In odd-numbered pixel circuit sequences, the relationship between the color of the pixel circuit and its position in the Y direction is the same. In even-numbered pixel circuit sequences, the relationship between the color of the pixel circuit and its position in the Y direction is the same.

[0065] Each pixel circuit row consists of alternating pairs of two-color pixel circuits. Adjacent pixel circuit rows consist of pixel circuits of different color pairs. In the example in Figure 4, the top pixel circuit row consists of alternating red and blue pixel circuits, the row below it consists of alternating green and red pixel circuits, and the row below that consists of alternating blue and green pixel circuits.

[0066] Figure 4 shows Y Extending in that direction, X This shows multiple data lines arranged in a directional manner. The data lines, which transmit data signals to the three colored pixel circuits, are arranged cyclically. X They are arranged in a directional manner. In Figure 4, the data lines extend linearly in the Y direction, but for example, a portion of them may be bent.

[0067] Data lines XRt and XRt+1 are the t-th and t+1-th data lines, respectively, that transmit data signals to the red pixel circuit 431R. Data lines XRt and XRt+1 are connected to multiple red pixel circuits 431R, but not to pixel circuits of other colors. The data lines of the red pixel circuits are also called red data lines.

[0068] Data lines XGt and XGt+1 are the t-th and t+1-th data lines, respectively, that transmit data signals to the green pixel circuit 431G. Data lines XGt and XGt+1 are connected to multiple green pixel circuits 431G, but not to pixel circuits of other colors. The data lines of the green pixel circuits are also called green data lines.

[0069] Data lines XBt and XBt+1 are the t-th and t+1-th data lines, respectively, that transmit data signals to the blue pixel circuit 431B. Data lines XBt and XBt+1 are connected to multiple red pixel circuits 431B, but not to pixel circuits of other colors. The data lines of the blue pixel circuits are also called blue data lines.

[0070] As described above, in one embodiment of this specification, each data line sequentially transmits a data signal to a pixel circuit of only one color. In a typical display image, the difference in gradation between adjacent data of the same color tends to be small, so even if the selection period of the data lines is the same, the signal writing rate to each data line is improved, and the deterioration of image quality due to insufficient writing of data signals to the pixel circuit can be suppressed.

[0071] The data lines XRt, XGt, and XBt constitute a single data line set and are associated with a pair of pixel circuit arrays that control the main pixel array 461t. Similarly, the data lines XRt+1, XGt+1, and XBt+1 constitute a single data line set and are associated with a pair of pixel circuit arrays that control the main pixel array 461t+1.

[0072] Thus, each data line set consists of different data lines, and each data line set consists of three consecutively arranged data lines of different colors. Each data line set is associated with a different principal pixel array, that is, a different pair of pixel circuit arrays.

[0073] In the configuration example shown in Figure 4, data line XGt is the data line closest to the center in the X direction of the pixel circuit array pair corresponding to the main pixel array 461t, and passes between the sub-pixel arrays of the main pixel array 461t. Data line XRt is the data line closest to the left end of the pixel circuit array pair, and data line XBt is the data line closest to the right end of the pixel circuit array pair.

[0074] The positional relationship between data lines XRt+1, XGt+1, and XBt+1 and the pixel circuit row pair corresponding to the main pixel row 461t+1 is the same as the positional relationship between data lines XRt, XGt, and XBt and the pixel circuit row pair corresponding to the main pixel row 461t. Note that Figure 4 shows an example of the positional relationship between the pixel circuit row pair and the data line set, and is not limited to this.

[0075] Each data line and each pixel circuit are connected by a lead-out section that includes a switch TFT. In Figure 4, the red data line and red A portion of the lead-out section connecting the pixel circuit is indicated by the code 471R1 or 471R2. A portion of the lead-out section connecting the green data line and the green pixel circuit is indicated by the code 471G1 or 471G2. The blue data line and blue A portion of the lead-out section connecting to the pixel circuit is indicated by the reference numeral 471B1 or 471B2.

[0076] Each lead-out switch TFT is turned ON / OFF by one of the scan lines Yk to Yk+3, where k is an integer. The scan lines Yk to Yk+3 each extend in the X direction and are arranged in the Y direction. By turning the lead-out switch TFTs ON / OFF, the scan lines Yk to Yk+3 switch the presence or absence of conductivity between the data lines and the pixel circuit.

[0077] Figure 5 is a diagram illustrating the connection points between data lines and pixel circuits. Figure 5 shows the data lines XRt, XGt, XBt, and XRt+1, the pixel circuits within the main pixel array 461t, and the connection points between them.

[0078] Each of the green data lines, including data lines XGt and XGt+1, transmits a data signal to the green pixel circuit in the corresponding pixel circuit pair that constitutes the main pixel row. In the configuration example in Figure 5, the green data line XGt is connected to the green pixel circuit 431G of the left pixel circuit row of the corresponding pixel circuit pair by a lead-out section 471G1. The green data line XGt is connected to the green pixel circuit 431G of the right pixel circuit row of the corresponding pixel circuit pair by a lead-out section 471G2. The lead-out sections connect the green data lines and the green pixel circuits without crossing any data lines.

[0079] Each of the blue data lines, including data lines XBt and XBt+1, transmits a data signal to the blue pixel circuit in the corresponding pixel circuit pair that constitutes the main pixel row. In the configuration example in Figure 5, the blue data line XBt is connected to the blue pixel circuit 431B of the left pixel circuit row of the corresponding pixel circuit pair by a lead-out section 471B2. The blue data line XBt is connected to the blue pixel circuit 431B of the right pixel circuit row of the corresponding pixel circuit pair by a lead-out section 471B1.

[0080] The blue lead-out section 471B1 connects the blue data line XBt to the blue pixel circuit 431B without crossing any data lines. On the other hand, the blue lead-out section 471B2 is long and also crosses the green data line XGt. Such long lead-out sections increase the area and reduce the usable area of ​​the pixel circuit. Furthermore, intersections between lead-out sections and other wiring make element placement difficult and can cause crosstalk. It is preferable for lead-out sections to be short and to have few intersections with data lines.

[0081] In the configuration examples shown in Figures 4 and 5, the lead-out between the red data line and the red pixel circuit is formed to avoid other data lines. The red data line transmits data signals to the red pixel circuit of the corresponding pixel circuit row pair and to the red pixel circuit of the adjacent pixel circuit row pair.

[0082] In the configuration example shown in Figure 5, the red pixel circuit of the left pixel circuit row of the main pixel row 461t pair is connected to the red data line XRt by a lead-out section 471R1. The red data line XRt is included in the data line set associated with that pixel circuit row pair. On the other hand, the red pixel circuit of the right pixel circuit row of the same pixel circuit row pair is connected to the red data line XRt+1 by a lead-out section 471R2. Data line XRt+1 is closer to the rightmost pixel circuit row than data line XRt. Both lead-out sections 471R1 and 471R2 connect the pixel circuit to the data line without crossing any data line.

[0083] Thus, the red pixel circuit of a pair of pixel circuit arrays receives its data signal from the closer red data line, between the red data line within its associated data line set and the red data line outside of its associated data line set. All red leads connect the red data line to the red pixel circuit without crossing any other data lines.

[0084] Note that in the configuration examples shown in Figures 4 and 5, the red pixel circuit within the pixel circuit array pair is connected to the red data line of a different data line set. In other configuration examples, other colors, such as the blue lead-out section, may be configured as described above. X The order of the data line colors in the direction may differ from the examples shown in Figures 4 and 5, and the selected color lead-out sections may be configured as lead-out sections 471R1 and 471R2 accordingly.

[0085] Figure 6A schematically shows an example configuration of the demultiplexer circuit 136 between the data lines and the driver IC 134 shown in Figure 4. Figure 6A shows an example of a 1:2DeMUX circuit with color rotation of the driver IC output.

[0086] Figure 6A shows three demultiplexers 361, 362, and 363, corresponding to the output terminals OUT1, OUT2, and OUT3 of the driver IC 134, respectively. Demultiplexer 361 receives the data signal from output terminal OUT1 of the driver IC 134 via its input terminal and outputs it to one of the data lines XRt or XGt, selected from the two. Output terminal OUT1 alternately outputs the data signal for the red pixel circuit and the data signal for the green pixel circuit (color rotation).

[0087] The demultiplexer 362 receives the data signal from the driver IC 134's output terminal OUT2 via the input terminal and outputs it to one of the data lines XBt or XRt+1, selected from the two. Output terminal OUT2 alternately outputs the data signal for the blue pixel circuit and the data signal for the red pixel circuit (color rotation).

[0088] The demultiplexer 363 receives the data signal from the output terminal OUT3 of the driver IC 134 via its input terminal and outputs it to one of the data lines XGt+1 or XBt+1 selected from the two. Output terminal OUT3 alternately outputs the data signal for the green pixel circuit and the data signal for the blue pixel circuit (color rotation).

[0089] The selection of each data line in the demultiplexer is controlled by selection signals from control terminals MUX1 and MUX2. These selection signals are provided, for example, by driver IC 134. The configuration shown in Figure 6A allows for a simplified wiring of the demultiplexer circuit 136, enabling a narrow bezel.

[0090] Figure 6B shows an example configuration of a 1:4 DeMUX circuit. In this configuration, the output terminal of the driver IC 134 sequentially outputs data signals to pixel circuits of different colors (color rotation). This simplifies the wiring of the demultiplexer circuit 136, allowing for a narrower bezel area.

[0091] The demultiplexer circuit 136 includes multiple switch TFTs 651-662. Switches TFTs 651 and 657 are connected to data line XRt. Switches TFTs 652 and 658 are connected to data line XGt. Switches TFTs 653 and 659 are connected to data line XBt. Switches TFTs 654 and 660 are connected to data line XRt+1. Switches TFTs 655 and 661 are connected to data line XGt+1. Switches TFTs 656 and 662 are connected to data line XBt+1.

[0092] Switches TFT651, 653, and 655 are controlled ON / OFF by a selection signal from control terminal MUX1. Switches TFT652, 654, and 656 are controlled ON / OFF by a selection signal from control terminal MUX2. Switches TFT657, 659, and 661 are controlled ON / OFF by a selection signal from control terminal MUX3. Switches TFT658, 660, and 662 are controlled ON / OFF by a selection signal from control terminal MUX4.

[0093] Control terminals MUX1 to MUX4 output ON pulses sequentially and cyclically. Control terminals MUX1 and MUX2 output ON pulses sequentially within one horizontal period, and control terminals MUX3 and MUX4 output ON pulses sequentially within the next horizontal period.

[0094] The demultiplexer to which output terminal OUT1 is connected consists of switches TFT651, 652, 657, and 658. Output terminal OUT1 alternately outputs data signals from the red pixel circuit and the green pixel circuit. The demultiplexer to which output terminal OUT2 is connected consists of switches TFT653, 654, 659, and 660. Output terminal OUT2 alternately outputs data signals from the blue pixel circuit and the red pixel circuit. The demultiplexer to which output terminal OUT3 is connected consists of switches TFT655, 656, 661, and 662. Output terminal OUT3 alternately outputs data signals from the green pixel circuit and the blue pixel circuit.

[0095] Figure 7 schematically shows another configuration of the demultiplexer circuit 136 between the data lines and the driver IC 134 shown in Figure 4. Figure 7 shows an example of a 1:2 DeMUX circuit without color rotation of the driver IC output. Since the output color from each output terminal of the driver IC 134 is fixed, the delay from the driver IC 134 to the demultiplexer circuit 136 can be reduced, improving the data writing capability to the pixel circuit.

[0096] Figure 7 shows the three demultiplexers corresponding to the output terminals OUT1, OUT2, and OUT3 from the driver IC 134. The demultiplexer for output terminal OUT1 consists of switches TFT371 and 374. The demultiplexer for output terminal OUT2 consists of switches TFT372 and 375. The demultiplexer for output terminal OUT3 consists of switches TFT373 and 376. The output colors from output terminals OUT1, OUT2, and OUT3 are red, green, and blue, respectively.

[0097] Similarly, a demultiplexer circuit with an arbitrary ratio of 1:n (where n is an integer greater than or equal to 3) is described in two types: with color rotation and without color rotation. Driver IC It can be configured for this purpose.

[0098] Figure 8 shows an example of a circuit layout near the edge of the display area, corresponding to the configuration example shown in Figure 4. Figure 8 shows the T-th column of primary pixels 461T at the edge of the display area 125, and the data lines XRT, XGT, and XBT of the associated data line set. This configuration example further includes an additional red data line XRT+1 and a dummy circuit 510 connected to it in the peripheral area 127 outside the display area 125. The data line XRT+1 is located outside the multiple data line sets within the display area 125.

[0099] As explained with reference to Figures 4 and 5, some of the red pixel circuits are supplied with data signals from the red data lines of the data line sets adjacent to the data line set associated with the main pixel row. An additional red data line XRT+1 transmits data signals to the red pixel circuits in the pixel circuit row at the edge of the display area. The lead-out section 517 connects the additional red data line XRT+1 to the red pixel circuits in the pixel circuit row at the edge of the display area 125. The additional red data line XRT+1 is the red data line closest to the pixel circuit row at the edge of the display area.

[0100] In the example described with reference to Figures 4, 5, and 8, the red data line closest to the red pixel circuit provides a data signal to that red pixel circuit. In this configuration, the lead-out section can connect the red pixel circuit and the red data line without crossing other data lines.

[0101] In the configuration example shown in Figure 8, the additional red data line XRT+1 is connected to the dummy circuit 510. This allows the loading of the additional red data line XRT+1 to be brought closer to that of the other data lines in the display area 125. In the configuration example in Figure 8, the dummy circuit 510 includes a dummy red pixel circuit 511 connected to the additional red data line XRT+1, and an unconnected dummy pixel circuit 512. The dummy circuit 510 also includes a dummy subpixel (anode electrode) connected to the dummy pixel circuit. In Figure 8, one dummy subpixel is indicated by the code 513.

[0102] The configuration of the dummy pixel circuit 511 and the normal pixel circuits in the display area 125 are the same. The number of dummy pixel circuits 511 and normal pixel circuits in the display area 125 connected to the additional red data line XRT+1 is the same as the number of data lines in the display area 125. These may be different. Pixel circuits not connected to the additional red data line XRT+1 may be omitted, and subpixels including anode electrodes may be omitted.

[0103] The demultiplexer circuit 136 includes a circuit block for outputting a data signal to an additional red data line XRT+1. In one example, the demultiplexer circuit 136 may include a single demultiplexer block that has the additional red data line XRT+1 as its output destination. This reduces the loading difference within the demultiplexer circuit 136.

[0104] <Embodiment 2> In the configuration example described with reference to Figures 4, 5, and 8, the red pixel circuit, green pixel circuit, and blue pixel circuit have the same shape and occupied area. In the configuration example described below, the occupied area of ​​the green pixel circuit is larger than that of the red and blue pixel circuits. The luminous sensitivity of green is higher than that of red and blue, making brightness unevenness more noticeable. For example, output current deviation can be suppressed by increasing the holding capacitance of the green pixel circuit or by increasing the channel length of the driving TFT. By increasing the occupied area of ​​the green pixel circuit, a circuit configuration that suppresses brightness unevenness can be implemented.

[0105] Figure 9 shows an example of a circuit layout configuration, where the green pixel circuit occupies a larger area than the red and blue pixel circuits. One green pixel circuit is indicated by code 551G as an example, one red pixel circuit by code 551R as an example, and one blue pixel circuit by code 551B as an example.

[0106] All color pixel circuits 551R, 551G, and 551B have a common length LY in the Y direction. The red pixel circuit 551R and the blue pixel circuit 551B have a length LX1 in the X direction. Pixel circuit 551G has a length LX2 in the X direction. Length LX2 is greater than length LX1. Since the length in the Y direction is common to all pixel circuits, it is possible to avoid affecting control lines and power lines that extend in both the X and Y directions, including scan lines and anode power lines.

[0107] <Embodiment 3> Figure 10 shows another example of the circuit layout. The configuration example shown in Figure 10 is the same as the configuration example shown in Figure 5, but with the positions of the blue and green data lines swapped. The differences from the configuration example shown in Figure 5 will be explained below. Multiple data lines are arranged cyclically in the order of red data line, blue data line, and green data line. Figure 10 shows the red data lines XRt, XRt+1, the blue data line XBt, and the green data line XGt.

[0108] In each data line set, the data lines are arranged from left to right in the order of red data line, blue data line, and green data line. The configuration of the lead-out section between the red data line XRt and the red pixel circuit 431G is the same as in the example in Figure 5.

[0109] The blue data line XBt is connected to the blue pixel circuit 431B of the left pixel circuit row of the corresponding pixel circuit row pair by a lead-out section 571B1. The blue data line XBt is connected to the blue pixel circuit 431B of the right pixel circuit row of the corresponding pixel circuit row pair by a lead-out section 571B2. The lead-out sections connect the blue data line and the blue pixel circuit without crossing any data lines.

[0110] Green data line XGt This transmits a data signal to the green pixel circuit within the pixel circuit array pair that constitutes the corresponding main pixel array. The green data line XGt and the green pixel circuit 431G of the left pixel circuit array of the corresponding pixel circuit array pair are connected by a lead-out section 571G2. The green data line XGt and the green pixel circuit 431G of the right pixel circuit array of the corresponding pixel circuit array pair are connected by a lead-out section 571G1.

[0111] The green lead-out section 571G1 connects the green data line XGt and the green pixel circuit 431G without crossing any data lines. On the other hand, the green lead-out section 571G2 crosses the blue data line XBt.

[0112] In other configuration examples, the data line set may consist of data lines arranged from left to right in the order of blue data line, green data line, and red data line. In that configuration, the configurations of the red, blue, and green lead-out sections shown in Figure 10 can be applied to the blue, green, and red lead-out sections, respectively.

[0113] <Embodiment 4> The following describes the circuit layout of one embodiment of this specification. Referring to Figures 4, 5, and 8, in the backplate configuration example, only the red data line transmits the data signal to the red pixel circuit of a different pixel circuit array pair. In the configuration example described below, in addition to the red data line, the blue data line transmits the data signal to the blue pixel circuit of a different pixel circuit array pair. The red and blue data lines are the data lines at both ends of the data line set corresponding to the pixel circuit array pair. This prevents the blue lead from crossing over other data lines; that is, all lead can connect the pixel circuit and the data line without crossing over any other data line.

[0114] Figure 11 shows the circuit layout of one embodiment of this specification. The differences from the configuration example shown in Figure 5 will be mainly explained below. Figure 11 shows the data lines XBt-1, XRt, XGt, XBt, XRt+1, the pixel circuits within the main pixel row 461t, and the lead-out sections between them. The layout of the data lines and pixel circuits can be described with reference to Figure 5. The configuration of the lead-out sections differs from the example shown in Figure 5.

[0115] The connection between the red data lines XRt and XRt+1 and the red pixel circuit 431R, via the red lead-outs 471R1 and 471R2, is the same as in the example in Figure 5. Similarly, the connection between the green data line XGt and the green pixel circuit 431G, via the green lead-outs 471G1 and 471G2, can be explained using the same method as shown in Figure 5.

[0116] In the configuration example shown in Figure 11, the blue pixel circuit 431B of the leftmost pixel circuit in the pair of circuit arrays receives a data signal from the blue data line XBt-1 of the adjacent data line set. The blue data line XBt-1 is the blue data line closest to the pixel circuit array in question. The blue data line XBt-1 and the blue pixel circuit 431B of the leftmost pixel circuit array are connected by a lead-out section 472B2 that includes a switch TFT. The lead-out section 472B2 does not intersect with any other data lines.

[0117] The blue pixel circuit 431B in the right-hand pixel circuit row receives a data signal from the blue data line XBt of the data line set corresponding to that pixel circuit row pair. The blue data line XBt is the blue data line closest to that pixel circuit row. The blue data line XBt and the blue pixel circuit 431B in the right-hand pixel circuit row are connected by a lead-out section 471B1 which includes a switch TFT. The lead-out section 471B1 does not cross any other data lines.

[0118] The pixel circuit within the display area 125 is composed of multiple layout cells 440. Each layout cell 440 consists of two main pixel circuits and lead-out sections, and comprises a 3x2 pixel circuit and empty lead-out sections. The layout cell 440 includes lead-out sections extending to the left and right, which connect to the data lines of each data line set on either side of the corresponding data line set.

[0119] Figure 12 shows a wider area following the circuit layout shown in Figure 11. Figure 12 shows the blue data lines XBt-1 to XBt+3, the red data lines XRt to XRt+4, and the green data lines XGt to XGt+3. Figure 12 further shows the pixel circuit array of the main pixel array from column t to column t+3. As explained with reference to Figure 11, each pixel circuit is connected to a single data line of the same color via a lead-out. In Figure 12, the dashed lines extending in the Y direction with refraction indicate the boundaries of the layout cell patterns. The boundaries of the layout cell patterns have a nested shape.

[0120] For each data line, lead-out sections extending to the left and right are arranged alternately in the Y direction. As described above, a data line set consisting of adjacent red, green, and blue data lines is associated with a single principal pixel row, and the principal pixel row is controlled by a pair of pixel circuit rows consisting of adjacent pixel circuit rows. In this example, the data line set consists of the red data line at the left end, the blue data line at the right end, and the green data line in between them.

[0121] The green data lines are connected to the green pixel circuits of their corresponding pixel circuit array pairs via their lead-out sections. For example, the green data line XGt is connected to the green pixel circuit in the pixel circuit array pair of the main pixel array 461t. The same applies to the other green data lines XGt+1 to XGt+3.

[0122] The red data line transmits data signals to the red pixel circuit of the corresponding pixel circuit array pair and to the red pixel circuit of the adjacent pixel circuit array pair. In the configuration example shown in Figure 12, the red data line is connected via a lead-out to the red pixel circuit of the leftmost pixel circuit array of the corresponding pixel circuit array pair and to the red pixel circuit of the rightmost pixel circuit array of the pixel circuit array pair adjacent to the left. For example, the red data line XRt+1 transmits data signals to the pixel circuit array to the right of the main pixel array 461t and to the pixel circuit array to the left of the main pixel array 461t+1. The same applies to the other red data lines.

[0123] The blue data lines transmit data signals to the blue pixel circuits of the corresponding pixel circuit array pair and the blue pixel circuits of the adjacent pixel circuit array pair. In the configuration example shown in Figure 12, the blue data lines are connected via lead-outs to the blue pixel circuits of the rightmost pixel circuit array of the corresponding pixel circuit array pair and to the blue pixel circuits of the leftmost pixel circuit array of the adjacent pixel circuit array pair to the right. For example, the blue data line XBt+1 transmits data signals to the rightmost pixel circuit array of the main pixel array 461t+1 and to the leftmost pixel circuit array of the main pixel array 461t+2. The same applies to the other blue data lines.

[0124] As explained with reference to Figure 8 regarding the additional red data lines, the circuit layout in this example includes additional blue data lines outside the display area 125. For example, in Figure 12, if the main pixel row 461t is the leftmost main pixel row in the display area 125, then the blue data line XBt-1 is the additional blue data line outside the display area 125.

[0125] The additional blue data line XBt-1 is located on the opposite side of the display area 125 from the additional red data line. X Bt-1 does not belong to any data line set within the display area and is located outside of multiple data line sets. The blue pixel circuit in the leftmost pixel circuit row of the display area is an additional blue data line. X Data signals are supplied from Bt-1.

[0126] The additional blue data line XBt-1 may be connected to a dummy circuit, similar to the additional red data line described with reference to Figure 8. The description of the dummy circuit with reference to Figure 8 can be applied to the dummy circuit connected to the additional blue data line. The same applies to the description of the demultiplexer circuit.

[0127] As described above, blue or red pixel circuits are supplied with data signals from the nearest blue or red data line, between the blue or red data lines within their associated data line set and the blue or red data lines outside their associated data line set (including additional data lines). Green pixel circuits are supplied with data signals from the green data lines within their associated data line set. As a result, each pixel circuit is supplied with data signals from the nearest data line of the same color as the pixel circuit. This minimizes the area occupied by the lead-out section, including the switch TFT, and facilitates higher resolution pixels. Furthermore, crosstalk caused by capacitive coupling between the data lines and lead-out section and the holding capacitors inside the pixel circuit can also be minimized.

[0128] As described above, each pixel circuit within the display area 125 is connected via a lead-out to either a data line within the display area 125 or an additional data line. There is a one-to-one correspondence between these lead-outs and the pixel circuits.

[0129] Figure 13 shows an example configuration of a 1:2 demultiplexer circuit 136 that outputs data signals to the data lines shown in Figure 12. In this example configuration, the output terminal of the driver IC 134 sequentially outputs data signals to pixel circuits of the same color. This improves display quality.

[0130] The demultiplexer circuit 136 includes several switch TFTs 621-636. Switches TFTs 621 and 622 are connected to data line XBt-1. Switches TFTs 623 and 624 are connected to data line XRt. Switches TFTs 625 and 626 are connected to data line XGt. Switches TFTs 627 and 628 are connected to data line XBt.

[0131] Switches TFT629 and 630 are connected to data line XRt+1. Switches TFT631 and 632 are connected to data line XGt+1. Switches TFT633 and 634 are connected to data line XBt+1. Switches TFT635 and 636 are connected to data line XRt+2.

[0132] Switches TFT621, 624, 625, 627, and 636 are controlled ON / OFF by a selection signal from control terminal MUX1. Switches TFT622, 629, 631, and 634 are controlled ON / OFF by a selection signal from control terminal MUX2. Switches TFT626, 630, and 633 are controlled ON / OFF by a selection signal from control terminal MUX3. Switches TFT623, 628, 632, and 635 are controlled ON / OFF by a selection signal from control terminal MUX4.

[0133] Control terminals MUX1 to MUX4 output ON pulses sequentially and cyclically. Control terminals MUX1 and MUX2 output ON pulses sequentially within one horizontal period, and control terminals MUX3 and MUX4 output ON pulses sequentially within the next horizontal period.

[0134] The demultiplexer circuit 136 includes multiple demultiplexers, each of which sequentially receives a data signal from one output terminal of the driver IC 134 and outputs it to a selected data line. Each demultiplexer is connected to a different output terminal of the driver IC 134. The output of each demultiplexer is a set of data lines of a common color. Figure 13 shows, for example, a demultiplexer receiving a data signal from the output terminal OUT1n of the driver IC 134, indicated by a dashed line and reference numeral 611.

[0135] The output terminal OUT1n alternately outputs the data signals of the red pixel circuits of the main pixel row 461t and the main pixel row 461t+1. The demultiplexer 611 of the output terminal OUT1n is composed of switches TFT624, 629, 630, and 635. The demultiplexer 611 outputs the data signals from the output terminal OUT1n to the data lines selected sequentially from the red data lines XRt, XRt+1, and XRt+2.

[0136] The output terminal OUT2n alternately outputs the data signals from the green pixel circuits of the main pixel row 461t and the main pixel row 461t+1. The demultiplexer for output terminal OUT2n consists of switches TFT625, 626, 631, and 632. This demultiplexer outputs the data signal from output terminal OUT2n to the data line alternately selected from the green data lines XGt and XGt+1.

[0137] The output terminal OUT3n alternately outputs the data signals of the blue pixel circuits of the main pixel row 461t and the main pixel row 461t+1. The demultiplexer of output terminal OUT3n consists of switches TFT622, 627, 628, and 633. This demultiplexer outputs the data signals from output terminal OUT3n to the data lines selected sequentially from the blue data lines XBt-1, XBt, and XBt+1.

[0138] Output terminal OUT1n-1 alternately outputs data signals from the red pixel circuits of main pixel arrays 461t-2 and 461t-1. Output terminal OUT3n-1 alternately outputs data signals from the blue pixel circuits of main pixel arrays 461t-2 and 461t-1. Output terminal OUT1n+1 alternately outputs data signals from the red pixel circuits of main pixel arrays 461t+2 and 461t+3. Output terminal OUT3n+1 alternately outputs data signals from the blue pixel circuits of main pixel arrays 461t+2 and 461t+3.

[0139] Switch TFT621 turns the continuity between output terminal OUT3n-1 and data line XBt-1 ON / OFF. Switch TFT623 turns the continuity between output terminal OUT1n-1 and data line XRt ON / OFF. Switch TFT634 turns the continuity between output terminal OUT3n+1 and data line XBt+1 ON / OFF. Switch TFT636 turns the continuity between output terminal OUT1n+1 and data line XRt+2 ON / OFF.

[0140] Each green data line is connected to only one demultiplexer, which in turn connects to only one output terminal of the driver IC 134. For example, data lines XGt and XGt+1 each transmit data signals from output terminal OUT2n only.

[0141] The red data lines include data lines connected to only one demultiplexer and data lines connected to different demultiplexers. For example, data line XRt+1 is connected only to demultiplexer 611 and transmits data signals only from output terminal OUT1n.

[0142] On the other hand, data lines XRt and XRt+2 are connected to two demultiplexers, respectively, and transmit data signals from the two output terminals of the driver IC13. Data line XRt transmits data signals from output terminals Out1n-1 and Out1n. Data line XRt+2 transmits data signals from output terminals Out1n and Out1n+1.

[0143] The blue data lines include data lines connected to only one demultiplexer and data lines connected to different demultiplexers. For example, data line XRt+1 is connected only to demultiplexer 611 and transmits data signals only from output terminal OUT1n.

[0144] On the other hand, data lines XRt and XRt+2 are connected to two demultiplexers, respectively, and transmit data signals from the two output terminals of the driver IC13. Data line XRt transmits data signals from output terminals Out1n-1 and Out1n. Data line XRt+2 transmits data signals from output terminals Out1n and Out1n+1.

[0145] Furthermore, within a group of red data lines connected to a single demultiplexer, data lines connected to different demultiplexers are located at the ends of that group of red data lines. In the example in Figure 13, the group of red data lines connected to the demultiplexer of output terminal OUT1n are data lines XRt, XRt+1, and XRt+2. In this group, the data line XRt at the end is also connected to the demultiplexer of output terminal OUT1n-1. Additionally, the data line XRt+2 at the end is also connected to the demultiplexer of output terminal OUT1n+1.

[0146] Similarly, within a group of blue data lines connected to a single demultiplexer, data lines connected to different demultiplexers are located at the ends of that group of blue data lines. In the example in Figure 13, the group of blue data lines connected to the demultiplexer of output terminal OUT3n are data lines XBt-1, XBt, and XBt+1. In this group, the data line XBt-1 at the end is also connected to the demultiplexer of output terminal OUT3n-1. Furthermore, the data line XBt+1 at the end is also connected to the demultiplexer of output terminal OUT3n+1.

[0147] Although embodiments of the present invention have been described above, the present invention is not limited to the above embodiments. Those skilled in the art can easily modify, add to, or transform each element of the above embodiments within the scope of the present invention. It is possible to replace a part of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add the configuration of another embodiment to the configuration of one embodiment. [Explanation of Symbols]

[0148] 10 OLED display device, 41B blue subpixel, 41G green subpixel, 41R red subpixel, 42 subpixel row, 43 subpixel row, 51 primary pixel, 52 secondary pixel, 61 primary pixel row, 62 secondary primary pixel row, 63 primary pixel row, 100 TFT substrate, 114 cathode electrode formation area, 125 display area, 131 scanning driver, 132 emission driver, 133 protection circuit, 136 demultiplexer circuit

Claims

1. A display panel in which pixels of three colors, consisting of a first color, a second color, and a third color, are arranged in a delta nabla layout, Multiple pixel circuit arrays, Multiple data lines, Includes, The plurality of pixel circuit arrays extend in a first direction and are arranged in a second direction perpendicular to the first direction. Each of the aforementioned plurality of pixel circuit arrays is composed of the three colored pixel circuits arranged in a cyclic manner. Each of the three colored pixel circuits controls the light intensity of the pixel of the same color as the pixel circuit. The aforementioned plurality of pixel circuit arrays are composed of a plurality of pixel circuit array pairs, each consisting of two adjacent pixel circuit arrays. The plurality of data lines extend in the first direction and are arranged in the second direction. In the aforementioned plurality of data lines, the three colored data lines are arranged in a cyclical manner. Each of the aforementioned data lines transmits a data signal to a pixel circuit of the same color as the data line. The plurality of data lines consist of a plurality of data line sets and one or more additional data lines located outside the plurality of data line sets, including additional data lines of the first color. Each data line set of the plurality of data line sets consists of a first color data line, a second color data line, and a third color data line arranged in a continuous sequence. The plurality of pixel circuit array pairs are associated with different data line sets in the plurality of data line sets, Each pixel circuit of the first color in each of the plurality of pixel circuit array pairs receives a data signal from the closer first color data line, which is either a first color data line within the associated data line set or a first color data line outside the associated data line set that is adjacent to the third color data line in the associated data line set. Display panel.

2. A display panel according to claim 1, Each pixel circuit of the second color in each of the plurality of pixel circuit array pairs receives a data signal from the second color data line in the associated data line set. All or part of the third-color pixel circuits of each of the plurality of pixel circuit array pairs are supplied with data signals from the third-color data lines in the associated data line set. Display panel.

3. A display panel according to claim 1, In the three colors mentioned above, the area occupied by the pixel circuit of the color with the highest visual sensitivity is larger than the area occupied by the pixel circuits of the other two colors. Display panel.

4. A display panel according to claim 1, Each pixel circuit in the plurality of pixel circuit arrays is supplied with a data signal from the nearest data line of the same color as the pixel circuit. Display panel.

5. A display panel according to claim 1, The aforementioned additional first color data lines are connected to a plurality of dummy pixel circuits. Display panel.

6. A display panel according to claim 1, The one or more additional data lines further include additional data lines of a third color, which are positioned on the opposite side of the additional data lines of the first color, with respect to the set of data lines. Each pixel circuit of the second color in each of the plurality of pixel circuit array pairs receives a data signal from the second color data line in the associated data line set. Each pixel circuit of the third color in each of the plurality of pixel circuit array pairs receives a data signal from the closer data line of the third color, which is between the data line of the third color within the associated data line set and the data line of the third color outside the associated data line set. Display panel.

7. A display panel according to claim 6, The additional first color data lines and the additional third color data lines are each connected to a dummy pixel circuit. Display panel.

8. A display panel according to claim 1, The demultiplexer circuit further includes multiple demultiplexers, Each of the aforementioned demultiplexers outputs a data signal input from one input terminal to a data line selected sequentially from among the connected data lines. All outputs of each of the aforementioned demultiplexers are connected to data lines of the same color. Display panel.

9. A display panel according to claim 6, The demultiplexer circuit further includes multiple demultiplexers, Each of the aforementioned demultiplexers outputs a data signal input from one input terminal to a data line selected sequentially from among the connected data lines. All outputs of each of the aforementioned demultiplexers are connected to data lines of the same color. The first color data lines include data lines connected to only one demultiplexer and data lines connected to different demultiplexers. Each of the two data lines of the aforementioned second color is connected to only one demultiplexer. The third color data line includes data lines connected to only one demultiplexer and data lines connected to different demultiplexers. Display panel.

10. A display panel according to claim 9, In the group of data lines of the first color connected to one demultiplexer, the data lines connected to a different demultiplexer are located at the end of the group of data lines of the first color. In the group of third-color data lines connected to one demultiplexer, the data lines connected to a different demultiplexer are located at the ends of the group of third-color data lines. Display panel.

11. A display device, The display panel according to claim 1, The drive circuit and Includes, The aforementioned display panel is The demultiplexer circuit further includes multiple demultiplexers, Each of the multiple demultiplexers receives a data signal output from one of the output terminals of the drive circuit and outputs it to a data line selected sequentially from the multiple connected data lines. Display device.

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