Semiconductor device, power converter, and method for manufacturing a semiconductor device

Abstract

This semiconductor device comprises second-conductive-type first pillar regions (13) that are formed below a plurality of gate trenches (6) in which gate electrodes (8) are embedded, and first-conductive-type second pillar regions (14) that are formed between the adjacent first pillar regions (13) and have a peak impurity concentration higher than that of a drift layer (2). The second pillar regions (14) are each formed of a high-concentration region (14a) and a low-concentration region (14b) that is provided on at least one side of the second pillar region (14) and has a peak impurity concentration lower than that of the high-concentration region (14a).

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices, and more particularly to trench gate type semiconductor devices. [Background technology]

[0002] In power electronics equipment, it is necessary to switch between power supply and deactivation to drive loads such as electric motors. Therefore, switching elements such as silicon-based IGBTs (Insulated Gate Bipolar Transistors) or MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) are used.

[0003] Switching devices intended for use as power semiconductor devices often employ vertical MOSFETs and IGBTs, which are referred to as "vertical MOSFETs" and "vertical IGBTs," respectively. Furthermore, vertical MOSFETs and vertical IGBTs are classified into planar gate type and trench gate type depending on their gate structure.

[0004] In a trench-gate MOSFET having a trench (hereinafter referred to as "gate trench") in which the gate electrode is embedded in the active region of the first conductivity type (e.g., n-type) drift layer, due to its structure, a high electric field is applied to the gate insulating film at the bottom of the gate trench when it is off, and there is a risk that the gate insulating film at the bottom of the gate trench may be destroyed.

[0005] As a technique to solve this problem, for example, Patent Document 1 discloses a technique to mitigate the electric field applied to the gate insulating film on the bottom surface of a gate trench by providing a "trench bottom protective layer," which is an electric field relaxation region of a second conductivity type (e.g., p-type), so as to cover the bottom surface of the gate trench. Furthermore, Patent Document 1 also discloses a technique to reduce conduction loss during the ON state by providing a "depletion suppression layer," which is a current diffusion layer of a first conductivity type, on the side surface of the gate trench, thereby preventing the on-current path between the gate trenches from being narrowed by the trench bottom protective layer. The depletion suppression layer in Patent Document 1 is formed by implanting a first conductivity type impurity, which acts as a donor, into the side surface of the gate trench by gradient ion implantation. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Patent No. 6377309 [Overview of the project] [Problems that the invention aims to solve]

[0007] By extending the trench bottom protection layer and depletion suppression layer described above to the depths of the drift layer and utilizing them as the p-type pillar region and n-type pillar region of the semi-superjunction structure, it is possible to lower the resistance and increase the breakdown voltage of the trench gate type MOSFET. A semi-superjunction structure refers to a superjunction structure in which the p-type pillar region and n-type pillar region are formed to a certain depth within the semiconductor layer.

[0008] However, when forming n-type pillar regions as depletion suppression layers at shallow positions in gate trenches by gradient ion implantation, variations in the width and depth of the gate trenches result in many donors (n-type dopants) being injected into the p-type pillar regions, which act as trench bottom protective layers. This makes it difficult to balance the charge between the p-type and n-type pillar regions, leading to variations in the breakdown voltage characteristics of the semiconductor device, and thus preventing the full benefits of low resistance and high breakdown voltage achieved by the semi-superjunction structure from being obtained.

[0009] This disclosure is made to solve the above-mentioned problems and aims to suppress the injection of a dopant from the second pillar region into the first pillar region below the gate trench in a semiconductor device having a semi-superjunction structure. [Means for solving the problem]

[0010] The semiconductor device according to this disclosure comprises a semiconductor layer, a drift layer of a first conductivity type formed on the semiconductor layer, a well region of a second conductivity type formed on the surface of the semiconductor layer, a source region of a first conductivity type formed on the surface of the well region, a source electrode electrically connected to the well region and the source region, a plurality of gate trenches penetrating the source region and the well region and in which gate electrodes are embedded via a gate insulating film, a first pillar region of a second conductivity type formed below the plurality of gate trenches, and a second pillar region of a first conductivity type formed between adjacent first pillar regions and having a higher impurity peak concentration than the drift layer, wherein the second pillar region is composed of a high-concentration region and a low-concentration region provided on at least one side of the second pillar region and having a lower impurity peak concentration than the high-concentration region, and the high-concentration region and the low-concentration region are at different depths from the surface of the semiconductor layer. Furthermore, the depth from the surface of the semiconductor layer at the lower end of the second pillar region is deeper than the depth at the lower end of the first pillar region. . [Effects of the Invention]

[0011] According to the semiconductor device of the present disclosure, it is possible to suppress the injection of the dopant in the second pillar region into the first pillar region below the gate trench. Therefore, it is possible to prevent the charge balance between the first pillar region and the second pillar region from being disrupted, and it can contribute to reducing the resistance and increasing the breakdown voltage by the semi-super junction structure.

[0012] The object, features, aspects, and advantages of the present disclosure will become clearer from the following detailed description and the accompanying drawings.

Brief Description of the Drawings

[0013] [Figure 1] It is a cross-sectional view schematically showing the structure of the semiconductor device according to Embodiment 1. [Figure 2] It is a cross-sectional view schematically showing the structure of the semiconductor device according to a modification of Embodiment !. [Figure 3] It is a cross-sectional view schematically showing the structure of the semiconductor device according to a modification of Embodiment 1. [Figure 4] It is a cross-sectional view schematically showing the structure of the semiconductor device according to a modification of Embodiment 1. [Figure 5] It is a cross-sectional view schematically showing the structure of the semiconductor device according to a modification of Embodiment 1. [Figure 6] It is a cross-sectional view schematically showing the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 7] It is a cross-sectional view schematically showing the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 8] It is a cross-sectional view schematically showing the manufacturing method of the semiconductor device according to Embodiment 1. [Figure 9] It is a plan view schematically showing the structure of the semiconductor device according to Embodiment 2. [Figure 10] It is a cross-sectional view along the line A1 - A2 in FIG. 9. [Figure 11] It is a cross-sectional view along the line B1 - B2 in FIG. 9. [Figure 12] It is a cross-sectional view along the line C1 - C2 in FIG. 9. [Figure 13]This is a schematic cross-sectional view showing the structure of a semiconductor device according to Embodiment 3. [Figure 14] This is a schematic plan view showing the structure of a semiconductor device according to Embodiment 4. [Figure 15] This is a cross-sectional view along the line A1-A2 in Figure 14. [Figure 16] This is a cross-sectional view along the line B1-B2 in Figure 14. [Figure 17] This is a cross-sectional view along the line C1-C2 in Figure 14. [Figure 18] This is a block diagram showing the configuration of the power conversion system according to Embodiment 5. [Modes for carrying out the invention]

[0014] Embodiments of the technology relating to this disclosure will be described below with reference to the drawings. Note that the drawings are schematic representations, and the relative sizes and positions of components shown in different drawings are not necessarily accurately described and may be modified as appropriate. Furthermore, the same reference numerals are used for identical or corresponding components in different drawings, and redundant explanations for them may be omitted. Also, terms such as "top," "bottom," "side," "bottom," "front," or "back" used in the description to indicate position or direction are used for convenience to facilitate understanding and do not necessarily represent the position or direction in actual use.

[0015] Furthermore, in the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but conversely, the first conductivity type may be p-type and the second conductivity type may be n-type.

[0016] <Embodiment 1> Figure 1 is a schematic cross-sectional view showing the structure of a semiconductor device according to Embodiment 1. In Embodiment 1, a vertical trench-gate silicon carbide MOSFET is shown as an example of a semiconductor device. The semiconductor device according to Embodiment 1 has an active region formed by arranging MOSFET cells (active unit cells) and a terminal region outside the active region, and Figure 1 shows the configuration of the active region.

[0017] The semiconductor device according to Embodiment 1 is formed using an n-type (first conductivity type) semiconductor substrate 1 made of silicon carbide having a 4H polytype. A semiconductor layer 20 made of silicon carbide is formed on the semiconductor substrate 1. The upper surface of the semiconductor substrate 1 is a (0001) plane having an off-angle θ tilted in the [11-20] axis direction. The off-angle θ may be 10° or less. An n-type drift layer 2 with a lower impurity peak concentration than that of the semiconductor substrate 1 is formed on the semiconductor layer 20.

[0018] In the active region, a p-type (second conductivity type) well region 3 is formed on the surface of the semiconductor layer 20. On the surface of the well region 3, an n-type source region 4 and a p-type well contact region 5 with a higher impurity peak concentration than the well region 3 are selectively (i.e., partially) formed. The well contact region 5 is provided in contact with the source region 4 and electrically connects the source electrode 10 (described later) and the well region 3.

[0019] Furthermore, a gate trench 6 is formed in the semiconductor layer 20 so as to penetrate the source region 4 and the well region 3. A gate insulating film 7 is formed on the sides and bottom of the gate trench 6. A gate electrode 8 is formed on the gate insulating film 7 so as to be embedded in the gate trench 6. The upper surface of the gate electrode 8 is located deeper than the surface of the semiconductor layer 20. That is, the upper surface of the gate electrode 8 is located deeper than the upper end of the gate trench 6. An interlayer insulating film 9 is formed in the upper part of the gate trench 6 so as to cover the gate electrode 8.

[0020] In this embodiment, since the gate trench 6 penetrates the source region 4, the edge portion of the gate trench 6 in the semiconductor layer 20 becomes the source region 4. However, no gate electrode 8 is formed at the upper end of the gate trench 6, and the gate insulating film 7 in that portion is covered by the interlayer insulating film 9. Therefore, at the edge portion of the gate trench 6, the source region 4 and the gate electrode 8 do not face each other.

[0021] A source electrode 10 is formed on the semiconductor layer 20. The source electrode 10 is electrically connected to the source region 4 and the well region 3. In this embodiment, a silicide layer 15 is formed on the surfaces of the source region 4 and the well contact region 5, and a barrier metal 16 is provided on the bottom surface of the source electrode 10. Therefore, the source electrode 10 is connected to the source region 4 and the well contact region 5 via the silicide layer 15 and the barrier metal 16. Furthermore, a drain electrode 11 is formed on the bottom surface of the semiconductor substrate 1, which is electrically connected to the semiconductor substrate 1.

[0022] A p-type trench bottom protection layer 12 is formed at the bottom of the gate trench 6 in the semiconductor layer 20. The trench bottom protection layer 12 is electrically connected to the source electrode 10. The trench bottom protection layer 12 functions to mitigate the electric field applied to the bottom and sides of the gate trench 6 when the MOSFET is off. It is desirable that the trench bottom protection layer 12 is in contact with the gate trench 6.

[0023] The semiconductor layer 20 has a semi-superjunction structure in which p-type pillar regions 13, which are p-type first pillar regions, and n-type pillar regions 14, which are n-type second pillar regions, are arranged alternately. The p-type pillar regions 13 are formed below the trench bottom protective layer 12, and the n-type pillar regions 14 are formed between adjacent p-type pillar regions 13.

[0024] In this embodiment, the n-type pillar region 14 is composed of a high-concentration n-type pillar region 14a and a low-concentration n-type pillar region 14b (for ease of illustration, the high-concentration n-type pillar region 14a in each figure is hatched with a grain pattern). The peak concentration of impurities in the high-concentration n-type pillar region 14a is higher than the peak concentration of impurities in the low-concentration n-type pillar region 14b. The low-concentration n-type pillar region 14b is located in at least a part of the side of the n-type pillar region 14 (i.e., the part in contact with the p-type pillar region 13). Hereinafter, the side of the n-type pillar region 14 may also be referred to as the "side of the high-concentration n-type pillar region 14a".

[0025] Since the n-type pillar region 14 is sandwiched between two p-type pillar regions 13, the n-type pillar region 14 has two sides. The low-concentration n-type pillar region 14b is formed on at least one of the two sides of the n-type pillar region 14. That is, the high-concentration n-type pillar region 14a may be provided only on one side of the high-concentration n-type pillar region 14a.

[0026] Furthermore, in Figure 1, the width of the top and bottom of the low-concentration n-type pillar region 14b are the same. However, as shown in Figure 2, for example, the top or side surface of the low-concentration n-type pillar region 14b may be inclined such that the width of the bottom of the low-concentration n-type pillar region 14b is wider than the width of the top.

[0027] As will be explained in more detail later, the structures of the high-concentration n-type pillar region 14a and the low-concentration n-type pillar region 14b shown in Figures 1 and 2 are formed by gradient ion implantation on both sides of the gate trench 6, that is, by ion implantation from a direction that is inclined with respect to the depth direction of the semiconductor layer 20.

[0028] However, the n-type pillar region 14, which consists of a high-concentration n-type pillar region 14a and a low-concentration n-type pillar region 14b, can also be formed by gradient ion implantation on one side of the gate trench 6. In that case, as shown in Figures 3, 4, or 5, the bottom of the n-type pillar region 14 is sloped, and the depth of the n-type pillar region 14 becomes asymmetrical. Figure 3 is an example in gradient ion implantation where a high-concentration impurity is implanted from the side of the gate trench 6, which is the implantation surface, to an intermediate position between it and the adjacent gate trench 6 to form a low-concentration n-type pillar region 14b. Figure 4 is an example in gradient ion implantation where a high-concentration impurity is implanted from the side of the gate trench 6, which is the implantation surface, to a deep position (near the trench bottom protective layer 12 and the p-type pillar region 13 below the adjacent gate trench 6) to form a low-concentration n-type pillar region 14b. Figure 5 shows an example in which a high concentration of impurities is implanted at a shallow position from the side of the gate trench 6, which is the implantation surface for gradient ion implantation (near the trench bottom protective layer 12 and the p-type pillar region 13 below the gate trench 6) to form a low concentration n-type pillar region 14b.

[0029] Regarding the positional relationship between the p-type pillar region 13 and the n-type pillar region 14 in the depth direction from the upper surface of the semiconductor layer 20, in order to avoid current constriction between adjacent p-type pillar regions 13, it is desirable that the lower end of the high-density n-type pillar region 14a or the low-density n-type pillar region 14b be at the same depth as the lower end of the p-type pillar region 13, or even deeper.

[0030] Furthermore, it is desirable that the p-type pillar region 13 and the n-type pillar region 14 are formed to a depth greater than the distance between adjacent gate trenches 6, or greater than the distance between adjacent p-type pillar regions 13, relative to the position of the bottom of the gate trench 6. In other words, it is desirable that the depth from the bottom of the gate trench 6 to the lower end of the p-type pillar region 13, and the depth from the bottom of the gate trench 6 to the lower end of the n-type pillar region 14, be greater than the distance between adjacent gate trenches 6, or the distance between adjacent p-type pillar regions 13.

[0031] Hereinafter, a method for manufacturing a semiconductor device according to Embodiment 1 shown in FIG. 1 will be described.

[0032] First, a semiconductor layer 20 made of n-type silicon carbide having a relatively high resistance n-type (n - -type) is epitaxially grown on the surface of an n-type semiconductor substrate 1 having a 4H polytype. At this time, the semiconductor layer 20 may be formed so as to have an n-type impurity concentration of 1×10 14 [cm -3 or more and 1×10 17 [cm -3 or less.

[0033] Next, an alignment mark is formed on the semiconductor layer 20 by reactive ion etching (RIE: Reactive Ion Etching). This alignment mark may be formed simultaneously with the gate trench 6.

[0034] Thereafter, based on the alignment mark, a p-type well region 3 and a relatively low resistance n-type (n + -type) source region 4 are formed in the surface layer portion of the semiconductor layer 20 by ion implantation. As an implantation mask for selectively forming the source region 4 by ion implantation, for example, a resist mask or the like can be used.

[0035] The source region 4 has an n-type impurity concentration of 5×10 18 [cm -3 or more and 5×10 20 [cm -3 or less, and the well region 3 may be formed so as to have a p-type impurity concentration of 1×10 16 [cm -3 or more and 3×10 19 [cm -3 or less. In order to form the source region 4 in the surface layer portion of the well region 3, the n-type impurity concentration of the source region 4 is set to be higher than the p-type impurity concentration of the well region 3. At this time, an n-type region in the semiconductor layer 20 where the well region 3 and the source region 4 are not formed remains as the drift layer 2.

[0036] The impurity concentration in well region 3 may or may not be constant in the depth direction. For example, the distribution may be such that the concentration is lower at the surface of well region 3, or it may be such that there is a peak in the deeper parts.

[0037] Next, a p-type well contact region 5 is formed by ion implantation. At this time, the well contact region 5 is 1 × 10 19 [cm -3 ] Above 1 x 10 22 [cm -3 It is sufficient if it is formed to have the following p-type impurity concentrations.

[0038] Next, an etching mask 18 (see Figure 6) with a pattern in which the gate trench 6 formation region is opened is formed on the semiconductor layer 20, and a gate trench 6 that penetrates the well region 3 and reaches the drift layer 2 is formed in the semiconductor layer 20 by RIE using the etching mask 18.

[0039] Next, as shown in Figure 6, a p-type trench bottom protective layer 12 and a p-type pillar region 13 are formed on the bottom surface of the gate trench 6 by ion implantation using the etching mask 18 as an implantation mask. At this time, the trench bottom protective layer 12 is 1 × 10 17 [cm -3 ] Above 1 x 10 20 [cm -3 It is sufficient that the p-type impurity concentration is as follows, and the p-type pillar region 13 is 1 × 10 16 [cm -3 ] Above 1 x 10 18 [cm -3 It is sufficient if it is formed to have the following p-type impurity concentrations.

[0040] After removing the etching mask 18, an n-type pillar region 14 consisting of a high-concentration n-type pillar region 14a and a low-concentration n-type pillar region 14b is formed beneath the mesa-like semiconductor layer 20 between the gate trenches 6 by gradient ion implantation. Specifically, as shown in Figure 7, first, a low-concentration n-type pillar region 14b is formed beneath the mesa-like semiconductor layer 20 by implanting n-type impurities into one side of the gate trench 6 by gradient ion implantation. Furthermore, as shown in Figure 8, a low-concentration n-type pillar region 14b is formed beneath the mesa-like semiconductor layer 20 by implanting n-type impurities into the other side of the gate trench 6 by gradient ion implantation. A high-concentration n-type pillar region 14a is formed in the region where the impurities are implanted in layers by these two gradient ion implantations.

[0041] In gradient ion implantation for forming high-concentration n-type pillar regions 14a and low-concentration n-type pillar regions 14b, it is important to implant n-type impurities from the side of each gate trench 6 to the vicinity of the trench bottom protective layer 12 and the p-type pillar region 13 below the adjacent gate trench 6.

[0042] Furthermore, in this gradient ion implantation, the lower surface of the gate trench 6 is in the shadow of the mesa-shaped semiconductor layer 20, thus suppressing the implantation of n-type impurities into the lower surface of the gate trench 6. This suppresses the implantation of donors into the trench bottom protective layer 12 and the p-type pillar region 13 below the gate trench 6, enabling a stable charge balance. Structurally, the concentration of n-type impurities in the p-type pillar region 13 is lower than the concentration of n-type impurities in the low-concentration n-type pillar region 14b.

[0043] The high-concentration n-type pillar region 14a is 1 × 10 15 [cm -3 ] 5 x 10 18 [cm -3 It is sufficient that it is formed to have the following n-type impurity concentrations, and the low-concentration n-type pillar region 14b is 5 × 10 14 [cm -3 ] Above 1 x 10 18 [cm -3It is sufficient if it is formed to have the following n-type impurity concentrations.

[0044] Subsequently, annealing is performed at a temperature range of 1500°C to 2200°C for a period of 0.5 minutes to 60 minutes to activate the implanted ions.

[0045] Furthermore, an insulating film is formed on the surface of the semiconductor layer 20 by thermal oxidation or chemical vapor deposition (CVD), and a field insulating film (not shown) for protecting the terminal region is formed by patterning the insulating film with wet etching or dry etching.

[0046] Next, a gate insulating film 7 is formed on the surface of the semiconductor layer 20, including the interior of the gate trench 6, by a method such as thermal oxidation or CVD.

[0047] Next, polysilicon doped with impurities, which is the material for the gate electrode 8, is formed on the entire surface of the semiconductor layer 20 on which the gate insulating film 7 is formed, using a CVD method or the like. At this time, the inside of the gate trench 6 is filled with polysilicon. When polysilicon is formed by the CVD method, polysilicon grows not only upward from the bottom surface of the gate trench 6 but also laterally, so the gate trench 6 can be filled with polysilicon relatively easily.

[0048] Next, the polysilicon on the surface of the semiconductor layer 20 is removed by etch-back. At this time, the polysilicon embedded in the gate trench 6 remains and becomes the gate electrode 8. Note that if the polysilicon on the surface of the semiconductor layer 20 is to be completely removed, a certain amount of over-etching will be necessary, so the upper surface of the gate electrode 8 in the gate trench 6 will be located deeper than the upper end of the gate trench 6.

[0049] Next, an interlayer insulating film 9 is formed to cover the terminal region and the gate electrode 8, and the source region 4 and the well contact region 5 are exposed from the interlayer insulating film 9 by dry etching or the like. Then, a silicide layer 15 is formed on top of the well contact region 5 and the n-type source region 4. Furthermore, a gate contact hole (not shown) reaching the gate electrode 8 is formed in the interlayer insulating film 9 by dry etching or wet etching or the like.

[0050] Subsequently, a source electrode 10 is formed on the semiconductor layer 20. A gate pad or wiring for connecting to the gate pad is also formed, which connects to the gate insulating film 7 through the gate contact hole.

[0051] Finally, by forming the drain electrode 11 on the lower surface of the semiconductor substrate 1, the semiconductor device with the structure shown in Figure 1 is completed.

[0052] The following describes the effects of the semiconductor device according to Embodiment 1.

[0053] First, let's discuss the effect of the trench bottom protective layer 12. By providing the trench bottom protective layer 12 below the gate trench 6, the electric field applied to the gate insulating film 7 when the MOSFET is in the off state can be significantly reduced.

[0054] Next, we will discuss the effects of the p-type pillar region 13 and the n-type pillar region 14 (high-concentration n-type pillar region 14a, low-concentration n-type pillar region 14b). By providing the p-type pillar region 13 and the n-type pillar region 14 deep within the drift layer 2, and by balancing the charge between the p-type pillar region 13 and the n-type pillar region 14 while increasing their impurity concentrations compared to the drift layer 2, a superjunction effect can be obtained. That is, when the semiconductor device is off, a depletion layer extends laterally between the p-type pillar region 13 and the n-type pillar region 14, allowing the regions of the p-type pillar region 13 and the n-type pillar region 14 to share a larger electric field than the drift layer 2, thus contributing to higher voltage resistance of the semiconductor device. Furthermore, when the semiconductor device is on, the n-type pillar region 14, which has lower resistance than the drift layer 2, becomes the current path, thus contributing to lower on-resistance of the semiconductor device.

[0055] Here, we will describe the effects of the n-type pillar region 14 being composed of a high-concentration n-type pillar region 14a and a low-concentration n-type pillar region 14b. In the superjunction effect described above, the high-concentration n-type pillar region 14a functions as a lower-resistance current path when on, and the low-concentration n-type pillar region 14b functions as a higher voltage-resistant region when off, by making it easier to extend the depletion layer.

[0056] Furthermore, the effects of the method for forming the high-concentration n-type pillar region 14a and the low-concentration n-type pillar region 14b will be described. When the high-concentration n-type pillar region 14a and the low-concentration n-type pillar region 14b are formed by gradient ion implantation, the lower surface of the gate trench 6 is in the shadow of the mesa-shaped semiconductor layer 20, thereby suppressing the implantation of n-type impurities into the lower surface of the gate trench 6. As a result, the implantation of donors into the trench bottom protective layer 12 and the p-type pillar region 13 below the gate trench 6 is suppressed, and a stable charge balance can be achieved.

[0057] To obtain a higher superjunction effect, it is desirable that the p-type pillar region 13 and the n-type pillar region 14 be formed to a position deeper than the distance between adjacent gate trenches 6, or deeper than the distance between adjacent p-type pillar regions 13, with reference to the position of the bottom of the gate trench 6.

[0058] The cell structure formed within the active region of the semiconductor device can be any structure; for example, it may be a continuous stripe shape in plan view, or it may be partially grid-like or T-shaped in a way that forms bridges in the gate trench 6. It may also be partially polygonal or wave-shaped.

[0059] Furthermore, the crystal orientation of the side surface of gate trench 6 can be any crystal plane. That is, it can be any of the (11-20) plane, (-1120) plane, (1-100) plane, or (-1100) plane, and is not limited to any particular plane.

[0060] Furthermore, in Embodiment 1, the surface of the semiconductor substrate 1 was assumed to be a (0001) plane having an off-angle θ tilted in the [11-20] axis direction. However, even if the surface is a (000-1) plane having an off-angle θ tilted in the [11-20] axis direction, a trench gate type MOSFET with a similar structure can be fabricated, and the effects of Embodiment 1 can be obtained. Needless to say, other planes such as the (1-100) plane or the (03-38) plane may also be used.

[0061] Furthermore, the semiconductor device is not limited to MOSFETs. For example, if the conductivity type of the semiconductor substrate 1 is changed to p-type in the structure shown in Figure 1, or if the semiconductor substrate 1 is removed and a p-type impurity region is formed on the underside of the drift layer 2, it becomes an IGBT configuration. In this case, the source region 4 corresponds to the emitter region of the IGBT, and the drain electrode 11 corresponds to the collector electrode of the IGBT. Even if the semiconductor device is an IGBT, the same effects as in the case of a MOSFET can be obtained.

[0062] Embodiment 1 shows an example in which silicon carbide (SiC) is used as the semiconductor material constituting the semiconductor device, but other semiconductor materials may be used. Examples of semiconductor materials include silicon (Si) and wide-bandgap materials. Examples of wide-bandgap materials include SiC, Ga2O3, GaN (Gallium Nitride), and diamond.

[0063] Semiconductor devices using wide-bandgap materials are particularly expected to be used in high-temperature and high-voltage applications. Since the reliability of insulating films tends to decrease at high temperatures, applying Embodiment 1 is highly effective. Furthermore, as semiconductor devices achieve higher voltages, the voltage applied to the insulating film also increases, thus further enhancing the effectiveness of applying Embodiment 1.

[0064] Furthermore, it is known that silicon carbide semiconductor devices have more electron traps at the MOS interface between the gate insulating film 7 and the drift layer 2 compared to silicon (Si) semiconductor devices, resulting in lower reliability of the MOS interface and the gate insulating film 7 compared to silicon (Si) semiconductor devices. Therefore, applying Embodiment 1, which can reduce the electric field applied to the gate insulating film 7, is highly effective.

[0065] In Embodiment 1, n-type impurities are assumed to include nitrogen and phosphorus, while p-type impurities are assumed to include aluminum and boron.

[0066] <Embodiment 2> Figure 9 is a schematic plan view showing the structure of a trench gate type MOSFET as a semiconductor device according to Embodiment 2. Figure 10 is a cross-sectional view along line A1-A2 in Figure 9, Figure 11 is a cross-sectional view along line B1-B2 in Figure 9, and Figure 12 is a cross-sectional view along line C1-C2 in Figure 9.

[0067] In Embodiment 2, as shown in Figure 10, a p-shaped sidewall well region 17 is formed in a part of the sidewall of the gate trench 6. The sidewall well region 17 plays a role in electrically connecting the trench bottom protective layer 12 or the p-shaped pillar region 13 with the well region 3 or the well contact region 5.

[0068] Note that in Figure 9, some components are omitted from the illustration in order to more clearly show the arrangement of the side wall well region 17. Figures 10 to 12 show the cross-section of the periodic structure of the unit cell at a position in the active region that includes the gate trench 6 in its cross-section.

[0069] As shown in Figure 11, in the cross-section along the line B1-B2 in Figure 9, the sidewall well region 17 is not formed, but the well contact region 5 is formed. As shown in Figure 12, in the cross-section along the line C1-C2 in Figure 9, neither the sidewall well region 17 nor the well contact region 5 is formed, and the well region 3 reaches the surface of the semiconductor layer 20. Thus, the semiconductor device according to Embodiment 2 may have a cross-section in which there is no sidewall well region 17 but there is a well contact region 5, or a cross-section in which there is neither a sidewall well region 17 nor a well contact region 5.

[0070] Furthermore, two or more cells with the cross-sectional structures shown in Figures 10 to 12 may be mixed in one cross-section of the active region of the semiconductor device. In other words, the cross-sectional structures shown in Figures 10 to 12 may each be localized. Also, there are no restrictions on the proportion in which each of the cross-sectional structures shown in Figures 10 to 12 is arranged, and they can be freely designed.

[0071] A method for manufacturing the p-type sidewall well region 17 will be described. The sidewall well region 17 can be formed by injecting p-type impurities into the sidewall of the gate trench 6 by gradient ion implantation or the like after forming the gate trench 6. The sidewall well region 17 may be formed simultaneously with the trench bottom protective layer 12 or separately. The sidewall well region 17 is 1 × 10 17 [cm -3 ] Above 1 x 10 22 [cm -3It is sufficient if it is formed to have the following p-type impurity concentrations.

[0072] The effects of the sidewall well region 17 will now be explained. The sidewall well region 17 electrically connects the trench bottom protective layer 12 and the p-type pillar region 13 to the well region 3 or the well contact region 5. As a result, during the switching operation of the MOSFET, a current path is secured for charging and discharging the pn junction formed between the trench bottom protective layer 12 and the p-type pillar region 13 and the n-type pillar region 14 and the drift layer 2, thereby reducing switching losses. Since the sidewall well region 17 is formed only on a part of the sidewall of the gate trench 6, it does not cause a significant decrease in channel density, and as a result, the on-resistance can be reduced.

[0073] The gate trench 6 may be made into stripes parallel to the off-angle direction, and the gate trench 6 may have sidewalls where no sidewall well region 17 is formed. In this case, an inverted channel with uniform channel characteristics is formed, which does not lead to current concentration on a specific channel plane or instability of the threshold voltage, and a device with high operational stability can be realized.

[0074] In Embodiment 2, as shown in Figures 9 and 10, an example is shown in which a sidewall well region 17 is provided only on one side wall of the gate trench 6. However, sidewall well regions 17 may be provided on both side walls of the gate trench 6, and there are no restrictions on the formation position of the sidewall well regions 17. However, if the spacing between the sidewall well regions 17 is too narrow, it may lead to a decrease in channel density. Therefore, it is preferable that the spacing between adjacent sidewall well regions 17 is the same as or greater than the spacing between adjacent gate trenches 6.

[0075] <Embodiment 3> Figure 13 is a schematic plan view showing the structure of a trench gate type MOSFET as a semiconductor device according to Embodiment 3. In the semiconductor device according to Embodiment 3, the trench bottom protective layer 12 is omitted, and the p-type pillar region 13 is formed to be in contact with the bottom of the gate trench 6. Therefore, in Embodiment 3, the p-type pillar region 13 takes on the role of the trench bottom protective layer 12, which mitigates the electric field applied to the bottom and sides of the gate trench 6.

[0076] According to Embodiment 3, the formation of the trench bottom protective layer 12 can be omitted, thus simplifying the manufacturing process and reducing the manufacturing cost of semiconductor devices. Furthermore, since the p-type pillar region 13 can mitigate the electric field applied to the bottom and sides of the gate trench 6 instead of the trench bottom protective layer 12, the same effects as in Embodiment 1 can be obtained.

[0077] <Embodiment 4> Figure 14 is a schematic plan view showing the structure of a trench gate type MOSFET as a semiconductor device of Embodiment 4. Figure 15 is a cross-sectional view along line A1-A2 in Figure 14, Figure 16 is a cross-sectional view along line B1-B2 in Figure 14, and Figure 17 is a cross-sectional view along line C1-C2 in Figure 14.

[0078] In Embodiment 4, as shown in Figure 14, the well contact region 5 is formed in a line shape perpendicular to the gate trench 6. In other words, the well contact region 5 extends across the mesa-shaped semiconductor layer 20 between adjacent gate trenches 6 so as to be in contact with both of them.

[0079] Furthermore, in Embodiment 4, the technology of Embodiment 2 is applied, and a side wall well region 17 is provided on a part of the side wall of the gate trench 6. The side wall well region 17 plays a role in electrically connecting the trench bottom protective layer 12 or the p-type pillar region 13 with the well region 3 or the well contact region 5.

[0080] As shown in Figure 15, in the cross-section along line A1-A2 in Figure 14, the sidewall well region 17 is formed to be in contact with the well contact region 5. As shown in Figure 16, in the cross-section along line B1-B2 in Figure 14, the sidewall well region 17 is not formed, but the well contact region 5 is formed. As shown in Figure 17, in the cross-section along line C1-C2 in Figure 9, neither the sidewall well region 17 nor the well contact region 5 is formed, and the well region 3 reaches the surface of the semiconductor layer 20.

[0081] For example, if the well contact area 5 is island-shaped, as shown in the plan view of Figure 9 in Embodiment 2, misalignment during the photoengraving process may cause the position of the well contact area 5 to shift relative to the gate trench 6, potentially leading to variations in channel characteristics.

[0082] In contrast, in Embodiment 4, since the well contact region 5 is in the shape of a line perpendicular to the gate trench 6, even if there is a misalignment in the photoengraving process, it does not affect the position of the well contact region 5 relative to the gate trench 6, thus preventing variations in channel characteristics.

[0083] Furthermore, since the sidewall well region 17 electrically connects the trench bottom protective layer 12 and the p-type pillar region 13 to the well contact region 5, a current path is secured for charging and discharging the pn junction formed between the trench bottom protective layer 12 and the p-type pillar region 13 and the n-type pillar region 14 and the drift layer 2 during the switching operation of the MOSFET, thereby reducing switching losses.

[0084] <Embodiment 5> Figure 18 is a block diagram showing the configuration of a power conversion system to which the power conversion device according to Embodiment 5 is applied. The power conversion system shown in Figure 18 consists of a power supply 100, a power conversion device 200, and a load 300. The power supply 100 is a DC power supply and supplies DC power to the power conversion device 200. The power supply 100 can be made up of various things, for example, a DC grid, a solar cell, a storage battery, or a rectifier circuit and AC / DC converter connected to an AC grid. Alternatively, the power supply 100 may be made up of a DC / DC converter that converts DC power output from a DC grid into a predetermined power.

[0085] The power converter 200 is a three-phase inverter connected between the power supply 100 and the load 300. It converts the DC power supplied from the power supply 100 into AC power and supplies AC power to the load 300. As shown in Figure 18, the power converter 200 includes a main conversion circuit 201 that converts DC power into AC power and outputs it, a drive circuit 202 that outputs drive signals to drive each switching element of the main conversion circuit 201, and a control circuit 203 that outputs control signals to the drive circuit 202 to control the drive circuit 202.

[0086] Load 300 is a three-phase motor driven by AC power supplied from power converter 200. Note that Load 300 is not limited to a specific application; it is a motor installed in various electrical devices, such as hybrid vehicles, electric vehicles, railway vehicles, elevators, or air conditioning equipment.

[0087] The details of the power converter 200 are described below. The main conversion circuit 201 is equipped with switching elements and freewheeling diodes (not shown), and by switching the switching elements, it converts the DC power supplied from the power supply 100 into AC power and supplies it to the load 300. There are various specific circuit configurations for the main conversion circuit 201, but the main conversion circuit 201 according to this embodiment is a two-level three-phase full-bridge circuit and can be composed of six switching elements and six freewheeling diodes antiparallel to each switching element. Each switching element of the main conversion circuit 201 is a semiconductor device according to any of the embodiments 1 to 4 described above or their modifications. The six switching elements are connected in series in pairs to form upper and lower arms, and each upper and lower arm constitutes each phase (U phase, V phase, W phase) of the full-bridge circuit. The output terminals of each upper and lower arm, i.e., the three output terminals of the main conversion circuit 201, are connected to the load 300.

[0088] The drive circuit 202 generates drive signals to drive the switching elements of the main conversion circuit 201 and supplies them to the control electrodes of the switching elements of the main conversion circuit 201. Specifically, according to the control signal from the control circuit 203, which will be described later, it outputs drive signals to turn on the switching elements and drive signals to turn off the switching elements to the control electrodes of each switching element. When the switching elements are kept in the ON state, the drive signal is a voltage signal (ON signal) that is greater than or equal to the threshold voltage of the switching elements, and when the switching elements are kept in the OFF state, the drive signal is a voltage signal (OFF signal) that is less than the threshold voltage of the switching elements.

[0089] The control circuit 203 controls the switching elements of the main converter circuit 201 so that the desired power is supplied to the load 300. Specifically, it calculates the time (on time) that each switching element of the main converter circuit 201 should be in the ON state based on the power to be supplied to the load 300. For example, the main converter circuit 201 can be controlled by PWM control, which modulates the on time of the switching elements according to the voltage to be output. Then, it outputs a control command (control signal) to the drive circuit 202 so that an ON signal is output to the switching elements that should be in the ON state at each point in time, and an OFF signal is output to the switching elements that should be in the OFF state. The drive circuit 202 outputs an ON signal or an OFF signal as a drive signal to the control electrode of each switching element according to this control signal.

[0090] In the power conversion device according to this embodiment, since the semiconductor devices according to Embodiments 1 to 4 are used as switching elements in the main conversion circuit 201, a low-loss power conversion device can be realized.

[0091] In this embodiment, an example of applying the semiconductor device according to Embodiments 1 to 4 to a two-level three-phase inverter has been described, but it is not limited to this and can be applied to various power conversion devices. In this embodiment, a two-level power conversion device is used, but it may also be a three-level or multi-level power conversion device, or it may be applied to a single-phase inverter when supplying power to a single-phase load. Furthermore, when supplying power to a DC load, it can also be applied to a DC / DC converter or an AC / DC converter.

[0092] Furthermore, the power conversion device using the semiconductor device according to Embodiments 1 to 4 is not limited to cases where the load is an electric motor, but can also be used, for example, as a power supply device for an electrical discharge machine, a laser processing machine, an induction cooker, or a non-contact power supply system, and can even be used as a power conditioner for a solar power generation system or an energy storage system.

[0093] Furthermore, it is possible to freely combine each embodiment, or to modify or omit each embodiment as appropriate.

[0094] The above description is illustrative in all embodiments, and it should be understood that countless variations not illustrated are conceivable. [Explanation of symbols]

[0095] 1 Semiconductor substrate, 2 Drift layer, 3 Well region, 4 Source region, 5 Well contact region, 6 Gate trench, 7 Gate insulating film, 8 Gate electrode, 9 Interlayer insulating film, 10 Source electrode, 11 Drain electrode, 12 Trench bottom protective layer, 13 p-type pillar region, 14 n-type pillar region, 14a High-density n-type pillar region, 14b Low-density n-type pillar region, 15 Silicide layer, 16 Barrier metal, 17 Sidewall well region, 18 Etching mask, 20 Semiconductor layer, 100 Power supply, 200 Power converter, 201 Main conversion circuit, 202 Drive circuit, 203 Control circuit, 300 Load.

Claims

1. Semiconductor layer, A first conductivity type drift layer formed on the semiconductor layer, A second conductivity type well region formed on the surface of the semiconductor layer, A first conductivity type source region formed on the surface of the well region, A source electrode electrically connected to the well region and the source region, Multiple gate trenches penetrate the source region and the well region, and gate electrodes are embedded via a gate insulating film, A second conductivity type first pillar region formed below the multiple gate trenches, A second pillar region of a first conductivity type is formed between adjacent first pillar regions and has a higher peak concentration of impurities than the drift layer, Equipped with, The second pillar region is composed of a high-concentration region and a low-concentration region provided on at least one side of the second pillar region, in which the peak concentration of impurities is lower than that of the high-concentration region. The high-concentration region and the low-concentration region differ in depth from the surface of the semiconductor layer. The depth from the surface of the semiconductor layer at the lower end of the second pillar region is greater than the depth at the lower end of the first pillar region. Semiconductor equipment.

2. Semiconductor layer, A first conductivity type drift layer formed on the semiconductor layer, A second conductivity type well region formed on the surface of the semiconductor layer, A first conductivity type source region formed on the surface of the well region, A source electrode electrically connected to the well region and the source region, Multiple gate trenches penetrate the source region and the well region, and gate electrodes are embedded via a gate insulating film, A second conductivity type first pillar region formed below the multiple gate trenches, A second pillar region of a first conductivity type is formed between adjacent first pillar regions and has a higher peak concentration of impurities than the drift layer, Equipped with, The second pillar region is composed of a high-concentration region and a low-concentration region provided on at least one side of the second pillar region, in which the peak concentration of impurities is lower than that of the high-concentration region. The high-concentration region and the low-concentration region differ in depth from the surface of the semiconductor layer. The depth from the bottom of the gate trench to the lower end of the first pillar region is longer than the distance between adjacent gate trenches. Semiconductor equipment.

3. Semiconductor layer, A first conductivity type drift layer formed on the semiconductor layer, A second conductivity type well region formed on the surface of the semiconductor layer, A first conductivity type source region formed on the surface of the well region, A source electrode electrically connected to the well region and the source region, Multiple gate trenches penetrate the source region and the well region, and gate electrodes are embedded via a gate insulating film, A second conductivity type first pillar region formed below the multiple gate trenches, A second pillar region of a first conductivity type is formed between adjacent first pillar regions and has a higher peak concentration of impurities than the drift layer, Equipped with, The second pillar region is composed of a high-concentration region and a low-concentration region provided on at least one side of the second pillar region, in which the peak concentration of impurities is lower than that of the high-concentration region. The high-concentration region and the low-concentration region differ in depth from the surface of the semiconductor layer. The depth from the bottom of the gate trench to the lower end of the first pillar region is longer than the distance between adjacent first pillar regions. Semiconductor equipment.

4. The gate trench is further provided with a second conductive trench bottom protective layer formed at the bottom of the gate trench, having a higher peak impurity concentration than the first pillar region. The first pillar region is formed below the trench bottom protective layer, The semiconductor device according to any one of claims 1 to 3.

5. The low-concentration region is provided on both sides of the second pillar region. The semiconductor device according to any one of claims 1 to 3.

6. The concentration of the first conductivity type impurity contained in the first pillar region is lower than the concentration of the first conductivity type impurity contained in the low concentration region. The semiconductor device according to any one of claims 1 to 3.

7. The lower end of the low-concentration region is located deeper from the surface of the semiconductor layer than the lower end of the first pillar region. The semiconductor device according to any one of claims 1 to 3.

8. The well region is further provided with a second conductivity type well contact region formed on its surface so as to be in contact with the source region, and having a higher peak concentration of impurities than the well region. The semiconductor device according to any one of claims 1 to 3.

9. The well contact region is formed in the shape of a line perpendicular to the gate trench. The semiconductor device according to claim 8.

10. The gate trench is formed in part of the side wall and further comprises a second conductive type side wall well region for electrically connecting the trench bottom protective layer and the first pillar region with the source electrode, The semiconductor device according to claim 4.

11. The distance between adjacent side wall well regions is greater than or equal to the distance between adjacent gate trenches. The semiconductor device according to claim 10.

12. The well region is further provided with a second conductivity type well contact region formed on its surface so as to be in contact with the source region, and having a higher peak concentration of impurities than the well region. The side wall well region is in contact with the well contact region. The semiconductor device according to claim 10.

13. The well contact region is formed in the shape of a line perpendicular to the gate trench. The semiconductor device according to claim 12.

14. The gate trench is embedded with an interlayer insulating film covering the gate electrode. The semiconductor device according to any one of claims 1 to 3.

15. A semiconductor device according to any one of claims 1 to 3, comprising a main conversion circuit that converts and outputs input power, A drive circuit that outputs a drive signal to the semiconductor device to drive the semiconductor device, A control circuit that outputs a control signal to the drive circuit to control the drive circuit, A power conversion device equipped with this device.

16. A step of forming a semiconductor layer including a first-conductivity drift layer, The process of forming a second conductivity type well region on the surface of the semiconductor layer, The process involves forming a source region of a first conductivity type on the surface of the well region, A step of forming a plurality of gate trenches that penetrate the source region and the well region, A step of forming a first pillar region of a second conductivity type below a plurality of gate trenches, A step of forming a second pillar region of a first conductivity type having a higher impurity peak concentration than the drift layer between adjacent first pillar regions, A step of forming a gate electrode in a plurality of gate trenches via a gate insulating film, A step of forming a source electrode electrically connected to the well region and the source region, Equipped with, The second pillar region is composed of a high-concentration region and a low-concentration region provided on at least one side of the second pillar region, in which the peak concentration of impurities is lower than that of the high-concentration region. The formation of the high-concentration region and the low-concentration region is carried out by implanting impurities of a first conductivity type into the side surfaces of a plurality of gate trenches by ion implantation at an angle inclined with respect to the depth direction of the semiconductor layer. The high-concentration region and the low-concentration region differ in depth from the surface of the semiconductor layer. The depth from the surface of the semiconductor layer at the lower end of the second pillar region is greater than the depth at the lower end of the first pillar region. A method for manufacturing a semiconductor device.

17. A step of forming a semiconductor layer including a first-conductivity drift layer, The process of forming a second conductivity type well region on the surface of the semiconductor layer, The process involves forming a source region of a first conductivity type on the surface of the well region, A step of forming a plurality of gate trenches that penetrate the source region and the well region, A step of forming a first pillar region of a second conductivity type below a plurality of gate trenches, A step of forming a second pillar region of a first conductivity type having a higher impurity peak concentration than the drift layer between adjacent first pillar regions, A step of forming a gate electrode in a plurality of gate trenches via a gate insulating film, A step of forming a source electrode electrically connected to the well region and the source region, Equipped with, The second pillar region is composed of a high-concentration region and a low-concentration region provided on at least one side of the second pillar region, in which the peak concentration of impurities is lower than that of the high-concentration region. The formation of the high-concentration region and the low-concentration region is carried out by implanting impurities of a first conductivity type into the side surfaces of a plurality of gate trenches by ion implantation at an angle inclined with respect to the depth direction of the semiconductor layer. The high-concentration region and the low-concentration region differ in depth from the surface of the semiconductor layer. The depth from the bottom of the gate trench to the lower end of the first pillar region is longer than the distance between adjacent gate trenches. A method for manufacturing a semiconductor device.

18. A step of forming a semiconductor layer including a first-conductivity drift layer, The process of forming a second conductivity type well region on the surface of the semiconductor layer, The process involves forming a source region of a first conductivity type on the surface of the well region, A step of forming a plurality of gate trenches that penetrate the source region and the well region, A step of forming a first pillar region of a second conductivity type below a plurality of gate trenches, A step of forming a second pillar region of a first conductivity type having a higher impurity peak concentration than the drift layer between adjacent first pillar regions, A step of forming a gate electrode in a plurality of gate trenches via a gate insulating film, A step of forming a source electrode electrically connected to the well region and the source region, Equipped with, The second pillar region is composed of a high-concentration region and a low-concentration region provided on at least one side of the second pillar region, in which the peak concentration of impurities is lower than that of the high-concentration region. The formation of the high-concentration region and the low-concentration region is carried out by implanting impurities of a first conductivity type into the side surfaces of a plurality of gate trenches by ion implantation at an angle inclined with respect to the depth direction of the semiconductor layer. The high-concentration region and the low-concentration region differ in depth from the surface of the semiconductor layer. The depth from the bottom of the gate trench to the lower end of the first pillar region is longer than the distance between adjacent first pillar regions. A method for manufacturing a semiconductor device.

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