Nitride semiconductor device and method for manufacturing a nitride semiconductor device

Abstract

A nitride semiconductor device (10) comprises: an electron transit layer (16); an electron supply layer (18) formed on the electron transit layer (16); a gate layer (22) formed on the electron supply layer (18); a gate electrode (24) formed on the gate layer (22); an insulation layer (26) that covers the electron supply layer (18), the gate layer (22), and the gate electrode (24) and that includes a first opening section (26A) and a second opening section (26B); and a source electrode (28) and a drain electrode (30) that are in contact with the electron supply layer (18) via the first opening section (26A) and the second opening section (26B), respectively. The insulation layer (26) includes: a first insulation layer section (26P1) located on the electron supply layer (18); and a second insulation layer section (26P2) located on the gate electrode (24). A second thickness (D2) of the second insulation layer section (26P2) is greater than a first thickness (D1) of the first insulation layer section (26P1).

Description

Technical Field

[0001] The present disclosure relates to a nitride semiconductor device and a method for manufacturing the nitride semiconductor device.

Background Art

[0002] In recent years, high electron mobility transistors (hereinafter referred to as HEMTs) using a nitride semiconductor as the main material of an active region have been proposed, and their applications to power devices have been expanding. A nitride semiconductor is a semiconductor in which nitrogen is used as a group V element in a group III-V semiconductor. Compared with typical silicon carbide (SiC) power devices, power devices using a nitride semiconductor are recognized as devices that have a low on-resistance characteristic similar to that of SiC power devices and can operate at higher speeds and higher frequencies than SiC power devices.

[0003] For example, Patent Document 1 describes a HEMT having a gate portion including a GaN layer (p-type GaN layer) containing an acceptor-type impurity and a gate electrode formed on the p-type GaN layer.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In a HEMT, in order to reduce the switching time and enable high-frequency operation, it is desirable to reduce the input capacitance C iss and the total gate charge Q g However, in a HEMT as described in Patent Document 1, since the gate electrode is covered with the source electrode via a passivation film, the gate-source capacitance C gsSuch a gate-source capacitance C exists. gs The existence of input capacitance C iss and total gate charge Q g This leads to an increase in power consumption, reducing the switching speed and power efficiency of the HEMT. [Means for solving the problem]

[0006] A nitride semiconductor device according to one aspect of the present disclosure comprises: an electron transport layer made of a nitride semiconductor; an electron supply layer formed on the electron transport layer and made of a nitride semiconductor having a larger band gap than the electron transport layer; a gate layer formed on the electron supply layer and made of a nitride semiconductor containing acceptor-type impurities; a gate electrode formed on the gate layer; an insulating layer covering the electron supply layer, the gate layer, and the gate electrode, and having a first opening and a second opening; a source electrode in contact with the electron supply layer through the first opening; and a drain electrode in contact with the electron supply layer through the second opening. The gate layer is located between the first opening and the second opening. The source electrode includes a source field plate portion covering the insulating layer, and the source field plate portion includes an end portion located between the second opening and the gate layer in a plan view. The insulating layer includes a first insulating layer portion having a first thickness and in contact with the drain electrode and located on the electron supply layer, and a second insulating layer portion having a second thickness and in contact with the source field plate portion and located on the gate electrode. The end portion of the source field plate portion is located on the first insulating layer portion. The second thickness of the second insulating layer portion is greater than the first thickness of the first insulating layer portion.

[0007] A method for manufacturing a nitride semiconductor device according to one aspect of the present disclosure includes: forming an electron transport layer made of a nitride semiconductor; forming an electron supply layer made of a nitride semiconductor having a larger band gap than the electron transport layer on the electron transport layer; forming a gate layer made of a nitride semiconductor containing acceptor-type impurities on the electron supply layer; forming a gate electrode on the gate layer; forming an insulating layer covering the electron supply layer, the gate layer, and the gate electrode, and having a first opening and a second opening; forming a source electrode in contact with the electron supply layer through the first opening; and forming a drain electrode in contact with the electron supply layer through the second opening. The gate layer is located between the first opening and the second opening. The source electrode includes a source field plate portion covering the insulating layer, and the source field plate portion includes an end portion located between the second opening and the gate layer in a plan view. The insulating layer includes a first insulating layer portion having a first thickness and in contact with the drain electrode and located on the electron supply layer, and a second insulating layer portion having a second thickness and in contact with the source field plate portion and located on the gate electrode. The end portion of the source field plate portion is located on the first insulating layer portion. The second thickness of the second insulating layer portion is greater than the first thickness of the first insulating layer portion. [Effects of the Invention]

[0008] According to the nitride semiconductor device and method for manufacturing a nitride semiconductor device of this disclosure, the gate-source capacitance C gs This can be reduced. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a schematic plan view showing an exemplary formation pattern of the nitride semiconductor device shown in Figure 1. [Figure 3]Figure 3 is a schematic cross-sectional view showing an exemplary manufacturing process of the nitride semiconductor device shown in Figure 1. [Figure 4] Figure 4 is a schematic cross-sectional view showing the manufacturing process following Figure 3. [Figure 5] Figure 5 is a schematic cross-sectional view showing the manufacturing process following Figure 4. [Figure 6] Figure 6 is a schematic cross-sectional view showing the manufacturing process following Figure 5. [Figure 7] Figure 7 is a schematic cross-sectional view showing the manufacturing process following Figure 6. [Figure 8] Figure 8 is a graph showing the relationship between input capacitance and drain voltage of nitride semiconductor devices in Experimental Example 1 and Experimental Example 2. [Figure 9] Figure 9 is a graph showing the relationship between the total gate charge and gate voltage of the nitride semiconductor devices in Experimental Example 1 and Experimental Example 2. [Figure 10] Figure 10 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to a modified example of the first embodiment. [Figure 11] Figure 11 is a schematic cross-sectional view of an exemplary nitride semiconductor device according to the second embodiment. [Figure 12] Figure 12 is a schematic cross-sectional view showing an exemplary manufacturing process of the nitride semiconductor device shown in Figure 11. [Figure 13] Figure 13 is a schematic cross-sectional view showing the manufacturing process following Figure 12. [Figure 14] Figure 14 is a schematic cross-sectional view showing the manufacturing process following Figure 13. [Figure 15] Figure 15 is a schematic cross-sectional view showing the manufacturing process following Figure 14. [Figure 16] Figure 16 is a schematic cross-sectional view showing the manufacturing process following Figure 15. [Figure 17] Figure 17 is a schematic cross-sectional view showing the manufacturing process following Figure 16. [Figure 18] Figure 18 is a schematic cross-sectional view showing the manufacturing process following Figure 17. [Modes for carrying out the invention]

[0010] Hereinafter, some embodiments of nitride semiconductor devices in this disclosure will be described with reference to the attached drawings. For the sake of simplicity and clarity, the components shown in the drawings are not necessarily depicted to a consistent scale. Furthermore, hatching lines may be omitted in cross-sectional views for easier understanding. The accompanying drawings are merely illustrative of embodiments of this disclosure and should not be considered limiting.

[0011] The following detailed description includes apparatus, systems, and methods that embody exemplary embodiments of the present disclosure. This detailed description is for illustrative purposes only and is not intended to limit the embodiments of the present disclosure or the application and use of such embodiments.

[0012] [First Embodiment] Figure 1 is a schematic cross-sectional view of an exemplary nitride semiconductor device 10 according to the first embodiment. In this disclosure, the term "plan view" refers to viewing the nitride semiconductor device 10 in the Z-axis direction of the mutually orthogonal XYZ axes shown in Figure 1. Furthermore, in the nitride semiconductor device 10 shown in Figure 1, the +Z direction is defined as up, the -Z direction as down, the +X direction as right, and the -X direction as left. Unless explicitly stated otherwise, "plan view" refers to viewing the nitride semiconductor device 10 from above along the Z-axis.

[0013] The nitride semiconductor device 10 is a high electron mobility transistor (HEMT) using a nitride semiconductor. The nitride semiconductor device 10 includes a substrate 12, a buffer layer 14 formed on the substrate 12, an electron transport layer 16 formed on the buffer layer 14, and an electron supply layer 18 formed on the electron transport layer 16.

[0014] As the substrate 12, for example, a silicon (Si) substrate can be used. Alternatively, instead of the Si substrate, a silicon carbide (SiC) substrate, a gallium nitride (GaN) substrate, or a sapphire substrate can also be used. The thickness of the substrate 12 can be, for example, 200 μm or more and 1500 μm or less. In the following description, unless otherwise explicitly stated, the thickness refers to the dimension along the Z direction in FIG. 1.

[0015] The buffer layer 14 is located between the substrate 12 and the electron traveling layer 16 and can be composed of any material that can relax the lattice mismatch between the substrate 12 and the electron traveling layer 16. Further, the buffer layer 14 can include one or more nitride semiconductor layers. For example, it may include at least one of an aluminum nitride (AlN) layer, an aluminum gallium nitride (AlGaN) layer, and a graded AlGaN layer having different aluminum (Al) compositions. For example, the buffer layer 14 may be composed of a single film of AlN, a single film of AlGaN, a film having an AlGaN / GaN superlattice structure, a film having an AlN / AlGaN superlattice structure, or a film having an AlN / GaN superlattice structure.

[0016] In one example, the buffer layer 14 can include a first buffer layer that is an AlN layer formed on the substrate 12 and a second buffer layer that is an AlGaN layer formed on the AlN layer. The first buffer layer may be, for example, an AlN layer having a thickness of 200 nm, and the second buffer layer may be, for example, an AlGaN layer having a thickness of 100 nm. In order to suppress the leakage current in the buffer layer 14, impurities may be introduced into a part of the buffer layer 14 to make the region other than the surface layer region of the buffer layer 14 semi-insulating. In that case, the impurity is, for example, carbon (C) or iron (Fe), and the concentration of the impurity can be, for example, 4×10 16 cm -3 or more.

[0017] The electron transport layer 16 is composed of a nitride semiconductor, and for example, it may be a GaN layer. The thickness of the electron transport layer 16 can be, for example, 0.5 μm or more and 2 μm or less. In order to suppress the leakage current in the electron transport layer 16, impurities may be introduced into a part of the electron transport layer 16 to make the region other than the surface layer region of the electron transport layer semi-insulating. In that case, the impurity is, for example, C, and the concentration of the impurity can be, for example, 4×10 16 cm -3 or more. That is, the electron transport layer 16 can include a plurality of GaN layers with different impurity concentrations. In one example, it can include a C-doped GaN layer and an undoped GaN layer. In this case, the C-doped GaN layer is formed on the buffer layer 14 and can have a thickness of 0.5 μm or more and 2 μm or less. The C concentration in the C-doped GaN layer can be 5×10 17 cm -3 or more and 5×10 19 cm -3 or less. The undoped GaN layer is formed on the C-doped GaN layer and can have a thickness of 0.05 μm or more and 0.3 μm or less. The undoped GaN layer is in contact with the electron supply layer 18. In one example, the electron transport layer 16 includes an undoped GaN layer with a thickness of 0.1 μm and a C-doped GaN layer with a thickness of 0.9 μm, and the C concentration in the C-doped GaN layer is about 1×10 18 cm -3 is.

[0018] The electron supply layer 18 is composed of a nitride semiconductor having a larger bandgap than the electron transport layer 16, and for example, it may be an AlGaN layer. In a nitride semiconductor, the larger the Al composition, the larger the bandgap. Therefore, the electron supply layer 18 which is an AlGaN layer has a larger bandgap than the electron transport layer 16 which is a GaN layer. In one example, the electron supply layer 18 is composed of Al x Ga 1-x N, where x satisfies 0 < x < 0.4, and more preferably, 0.1 < x < 0.3. The electron supply layer 18 can have a thickness of, for example, 5 nm or more and 20 nm or less.

[0019] The electron transport layer 16 and the electron supply layer 18 have different lattice constants in the bulk region. Therefore, a lattice mismatch occurs between the electron transport layer 16 and the electron supply layer 18. Due to the spontaneous polarization of the electron transport layer 16 and the electron supply layer 18, and the piezoelectric polarization caused by the compressive stress on the heterojunction of the electron supply layer 18, the energy level of the conduction band of the electron transport layer 16 near the heterojunction interface between the electron transport layer 16 and the electron supply layer 18 is lower than the Fermi level. As a result, a two-dimensional electron gas (2DEG) 20 spreads within the electron transport layer 16 at a position close to the heterojunction interface between the electron transport layer 16 and the electron supply layer 18 (for example, at a distance of a few nanometers from the interface).

[0020] The nitride semiconductor device 10 further includes a gate layer 22 formed on an electron supply layer 18 and a gate electrode 24 formed on the gate layer 22. The gate layer 22 is formed on the electron supply layer 18 and has a smaller band gap than the electron supply layer 18. It is composed of a nitride semiconductor containing acceptor-type impurities. The gate layer 22 can be made of any material having a smaller band gap than the electron supply layer 18, which is, for example, an AlGaN layer. In one example, the gate layer 22 is a GaN layer (p-type GaN layer) doped with acceptor-type impurities. The acceptor-type impurities can include at least one of zinc (Zn), magnesium (Mg), and carbon (C). In one example, the maximum concentration of acceptor-type impurities in the gate layer 22 is 1 × 10⁻⁶. 18 cm -3 The above 1 x 10 20 cm -3 The following applies: The gate layer 22 may have a thickness of, for example, 80 nm to 150 nm and may have a rectangular, trapezoidal, or ridge-shaped cross-section.

[0021] As described above, the inclusion of acceptor-type impurities in the gate layer 22 raises the energy levels of the electron transport layer 16 and the electron supply layer 18. Therefore, in the region directly below the gate layer 22, the energy level of the conduction band of the electron transport layer 16 near the heterojunction interface between the electron transport layer 16 and the electron supply layer 18 is approximately the same as or higher than the Fermi level. Consequently, under zero bias conditions where no voltage is applied to the gate electrode 24, 2DEG20 is not formed in the electron transport layer 16 in the region directly below the gate layer 22. On the other hand, 2DEG20 is formed in the electron transport layer 16 in regions other than the region directly below the gate layer 22.

[0022] Thus, the presence of the acceptor-type impurity-doped gate layer 22 depletes 2DEG20 in the region directly beneath the gate layer 22, resulting in normally-off operation of the nitride semiconductor device 10. When an appropriate on-voltage is applied to the gate electrode 24, a channel of 2DEG20 is formed in the electron transport layer 16 in the region directly beneath the gate electrode 24, and the source-drain junction becomes conductive.

[0023] The gate electrode 24 is formed on the gate layer 22. The gate electrode 24 includes a bottom surface 24A (first surface) in contact with the gate layer 22, an upper surface 24B (second surface) opposite to the bottom surface 24A, and a side surface 24C (third surface) extending between the bottom surface 24A and the upper surface 24B. The gate electrode 24 is composed of one or more metal layers, one example being a titanium nitride (TiN) layer. Alternatively, the gate electrode 24 may be composed of a first metal layer made of Ti and a second metal layer made of TiN provided on the first metal layer. The thickness of the gate electrode 24 may be, for example, 50 nm or more and 200 nm or less. The gate electrode 24 can form a Schottky junction with the gate layer 22.

[0024] The nitride semiconductor device 10 further includes an insulating layer 26, a source electrode 28, and a drain electrode 30. The insulating layer 26 covers the electron supply layer 18, the gate layer 22, and the gate electrode 24, and has a first opening 26A and a second opening 26B. Each of the first opening 26A and the second opening 26B is spaced apart from the gate layer 22, and the gate layer 22 is located between the first opening 26A and the second opening 26B. More specifically, the gate layer 22 is located between the first opening 26A and the second opening 26B, and is closer to the first opening 26A than to the second opening 26B. The source electrode 28 is in contact with the electron supply layer 18 through the first opening 26A. The drain electrode 30 is in contact with the electron supply layer 18 through the second opening 26B.

[0025] The source electrode 28 and the drain electrode 30 are composed of one or more metal layers (e.g., Ti, Al, TiN, etc.). The source electrode 28 and the drain electrode 30 are in ohmic contact with the electron supply layer 18 through a first opening 26A and a second opening 26B, respectively.

[0026] The source electrode 28 includes a source contact portion 28A and a source field plate portion 28B that is continuous with the source contact portion 28A. The source contact portion 28A corresponds to the portion filled in the first opening 26A. The source field plate portion 28B is formed integrally with the source contact portion 28A. The source field plate portion 28B covers the insulating layer 26 and includes an end portion 28C located between the second opening 26B and the gate layer 22 in a plan view. Therefore, the source field plate portion 28B is spaced apart from the drain electrode 30 formed in the second opening 26B. The source field plate portion 28B extends along the surface of the insulating layer 26 from the source contact portion 28A to the end portion 28C toward the drain electrode 30. Since the insulating layer 26 covers the upper surface of the electron supply layer 18, the side and upper surfaces of the gate layer 22, and the side 24C and upper surface 24B of the gate electrode 24, the source field plate portion 28B extending along the surface of the insulating layer 26 has a non-flat surface. The source field plate portion 28B plays a role in mitigating electric field concentration near the ends of the gate electrode 24 when zero bias is applied and no gate voltage is applied to the gate electrode 24.

[0027] The insulating layer 26 includes a first insulating layer portion 26P1 having a first thickness D1 and a second insulating layer portion 26P2 having a second thickness D2. The first insulating layer portion 26P1 is in contact with the drain electrode 30 and is located on the electron supply layer 18. The first insulating layer portion 26P1 corresponds to the portion of the insulating layer 26 that has a constant thickness, a first thickness D1, between the gate layer 22 and the drain electrode 30. The first insulating layer portion 26P1 is partially covered by the source field plate portion 28B. More specifically, the portion of the first insulating layer portion 26P1 closer to the gate layer 22 is covered by the source field plate portion 28B. Therefore, the end portion 28C of the source field plate portion 28B is located on the first insulating layer portion 26P1. It can also be said that the first insulating layer portion 26P1 is the portion of the insulating layer 26 on which the end portion 28C of the source field plate portion 28B is located.

[0028] The second insulating layer portion 26P2 is in contact with the source field plate portion 28B and is located on the gate electrode 24. The second insulating layer portion 26P2 corresponds to the portion of the insulating layer 26 that has a second thickness D2, which is a constant thickness, on the gate electrode 24. The entire second insulating layer portion 26P2 is covered by the source field plate portion 28B.

[0029] The second thickness D2 of the second insulating layer portion 26P2 is greater than the first thickness D1 of the first insulating layer portion 26P1. The second thickness D2 may be between 1.2 and 5.0 times the first thickness D1. The first thickness D1 may be between 50 nm and 200 nm. The second thickness D2 may be between 100 nm and 400 nm.

[0030] The first thickness D1 is the thickness of the insulating layer 26 at the end 28C of the source field plate portion 28B in a plan view. In other words, the first thickness D1 is the distance between the electron supply layer 18 and the source electrode 28 at the end 28C of the source field plate portion 28B in a plan view. On the other hand, the second thickness D2 is the distance between the gate electrode 24 and the source electrode 28 in the region of the gate electrode 24 in a plan view. Therefore, by increasing the second thickness D2, the gate-source capacitance C gs This can be reduced.

[0031] Theoretically, increasing the second thickness D2 increases the gate-source capacitance C. gs It is possible to reduce it. However, when configuring a circuit using nitride semiconductor device 10, the feedback capacitance C rss (=gate-drain capacitance C) gd Input capacitance C for ) iss (=gate-drain capacitance C) gd +Gate-source capacitance C gs ) ratio (input capacitance C iss / Feedback Capacitance C rssWhen the value of the feedback capacitance C becomes smaller than a certain value (for example, 100), a through-current may flow due to the self-turn-on phenomenon. Therefore, the second thickness D2 is the feedback capacitance C rss Input capacitance C iss The ratio can be kept within a range that does not fall below a value determined considering the circuit design (for example, 150).

[0032] The insulating layer 26 includes a spacer layer 32 formed on the gate electrode 24, and a passivation layer 34 covering the electron supply layer 18, the gate layer 22, the gate electrode 24, and the spacer layer 32. The passivation layer 34 has a first opening 34A and a second opening 34B.

[0033] The first opening 34A and the second opening 34B of the passivation layer 34 correspond to the first opening 26A and the second opening 26B of the insulating layer 26, respectively. The first insulating layer portion 26P1 is formed by the passivation layer 34, and the second insulating layer portion 26P2 is formed by the spacer layer 32 and the passivation layer 34. For convenience of explanation, the portion of the passivation layer 34 that forms the first insulating layer portion 26P1 is referred to as the first passivation layer portion 34P1. Also, the portion of the passivation layer 34 that is located on the spacer layer 32 and forms the second insulating layer portion 26P2 together with the spacer layer 32 is referred to as the second passivation layer portion 34P2.

[0034] The spacer layer 32 may be made of one of the following materials, for example: silicon nitride (SiN), silicon dioxide (SiO2), silicon oxynitride (SiON), alumina (Al2O3), AlN, and aluminum oxynitride (AlON). In one example, the spacer layer 32 is made of SiO2. As shown in Figure 1, the spacer layer 32 has a third thickness D3. The presence of the spacer layer 32 on the gate electrode 24 increases the distance along the Z direction between the gate electrode 24 and the source electrode 28, thereby increasing the gate-source capacitance C gs This can be reduced.

[0035] The passivation layer 34 may be composed of one of the following materials, for example: SiN, SiO2, SiON, Al2O3, AlN, and AlON. In one example, the passivation layer 34 is composed of SiN. The passivation layer 34 can function as a protective film.

[0036] As shown in Figure 1, the passivation layer 34 has a first thickness D1 in the first insulating layer portion 26P1 and a fourth thickness D4 in the second insulating layer portion 26P2. In other words, the first passivation layer portion 34P1 has a first thickness D1, and the second passivation layer portion 34P2 has a fourth thickness D4. In this embodiment, the first thickness D1 is substantially equal to the fourth thickness D4. In this specification, "substantially equal" means that the difference is within the range of manufacturing variation (e.g., 20%).

[0037] Thus, in the second insulating layer portion 26P2, the spacer layer 32 has a third thickness D3, and the passivation layer 34 has a fourth thickness D4. Therefore, the second thickness D2 of the second insulating layer portion 26P2 is the sum of the third thickness D3 and the fourth thickness D4. The presence of the spacer layer 32 in addition to the passivation layer 34 increases the second thickness D2, and as a result, the gate-source capacitance C gs This can be reduced.

[0038] Figure 2 is a schematic plan view showing an exemplary formation pattern 100 of the nitride semiconductor device 10 of Figure 1. For ease of understanding, components similar to those in Figure 1 are given the same reference numerals in Figure 2. The source electrode 28, drain electrode 30, and passivation layer 34 are depicted as transparent so that the underlying components (e.g., spacer layer 32 and gate layer 22) are visible. For the source electrode 28 and drain electrode 30, only the outer edges are depicted with dashed lines. For the passivation layer 34, only the first opening 34A and the second opening 34B (corresponding to the first opening 26A and the second opening 26B of the insulating layer 26) are depicted.

[0039] As shown in Figure 2, the formation pattern 100 includes an active region 102 that contributes to transistor operation and an inactive region 104 that does not contribute to transistor operation. The active region 102 is the region in which current flows between the source and drain when a voltage is applied to the gate electrode 24.

[0040] In the active region 102, multiple nitride semiconductor devices (four in the example of Figure 2) are formed continuously along the X-axis. Each nitride semiconductor device shown in Figure 2 corresponds to the nitride semiconductor device 10 in Figure 1. That is, the cross-sectional view shown in Figure 1 corresponds to an enlarged view of the portion of the cross-section of the formation pattern 100 in the active region 102 in which one nitride semiconductor device (including the gate electrode, and associated source and drain electrodes) exists. In the active region 102, the source field plate portion 28B of the source electrode 28 includes an end portion 28C located between the second opening 34B (corresponding to the second opening 26B) and the gate layer 22. A drain electrode 30 is formed in the second opening 34B. On the other hand, in the inactive region 104, the drain electrode 30 is not formed.

[0041] As shown in Figure 2, the gate layer 22, the spacer layer 32, and the source electrode 28 are formed continuously in the Y-axis direction across the active region 102 and the inactive region 104.

[0042] Next, an example of a manufacturing method for the nitride semiconductor device 10 shown in Figure 1 will be described. Figures 3 to 7 are schematic cross-sectional views illustrating an exemplary manufacturing process of the nitride semiconductor device 10. For ease of understanding, components similar to those in Figure 1 are denoted by the same reference numerals in Figures 3 to 7. Furthermore, components that are ultimately formed as components similar to those of the nitride semiconductor device 10 are indicated in parentheses with the reference numerals from Figure 1.

[0043] A method for manufacturing a nitride semiconductor device 10 includes forming an electron transport layer 16 made of a nitride semiconductor, forming an electron supply layer 18 made of a nitride semiconductor having a larger band gap than the electron transport layer 16 on the electron transport layer 16, forming a gate layer 22 made of a nitride semiconductor containing acceptor-type impurities on the electron supply layer 18, forming a gate electrode 24 on the gate layer 22, and forming an insulating layer 26 (see Figure 1) that covers the electron supply layer 18, the gate layer 22, and the gate electrode 24 and has a first opening 26A and a second opening 26B. Forming the insulating layer 26 includes forming a spacer layer 32 on the gate electrode 24, and forming a passivation layer 34 that covers the electron supply layer 18, the gate layer 22, the gate electrode 24, and the spacer layer 32 and has a first opening 34A and a second opening 34B. The first opening 34A and the second opening 34B of the passivation layer 34 correspond to the first opening 26A and the second opening 26B of the insulating layer 26, respectively.

[0044] As shown in Figure 3, a buffer layer 14, an electron transport layer 16, an electron supply layer 18, a nitride semiconductor layer 52, a metal layer 54, and a spacer insulating layer 56 are formed in order on a substrate 12, which is, for example, a Si substrate.

[0045] The buffer layer 14, electron transport layer 16, electron supply layer 18, and nitride semiconductor layer 52 can be epitaxially grown using metal-organic chemical vapor deposition (MOCVD).

[0046] Although detailed illustrations are omitted, in one example, the buffer layer 14 is a multilayer buffer layer. After an AlN layer (first buffer layer) is formed on the substrate 12, a grated AlGaN layer (second buffer layer) is formed on the AlN layer. The grated AlGaN layer is formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25% in order from the side closest to the AlN layer.

[0047] A GaN layer is formed on the buffer layer 14 as the electron transport layer 16, and an AlGaN layer is formed on the electron transport layer 16 as the electron supply layer 18. Therefore, the electron supply layer 18 has a larger band gap than the electron transport layer 16. Next, a GaN layer containing acceptor-type impurities is formed on the electron supply layer 18 as the nitride semiconductor layer 52.

[0048] Since the buffer layer 14, electron transport layer 16, electron supply layer 18, and nitride semiconductor layer 52 are composed of nitride semiconductors with relatively similar lattice constants, they can be continuously epitaxially grown.

[0049] Subsequently, a metal layer 54 is formed on the nitride semiconductor layer 52. In one example, the metal layer 54 is a TiN layer formed by sputtering. Next, a spacer insulating layer 56 is formed on the metal layer 54. In one example, the spacer insulating layer 56 is an SiO2 layer formed by plasma CVD.

[0050] Figure 4 is a schematic cross-sectional view showing the manufacturing process following Figure 3. As shown in Figure 4, the metal layer 54 and the spacer insulating layer 56 are selectively removed by lithography and etching to form the gate electrode 24 and the spacer layer 32.

[0051] Figure 5 is a schematic cross-sectional view showing the manufacturing process following Figure 4. As shown in Figure 5, the nitride semiconductor layer 52 is selectively removed by lithography and etching to form the gate layer 22. As a result, a stacked structure including the gate layer 22, the gate electrode 24 formed on the gate layer 22, and the spacer layer 32 formed on the gate electrode 24 is formed on a portion of the upper surface of the electron supply layer 18.

[0052] Figure 6 is a schematic cross-sectional view showing the manufacturing process following Figure 5. As shown in Figure 6, the passivation insulating layer 58 is formed to cover the entire exposed surface of the electron supply layer 18, gate layer 22, gate electrode 24, and spacer layer 32. In one example, the passivation insulating layer 58 is a SiN layer formed by the low-pressure chemical vapor deposition (LPCVD) method. The passivation insulating layer 58 can have a thickness of 50 nm to 200 nm.

[0053] Figure 7 is a schematic cross-sectional view showing the manufacturing process following Figure 6. As shown in Figure 7, the passivation insulating layer 58 is selectively removed by lithography and etching to form a passivation layer 34 having a first opening 34A and a second opening 34B. More specifically, the passivation insulating layer 58 is patterned such that the gate layer 22 is located between the first opening 34A and the second opening 34B. The passivation layer 34 covers the electron supply layer 18, the gate layer 22, the gate electrode 24, and the spacer layer 32, and has the first opening 34A and the second opening 34B. Here, the insulating layer 26 is defined as including the spacer layer 32 and the passivation layer 34. The first opening 34A and the second opening 34B of the passivation layer 34 correspond to the first opening 26A and the second opening 26B of the insulating layer 26, respectively.

[0054] The method for manufacturing the nitride semiconductor device 10 further includes forming a source electrode 28 (see Figure 1) in contact with the electron supply layer 18 through a first opening 26A, and forming a drain electrode 30 (see Figure 1) in contact with the electron supply layer 18 through a second opening 26B.

[0055] In the manufacturing process following Figure 7, a metal layer is formed that fills the first opening 26A and the second opening 26B and covers the entire exposed surface of the passivation layer 34 (insulating layer 26). The source electrode 28 and drain electrode 30 are formed by patterning this metal layer (for example, one or more metal layers including Ti, Al, TiN, etc.) by lithography and etching. The source electrode 28 includes a source field plate portion 28B that covers the insulating layer 26, and the source field plate portion 28B includes an end portion 28C located between the second opening 26B and the gate layer 22 in a plan view. In this way, a nitride semiconductor device 10 as shown in Figure 1 is obtained.

[0056] The operation of the nitride semiconductor device 10 of this embodiment will be described below. In the nitride semiconductor device 10, the insulating layer 26 includes a first insulating layer portion 26P1 having a first thickness D1 and a second insulating layer portion 26P2 having a second thickness D2 greater than the first thickness D1. The second thickness D2 corresponds to the distance between the gate electrode 24 and the source electrode 28 in the region of the gate electrode 24 in a plan view. With this configuration, compared to the case where the second thickness D2 is equal to the first thickness D1, the distance along the Z direction between the gate electrode 24 and the source electrode 28 increases, thus increasing the gate-source capacitance C of the nitride semiconductor device 10. gs This can be reduced.

[0057] More specifically, in this embodiment, the insulating layer 26 includes a spacer layer 32 in addition to the passivation layer 34. Therefore, in this embodiment, compared to the case where a spacer layer 32 is not provided on the gate electrode 24, the distance along the Z direction between the gate electrode 24 and the source electrode 28 can be increased by the thickness of the spacer layer 32 (third thickness D3). As a result, the gate-source capacitance C of the nitride semiconductor device 10 gs This can be reduced.

[0058] Next, the operating characteristics of the nitride semiconductor device 10 will be explained using Experimental Example 1 and Experimental Example 2. In the nitride semiconductor device of Experimental Example 1, the second thickness D2 is approximately 2.0 times the first thickness D1. On the other hand, in the nitride semiconductor device of Experimental Example 2, the second thickness D2 is almost the same as the first thickness D1. The nitride semiconductor devices of Experimental Example 1 and Experimental Example 2 have the same configuration except for the second thickness D2. The nitride semiconductor device of Experimental Example 1, in which the second thickness D2 is greater than the first thickness D1, can correspond to the nitride semiconductor device 10.

[0059] Figure 8 shows the input capacitance C of the nitride semiconductor devices in Experimental Example 1 and Experimental Example 2. iss and drain voltage V ds This graph shows the relationship between the drain voltage V. The horizontal axis of the graph represents the drain voltage V. ds The vertical axis represents the input capacitance C. iss This is shown. In the graph, Experiment Example 1 is shown as a solid line, and Experiment Example 2 is shown as a dashed line.

[0060] As shown in Figure 8, the input capacitance C of Experimental Example 1 iss This is the input capacitance C in Experimental Example 2. iss For a given drain voltage V ds For example, it is reduced by approximately 18%. Input capacitance C iss This is the gate-source capacitance C. gs And the gate-drain capacitance C gd This is the sum of the two. Therefore, by increasing the second thickness D2 relative to the first thickness D1, the gate-source capacitance C is increased. gs By reducing the input capacitance C, iss This can be reduced.

[0061] Figure 9 shows the total gate charge Q of the nitride semiconductor devices in Experimental Example 1 and Experimental Example 2. g and gate voltage V gs This graph shows the relationship between the gates. The horizontal axis of the graph represents the total gate charge Q. g The vertical axis represents the gate voltage V. gs This is shown. In the graph, Experiment Example 1 is shown as a solid line, and Experiment Example 2 is shown as a dashed line.

[0062] As shown in Figure 9, the total gate charge Q in Experimental Example 1 gThis is the total gate charge Q in Experimental Example 2. g For a given gate voltage V gs For example, it is reduced by about 30%. Therefore, by increasing the second thickness D2 relative to the first thickness D1, the total gate charge Q of the nitride semiconductor device can be reduced. g This can be reduced.

[0063] Note that the total gate charge Q g This refers to the amount of charge that needs to be injected into the gate electrode to turn on a transistor. (Total gate charge Q) g If the gate charge Q is large, it takes longer to charge the transistor to the capacity required to turn it on, resulting in high switching losses. Therefore, the total gate charge Q g The smaller this value, the lower the switching loss, enabling high-speed switching.

[0064] The nitride semiconductor device 10 of the first embodiment provides the following effects. (1-1) The insulating layer 26 includes a first insulating layer portion 26P1 having a first thickness D1 and a second insulating layer portion 26P2 having a second thickness D2. The first insulating layer portion 26P1 is in contact with the drain electrode 30 and is located on the electron supply layer 18. The second insulating layer portion 26P2 is in contact with the source field plate portion 28B and is located on the gate electrode 24. The second thickness D2 of the second insulating layer portion 26P2 is greater than the first thickness D1 of the first insulating layer portion 26P1.

[0065] This configuration allows for an increase in the distance along the Z-direction between the gate electrode 24 and the source electrode 28, compared to the case where the second thickness D2 is equivalent to the first thickness D1. As a result, the gate-source capacitance C gs Because it can reduce the input capacitance C iss and total gate charge Q g This can suppress the increase of [the substance].

[0066] (1-2) The second thickness D2 is between 1.2 and 5.0 times the first thickness (D1). According to this configuration, the gate-source capacitance C gs Since the reduction in input capacitance C is relatively large, iss and total gate charge Q g This can more effectively suppress the increase.

[0067] (1-3) The insulating layer 26 includes a spacer layer 32 formed on the gate electrode 24, and a passivation layer 34 covering the electron supply layer 18, the gate layer 22, the gate electrode 24, and the spacer layer 32. The first insulating layer portion 26P1 is formed by the passivation layer 34, and the second insulating layer portion 26P2 is formed by the spacer layer 32 and the passivation layer 34.

[0068] In this configuration, the presence of the spacer layer 32 on the gate electrode 24 increases the distance along the Z direction between the gate electrode 24 and the source electrode 28. Therefore, the gate-source capacitance C gs This can be reduced.

[0069] [Second Embodiment] Figure 10 is a schematic cross-sectional view of an exemplary nitride semiconductor device 200 according to the second embodiment. In Figure 10, the same reference numerals are used for components that are the same as those in the nitride semiconductor device 10 according to the first embodiment. Detailed descriptions of components that are the same as those in the first embodiment are omitted.

[0070] In the nitride semiconductor device 200 of the second embodiment, the spacer layer 32 and the passivation layer 34 are made of the same material. In one example, each of the spacer layer 32 and the passivation layer 34 is made of SiN. Therefore, in Figure 10, the boundary between the spacer layer 32 and the passivation layer 34 contained in the insulating layer 26 is not depicted. In the nitride semiconductor device 200, an interface may or may not be formed between the spacer layer 32 and the passivation layer 34. However, it is possible that no visible interface is formed between the spacer layer 32 and the passivation layer 34, which are made of the same material. An exemplary formation pattern of the nitride semiconductor device 200 is similar to the formation pattern 100 shown in Figure 2.

[0071] The manufacturing method for the nitride semiconductor device 200 is substantially the same as that for the nitride semiconductor device 10. In the second embodiment, both the spacer insulating layer 56 and the passivation insulating layer 58 can be SiN layers formed by the LPCVD method.

[0072] The operating characteristics of the nitride semiconductor device 200 can correspond to Experimental Example 1 shown in Figures 8 and 9, similar to those of the nitride semiconductor device 10. Therefore, by increasing the second thickness D2 relative to the first thickness D1, the gate-source capacitance C can be increased. gs By reducing the input capacitance C, iss and total gate charge Q g This can be reduced.

[0073] Thus, the nitride semiconductor device 200 of the second embodiment provides the same effects as the nitride semiconductor device 10 of the first embodiment. [Third Embodiment] Figure 11 is a schematic cross-sectional view of an exemplary nitride semiconductor device 300 according to the third embodiment. In Figure 11, the same reference numerals are used for components similar to those in the nitride semiconductor device 10 according to the first embodiment. Detailed descriptions of components similar to those in the first embodiment are omitted.

[0074] The nitride semiconductor device 300 of the third embodiment includes an insulating layer 302 instead of an insulating layer 26 (see Figure 1). The insulating layer 302 covers the electron supply layer 18, the gate layer 22, and the gate electrode 24, and has a first opening 302A and a second opening 302B. Each of the first opening 302A and the second opening 302B is spaced apart from the gate layer 22, and the gate layer 22 is located between the first opening 302A and the second opening 302B. More specifically, the gate layer 22 is located between the first opening 302A and the second opening 302B, and is closer to the first opening 302A than to the second opening 302B. The source electrode 28 is in contact with the electron supply layer 18 through the first opening 302A. The drain electrode 30 is in contact with the electron supply layer 18 through the second opening 302B.

[0075] The insulating layer 302 includes a first insulating layer portion 302P1 having a first thickness D1 and a second insulating layer portion 302P2 having a second thickness D2. The first insulating layer portion 302P1 is in contact with the drain electrode 30 and is located on the electron supply layer 18. The first insulating layer portion 302P1 corresponds to the portion of the insulating layer 302 between the gate layer 22 and the drain electrode 30 that has a constant first thickness D1. The first insulating layer portion 302P1 is partially covered by the source field plate portion 28B. More specifically, the portion of the first insulating layer portion 302P1 closer to the gate layer 22 is covered by the source field plate portion 28B. Therefore, the end portion 28C of the source field plate portion 28B is located on the first insulating layer portion 302P1. It can also be said that the first insulating layer portion 302P1 is the portion of the insulating layer 302 where the end portion 28C of the source field plate portion 28B is located.

[0076] The second insulating layer portion 302P2 is in contact with the source field plate portion 28B and is located on the gate electrode 24. The second insulating layer portion 302P2 corresponds to the portion of the insulating layer 302 that has a second thickness D2, which is a constant thickness, on the gate electrode 24. The entire second insulating layer portion 302P2 is covered by the source field plate portion 28B.

[0077] The second thickness D2 of the second insulating layer portion 302P2 is greater than the first thickness D1 of the first insulating layer portion 302P1. The second thickness D2 may be between 1.2 and 5.0 times the first thickness D1. The first thickness D1 may be between 50 nm and 200 nm. The second thickness D2 may be between 100 nm and 400 nm.

[0078] The first thickness D1 is the thickness of the insulating layer 302 at the end 28C of the source field plate portion 28B in a plan view. In other words, the first thickness D1 is the distance between the electron supply layer 18 and the source electrode 28 at the end 28C of the source field plate portion 28B in a plan view. On the other hand, the second thickness D2 is the distance between the gate electrode 24 and the source electrode 28 in the region of the gate electrode 24 in a plan view. Therefore, by increasing the second thickness D2, the gate-source capacitance C gs This can reduce the feedback capacitance C. Note that, as in the first embodiment, the second thickness D2 is the feedback capacitance C. rss Input capacitance C iss The ratio can be kept within a range that does not fall below a value determined considering the circuit design (for example, 150).

[0079] In this embodiment, the insulating layer 302 is a passivation layer 304, and the first insulating layer portion 302P1 and the second insulating layer portion 302P2 are each formed by the passivation layer 304. That is, the insulating layer 302 is formed solely by the passivation layer 304.

[0080] The nitride semiconductor device 300 differs from the nitride semiconductor device 10 of the first embodiment in that it does not include a spacer layer 32. In the first embodiment, the second insulating layer portion 26P2 is formed by a spacer layer 32 and a passivation layer 34, but in the third embodiment, the second insulating layer portion 302P2 is formed by a passivation layer 304.

[0081] The insulating layer 302 (passivation layer 304) may be composed of one of the following materials, for example: SiN, SiO2, SiON, Al2O3, AlN, and AlON. In one example, the insulating layer 302 is composed of SiN. The insulating layer 302 can function as a protective film.

[0082] An exemplary formation pattern for the nitride semiconductor device 300 is similar to the formation pattern 100 shown in Figure 2. In the case of the formation pattern for the nitride semiconductor device 300, the insulating layer 26 (passivation layer 34) of formation pattern 100 is replaced by an insulating layer 302 (passivation layer 304).

[0083] Next, an example of a manufacturing method for the nitride semiconductor device 300 shown in Figure 11 will be described. Figures 12 to 18 are schematic cross-sectional views illustrating an exemplary manufacturing process of the nitride semiconductor device 300. For ease of understanding, components similar to those in Figure 11 are denoted by the same reference numerals in Figures 12 to 18. Furthermore, components that are ultimately formed as components similar to those of the nitride semiconductor device 300 are indicated in parentheses with the reference numerals from Figure 11.

[0084] A method for manufacturing a nitride semiconductor device 300 includes forming an electron transport layer 16 made of a nitride semiconductor, forming an electron supply layer 18 made of a nitride semiconductor having a larger band gap than the electron transport layer 16 on the electron transport layer 16, forming a gate layer 22 made of a nitride semiconductor containing acceptor-type impurities on the electron supply layer 18, forming a gate electrode 24 on the gate layer 22, and forming an insulating layer 302 that covers the electron supply layer 18, the gate layer 22, and the gate electrode 24 and has a first opening 302A and a second opening 302B (see Figure 11 for both).

[0085] In this embodiment, the insulating layer 302 is a passivation layer 304 (see Figure 11). Therefore, forming the insulating layer 302 involves covering the electron supply layer 18, the gate layer 22, and the gate electrode 24, and forming a passivation layer 304 having a first opening 304A and a second opening 304B. The first opening 304A and the second opening 304B of the passivation layer 304 correspond to the first opening 302A and the second opening 302B of the insulating layer 302, respectively.

[0086] Forming the insulating layer 302 (passivation layer 304) involves selectively etching the insulating layer 302 (passivation layer 304) such that the first insulating layer portion 302P1 and the second insulating layer portion 302P2 (both see Figure 11) have different thicknesses.

[0087] As shown in Figure 12, for example, a buffer layer 14, an electron transport layer 16, an electron supply layer 18, a nitride semiconductor layer 352, and a metal layer 354 are formed in order on a substrate 12, which is a Si substrate.

[0088] The buffer layer 14, electron transport layer 16, electron supply layer 18, and nitride semiconductor layer 352 can be epitaxially grown using the MOCVD method. Although detailed illustrations are omitted, in one example, the buffer layer 14 is a multilayer buffer layer. After an AlN layer (first buffer layer) is formed on the substrate 12, a grated AlGaN layer (second buffer layer) is formed on the AlN layer. The grated AlGaN layer is formed, for example, by stacking three AlGaN layers with Al compositions of 75%, 50%, and 25% in order from the side closest to the AlN layer.

[0089] A GaN layer is formed on the buffer layer 14 as the electron transport layer 16, and an AlGaN layer is formed on the electron transport layer 16 as the electron supply layer 18. Therefore, the electron supply layer 18 has a larger band gap than the electron transport layer 16. Next, a GaN layer containing acceptor-type impurities is formed on the electron supply layer 18 as the nitride semiconductor layer 352.

[0090] Since the buffer layer 14, electron transport layer 16, electron supply layer 18, and nitride semiconductor layer 352 are composed of nitride semiconductors with relatively similar lattice constants, they can be continuously epitaxially grown.

[0091] Subsequently, a metal layer 354 is formed on the nitride semiconductor layer 352. In one example, the metal layer 354 is a TiN layer formed by sputtering. Figure 13 is a schematic cross-sectional view showing the manufacturing process following Figure 12. As shown in Figure 13, the metal layer 354 is selectively removed by lithography and etching to form the gate electrode 24.

[0092] Figure 14 is a schematic cross-sectional view showing the manufacturing process following Figure 13. As shown in Figure 14, the nitride semiconductor layer 352 is selectively removed by lithography and etching to form the gate layer 22. As a result, a stacked structure including the gate layer 22 and the gate electrode 24 formed on the gate layer 22 is formed on a portion of the upper surface of the electron supply layer 18.

[0093] Figure 15 is a schematic cross-sectional view showing the manufacturing process following Figure 14. As shown in Figure 15, the passivation insulating layer 356 is formed to cover the entire exposed surface of the electron supply layer 18, the gate layer 22, and the gate electrode 24. In one example, the passivation insulating layer 356 is a SiN layer formed by the LPCVD method. The passivation insulating layer 356 can have a thickness of 100 nm to 400 nm.

[0094] Figure 16 is a schematic cross-sectional view showing the manufacturing process following Figure 15. As shown in Figure 16, a mask 358 (e.g., photoresist) is formed to cover a portion of the upper surface of the passivation insulating layer 356. In one example, the entire surface of the passivation insulating layer 356 is coated with photoresist and exposed so that a portion of the upper surface of the passivation insulating layer 356 is covered with the mask 358.

[0095] The region in which the mask 358 is formed includes, in a plan view, at least the formation regions of the gate layer 22 and the gate electrode 24. In a plan view, the mask 358 is formed in a region that is larger than the said formation region but does not cover the first opening 302A and the second opening 302B shown in Figure 11.

[0096] Figure 17 is a schematic cross-sectional view showing the manufacturing process following Figure 16. As shown in Figure 17, the passivation insulating layer 356 is selectively etched using a mask 358. As a result, the thickness of the passivation insulating layer 356 in the area covered by the mask 358 is maintained, but the thickness of the passivation insulating layer 356 in the area not covered by the mask 358 is reduced. The passivation insulating layer 356 in the area not covered by the mask 358 can have a thickness of 50 nm to 200 nm after etching. The mask 358 is removed after etching. Such selective etching of the passivation insulating layer 356 makes it possible for the resulting nitride semiconductor device 300 to have a first insulating layer portion 302P1 and a second insulating layer portion 302P2 with different thicknesses.

[0097] Figure 18 is a schematic cross-sectional view showing the manufacturing process following Figure 17. As shown in Figure 18, the passivation insulating layer 356 is selectively removed by lithography and etching to form an insulating layer 302 having a first opening 302A and a second opening 302B. More specifically, the passivation insulating layer 356 is patterned such that the gate layer 22 is located between the first opening 302A and the second opening 302B. As a result, an insulating layer 302 is formed that covers the electron supply layer 18, the gate layer 22, and the gate electrode 24, and has the first opening 302A and the second opening 302B.

[0098] The method for manufacturing the nitride semiconductor device 300 further includes forming a source electrode 28 (see Figure 11) in contact with the electron supply layer 18 through a first opening 302A, and forming a drain electrode 30 (see Figure 11) in contact with the electron supply layer 18 through a second opening 302B.

[0099] In the manufacturing process following Figure 18, a metal layer is formed that fills the first opening 302A and the second opening 302B and covers the entire exposed surface of the insulating layer 302. The source electrode 28 and the drain electrode 30 are formed by patterning this metal layer (for example, one or more metal layers including Ti, Al, TiN, etc.) by lithography and etching. The source electrode 28 includes a source field plate portion 28B that covers the insulating layer 302, and the source field plate portion 28B includes an end portion 28C located between the second opening 302B and the gate layer 22 in a plan view. In this way, a nitride semiconductor device 300 as shown in Figure 11 is obtained.

[0100] The operation of the nitride semiconductor device 300 of this embodiment will be described below. In the nitride semiconductor device 300, the insulating layer 302 includes a first insulating layer portion 302P1 having a first thickness D1 and a second insulating layer portion 302P2 having a second thickness D2 greater than the first thickness D1. The second thickness D2 corresponds to the distance between the gate electrode 24 and the source electrode 28 in the region of the gate electrode 24 in a plan view. With this configuration, compared to the case where the second thickness D2 is equal to the first thickness D1, the distance along the Z direction between the gate electrode 24 and the source electrode 28 increases, thus increasing the gate-source capacitance C of the nitride semiconductor device 300. gs This can be reduced.

[0101] The operating characteristics of the nitride semiconductor device 300 can correspond to Experimental Example 1 shown in Figures 8 and 9, similar to the nitride semiconductor device 10 of the first embodiment. Therefore, by increasing the second thickness D2 relative to the first thickness D1, the gate-source capacitance C can be increased. gs By reducing the input capacitance C, iss and total gate charge Q g This can be reduced.

[0102] The nitride semiconductor device 300 of the third embodiment provides the following effects. (3-1) The insulating layer 302 includes a first insulating layer portion 302P1 having a first thickness D1 and a second insulating layer portion 302P2 having a second thickness D2. The first insulating layer portion 302P1 is in contact with the drain electrode 30 and is located on the electron supply layer 18. The second insulating layer portion 302P2 is in contact with the source field plate portion 28B and is located on the gate electrode 24. The second thickness D2 of the second insulating layer portion 302P2 is greater than the first thickness D1 of the first insulating layer portion 302P1.

[0103] This configuration allows for an increase in the distance along the Z-direction between the gate electrode 24 and the source electrode 28, compared to the case where the second thickness D2 is equivalent to the first thickness D1. As a result, the gate-source capacitance C gs Because it can reduce the input capacitance C iss and total gate charge Q gThis can suppress the increase of [the substance].

[0104] (3-2) The second thickness D2 is between 1.2 and 5.0 times the first thickness (D1). According to this configuration, the gate-source capacitance C gs Since the reduction in input capacitance C is relatively large, iss and total gate charge Q g This can more effectively suppress the increase.

[0105] [Example of changes] Each of the above embodiments can be implemented with the following modifications. Furthermore, each of the above embodiments and the following modifications can be combined with each other to the extent that they do not contradict each other technically.

[0106] In the first embodiment, the gate-source capacitance C gs From the standpoint of reducing noise, the spacer layer 32 may be made of a material having a lower dielectric constant than the passivation layer 34.

[0107] In Figure 1, the spacer layer 32 is formed over the entire upper surface 24B of the gate electrode 24. However, the spacer layer 32 may be formed on only a portion of the upper surface 24B of the gate electrode 24. Alternatively, the spacer layer 32 may be formed on both the upper surface 24B and the side surface 24C of the gate electrode 24.

[0108] In the above embodiments, the passivation layer 34, the spacer layer 32, and the insulating layer 302 are described as being composed of one of SiN, SiO2, SiON, Al2O3, AlN, and AlON, but they may be composite films containing some of SiN, SiO2, SiON, Al2O3, AlN, and AlON.

[0109] The gate electrode 24 only needs to be formed on at least a portion of the gate layer 22. For example, in each of the above embodiments, the gate electrode 24 may be formed on the entire gate layer 22.

[0110] As used in this disclosure, the term “on” includes the meanings of “on” and “above” unless the context clearly indicates otherwise. Therefore, the expression “the first layer is formed on the second layer” is intended to mean that in one embodiment the first layer may be in contact with the second layer and directly positioned on the second layer, while in another embodiment the first layer may be positioned above the second layer without contact with it. In other words, the term “on” does not preclude structures in which another layer is formed between the first and second layers. For example, the embodiment in which the electron supply layer 18 is formed on the electron transport layer 16 also includes a structure in which an intermediate layer is located between the electron supply layer 18 and the electron transport layer 16 to stably form the 2DEG 20.

[0111] The Z-axis direction used in this disclosure does not necessarily have to be vertical, nor does it have to be perfectly aligned with the vertical. Therefore, the various structures described herein (e.g., the structure shown in Figure 1) are not limited to the Z-axis direction "up" and "down" being vertical. For example, the X-axis direction may be vertical, or the Y-axis direction may be vertical.

[0112] [Note] The technical concepts that can be understood from each of the above embodiments and their modifications are described below. Note that, not as an limitation but for the purpose of aiding understanding, the corresponding reference numerals in the embodiments for the components described in the appendices are shown in parentheses. These reference numerals are provided as examples for the purpose of aiding understanding, and the components described in each appendice should not be limited to those indicated by these reference numerals.

[0113] (Note A1) An electron transport layer (16) made of nitride semiconductor, An electron supply layer (18) is formed on the electron transport layer (16) and is made of a nitride semiconductor having a larger band gap than the electron transport layer (16), A gate layer (22) is formed on the electron supply layer (18) and is made of a nitride semiconductor containing acceptor-type impurities, A gate electrode (24) formed on the gate layer (22), An insulating layer (26) covering the electron supply layer (18), the gate layer (22), and the gate electrode (24), and having a first opening (26A) and a second opening (26B), The source electrode (28) is in contact with the electron supply layer (18) through the first opening (26A), The drain electrode (30) is in contact with the electron supply layer (18) through the second opening (26B) and Equipped with, The gate layer (22) is located between the first opening (26A) and the second opening (26B), The source electrode (28) includes a source field plate portion (28B) that covers the insulating layer (26), and the source field plate portion (28B) includes an end portion (28C) located between the second opening (26B) and the gate layer (22) in a plan view. The insulating layer (26) is A first insulating layer portion (26P1) is in contact with the drain electrode (30) and located on the electron supply layer (18), and has a first thickness (D1), The second insulating layer portion (26P2) is in contact with the source field plate portion (28B) and is located on the gate electrode (24), and has a second thickness (D2). Includes, The end portion (28C) of the source field plate portion (28B) is positioned on the first insulating layer portion (26P1), A nitride semiconductor device wherein the second thickness (D2) of the second insulating layer portion (26P2) is greater than the first thickness (D1) of the first insulating layer portion (26P1).

[0114] (Appendix A2) The nitride semiconductor device as described in Appendix A1, wherein the second thickness (D2) is 1.2 times or more and 5.0 times or less the first thickness (D1).

[0115] (Note A3) The nitride semiconductor device as described in Appendix A1 or A2, wherein the first thickness (D1) is 50 nm or more and 200 nm or less, and the second thickness (D2) is 100 nm or more and 400 nm or less.

[0116] (Note A4) The insulating layer (26) is A spacer layer (32) formed on the gate electrode (24), A passivation layer (34) covering the electron supply layer (18), the gate layer (22), the gate electrode (24), and the spacer layer (32), and having the first opening (26A) and the second opening (26B) Includes, The first insulating layer portion (26P1) is formed by the passivation layer (34), The nitride semiconductor device according to any one of the appendices A1 to A3, wherein the second insulating layer portion (26P2) is formed by the spacer layer (32) and the passivation layer (34).

[0117] (Note A5) In the first insulating layer portion (26P1), the passivation layer (34) has the first thickness (D1), In the second insulating layer portion (26P2), the spacer layer (32) has a third thickness (D3), and the passivation layer (34) has a fourth thickness (D4). The aforementioned second thickness (D2) is the sum of the aforementioned third thickness (D3) and the aforementioned fourth thickness (D4). Nitride semiconductor equipment as described in Appendix A4.

[0118] (Note A6) The first thickness (D1) is substantially equal to the fourth thickness (D4). Nitride semiconductor equipment as described in Appendix A5.

[0119] (Note A7) The nitride semiconductor device described in any one of the appendices A4 to A6, wherein the spacer layer (32) is composed of one of SiN, SiO2, SiON, Al2O3, AlN, and AlON.

[0120] (Note A8) The nitride semiconductor device according to any one of the appendices A4 to A7, wherein the spacer layer (32) and the passivation layer (34) are made of the same material.

[0121] (Note A9) The nitride semiconductor device according to any one of the appendices A4 to A8, wherein each of the spacer layer (32) and the passivation layer (34) is made of SiN.

[0122] (Note A10) The nitride semiconductor device according to any one of the appendices A4 to A7, wherein the spacer layer (32) is made of a material having a lower dielectric constant than the passivation layer (34).

[0123] (Note A11) The gate electrode (24) includes a first surface (24A) in contact with the gate layer (22) and a second surface (24B) opposite to the first surface (24A). The nitride semiconductor device according to any one of the appendices A4 to A10, wherein the spacer layer (32) is formed on a part of the second surface (24B) of the gate electrode (24).

[0124] (Note A12) The gate electrode (24) includes a first surface (24A) in contact with the gate layer (22), a second surface (24B) opposite to the first surface (24A), and a third surface (24C) extending between the first surface (24A) and the second surface (24B). The nitride semiconductor device according to any one of appendices A4 to A10, wherein the spacer layer (32) is formed on the second surface (24B) and the third surface (24C) of the gate electrode (24).

[0125] (Note A13) The aforementioned insulating layer (302) is a passivation layer (304), The nitride semiconductor device according to any one of the appendices A1 to A3, wherein the first insulating layer portion (302P1) and the second insulating layer portion (302P2) are each formed by the passivation layer (304).

[0126] (Note A14) The nitride semiconductor device according to any one of appendices A4 to A13, wherein the passivation layer (34;304) is composed of one of SiN, SiO2, SiON, Al2O3, AlN, and AlON.

[0127] (Note A15) The first thickness (D1) is the thickness of the insulating layer (26) at the end (28C) of the source field plate portion (28B) in a plan view. The second thickness (D2) is the distance between the gate electrode (24) and the source electrode (28) in the region of the gate electrode (24) in a plan view. Nitride semiconductor device as described in any one of the appendices A1 to A14.

[0128] (Note B1) Forming an electron transport layer (16) composed of a nitride semiconductor, An electron supply layer (18) is formed on the electron transport layer (16) by being made of a nitride semiconductor having a larger band gap than the electron transport layer (16). A gate layer (22) made of a nitride semiconductor containing acceptor-type impurities is formed on the electron supply layer (18). Forming a gate electrode (24) on the gate layer (22), An insulating layer (26) is formed to cover the electron supply layer (18), the gate layer (22), and the gate electrode (24), and to have a first opening (26A) and a second opening (26B). A source electrode (28) is formed in contact with the electron supply layer (18) through the first opening (26A), A drain electrode (30) is formed in contact with the electron supply layer (18) through the second opening (26B). Includes, The gate layer (22) is located between the first opening (26A) and the second opening (26B), The source electrode (28) includes a source field plate portion (28B) that covers the insulating layer (26), and the source field plate portion (28B) includes an end portion (28C) located between the second opening (26B) and the gate layer (22) in a plan view. The insulating layer (26) is A first insulating layer portion (26P1) is in contact with the drain electrode (30) and located on the electron supply layer (18), and has a first thickness (D1), The second insulating layer portion (26P2) is in contact with the source field plate portion (28B) and is located on the gate electrode (24), and has a second thickness (D2). Includes, The end portion (28C) of the source field plate portion (28B) is positioned on the first insulating layer portion (26P1), A method for manufacturing a nitride semiconductor device, wherein the second thickness (D2) of the second insulating layer portion (26P2) is greater than the first thickness (D1) of the first insulating layer portion (26P1).

[0129] (Note B2) The method for manufacturing a nitride semiconductor device as described in Appendix B1, wherein the second thickness (D2) is 1.2 times or more and 5.0 times or less the first thickness (D1).

[0130] (Note B3) A method for manufacturing a nitride semiconductor device as described in Appendix B1 or B2, wherein the first thickness (D1) is 50 nm or more and 200 nm or less, and the second thickness (D2) is 100 nm or more and 400 nm or less.

[0131] (Note B4) Forming the insulating layer (26) is Forming a spacer layer (32) on the gate electrode (24), A passivation layer (34) is formed to cover the electron supply layer (18), the gate layer (22), the gate electrode (24), and the spacer layer (32), and to have the first opening (26A) and the second opening (26B). Includes, The first insulating layer portion (26P1) is formed by the passivation layer (34), The second insulating layer portion (26P2) is formed by the spacer layer (32) and the passivation layer (34). A method for manufacturing a nitride semiconductor device as described in any one of the appendices B1 to B3.

[0132] (Note B5) In the first insulating layer portion (26P1), the passivation layer (34) has the first thickness (D1), In the second insulating layer portion (26P2), the spacer layer (32) has a third thickness (D3), and the passivation layer (34) has a fourth thickness (D4). The aforementioned second thickness (D2) is the sum of the aforementioned third thickness (D3) and the aforementioned fourth thickness (D4). The method for manufacturing a nitride semiconductor device as described in Appendix B4.

[0133] (Note B6) The first thickness (D1) is substantially equal to the fourth thickness (D4). The method for manufacturing nitride semiconductor devices as described in Appendix B5.

[0134] (Note B7) The method for manufacturing a nitride semiconductor device according to any one of the appendices B4 to B6, wherein the spacer layer (32) is composed of one of SiN, SiO2, SiON, Al2O3, AlN, and AlON.

[0135] (Note B8) A method for manufacturing a nitride semiconductor device according to any one of the appendices B4 to B7, wherein the spacer layer (32) and the passivation layer (34) are made of the same material.

[0136] (Note B9) A method for manufacturing a nitride semiconductor device according to any one of the appendices B4 to B8, wherein each of the spacer layer (32) and the passivation layer (34) is made of SiN.

[0137] (Note B10) The method for manufacturing a nitride semiconductor device according to any one of the appendices B4 to B7, wherein the spacer layer (32) is made of a material having a lower dielectric constant than the passivation layer (34).

[0138] (Note B11) The gate electrode (24) includes a first surface (24A) in contact with the gate layer (22) and a second surface (24B) opposite to the first surface. The method for manufacturing a nitride semiconductor device according to any one of appendices B4 to B10, wherein the spacer layer (32) is formed on a part of the second surface (24B) of the gate electrode (24).

[0139] (Note B12) The gate electrode (24) includes a first surface (24A) in contact with the gate layer (22), a second surface (24B) opposite to the first surface, and a third surface (24C) extending between the first surface (24A) and the second surface (24B). The method for manufacturing a nitride semiconductor device according to any one of appendices B4 to B10, wherein the spacer layer (32) is formed on the second surface (24B) and the third surface (24C) of the gate electrode (24).

[0140] (Note B13) Forming the aforementioned insulating layer (302) A passivation layer (304) is formed to cover the electron supply layer (18), the gate layer (22), and the gate electrode (24), and to have the first opening (304A) and the second opening (304B). Includes, A method for manufacturing a nitride semiconductor device according to any one of the appendices B1 to B3, wherein the first insulating layer portion (302P1) and the second insulating layer portion (302P2) are each formed by the passivation layer (304).

[0141] (Note B14) The method for manufacturing a nitride semiconductor device according to any one of appendices B4 to B13, wherein the passivation layer (34;302) is composed of one of SiN, SiO2, SiON, Al2O3, AlN, and AlON.

[0142] (Note B15) The first thickness (D1) is the thickness of the insulating layer (26) at the end (28C) of the source field plate portion (28B) in a plan view. The second thickness (D2) is the distance between the gate electrode (24) and the source electrode (28) in the region of the gate electrode (24) in a plan view. A method for manufacturing a nitride semiconductor device as described in any one of the appendices B1 to B14.

[0143] (Note B16) Forming the passivation layer (304) is Selective etching of the passivation layer (304) such that the first insulating layer portion (302P1) and the second insulating layer portion (302P2) have different thicknesses. including, A method for manufacturing a nitride semiconductor device as described in any one of the appendices B13 to B15.

[0144] (Note B17) Forming the aforementioned insulating layer (302) Selective etching of the insulating layer (302) such that the first insulating layer portion (302P1) and the second insulating layer portion (302P2) have different thicknesses. including, A method for manufacturing a nitride semiconductor device as described in any one of the appendices B1 to B3.

[0145] The above description is illustrative only. Those skilled in the art will recognize that many more possible combinations and substitutions are possible beyond the components and methods (manufacturing processes) enumerated for the purpose of illustrating the technology of this disclosure. This disclosure is intended to encompass all alternatives, variations, and modifications that fall within the scope of this disclosure, including the claims. [Explanation of Symbols]

[0146] 10,200,300… Nitride semiconductor equipment 12… Circuit board 14…Buffer layer 16…Electronic transport layer 18...electron supply layer 20...2D electron gas 22...Gate layer 24… Gate 24A…Bottom surface (first surface) 24B...Top surface (second surface) 24C…Side (3rd side) 26,302...insulating layer 26A, 34A, 302A, 304A…1st opening 26B, 34B, 302B, 304B…Second opening 26P1, 302P1…First insulating layer portion 26P2, 302P2…Second insulating layer portion 28…Source electrode 28A…Source contact section 28B...Source field plate section 28C...end 30…Drain electrode 32...Spacer layer 34,304... Passivation layer 34P1...First passivation layer 34P2…Second Passivation Layer 52,352… Nitride semiconductor layer 54,354…metal layer 56…Spacer insulating layer 58,356... Passivation insulation layer 100...Formation pattern 102... Active area 104...Inactive area 358… Mask D1...First thickness D2...Second thickness D3...Third thickness D4...Fourth thickness

Claims

1. An electron transport layer composed of a nitride semiconductor, An electron supply layer formed on the electron transport layer and composed of a nitride semiconductor having a larger band gap than the electron transport layer, A gate layer formed on the electron supply layer and composed of a nitride semiconductor containing acceptor-type impurities, A gate electrode formed on the gate layer, An insulating layer covering the electron supply layer, the gate layer, and the gate electrode, and having a first opening and a second opening, A source electrode in contact with the electron supply layer through the first opening, The drain electrode in contact with the electron supply layer through the second opening and Equipped with, The gate layer is located between the first opening and the second opening. The source electrode includes a source field plate portion covering the insulating layer, and the source field plate portion includes an end portion located between the second opening and the gate layer in a plan view. The aforementioned insulating layer is A first insulating layer portion that is in contact with the drain electrode and located on the electron supply layer, and having a first thickness, A second insulating layer portion having a second thickness is in contact with the source field plate portion and located on the gate electrode portion. Includes, The end portion of the source field plate is positioned on the first insulating layer portion, The second thickness of the second insulating layer portion is greater than the first thickness of the first insulating layer portion. The nitride semiconductor device wherein the source electrode, in a plan view, completely surrounds the drain electrode.

2. The nitride semiconductor device according to claim 1, wherein the second thickness is 1.2 times or more and 5.0 times or less the first thickness.

3. The nitride semiconductor device according to claim 1 or 2, wherein the first thickness is 50 nm or more and 200 nm or less, and the second thickness is 100 nm or more and 400 nm or less.

4. The aforementioned insulating layer is A spacer layer formed on the gate electrode, A passivation layer covering the electron supply layer, the gate layer, the gate electrode, and the spacer layer, and having the first opening and the second opening Includes, The first insulating layer portion is formed by the passivation layer, The nitride semiconductor device according to any one of claims 1 to 3, wherein the second insulating layer portion is formed by the spacer layer and the passivation layer.

5. In the first insulating layer portion, the passivation layer has the first thickness, In the aforementioned second insulating layer portion, the spacer layer has a third thickness, and the passivation layer has a fourth thickness. The second thickness is the sum of the third thickness and the fourth thickness. The nitride semiconductor device according to claim 4.

6. The first thickness is substantially equal to the fourth thickness. The nitride semiconductor device according to claim 5.

7. The spacer layer is made of SiN and SiO ２ , SiON, Al ２ O ３ A nitride semiconductor device according to any one of claims 4 to 6, comprising one of AlN and AlON.

8. The nitride semiconductor device according to any one of claims 4 to 7, wherein the spacer layer and the passivation layer are made of the same material.

9. The nitride semiconductor device according to any one of claims 4 to 8, wherein each of the spacer layer and the passivation layer is made of SiN.

10. The nitride semiconductor device according to any one of claims 4 to 7, wherein the spacer layer is made of a material having a lower dielectric constant than the passivation layer.

11. The gate electrode includes a first surface in contact with the gate layer and a second surface opposite to the first surface. The nitride semiconductor device according to any one of claims 4 to 10, wherein the spacer layer is formed on a part of the second surface of the gate electrode.

12. The gate electrode includes a first surface in contact with the gate layer, a second surface opposite to the first surface, and a third surface extending between the first and second surfaces. The nitride semiconductor device according to any one of claims 4 to 10, wherein the spacer layer is formed on the second and third surfaces of the gate electrode.

13. The aforementioned insulating layer is a passivation layer, The nitride semiconductor device according to any one of claims 1 to 3, wherein the first insulating layer portion and the second insulating layer portion are each formed by the passivation layer.

14. The passivation layer is made of SiN, SiO ２ , SiON, Al ２ O ３ A nitride semiconductor device according to any one of claims 4 to 13, comprising one of AlN and AlON.

15. The first thickness is the thickness of the insulating layer at the end of the source field plate portion in a plan view, The second thickness is the distance between the gate electrode and the source electrode in the region of the gate electrode in a plan view. A nitride semiconductor device according to any one of claims 1 to 14.

16. Forming an electron transport layer composed of nitride semiconductors, An electron supply layer is formed on the electron transport layer, which is made of a nitride semiconductor having a larger band gap than the electron transport layer. A gate layer made of a nitride semiconductor containing acceptor-type impurities is formed on the electron supply layer. Forming a gate electrode on the gate layer, To form an insulating layer that covers the electron supply layer, the gate layer, and the gate electrode, and has a first opening and a second opening, A source electrode is formed in contact with the electron supply layer through the first opening. A drain electrode is formed in contact with the electron supply layer through the second opening. Includes, The gate layer is located between the first opening and the second opening. The source electrode includes a source field plate portion covering the insulating layer, and the source field plate portion includes an end portion located between the second opening and the gate layer in a plan view. The aforementioned insulating layer is A first insulating layer portion that is in contact with the drain electrode and located on the electron supply layer, and having a first thickness, A second insulating layer portion having a second thickness is in contact with the source field plate portion and located on the gate electrode portion. Includes, The end portion of the source field plate is positioned on the first insulating layer portion, The second thickness of the second insulating layer portion is greater than the first thickness of the first insulating layer portion. A method for manufacturing a nitride semiconductor device, wherein the source electrode, in a plan view, completely surrounds the drain electrode.

17. The method for manufacturing a nitride semiconductor device according to claim 16, wherein the second thickness is 1.2 times or more and 5.0 times or less the first thickness.

18. The method for manufacturing a nitride semiconductor device according to claim 16 or 17, wherein the first thickness is 50 nm or more and 200 nm or less, and the second thickness is 100 nm or more and 400 nm or less.

19. Forming the aforementioned insulating layer means Forming a spacer layer on the gate electrode, A passivation layer is formed to cover the electron supply layer, the gate layer, the gate electrode, and the spacer layer, and to have the first opening and the second opening. Includes, The first insulating layer portion is formed by the passivation layer, The aforementioned second insulating layer portion is formed by the spacer layer and the passivation layer. A method for manufacturing a nitride semiconductor device according to any one of claims 16 to 18.

20. Forming the aforementioned insulating layer means Selective etching of the insulating layer such that the first insulating layer portion and the second insulating layer portion have different thicknesses. including, A method for manufacturing a nitride semiconductor device according to any one of claims 16 to 18.

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