Digital detector with digital charge integration function

Abstract

To provide a digital detector which includes a digital charge integration function.SOLUTION: A digital detector 100 comprises: a set of pixels (i,j) which are arrayed on a matrix array 13 descending a column on an image detector 100 and generate charges on the basis of the radiation; a column conductor Yj which is connected to the pixels P (i,j) of the column and intended to convey the charges generated by the pixels P (i,j); a charge preamplifier 20 which is connected to the column conductor Yj for each column conductor Yj on an integrated read-out circuit 33 and forms a pre-amplified column conductor 21j that is intended to integrate the charges conveyed by the column conductor Yj; an analog-digital converter 22j; and a serialized circuit block 23 which is connected to the analog-digital converter 22j and intended to generate the output voltage.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The technical field of the present invention is that of medical imaging, and more particularly, that of the readout of a matrix array of passive pixels on a tile of typically aSi (amorphous silicon) or IGZO (indium gallium zinc oxide). More specifically, the present invention relates to a digital detector and to integrating the charge generated from pixels through the columns of a matrix array of pixels and converting these directly into digital signals.

Background Art

[0002] In the field of X-ray image acquisition, there are four different components: a. A radiation source that emits X-rays, b. A filter that modulates the characteristics of the radiation according to the needs of the application, c. An imaging object, d. A detector that converts X-ray photons into a digital image

[0003] The present invention relates to digital detectors, and more specifically to converting the charge received at the pixel level into an electrical signal proportional to the amount of charge received. Digital detectors can implement various conceivable technologies. One of these technologies utilizes a scintillator that enables the conversion of X-rays into photons of visible light and a photodiode matrix array that enables the conversion of photons of visible light into an electrical signal. It may also be applicable using a photoconductor that directly converts X-rays into electrons.

[0004] The quality of the image is directly related to the noise of the electronic system, a substantial proportion of which originates from the capacitance of the columns of the pixel matrix array.

[0005] In the latest systems, a direct analog-voltage conversion circuit associated with an analog-digital converter is used.

[0006] Firstly, the configuration of a standard charge integrator performing charge-voltage conversion is not optimal with respect to the processes of integration and charge-to-voltage conversion. These are generally associated with a correction mechanism known as correlated double sampling (CDS), which requires a second blank integral of the charge on the column, and therefore requires additional operating time, which is disadvantageous in terms of execution speed.

[0007] Secondly, the downstream analog-to-digital converter requires an analog image chain to adapt the analog output signal to the input voltage for the analog-to-digital converter. This results in failures due to the correlation of the two blocks. Previously, they were external, causing parasitic effects at each interface, and now it is common to integrate the analog-to-digital converter into the same circuit, but the two functions are still separated from the analog-to-digital converter block and require multiplexing.

[0008] The solutions proposed in prior art are basically based on the use of CDS (Correlated Double Sampling).

[0009] Solutions that do not include any preamplifiers require the use of correction, which has a negative impact on integration time because the column must be read twice to eliminate unwanted effects. Specifically, CDS-type correction requires resetting the column and performing a blank readout, which is then subtracted from the signal. This reset introduces new kTC noise that must be filtered out. Low-pass filtering is used to mitigate this column noise, but the time constant required for effective filtering is incompatible with the pixel conversion time, and therefore affects the readout time of the pixel matrix array.

[0010] In the case of readout by a charge preamplifier associated with a column, this component can integrate the charge from the column in the minimum time required to transfer the charge from the pixel to the column.

[0011] In CDS mode readout using an integrator without a charge preamplifier, additional time is required to reset the column, sample the signal, and then integrate the charge from the column in the minimum time necessary to transmit the charge from the pixel to the column.

[0012] In other words, the prior art solution proposes converting charge into analog voltage within a column, and then multiplexing the various columns into analog-to-digital conversion blocks. The analog data is multiplexed for the analog-to-digital converter. The presence of a separate ADC circuit introduces further distortion and noise. Prior art matrix array detectors are disclosed in U.S. Patent No. 5,184018 A and U.S. Patent No. 6,642494 B1. In both cases, the system does not have a charge preamplifier between the upstream, pixel matrix array sensor and the processing system, and uses a circuit with a block ADC and an analog multiplexer, with the ADC located outside the substrate of the processing circuit. Simoni et al., “A digital vision sensor” (XP027220184), discloses a sensor that includes one analog-to-digital converter per channel, does not include a preamplifier, and aims to convert current from an embedded photodiode that generates a significantly larger current.

[0013] In the case of block or monolithic ADCs, channel multiplexing at the input is required, and the conversion time is equal to the low time divided by the same number of channels as the pixel matrix array (which is typically 1000-5000 channels, and possibly more), so that the total conversion time is transparent with respect to the read time of the pixel matrix array, connecting the lows to the image without introducing latency. With parallel ADCs integrated in columns, the conversion time can be reduced to the time of only one low, because there is one ADC for each processing channel. As a result, in addition to the initial resolution remaining the same, the conversion speed is completely different in each of the two cases, and the power consumption and area constraints vary greatly, resulting in entirely unique ADC designs.

[0014] It should be noted that fabricating such an ADC is not straightforward, as it lies on the boundary between two types of converters: very high resolution and low speed, and low resolution and high speed. The characteristics required for an ADC for such an application correspond to a balance between the relevant moderate resolution and high speed. [Prior art documents] [Patent Documents]

[0015] [Patent Document 1] U.S. Patent No. 5184018A [Patent Document 2] U.S. Patent No. 6,642,494, B1 [Non-patent literature]

[0016] [Non-Patent Document 1] “A digital vision sensor”(XP027220184) [Overview of the project] [Problems that the invention aims to solve]

[0017] The present invention aims to overcome all or part of the aforementioned problems by providing a digital detector that combines a charge preamplifier and an analog-to-digital converter within a single processing channel, so that everything resides within the same monolithic integrated circuit. Such a combination makes it possible to reduce kTC noise generated by the column and minimize noise in the downstream system. The preamplifier makes it possible to reduce the inherent column noise known as kTC. The integration of the ADC and its combination with the charge-to-voltage converter, in turn, reduces parasitic noise by shortening the processing system and avoiding data multiplexing at the input. This result is transmitted in the form of a series-converted digital voltage, thereby ensuring that the signal is not subjected to subsequent degradation. The present invention makes it possible to integrate the charge from the matrix array of pixels at high speed while generating only minimal signal interference. [Means for solving the problem]

[0018] The challenges in implementing the present invention with parallel ADCs are the challenge of integrating ADCs, which are essentially blocks, and the challenge of combining them with the unit routing of channels (columns). In addition to the specific manufacturing complexities, area and power consumption become important because there are as many ADCs as there are columns in the pixel matrix array.

[0019] Therefore, the gist of the present invention is a digital detector comprising a planar sensor, a first monolithic substrate, and a second monolithic substrate, wherein the planar sensor is fabricated on the first monolithic substrate, and the detector is: On the first monolithic substrate: -A set of pixels aligned in a matrix array that descends a column along the row, configured to generate a charge based on radiation that collides with the detector, - Column conductors, each connected to a pixel in the same column, intended to carry the charge generated by the pixel. Includes, On the second monolithic substrate: - For each of the column conductors, a charge preamplifier that is connected to the column conductor and is intended to form a preamplified column conductor for integrating the charges carried by the column conductor, - At least one analog-to-digital converter that is connected in series to the preamplified column conductor and is intended to convert the charges integrated at the output of the charge preamplifier into a digital voltage, - A serialization circuit block that is connected to the at least one analog-to-digital converter and is intended to generate an output voltage based on the digital voltage from the at least one analog-to-digital converter is included.

[0020] In an advantageous aspect, one of the at least one analog-to-digital converters is connected to each of the preamplified column conductors.

[0021] In an advantageous aspect, at least two of the preamplified column conductors are connected to each other, and these at least two interconnected preamplified column conductors converge towards one of the at least one analog-to-digital converters.

[0022] In an advantageous aspect, the serialization circuit block is positioned downstream of the at least one analog-to-digital converter on a second monolithic substrate.

[0023] Reading the detailed description of one embodiment provided as an example, the present invention will be better understood and further advantages will become apparent, and this description is illustrated by the accompanying drawings as follows:

Brief Description of the Drawings

[0024] [Figure 1] Schematically shows a conventional image detector. [Figure 2] Schematically shows a prior art image detector and the details of the charge integration structure of the prior art image detector. [Figure 3] Schematically shows an image detector according to the present invention and the details of the charge integration structure of the image detector according to the present invention. [Modes for carrying out the invention]

[0025] For clarity, these drawings are not all necessarily to the same scale. Furthermore, the same elements are given the same reference numerals in various drawings.

[0026] Generally, the present invention refers to a conventional image detector including a planar sensor comprising a set of pixels aligned in a matrix typically along rows and down columns, a row addressing block, a column readout block, row conductors connecting the rows of pixels to the row addressing block, and column conductors connecting the columns of pixels to the column readout block. It should be noted that, in the context of this patent application, the concepts of rows and columns are only relative, and the rows of pixels and the columns of pixels are, for example, rows of pixels arranged perpendicular to each other, but are not limited to these. Row conductors, or column conductors, are defined as being oriented parallel to the rows of pixels or columns of pixels.

[0027] Figure 1 shows a conventional image detector 10. The image detector 10 includes a sensor 11 formed on a first monolithic substrate 12. The first monolithic substrate 12 includes a set of pixels P(i,j) aligned in a matrix array 13 that descends along a row Li and down a column Cj. The matrix array 13 may contain any number of rows and columns to form pixels P(i,j). The matrix array 13 forms a geometric region on the first substrate 12. The pixels are denoted by the general form P(i,j), where i and j are positive integers indicating the rank of the row and the rank of the column in the matrix array 13, respectively. The set of pixels P(i,j) is configured to generate a signal based on radiation that collides with the detector 10. The sensor 11 includes column conductors Yj, each connected to a hixel in the same column Cj. The column conductors Yj are intended to carry the signals generated by the pixels P(i,j). Similarly, sensor 11 includes low conductors Xi, each connected to a pixel of the same low Li. The matrix array 13 of pixels P(i,j) includes even-order and odd-order column Cj. Similarly, the matrix array 13 of pixels P(i,j) includes even-order and odd-order low Li. Sensor 10 includes a contact pad 14 located on the edge of the first substrate 12, outside the matrix array 13 of pixels P(i,j). The contact pad 14 is connected to column conductor Yj. Image detector 10 includes a low addressing block 15 located near the first substrate 12 and connected to low conductors Xi. Low addressing block 15 is a name given to any assembly that includes at least one low addressing block. Block 15 may be incorporated into the first substrate 12 as shown in Figure 1, or it may be incorporated into a different substrate. The low addressing block 15 allows each row of pixel Li to be addressed individually. The image detector 10 includes a column readout block 16 formed on a second substrate 17 which is generally different from the first substrate 12. The column readout block 16 includes connection points 18 that connect the column readout block 16 to the contact pads 14.The column readout block 16 makes it possible to read the signal generated by the low pixel selected by the low addressing block.

[0028] Pixel P(i,j) includes a photodiode Dp(i,j) associated with an electronic switch T(i,j). The photodiode Dp(i,j) can, of course, be replaced with a photosensitive element capable of generating an electrical signal when exposed to photon emission. The pixel structure shown in Figure 1 is intentionally simplified, and more complex structures can also be implemented within the scope of this invention.

[0029] The switch T(i,j) formed by the transistor is connected to the low conductor Xi of low i by its gate Gi, to the column conductor Yi by its drain Di, and to the cathode of the photodiode Dp(i,j) by its source Sij. The anodes of all photodiodes Dp(i,j) are connected to a common potential, such as ground. The low addressing block 15 includes elements for generating a signal that is injected into the low conductor Xi to drive the opening and closing of the transistor T(i,j). The column readout block 16 may include elements for processing the signal received at the column conductor Yj. These may, in particular, be amplifiers and / or analog-to-digital converters.

[0030] The image detector 11 conventionally operates as follows: During the image acquisition phase, the photodiode Dp(i,j) is exposed to radiation, generating a charge at source Sij. The amount of charge at each source Sij depends on the intensity of the radiation received by the pixel P(i,j) under consideration. The image acquisition phase is followed by a readout phase, which is performed for each low. The signals injected into the various low conductors Xi become continuously active, and the potential of each column conductor Yj continuously represents the amount of charge generated in the various pixels P(i,j) of column j.

[0031] Figure 2 schematically shows the prior art image detector 10 and the details of the charge integration configuration of the prior art image detector. The prior art digital detector 10 includes a planar sensor 11 formed on a first monolithic substrate. The planar sensor is aligned in a matrix array 13 that descends column Ci along low Li and is configured to generate charge based on radiation 19 that collides with the detector 10. The sensor 11 includes column conductors Yj, each connected to a pixel P(i,j) in the same column Cj and intended to carry the charge generated by the pixel P(i,j). At this stage, the signal is analog. At the output of the sensor 11, there is a set of integrated readout circuits 33, which have analog outputs. These circuits 33 are connected to a daughterboard 34, which is connected to an analog-to-digital converter 31 by a board connector 35. In other words, the signal is processed in an analog manner outside the first substrate. The analog signal region is denoted by reference code SA. Digital processing, denoted by reference code SN, takes place after the output of the analog-to-digital converter 31.

[0032] The integral of the charge at the foot of the column will be explained using the details shown on the right side of the figure.

[0033] In this charge integration configuration of the prior art detector 10, each of the N columns is connected to an analog multiplexer 30, which in turn is connected to an analog-to-digital converter block 31. In other words, the charges from the N channels, i.e., the N column conductors Yj, are integrated, sampled (29), then multiplexed in an analog manner, and input to one or more external analog-to-digital converter blocks 31. Data conversion is performed outside this configuration and requires signal matching (gain, buffering 53, etc.). For each channel, the signal can be serialized by a serialization circuit block 23 and output to, for example, an FPGA circuit 36. Finally, CDS correction is applied; that is, in the prior art configuration, the columns are pre-reset and a second readout is performed, followed by a blank readout, which is then subtracted from the signal.

[0034] In this prior art configuration, the conversion of electric charge to analog voltage takes place within the column. Next, outside the column, the various columns are multiplexed into analog-to-digital converter blocks. The analog data is then multiplexed and sent to the converter.

[0035] In addition to the multiplexing function, this prior art solution requires additional processing time due to correlated double sampling, which can be disadvantageous in terms of execution speed. Furthermore, analog processing of signals downstream of the column does not guarantee data integrity.

[0036] Figure 3 schematically shows the image detector 100 according to the present invention and details of the charge integration configuration of the image detector according to the present invention. The basic description of the digital detector 100 is the same as that of detector 10 in Figure 1. The differences are seen here at the level of the integration block, which is shown in more detail on the right side of the figure. Hereafter, reference numerals are used based on common elements in the detectors of Figures 1 and 2, although not all of them are shown in Figure 3. The digital detector 100 according to the present invention includes a planar sensor 11 and a first monolithic substrate and a second monolithic substrate, with the planar sensor 11 positioned on the first monolithic substrate. The planar sensor includes a set of pixels P(i,j) aligned in a matrix array 13 descending column Cj along low Li and configured to generate charge based on radiation 19 that collides with the detector 100. The sensor 11 includes a column conductor Yj, each connected to a pixel P(ij) on the same column Cj and intended to carry the charge generated by the pixels P(i,j). According to the present invention, the detector includes, on a second monolithic substrate distinct from the first substrate, a charge preamplifier 20 connected to each of the column conductors Yj, forming a pre-amplified column conductor 21j which is intended to integrate the charge carried by the column conductor Yj. The sensor 11 includes at least one analog-to-digital converter 22j connected in series with the pre-amplified column conductor 21j which is intended to convert the charge integrated at the output of the charge preamplifier 20 into a digital voltage. Finally, the sensor 11 includes a series circuit block 23 connected to at least one analog-to-digital converter 22j which is intended to generate an output voltage based on the digital voltage from at least one analog-to-digital converter 22j. As can be seen from Figure 3, the signal is processed in an analog manner on the second monolithic substrate. The analog signal region is denoted by reference code SA. The digital processing, denoted by reference code SN, takes place at the output of the first monolithic substrate.

[0037] In the digital detector of the present invention, the serial circuit block 23 is located downstream of at least one analog-to-digital converter 22j on a second monolithic substrate.

[0038] Analog-to-digital conversion is performed in parallel on each channel and then serialized into one or more digital outputs, which can be similar to digital multiplexing. One characteristic of the present invention is that a charge preamplifier and a channel-by-channel analog-to-digital converter are combined upstream of the serialization circuit block on a single monolithic substrate, separated from the photodiode matrix array.

[0039] The principle of this invention is therefore based on a monolithic circuit that performs the conversion of electric charge to digital voltage. In other words, digitization is performed in each column before multiplexing. This invention therefore makes it possible to perform digital multiplexing that is less susceptible to noise and interference from analog signals. This digital multiplexing is made possible through the use of sigma-delta converters in each column. In other words, this invention aims to convert X-rays into electric charge via a special sensor, and then amplify this charge (on the order of pC) through pre-amplification and integration stages to digitize it.

[0040] The present invention enables conversion of more than 16 bits in a matrix array that is typically very large (exceeding 1 million pixels) with an equivalent number of frames.

[0041] Unlike prior art that proposes solutions in which digitization is performed after analog multiplexing, the present invention proposes positioning an analog-to-digital converter for each channel and then performing digital multiplexing. The present invention consists of fusing, i.e., combining, ADCs on a second substrate. As a result, the channels can be routed to the rest of the block.

[0042] In a first embodiment of the present invention, the solution involves associating a charge preamplifier 20 and an analog-to-digital converter (ADC) 22j within the same monolithic integrated circuit for each channel. In other words, the analog-to-digital converter 22j is connected to each of the pre-amplified column conductors 21j.

[0043] By integrating the analog-to-digital converter directly onto the first board and with the pre-amplified column conductors, the number of interfaces between the analog and digital domains can be reduced. This solution allows for the direct generation of one or more digital outputs from the first chip without the risk of signal degradation after the output. Finally, this direct integration simplifies the circuit board for subsequent signal processing.

[0044] Therefore, this integration can significantly improve linearity, noise, and crosstalk performance, while simultaneously reducing the cost and bulk of the components that perform the integration / digitalization functions.

[0045] In another embodiment of the present invention, each channel is associated with a charge preamplifier, and one analog-to-digital converter (ADC) 22j is associated with multiple channels within the same monolithic integrated circuit. In other words, the analog-to-digital converter 22j is connected to multiple pre-amplified column conductors 21j. In this variant, the analog-to-digital converter is shared among multiple channels to reduce space and density where possible, depending on the application.

[0046] In one variation of the present invention, at least two (e.g., four) of the pre-amplified column conductors 21j are interconnected, and these interconnected at least two pre-amplified column conductors 21j are focused toward one of at least one analog-to-digital converters 22j.

[0047] The present invention is based on manufacturing a converter for directly converting the charge from a matrix array of pixels into a digital voltage on a second monolithic substrate. As can be seen from Figure 3, at the output of the sensor, the signal is digital, thereby ensuring the data integrity of this signal.

[0048] The present invention differs from the prior art in that it associates the channel preamplifier and analog-to-digital converter (ADC) within the same monolithic integrated circuit for each channel or at least a number of channels. This integration significantly improves linearity, noise, and crosstalk performance while simultaneously reducing the cost and bulk of the integration / digitalization components.

[0049] More precisely, the charge preamplifier overcomes the limitations of a standard integration stage by enabling the integration of the charge at the same speed as the charge is transmitted from the pixel through the column to the input of the integrator circuit. This arrangement has two advantages. The first advantage is the absence of time loss, resulting in significant time savings in overall processing time, and therefore in read speed and transmission time (data processing time is shorter than integration time) for tiles. The second advantage is a significant noise reduction, especially at high gains, as a result of the integration of the input charge.

[0050] In addition, the direct association between the preamplifier and the analog-to-digital converter (ADC) eliminates the need for the conventional analog multiplexing stage between the column group and its single converter.

[0051] By integrating the analog-to-digital converter (ADC) within the processing channel, it becomes possible to have an ADC that is perfectly designed, adapted to the specific situation, and thereby limits any parasitic effects. The advantages of this integration are numerous: a. A very significant improvement in overall integrated linearity b. Significant improvements in spatial linearity (especially between channels) c. Significant reduction in noise performance d. Limiting vertical crosstalk effects between channels (each processing channel remains independent until final digitization). e. Overall cost reduction of the solution as a result of integration

[0052] However, drawbacks should also be considered. In particular, there is the difficulty in developing and integrating an analog-to-digital converter (ADC) that is compatible with applications requiring high resolution (14-16 bits) and such performance levels (speed, linearity, noise). In addition, the solution proposed by the present invention requires an increase in chip area and the resulting chip cost. Finally, the solution proposed by the present invention increases the chip's power consumption and necessitates adequate heat dissipation.

[0053] The present invention makes it possible to reduce kTC noise originating from the column as a result of a specific arrangement of a charge preamplifier combined with an analog-to-digital converter (ADC) to minimize noise in the downstream system. The result is transmitted in the form of a series-connected digital voltage (and the signal does not degrade further after this step).

[0054] The present invention addresses the need to minimize signal interference (noise / linearity / leakage / crosstalk) while integrating the charge from the pixel matrix array as quickly as possible, which is made possible by a charge preamplifier combined with an ADC in the same block on the same chip. The transmission speed of the ADC and the digital output should be sufficiently fast with respect to the characteristics of the pixel matrix array (particularly the pixel focusing time).

[0055] In the detector 100 of the present invention, the analog-to-digital converter is installed inside the column. This configuration eliminates the need for a multiplexer, thereby saving time. Analog processing is performed within the column, and a digital voltage is provided at the column output. Here, the concept of a column should be understood to extend beyond the physical column on the photodiode matrix array to include individual "channels" in the conversion circuit outside the matrix array. This eliminates problems of signal contamination or stability. At the column output, according to the detector of the present invention, digital signal processing is possible, thereby ensuring the integrity of the image of the analog data from the sensor.

[0056] The features of this invention are based on the direct conversion of electric charge into a digital signal, without signal modulation by intermediate steps and / or stages. This invention is based on coupling a charge preamplifier with an analog-to-digital converter (ADC) within the same processing channel of a pixel column.

[0057] By designing analog-to-digital converters and using them in parallel, it becomes possible to directly convert electric charge into a digital signal without any intermediate steps (especially analog multiplexing), thus limiting the sources of noise and distortion.

[0058] By combining a preamplifier with such a parallel analog-to-digital converter (ADC), it becomes possible to create a true "charge-to-digital" converter (charge digitization circuit), where the entire conversion takes place within the column's processing channel, eliminating the need for additional operations of a similar form, such as multiplexing.

[0059] The analog-to-digital converters (ADCs) are in parallel (i.e., one ADC per channel / preamplifier, or one per group of channels / preamplifiers) and must be integrated into the processing unit immediately following the column. The ADCs can be of any type (especially successive approximation or sigma-delta), and resolution is not a concern (generally 14 or 16 bits, perhaps more).

[0060] Depending on the requirements of the target application (speed, noise / linearity, pixel size, binning capability), as mentioned above, one parallel analog-to-digital converter common to multiple channels can be considered to optimize the circuit design in terms of area.

[0061] The principle of the present invention can be applied to passive pixel (1T imager) imaging devices of all kinds, particularly in medical or NDT applications. [Explanation of Symbols]

[0062] 11. Flat-plate sensor 13 Matrix Arrays 19 Radiation 20 Charge Preamplifier 21j pre-amplified column conductor 22j Analog-to-Digital Converter 23 Series Circuit Block 100 Digital Detectors CJ Column Li Low P(i,j) pixels

Claims

1. The digital detector (100) includes a flat plate sensor (11), a first monolithic substrate, and a second monolithic substrate, wherein the flat plate sensor (11) is positioned on the first monolithic substrate. On the aforementioned first monolithic substrate: a. A set of pixels (P(i,j)) aligned in a matrix array (13) along a row (Li) and descending a column (Cj), configured to generate a charge based on radiation (19) that collides with the digital detector (100), b. Column conductors (Yj), each connected to the pixels (P(i,j)) of the same column (Cj), and intended to carry the charge generated by the pixels (P(i,j)). Includes, On the second monolithic substrate, which is different from the first monolithic substrate: c. For each of the column conductors (Yj), a charge preamplifier (20) is provided, which is connected to the column conductor (Yj) and forms a pre-amplified column conductor (21j) intended to integrate the charge carried by the column conductor (Yj), d. At least one analog-to-digital converter (22j) connected in series with the pre-amplified column conductor (21j), intended to convert the charge integrated at the output of the charge preamplifier (20) into a digital voltage, e. A serial circuit block (23) connected to the at least one analog-to-digital converter (22j), wherein the at least one analog-to-digital converter (22j) is located upstream of the serial circuit block (23) on the second monolithic board and the serial circuit block (23) is intended to generate an output voltage based on the digital voltage from the at least one analog-to-digital converter (22j). A digital detector (100) including the above.

2. The digital detector (100) according to claim 1, wherein one of the at least one analog-to-digital converters (22j) is connected to each pre-amplified column conductor (21j).

3. The digital detector (100) according to claim 1, wherein at least two of the pre-amplified column conductors (21j) are connected to each other, and the at least two connected pre-amplified column conductors (21j) are focused toward one of the at least one analog-to-digital converters (22j).

4. The digital detector (100) according to claim 1, wherein the serialized circuit block (23) is located downstream of the at least one analog-to-digital converter (22j) on the second monolithic substrate.

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