Transparent display device

Abstract

To provide a transparent display device that can improve transparency by increasing the transmission area.SOLUTION: The transparent display device may comprise a first layer including a first power wire and a second power wire along a first direction, a second layer disposed on the first layer and including a third power wire, a fourth power wire, a first data signal wire, a second data signal wire, and a plurality of connecting wires along the first direction, a driving IC disposed between the third power wire and the fourth power wire, and a light-emitting element disposed between the third power wire and the fourth power wire. The first power wire and the third power wire may overlap vertically, and the second power wire and the fourth power wire may overlap vertically.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The embodiments relate to a transparent display device.

Background Art

[0002] Various display devices for embodying images have been developed. For example, there are LCD (liquid crystal display) devices, light-emitting element display devices, OLED (organic light-emitting diode) display devices, and the like.

[0003] On the other hand, an AM (active matrix) type transparent display device that can display an image while allowing light to pass through from the front and rear surfaces without disturbing the visual field has been in the spotlight. In order to embody an AM (active matrix) type transparent display device, various opaque members such as a driving IC, a light-emitting element such as an LED (light-emitting diode), a power wiring, and a signal wiring are arranged.

[0004] There is a problem that the transparency of the transparent display device is reduced by these various opaque members.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The embodiments aim to solve the above-described problems and other problems.

[0006] Another object of the embodiments is to provide a transparent display device that can increase the transmission area and improve the transparency.

[0007] The technical problems of the embodiments are not limited to those described in this section and include those understood from the description of the invention.

Means for Solving the Problems

[0008] To achieve the aforementioned or other objective, according to one aspect of the embodiment, the transparent display device includes: a first layer including a first power supply wiring and a second power supply wiring along a first direction; a second layer disposed on the first layer and including a third power supply wiring, a fourth power supply wiring, a first data signal wiring, a second data signal wiring and a plurality of link wirings along the first direction; a driver IC disposed between the third power supply wiring and the fourth power supply wiring; and a light-emitting element disposed between the third power supply wiring and the fourth power supply wiring, wherein the driver IC is electrically connected to one of the first power supply wiring and the third power supply wiring, one of the second power supply wiring and the fourth power supply wiring, the first data signal wiring, the second data signal wiring and the plurality of link wirings; the light-emitting element is electrically connected to one of the second power supply wiring and the fourth power supply wiring and the plurality of link wirings, the first power supply wiring and the third power supply wiring overlap vertically, and the second power supply wiring and the fourth power supply wiring overlap vertically.

[0009] The transparent display device may further include a substrate having a lower surface on which the first layer is arranged and an upper surface on which the second layer is arranged.

[0010] The first and second power supply wirings may be low-potential wirings, while the third and fourth power supply wirings may be high-potential wirings.

[0011] The first layer may further include a coupling portion that electrically connects the first power supply wiring and the second power supply wiring across the second data signal wiring in a second direction, and a coupling pattern that electrically connects the third power supply wiring and the fourth power supply wiring via first and second vias on the substrate across the first data signal wiring in a second direction.

[0012] The second power supply wiring is electrically connected to the drive IC and the light-emitting element via vias on the substrate, and the third power supply wiring is electrically connected to the drive IC.

[0013] The first and second power supply wirings may be high-potential wirings, while the third and fourth power supply wirings may be low-potential wirings.

[0014] The first layer may further include a coupling portion that electrically connects the first power supply wiring and the second power supply wiring across the first data signal wiring in a second direction, and a coupling pattern that electrically connects the third power supply wiring and the fourth power supply wiring via first and second vias on the substrate across the second data signal wiring in a second direction.

[0015] The connecting portion is electrically connected to the drive IC via vias on the substrate, and the fourth power supply wiring is electrically connected to the drive IC and the light-emitting element.

[0016] The first and fourth power supply wirings may be low-potential wirings, while the second and third power supply wirings may be high-potential wirings.

[0017] The first layer may further include a first connecting portion that electrically connects the first power supply wiring and the fourth power supply wiring via a first via on the substrate, crossing the first data signal wiring in a second direction, and a second connecting portion that electrically connects the second power supply wiring and the third power supply wiring via a second via on the substrate, crossing the second data signal wiring in a second direction.

[0018] The third power supply wiring is electrically connected to the drive IC, and the fourth power supply wiring is electrically connected to the drive IC and the light-emitting element.

[0019] The transparent display device further includes a first substrate having a lower surface on which the first layer is arranged, and a second substrate having an upper surface on which the second layer is arranged, and the drive IC and the light-emitting element are arranged between the first substrate and the second substrate.

[0020] The transparent display device can further include a conductive spacer between the first substrate and the second substrate.

[0021] The light-emitting elements can be stacked perpendicular to each other and include a plurality of light-emitting elements electrically connected to the plurality of connection wirings.

[0022] The light-emitting elements can be horizontally arranged adjacent to each other along the second direction and include a plurality of light-emitting elements connected to the plurality of connection wirings.

Advantages of the Invention

[0023] The effects of the transparent display device according to the embodiment will be described as follows.

[0024] According to at least one of the embodiments, the first power supply wiring and the second power supply wiring on the lower surface of the substrate overlap perpendicularly with the third power supply wiring and the fourth power supply wiring on the upper surface of the substrate, respectively, so that there is an advantage that the transmission area increases and the transparency is improved.

[0025] According to at least one of the embodiments, by electrically connecting the third power supply wiring and the fourth power supply wiring on the upper surface of the substrate through a connection pattern arranged on the lower surface of the substrate, the first data signal wiring and the second data signal wiring arranged between the third power supply wiring and the fourth power supply wiring on the upper surface of the substrate can be prevented from being electrically short-circuited with the third power supply wiring and the fourth power supply wiring.

[0026] According to at least one of the embodiments, capacitors are respectively formed by the first power supply wiring, the substrate, and the third power supply wiring that overlap perpendicularly with each other, and the second power supply wiring, the substrate, and the fourth power supply wiring that overlap perpendicularly with each other, so that a noise reduction effect of being insensitive to noise can be obtained. As a result, signal distortion due to noise does not occur, and thus image quality degradation is prevented.

[0027] The additional scope of applicability of the embodiments will become apparent from the following detailed description. However, various changes and modifications within the spirit and scope of the embodiments will be clearly understood by those skilled in the art, so specific embodiments such as the detailed description and preferred embodiments should be understood as merely illustrative.

Brief Description of the Drawings

[0028] [Figure 1] FIG. 1 is a cross-sectional view of a transparent display device according to a first embodiment. [Figure 2] FIG. 2 is a plan view of a transparent display device according to a first embodiment. [Figure 3A] FIG. 3A illustrates the first layer shown in FIG. 2. [Figure 3B] FIG. 3B illustrates the second layer shown in FIG. 2. [Figure 4] FIG. 4 illustrates the connection relationship between a driving IC and a plurality of light-emitting element chips. [Figure 5] FIG. 5 is a plan view of a transparent display device according to a second embodiment. [Figure 6A] FIG. 6A illustrates the first layer shown in FIG. 5. [Figure 6B] FIG. 6B illustrates the second layer shown in FIG. 5. [Figure 7] FIG. 7 is a plan view of a transparent display device according to a third embodiment. [Figure 8A] FIG. 8A is a cross-sectional view of the transparent display device shown in FIG. 7 cut along the A-A' line. [Figure 8B] FIG. 8B is a cross-sectional view of the transparent display device shown in FIG. 7 cut along the B-B' line. [Figure 9] FIG. 9 illustrates a state in which the second power supply wiring of the first layer and the third power supply wiring of the second layer are electrically connected to each other along the first direction in the transparent display device shown in FIG. 7. [Figure 10]Figure 10 illustrates how the first power wiring of the first layer and the fourth power wiring of the second layer are electrically connected to each other along the first direction in the transparent display device shown in Figure 7. [Figure 11] Figure 11 is a plan view of a transparent display device according to the fourth embodiment. [Figure 12A] Figure 12A illustrates the first layer shown in Figure 11. [Figure 12B] Figure 12B illustrates the second layer shown in Figure 11. [Figure 13] Figure 13 is a cross-sectional view of a transparent display device according to the second embodiment. [Figure 14A] Figure 14A is a cross-sectional view illustrating an example of a transparent display device according to the third embodiment. [Figure 14B] Figure 14B is a cross-sectional view illustrating another example of a transparent display device according to the third embodiment.

[0029] The size, shape, and numerical values ​​of the components shown in the drawings do not necessarily match those of the actual components. Furthermore, even if the same component is shown with different sizes, shapes, and numerical values ​​in different drawings, this is merely one example on the drawing, and the same component can have the same size, shape, and numerical values ​​in different drawings. [Modes for carrying out the invention]

[0030] The embodiments disclosed herein will be described in detail below with reference to the attached drawings, but identical or similar components will be given the same reference numeral regardless of the drawing reference numerals, and redundant descriptions will be omitted. The suffixes “module” and “part” used for components in the following description are given or used interchangeably to facilitate the writing of the specification and do not have any mutually distinguishing meaning or role in themselves. The attached drawings are provided to facilitate the understanding of the embodiments disclosed herein and do not limit the technical ideas disclosed herein. Furthermore, when an element such as a layer, region, or substrate 110 is referred to as being “on” another component, this includes elements that are directly on other elements or where other intermediate elements may exist between them.

[0031] Figure 1 is a cross-sectional view of the transparent display device according to the first embodiment. Figure 2 is a plan view of the transparent display device according to the first embodiment. Figure 3A shows the first layer shown in Figure 2, and Figure 3B shows the second layer shown in Figure 2.

[0032] In Figure 2, the transparent display device is illustrated as containing one pixel. The transparent display device may be composed of multiple pixels as illustrated in Figure 2.

[0033] Referring to Figures 1 and 2, the transparent display device according to the first embodiment may include a substrate 110, a first layer 120, a second layer 130, a driver IC 140, a light-emitting element chip 150, and the like. The driver IC 140 may consist of a chip or a die.

[0034] The substrate 110 may be a transparent substrate, a flexible substrate, or a rigid substrate. The substrate 110 may be a transparent and flexible substrate. The substrate 110 may be a transparent and rigid substrate.

[0035] The substrate 110 can be made of a transparent material. The substrate 110 can be made of a flexible or rigid material. For example, the substrate 110 can be made of plastic, polymer resin, glass, etc.

[0036] Multiple vias 111 to 113 are formed on the substrate 110. Each via 111 to 113 can refer to a hole that penetrates the substrate 110, or to a conductor such as a metal with excellent electrical conductivity that is filled into the hole. Each via 111 to 113 can penetrate the substrate 110 and electrically connect the first layer 120 and the second layer 130.

[0037] The first layer 120 is placed on the lower surface of the substrate 110, and the second layer 130 is placed on the upper surface of the substrate 110.

[0038] The first layer 120 has a first power supply wiring 121 and a second power supply wiring 122 arranged along the first direction Y. The first power supply wiring 121 and the second power supply wiring 122 may be arranged parallel to each other along the first direction Y, but are not limited to this arrangement.

[0039] The first power supply wiring 121 may be a low-potential wiring that supplies a low potential voltage. The first power supply wiring 121 may have a mesh shape or a ladder shape. The second power supply wiring 122 may be a low-potential wiring that supplies a low potential voltage. The second power supply wiring 122 may have a mesh shape or a ladder shape.

[0040] The first layer 120 may include a connecting portion 123. The connecting portion 123 is located between the first power wiring 121 and the second power wiring 122.

[0041] The connecting section 123 can electrically connect the first power supply wiring 121 and the second power supply wiring 122 along the second direction X. If the low potential voltage supplied to the first power supply wiring 121 is greater than the low potential voltage supplied to the second power supply wiring 122, the low potential voltage supplied to the first power supply wiring 121 is supplied to the second power supply wiring 122 via the connecting section 123. The low potential voltage supplied to the first power supply wiring 121 is supplied to the second power supply wiring 122 via the connecting section 123 until the low potential voltage supplied to the first power supply wiring 121 and the low potential voltage supplied to the second power supply wiring 122 become the same. Therefore, the connecting section 123 may be an equipotential power supply wiring such that the low potential voltage supplied to the first power supply wiring 121 and the low potential voltage supplied to the second power supply wiring 122 become the same.

[0042] The first power wiring 121, the second power wiring 122, and the connecting portion 123 may be integrally formed from the same metal, but are not limited to this.

[0043] The first layer 120 may include a coupling pattern 124. The coupling pattern 124 is placed between the first power supply wiring 121 and the second power supply wiring 122.

[0044] The coupling pattern 124 is arranged along the second direction X. The coupling pattern 124 is positioned to be spaced apart from the first power supply wiring 121 and the second power supply wiring 122, respectively. As will be described later, the coupling pattern 124 can electrically connect the third power supply wiring 131 and the fourth power supply wiring 132 of the second layer 130. The first data signal wiring 133 of the second layer 130 is positioned between the third power supply wiring 131 and the fourth power supply wiring 132. The coupling pattern 124 of the first layer 120 can electrically connect the third power supply wiring 131 and the fourth power supply wiring 132 in the second layer 130 without electrically short-circuiting with the data signal wiring 133.

[0045] The first power wiring 121, the second power wiring 122, the connecting portion 123, and the connecting pattern 124 may be formed from the same metal using the same photolithography process, but are not limited to this.

[0046] On the other hand, the second layer 130 may include a third power supply wiring 131, a fourth power supply wiring 132, a first data signal wiring 133, a second data signal wiring 134, multiple linking wirings 135-138, multiple pads 181-187, 191-194, etc., along the first direction Y.

[0047] The third power supply wiring 131, the fourth power supply wiring 132, the first data signal wiring 133, the second data signal wiring 134, and the multiple connecting wirings 135-138 may be formed from the same metal using the same photolithography process, but are not limited to this.

[0048] The third power supply wiring 131 and the fourth power supply wiring 132 may be arranged parallel to each other along the first direction Y, but are not limited to this arrangement. The first data signal wiring 133 and the second data signal wiring 134 may be arranged in a line along the first direction Y. The first data signal wiring 133 and the second data signal wiring 134 may be arranged parallel to the third power supply wiring 131 or the fourth power supply wiring 132 along the first direction Y, but are not limited to this arrangement.

[0049] The third power supply wiring 131 may be a high-potential wiring that supplies a high potential voltage. The third power supply wiring 131 may have a mesh shape or a ladder shape.

[0050] The fourth power supply wiring 132 may be a high-potential wiring that supplies a high potential voltage. The fourth power supply wiring 132 may have a mesh shape or a ladder shape.

[0051] As mentioned above, the first layer 120 may include a coupling pattern 124. The coupling pattern 124 can electrically connect the third power supply wiring 131 and the fourth power supply wiring 132 via the first via 111 and the second via 112. That is, one side of the coupling pattern 124 of the first layer 120 is electrically connected to the third power supply wiring 131 of the second layer 130 via the first via 111, and the other side of the coupling pattern 124 of the first layer 120 is electrically connected to the fourth power supply wiring 132 of the second layer 130 via the second via 112.

[0052] If the high potential voltage supplied to the third power supply wiring 131 is greater than the high potential voltage supplied to the fourth power supply wiring 132, the high potential voltage supplied to the third power supply wiring 131 is supplied to the fourth power supply wiring 132 via the connecting pattern 124 of the first layer 120. If the high potential voltage supplied to the third power supply wiring 131 and the high potential voltage supplied to the fourth power supply wiring 132 are the same, the high potential voltage supplied to the third power supply wiring 131 is not supplied to the fourth power supply wiring 132 via the connecting pattern 124, and the high potential voltage supplied to the fourth power supply wiring 132 is not supplied to the third power supply wiring 131 via the connecting pattern 124. In other words, the connecting pattern 124 may be an equipotential power supply wiring such that the high potential voltage supplied to the third power supply wiring 131 and the high potential voltage supplied to the fourth power supply wiring 132 are the same.

[0053] In this embodiment, the high potential voltage is greater than the low potential voltage. The high potential voltage may be called the VDD voltage, and the low potential voltage may be called the VSS voltage. The low potential voltage may be called the first power supply voltage, and the high potential voltage may be called the second power supply voltage, or vice versa.

[0054] On the other hand, since the first power supply wiring 121, the second power supply wiring 122, the third power supply wiring 131, and the fourth power supply wiring 132 are usually arranged on the same plane at a distance from each other so that no electrical short circuits occur, there is a problem that the transparent area of ​​the transparent substrate 110 decreases, resulting in reduced transparency.

[0055] However, in this embodiment, the first power wiring 121 of the first layer 120 and the third power wiring 131 of the second layer 130 can overlap vertically. The first power wiring 121 of the first layer 120 and the third power wiring 131 of the second layer 130 can overlap vertically with the substrate 110 in between. The second power wiring 122 of the first layer 120 and the fourth power wiring 132 of the second layer 130 can overlap vertically. The third power wiring 131 of the first layer 120 and the fourth power wiring 132 of the second layer 130 can overlap vertically with the substrate 110 in between. As a result, the first power wiring 121 and the second power wiring 122 on the lower surface of the substrate 110 overlap vertically with the third power wiring 131 and the fourth power wiring 132 on the upper surface of the substrate 110, respectively, increasing the transparent area and improving transparency.

[0056] Furthermore, in the embodiment, the substrate 110 can have a dielectric constant. In such a case, a first capacitor is formed by the first power supply wiring 121, the third power supply wiring 131, and the substrate 110 between the first power supply wiring 121 and the third power supply wiring 131, and a second capacitor is formed by the second power supply wiring 122, the fourth power supply wiring 132, and the substrate between the second power supply wiring 122 and the fourth power supply wiring 132. As a result, a noise reduction effect that makes the signal less sensitive to noise is obtained by the first and second capacitors. Therefore, signal distortion due to noise does not occur, and image quality defects are prevented.

[0057] On the other hand, the first data signal wiring 133 and the second data signal wiring 134 can serve the role of supplying data signals. As will be described later, the first data signal wiring 133 and the second data signal wiring 134 are connected to the drive IC 140. In such a case, the first data signal wiring 133 may be an input data signal wiring for inputting data signals to the drive IC 140, and the second data signal wiring 134 may be an output data signal wiring for outputting data signals from the drive IC 140 to the drive IC 140 of the next pixel.

[0058] A first data signal wiring 133 and a second data signal wiring 134, electrically connected to the drive IC 140, are arranged for each of several pixels (not shown) along the first direction Y.

[0059] The first data signal wiring 133 and the second data signal wiring 134 are positioned between the third power wiring 131 and the fourth power wiring 132, respectively. As described above, the coupling pattern 124 can electrically connect the third power wiring 131 and the fourth power wiring 132 via the first via 111 and the second via 112 on the substrate 110. This prevents the third power wiring 131 and the fourth power wiring 132 from having an electrical short circuit with the first data signal wiring 133.

[0060] Since the second data signal wiring 134 is located on the second layer 130, even if the connecting portion 123 on the first layer 120 crosses the second data signal wiring 134, the connecting portion 123 on the first layer 120 prevents an electrical short circuit of the second data signal wiring 134.

[0061] On the other hand, the multiple connecting wires 135-138 are arranged between the third power supply wire 131 and the fourth power supply wire 132. The multiple connecting wires 135-138 can electrically connect the drive IC 140 and the light-emitting element chip 150.

[0062] The fourth connection wiring 138 is electrically connected to the second power supply wiring 122 via via 113 on the substrate 110. The fourth connection wiring 138 is also electrically connected to the driver IC 140 and the light-emitting element chip 150.

[0063] Multiple pads 181-187 and 191-194 are arranged in the region where the driver IC 140 is located and the region where the light-emitting element chip 150 is located.

[0064] Multiple pads 181-187 are located on a first region of the substrate 110 between the third power supply wiring 131 and the fourth power supply wiring 132. The driver IC 140 is located in the first region and is physically attached to and electrically connected to the multiple pads 181-187. The multiple pads 181-187 are electrically connected to the third power supply wiring 131, the first data signal wiring 133, the second data signal wiring 134, and multiple connection wirings 135-138.

[0065] Multiple pads 191-194 are arranged on a second region of the substrate 110 between the third power supply wiring 131 and the fourth power supply wiring 132. The light-emitting element chip 150 is placed in the second region and is physically attached to and electrically connected to the multiple pads 191-194. Physical attachment can be performed using a die bonding method, but is not limited to this.

[0066] The first pad 191 of the second region is electrically connected to the fifth pad 185 of the first region via the first connecting wire 135, the second pad 192 of the second region is electrically connected to the sixth pad 186 of the first region via the second connecting wire 136, and the third pad 193 of the second region is electrically connected to the seventh pad 187 of the first region via the third connecting wire 137. The fourth pad 194 of the second region is electrically connected to the second pad 182 of the first region via the fourth connecting wire 138. The fourth pad 194 is electrically connected to the second power supply wire 122 of the first layer 120 via the fourth connecting wire 138 and via 113 on the substrate 110. This supplies a low potential voltage from the second power supply wire 122 to the second pad 182 of the first region and the fourth pad 194 of the second region.

[0067] Meanwhile, the third power supply wiring 131 is electrically connected to the first pad 181 of the first region, and a high potential voltage is supplied from the third power supply wiring 131 to the first pad 181. The first data signal wiring 133 is electrically connected to the third pad 183 of the first region, and the data signal is transmitted to the drive IC 140 via the third pad 183. The drive IC 140 generates a drive signal in response to the data signal and transmits it to the light-emitting element chip 150, and the light-emitting element chip 150 can emit light in response to the drive signal. The drive signal may be a drive current, but is not limited to this. The second data signal wiring 134 is electrically connected to the fourth pad 184 of the first region, and the data signal is transmitted to the next pixel via the second data signal wiring 134.

[0068] The light-emitting element chip 150 may be a component that emits light. In this embodiment, the light-emitting element chip 150 can be made of an inorganic semiconductor material as a semiconductor light-emitting element chip 150.

[0069] As shown in Figure 1, the light-emitting element chip 150 may include a plurality of light-emitting elements 151 to 153 stacked perpendicularly to each other.

[0070] The first light-emitting element 151 may include a red light-emitting element that emits red light, the second light-emitting element 152 may include a green light-emitting element that emits green light, and the third light-emitting element 153 may include a blue light-emitting element that emits blue light, but is not limited to these.

[0071] The second light-emitting element 152 is positioned above the first light-emitting element 151, and the third light-emitting element 153 is positioned above the second light-emitting element. In this case, the red light generated by the first light-emitting element 151 is emitted forward via the second light-emitting element 152 and the third light-emitting element 153, the green light generated by the second light-emitting element 152 is emitted forward via the third light-emitting element 153, and the blue light generated by the third light-emitting element 153 can be emitted directly forward.

[0072] As mentioned above, the drive IC 140 can generate a drive signal (or drive current) in response to the data signal and transmit it to the light-emitting element chip 150. The brightness changes depending on the intensity of the drive signal (or drive current), enabling gradation expression.

[0073] The drive signals may be a first drive signal, a second drive signal, and a third drive signal. The first drive signal, the second drive signal, and the third drive signal may be different from each other.

[0074] The first light-emitting element 151 can emit red light in response to a first drive signal, the second light-emitting element 152 can emit green light in response to a second drive signal, and the third light-emitting element 153 can emit blue light in response to a third drive signal.

[0075] The first pads 191 to the third pads 193 are electrically connected to the anode electrodes of the first light-emitting element 151, the second light-emitting element 152, and the third light-emitting element 153, which are stacked vertically on top of each other. The anode electrode of the first light-emitting element 151 is electrically connected to the first connecting wire 135 via the first pad 191, the anode electrode of the second light-emitting element 152 is electrically connected to the second connecting wire 136 via the second pad 192, and the anode electrode of the third light-emitting element 153 is electrically connected to the third connecting wire 137 via the third pad 193.

[0076] The fourth pad 194 may be connected in common to the cathode electrodes of the vertically stacked first light-emitting element 151, second light-emitting element 152, and third light-emitting element 153. In this way, the fourth pad 194 can be called a common pad, but is not limited to this.

[0077] The driver IC 140 and the light-emitting element chip 150 may be surrounded by a first power supply wiring 121 (or third power supply wiring 131), a second power supply wiring 122 (or fourth power supply wiring 132), a connecting portion 123, and a connecting pattern 124. That is, with respect to the driver IC 140 and the light-emitting element chip 150, the first power supply wiring 121 may be arranged to the left, the second power supply wiring 122 to the right, the connecting portion 123 in front, and the connecting pattern 124 behind.

[0078] In this embodiment, the light-emitting element chip 150 can consist of a single chip or die in which multiple light-emitting elements 151 to 153 are packaged by stacking. The drawing shows one light-emitting element chip 150 in which multiple light-emitting elements 151 to 153 are packaged by stacking, but two or more light-emitting element chips may be provided. That is, two or more light-emitting element chips may be provided between the third power supply wiring 131 and the fourth power supply wiring 132.

[0079] In contrast, as shown in Figure 4, the light-emitting element chip 150' may include a first light-emitting element chip 151', a second light-emitting element chip 152', and a third light-emitting element chip 153', which are individually composed of chips or dies. In such a case, the first light-emitting element chip 151', the second light-emitting element chip 152', and the third light-emitting element chip 153' may be arranged horizontally to each other along the second direction X. For this purpose, a plurality of common pads 194a, 194b, and 194c are electrically connected to the fourth coupling wiring 138. For example, the fourth coupling wiring 138 may be long along the second direction X, and the first, second, and third regions of the fourth coupling wiring 138 may be assigned to the plurality of common pads 194a, 194b, and 194c.

[0080] The first pads 191 to the third pads 193 are arranged to correspond horizontally to each of the multiple common pads 194a, 194b, and 194c. In this case, the first light-emitting chip 151' is physically attached to the first pad 191 and the common pad 194a and electrically connected. The second light-emitting chip 152' is physically attached to the second pad 192 and the common pad 194b and electrically connected. The third light-emitting chip 153' is physically attached to the third pad 193 and the common pad 194c and electrically connected.

[0081] Figure 5 is a plan view of a transparent display device according to the second embodiment. Figure 6A shows the first layer shown in Figure 5, and Figure 6B shows the second layer shown in Figure 5.

[0082] In Figure 5, the transparent display device is illustrated as containing one pixel. The transparent display device may be composed of multiple pixels as illustrated in Figure 5.

[0083] Although a cross-sectional view of the transparent display device according to the second embodiment is not shown, this cross-sectional view is identical to the cross-sectional view shown in Figure 1.

[0084] The second embodiment is identical to the first embodiment (Figures 2 to 3B), except that the first power supply wiring 121 and the second power supply wiring 122 are high-potential wiring, and the third power supply wiring 131 and the fourth power supply wiring 132 are low-potential wiring. In the second embodiment, components having the same shape, structure and / or function as those in the first embodiment (Figures 2 to 3B) are assigned the same reference numerals, and detailed descriptions are omitted. The descriptions omitted below in relation to the second embodiment can be easily understood from the description of the first embodiment (Figures 2 to 3B).

[0085] Referring to Figures 1 and 5, the transparent display device according to the second embodiment may include a substrate 110, a first layer 120, a second layer 130, a driver IC 140, a light-emitting element chip 150, and the like.

[0086] The first layer 120 is placed on the lower surface of the substrate 110, and the second layer 130 is placed on the upper surface of the substrate 110.

[0087] As shown in Figure 6A, the first layer 120 may include a first power supply wiring 121, a second power supply wiring 122, a connecting section 125, a connecting pattern 126, and the like.

[0088] The first power wiring 121 and the second power wiring 122 are arranged along the first direction Y, and the connecting portion 125 and the connecting pattern 126 are arranged along the second direction X. The connecting portion 125 and the connecting pattern 126 are located between the first power wiring 121 and the second power wiring 122.

[0089] The connecting portion 125 can electrically connect the first power supply line 121 and the second power supply line 122 across the first data signal line 133 of the second layer 130 along the second direction X. The connecting pattern 126 can electrically connect the third power supply line 131 and the fourth power supply line 132 of the second layer 130 via the first via 114 and the second via 115 on the substrate 110 across the second data signal line 134 along the second direction X. This prevents the third power supply line 131 and the fourth power supply line 132 from having an electrical short circuit with the second data signal line 134.

[0090] The connecting portion 125 is electrically connected to the drive IC 140 via vias 116, pads 181, etc. on the substrate 110. As a result, the first power supply wiring 121 and the second power supply wiring 122 of the first layer 120 are electrically connected to the drive IC 140 via the connecting portion 125. The high potential voltage supplied to the first power supply wiring 121 and the second power supply wiring 122 is supplied to the drive IC 140 via the connecting portion 125.

[0091] The fourth power supply wire 132 is electrically connected to the driver IC 140 and the light-emitting element chip 150. The fourth power supply wire 132 is electrically connected to the light-emitting element chip 150 via the fourth coupling wire 138a, the fourth pad 194, etc. The low potential voltage supplied to the fourth power supply wire 132 is supplied to the light-emitting element chip 150 via the fourth coupling wire 138a. The fourth power supply wire 132 is further electrically connected to the driver IC 140 via another fourth coupling wire 138b, the second pad 192, etc. The low potential voltage supplied to the fourth power supply wire 132 is further supplied to the driver IC 140 via another fourth coupling wire 138b.

[0092] As shown in Figure 6B, the second layer 130 may include a third power supply wiring 131, a fourth power supply wiring 132, a first data signal wiring 133, a second data signal wiring 134, multiple linking wirings 135-138, multiple pads 181-187, 191-194, and so on.

[0093] The third power supply wiring 131, the fourth power supply wiring 132, the first data signal wiring 133, and the second data signal wiring 134 are arranged along the first direction Y.

[0094] The first data signal wiring 133 and the second data signal wiring 134 are located between the third power supply wiring 131 and the fourth power supply wiring 132.

[0095] As mentioned above, in the first embodiment (Figures 2 to 3B), the first power supply wiring 121 and the second power supply wiring 122 may be low-potential wiring, and the third power supply wiring 131 and the fourth power supply wiring 132 may be high-potential wiring.

[0096] However, as shown in Figures 5, 6A, and 6B, in the second embodiment, the first power supply wiring 121 and the second power supply wiring 122 may be high-potential wiring, and the third power supply wiring 131 and the fourth power supply wiring 132 may be low-potential wiring.

[0097] On the other hand, in this embodiment, the first power wiring 121 of the first layer 120 and the third power wiring 131 of the second layer 130 can overlap vertically. The first power wiring 121 of the first layer 120 and the third power wiring 131 of the second layer 130 can overlap vertically with the substrate 110 in between. The second power wiring 122 of the first layer 120 and the fourth power wiring 132 of the second layer 130 can overlap vertically. The third power wiring 131 of the first layer 120 and the fourth power wiring 132 of the second layer 130 can overlap vertically with the substrate 110 in between. As a result, the first power wiring 121 and the second power wiring 122 on the lower surface of the substrate 110 overlap vertically with the third power wiring 131 and the fourth power wiring 132 on the upper surface of the substrate 110, respectively, increasing the transparent area and improving transparency.

[0098] Furthermore, in the embodiment, the substrate 110 can have a dielectric constant. In such a case, a first capacitor is formed by the first power supply wiring 121, the third power supply wiring 131, and the substrate 110 between the first power supply wiring 121 and the third power supply wiring 131, and a second capacitor is formed by the second power supply wiring 122, the fourth power supply wiring 132, and the substrate between the second power supply wiring 122 and the fourth power supply wiring 132. As a result, a noise reduction effect that makes the signal less sensitive to noise is obtained by the first and second capacitors. Therefore, signal distortion due to noise does not occur, and image quality defects are prevented.

[0099] Figure 7 is a plan view of a transparent display device according to the third embodiment. Figure 8A is a cross-sectional view of the transparent display device shown in Figure 7, cut along the line A-A'. Figure 8B is a cross-sectional view of the transparent display device shown in Figure 7, cut along the line B-B'. Figure 9 shows how the second power wiring of the first layer and the third power wiring of the second layer are electrically connected to each other along the first direction in the transparent display device shown in Figure 7.

[0100] Figure 10 illustrates how the first power wiring of the first layer and the fourth power wiring of the second layer are electrically connected to each other along the first direction in the transparent display device shown in Figure 7.

[0101] Referring to Figures 7, 8A, and 8B, the transparent display device according to the third embodiment may include a substrate 110, a first layer 120, a second layer 130, and so on.

[0102] The first layer 120 is placed on the underside of the substrate 110, and the second layer 130 is placed on the topside of the substrate 110. The first layer 120 may include a plurality of first power supply lines 121, a plurality of second power supply lines 122, etc., and the second layer 130 may include a plurality of third power supply lines 131, a plurality of fourth power supply lines 132, etc.

[0103] Although not shown in the diagram, multiple pixels may be provided between multiple third power supply lines 131 and multiple fourth power supply lines 132. That is, multiple pixels may be provided along the first direction Y between adjacent third power supply lines 131 and fourth power supply lines 132. Furthermore, multiple pixels may be provided along the first direction Y between other adjacent third power supply lines 131 and fourth power supply lines 132.

[0104] Although not shown in the figures, each of the multiple pixels may be provided with a driver IC 140 and a light-emitting element chip 150. The driver IC 140 and the light-emitting element chip 150 may be mounted on the upper surface of the substrate 110.

[0105] Multiple first power supply wires 121 and multiple second power supply wires 122 are arranged on the underside of the substrate 110. The multiple first power supply wires 121 and multiple second power supply wires 122 may be arranged parallel to each other along the first direction Y, but are not limited to this arrangement.

[0106] Multiple third power supply lines 131 and multiple fourth power supply lines 132 are arranged on the upper surface of the substrate 110. The multiple third power supply lines 131 and multiple fourth power supply lines 132 may be arranged parallel to each other along the first direction Y, but are not limited to this.

[0107] In this embodiment, multiple first power supply wirings 121 of the first layer 120 and multiple third power supply wirings 131 of the second layer 130 can overlap vertically. Multiple first power supply wirings 121 of the first layer 120 and multiple third power supply wirings 131 of the second layer 130 can overlap vertically with the substrate 110 in between. Multiple second power supply wirings 122 of the first layer 120 and multiple fourth power supply wirings 132 of the second layer 130 can overlap vertically. Multiple third power supply wirings 131 of the first layer 120 and multiple fourth power supply wirings 132 of the second layer 130 can overlap vertically with the substrate 110 in between. As a result, the multiple first power supply lines 121 on the lower surface of the substrate 110 overlap perpendicularly with the multiple third power supply lines 131 on the upper surface of the substrate 110, and the multiple third power supply lines 131 on the lower surface of the substrate 110 overlap perpendicularly with the multiple fourth power supply lines 132 on the upper surface of the substrate 110, thereby increasing the transparent area and improving transparency.

[0108] Furthermore, in the embodiment, the substrate 110 can have a dielectric constant. In such a case, a first capacitor is formed by the first power supply wiring 121, the third power supply wiring 131, and the substrate 110 between the first power supply wiring 121 and the third power supply wiring 131, and a second capacitor is formed by the second power supply wiring 122, the fourth power supply wiring 132, and the substrate between the second power supply wiring 122 and the fourth power supply wiring 132. As a result, a noise reduction effect that makes the signal less sensitive to noise is obtained by the first and second capacitors. Therefore, signal distortion due to noise does not occur, and image quality defects are prevented.

[0109] On the other hand, the multiple first power supply lines 121 and the multiple second power supply lines 122 may be arranged alternately on the lower surface of the substrate 110 along the second direction X. The multiple third power supply lines 131 and the multiple fourth power supply lines 132 may be arranged alternately on the upper surface of the substrate 110 along the second direction X.

[0110] In this embodiment, the first power supply wiring 121 and the fourth power supply wiring 132 may be low-potential wiring, and the second power supply wiring 122 and the fourth power supply wiring 132 may be high-potential wiring, or the opposite may be true.

[0111] In such cases, as illustrated in Figures 8A and 9, multiple second power supply lines 122 of the first layer 120 and multiple third power supply lines 131 of the second layer 130 are electrically connected via multiple first vias 118 and multiple second vias 118' on the substrate 110. For example, a third power supply line 131 of the second layer 130 is electrically connected to one side of a second power supply line 122 of the first layer 120 via a first via 118 on the substrate 110. The other side of the second power supply line 122 of the first layer 120 is electrically connected to one side of yet another third power supply line 131 of the second layer 130 via a second via 118' on the substrate 110. One side of yet another third power supply line 131 of the second layer 130 is connected to one side of yet another second power supply line 122 of the first layer 120 via a first via 118. This creates a first supply passage through which a high potential voltage is alternately supplied to the upper and lower surfaces of the substrate 110 along the second direction X.

[0112] As shown in Figures 8B and 10, multiple first power supply lines 121 of the first layer 120 and multiple fourth power supply lines 132 of the second layer 130 are electrically connected via multiple first vias 117 and multiple second vias 117' on the substrate 110. For example, one first power supply line 121 of the first layer 120 is electrically connected to one side of the fourth power supply line 132 of the second layer 130 via the first via 117 on the substrate 110. The other side of the fourth power supply line 132 of the second layer 130 is electrically connected to one side of yet another first power supply line 121 of the first layer 120 via the second via 117' on the substrate 110. One side of yet another fourth power supply line 132 of the first layer 120 is connected to one side of yet another fourth power supply line 132 of the second layer 130 via the first via 117. This creates a second supply passage through which a low potential voltage is alternately supplied to the upper and lower surfaces of the substrate 110 along the second direction X.

[0113] Of the first power supply wiring 121 of the first layer 120 and the third power supply wiring 131 of the second layer 130, which overlap perpendicularly to each other along the first direction Y, the first power supply wiring 121 is electrically connected to the adjacent fourth power supply wiring 132 of the second layer 130, and the third power supply wiring 131 is electrically connected to the adjacent second power supply wiring 122 of the first layer 120, and this is formed alternately for each row line.

[0114] Of the second power supply wiring 122 of the first layer 120 and the fourth power supply wiring 132 of the second layer 130, which overlap perpendicularly to each other along the first direction Y, the second power supply wiring 122 is electrically connected to the adjacent third power supply wiring 131 of the second layer 130, and the fourth power supply wiring 132 is electrically connected to the adjacent first power supply wiring 121 of the first layer 120, in an alternating pattern.

[0115] On the other hand, at one end of the substrate 110, the first power supply wiring 121 and the fourth power supply wiring 132 are electrically connected to a low-voltage supply unit (or low-voltage supply pad) that supplies a low potential voltage, and the second power supply wiring 122 and the third power supply wiring 131 are electrically connected to a high-potential supply unit (or high-potential supply pad) that supplies a high potential voltage. The low-potential supply unit and the high-potential supply unit are located on the upper surface of the substrate 110. In this case, the first power supply wiring 121 and the second power supply wiring 122, located on the lower surface of the substrate 110, are electrically connected to the low-potential supply unit and the high-potential supply unit, respectively, via their corresponding vias on the substrate 110.

[0116] On the other hand, the IR drop increases as the number of vias increases due to resistive losses. However, in this embodiment, of the multiple first power supply wires 121 arranged on the lower surface of the substrate 110, only the first power supply wire 121 that is electrically connected to the fourth power supply wire 132 arranged on the upper surface of the substrate 110 requires a corresponding via in order to be electrically connected to the low potential supply section on the upper surface of the substrate 110. Also, of the multiple second power supply wires 122 arranged on the lower surface of the substrate 110, only the second power supply wire 122 that is electrically connected to the third power supply wire 131 arranged on the upper surface of the substrate 110 requires a corresponding via in order to be electrically connected to the high potential supply section on the upper surface of the substrate 110. As a result, the number of vias is reduced, and the IR drop is mitigated or minimized.

[0117] In particular, even if the first power supply wiring 121 and / or the second power supply wiring 122 located on the lower surface of the substrate 110 and the third power supply wiring 131 and / or the fourth power supply wiring 132 located on the upper surface of the substrate 110 have different thicknesses, the aforementioned connecting structures between the first power supply wiring 121 and the fourth power supply wiring 132 and between the second power supply wiring 122 and the third power supply wiring 131 allow the resistance on the first supply path to be equal to the resistance on the second supply path. As a result, IR drop is used symmetrically not only in pixels but also on the upper and lower surfaces of the substrate 110, ensuring uniform image quality.

[0118] Figure 11 is a plan view of a transparent display device according to the fourth embodiment. Figure 12A shows the first layer shown in Figure 11, and Figure 12B shows the second layer shown in Figure 11.

[0119] In Figure 11, the transparent display device is illustrated as containing one pixel. The transparent display device may be composed of multiple pixels as illustrated in Figure 11.

[0120] Although a cross-sectional view of the transparent display device according to the fourth embodiment is not shown, this cross-sectional view is identical to the cross-sectional view shown in Figure 1.

[0121] Referring to Figures 1 and 11, the transparent display device according to the fourth embodiment may include a substrate 110, a first layer 120, a second layer 130, a driver IC 140, a light-emitting element chip 150, and the like.

[0122] The first layer 120 is placed on the lower surface of the substrate 110, and the second layer 130 is placed on the upper surface of the substrate 110.

[0123] As shown in Figure 12A, the first layer 120 may include a first power supply wiring 121, a second power supply wiring 122, a first connecting section 127, a second connecting section 128, and so on.

[0124] The first power wiring 121 and the second power wiring 122 are arranged along the first direction Y, and the first connecting portion 127 and the second connecting portion 128 are arranged along the second direction X. The first connecting portion 127 and the second connecting portion 128 are located between the first power wiring 121 and the second power wiring 122.

[0125] As shown in Figure 12B, the second layer 130 may include a third power supply line 131, a fourth power supply line 132, a first data signal line 133, a second data signal line 134, multiple linking lines 135-138, multiple pads 181-187, 191-194, and so on.

[0126] The third power supply wiring 131, the fourth power supply wiring 132, the first data signal wiring 133, and the second data signal wiring 134 are arranged along the first direction Y.

[0127] In this embodiment, the first power wiring 121 of the first layer 120 and the third power wiring 131 of the second layer 130 can overlap vertically. The first power wiring 121 of the first layer 120 and the third power wiring 131 of the second layer 130 can overlap vertically with the substrate 110 in between. The second power wiring 122 of the first layer 120 and the fourth power wiring 132 of the second layer 130 can overlap vertically. The third power wiring 131 of the first layer 120 and the fourth power wiring 132 of the second layer 130 can overlap vertically with the substrate 110 in between. As a result, the first power wiring 121 and the second power wiring 122 on the lower surface of the substrate 110 overlap vertically with the third power wiring 131 and the fourth power wiring 132 on the upper surface of the substrate 110, respectively, increasing the transparent area and improving transparency.

[0128] Furthermore, in the embodiment, the substrate 110 can have a dielectric constant. In such a case, a first capacitor is formed by the first power supply wiring 121, the third power supply wiring 131, and the substrate 110 between the first power supply wiring 121 and the third power supply wiring 131, and a second capacitor is formed by the second power supply wiring 122, the fourth power supply wiring 132, and the substrate between the second power supply wiring 122 and the fourth power supply wiring 132. As a result, a noise reduction effect that makes the signal less sensitive to noise is obtained by the first and second capacitors. Therefore, signal distortion due to noise does not occur, and image quality defects are prevented.

[0129] On the other hand, in the first embodiment (Figures 2 to 3B), the first power wiring 121 and the second power wiring 122 of the first layer 120 may be low-potential wiring, and the third power wiring 131 and the fourth power wiring 132 of the second layer 130 may be high-potential wiring. In the second embodiment (Figures 5 to 6B), the first power wiring 121 and the second power wiring 122 of the first layer 120 may be high-potential wiring, and the third power wiring 131 and the fourth power wiring 132 of the second layer 130 may be low-potential wiring.

[0130] On the other hand, in the fourth embodiment (Figures 11 to 12B), the first power supply wiring 121 and the fourth power supply wiring 132 may be low-potential wiring, and the second power supply wiring 122 and the third power supply wiring 131 may be high-potential wiring.

[0131] The first power supply wiring 121 located on the underside of the substrate 110 may be a low-potential wiring, and the second power supply wiring 122 located on the underside of the substrate 110 may be a high-potential wiring. The third power supply wiring 131 located on the top surface of the substrate 110 and perpendicularly overlapping the first power supply wiring 121 may be a high-potential wiring. The fourth power supply wiring 132 located on the top surface of the substrate 110 and perpendicularly overlapping the second power supply wiring 122 may be a low-potential wiring.

[0132] In this case, the first power supply wiring 121 is electrically connected to the fourth power supply wiring 132, and the second power supply wiring 122 is electrically connected to the third power supply wiring 131.

[0133] For this purpose, the first layer 120 may include a first connecting section 127, a second connecting section 128, and so on. The first connecting section 127 and the second connecting section 128 are positioned between the first power wiring 121 and the second power wiring 122. The first connecting section 127 and the second connecting section 128 are positioned parallel to each other along the second direction X.

[0134] The first connection portion 127 may extend from the first power supply wiring 121 across the first data signal wiring 133 along a second positive (+) direction X and be positioned away from the second power supply wiring 122. The second connection portion 128 may extend from the second power supply wiring 122 across the second data signal wiring 134 along a second negative (-) direction X and be positioned away from the first power supply wiring 121.

[0135] The first connection portion 127 is positioned across the first data signal trace 133 of the second layer 130. The first connection portion 127 can electrically connect the first power trace 121 and the fourth power trace 132 via the first via 117 on the substrate 110. The first via 117 can be located on one area of ​​the first connection portion 127. The second connection portion 128 is positioned across the second data signal trace 134 of the second layer 130. The second connection portion 128 can electrically connect the second power trace 122 and the third power trace 131 via the second via 118 on the substrate 110. The second via 118 can be located on one area of ​​the second connection portion 128.

[0136] Due to the arrangement structure of the first connecting section 127 and the second connecting section 128 described above, and the arrangement positions of the first via 117 and the second via 118, electrical short circuits between the first power supply wiring 121 and the fourth power supply wiring 132 and the first data signal wiring 133 are prevented, and electrical short circuits between the second power supply wiring 122 and the third power supply wiring 131 and the second data signal wiring 134 are prevented.

[0137] With the aforementioned arrangement, a low potential voltage is supplied to the left of the driver IC 140 and light-emitting element via the first power supply wiring 121 on the underside of the substrate 110, and to the right of them via the fourth power supply wiring 132 on the topside of the substrate 110. Furthermore, a high potential voltage is supplied to the left of the driver IC 140 and light-emitting element via the third power supply wiring 131 on the topside of the substrate 110, and to the right of them via the second power supply wiring 122 on the underside of the substrate 110.

[0138] The first connection section 127 ensures that the low potential voltage supplied to the first power supply wiring 121 and the low potential voltage supplied to the fourth power supply wiring 132 are the same, so the first connection section 127 may be a first equipotential power supply wiring. The second connection section 128 ensures that the high potential voltage supplied to the second power supply wiring 122 and the high potential voltage supplied to the third power supply wiring 131 are the same, so the second connection section 128 may be a second equipotential power supply wiring.

[0139] Meanwhile, the third power supply wiring 131 is electrically connected to the drive IC 140, and the fourth power supply wiring 132 is electrically connected to both the drive IC 140 and the light-emitting element chip 150.

[0140] Figure 13 is a cross-sectional view of a transparent display device according to the second embodiment.

[0141] The second embodiment is identical to the first embodiment (Figure 1), except for the heat diffusion layers 161 and 162. In the second embodiment, components having the same shape, structure, and / or function as those in the first embodiment (Figure 1) are given the same reference numerals, and detailed descriptions are omitted. The descriptions omitted below in relation to the second embodiment can be easily understood from the description of the first embodiment (Figure 1).

[0142] As shown in Figure 13, the heat diffusion layers 161 and 162 are positioned on the underside of the substrate 110. The heat diffusion layers 161 and 162 can rapidly dissipate the heat generated by the drive IC 140 and / or the light-emitting element chip 150 to the outside. The heat diffusion layers 161 and 162 can be made of a material with excellent heat dissipation properties. For example, the heat diffusion layers 161 and 162 can be made of a metal such as aluminum with excellent heat dissipation properties. The heat diffusion layers 161 and 162 may also be heat dissipation plates.

[0143] The thermal diffusion layer may include a first thermal diffusion layer 161 on the underside of the substrate 110 corresponding to the drive IC 140 and a second thermal diffusion layer 162 on the underside of the substrate 110 corresponding to the light-emitting element chip 150. The first thermal diffusion layer 161 can quickly dissipate heat generated by the drive IC 140 to the outside, and the second thermal diffusion layer 162 can quickly dissipate heat generated by the light-emitting element chip 150 to the outside.

[0144] Although not shown in the drawings, the thermal diffusion layers 161 and 162 may not be separated into a first thermal diffusion layer 161 and a second thermal diffusion layer 162, but may be extended and arranged from a first region on the lower surface of the substrate 110 corresponding to the drive IC 140 to a second region on the lower surface of the substrate 110 corresponding to the light-emitting element chip 150. In other words, the thermal diffusion layers 161 and 162 may be arranged not only in the first and second regions but also in a third region between the first and second regions.

[0145] Instead of the heat diffusion layers 161 and 162, a light-blocking layer, a light-reflecting layer, a light-absorbing layer, etc., may be placed.

[0146] Figure 14A is a cross-sectional view illustrating an example of a transparent display device according to the third embodiment. Figure 14B is a cross-sectional view illustrating another example of a transparent display device according to the third embodiment.

[0147] Figure 14A is a cross-sectional view centered on the driver IC 140 and light-emitting element provided in one pixel, while Figure 14B is a cross-sectional view centered on the region of one pixel where the driver IC 140 and light-emitting element are not located.

[0148] The third embodiment is similar to the first embodiment (Figure 1), except for the first substrate 171 and the second substrate 172. In the third embodiment, components having the same shape, structure, and / or function as those in the first embodiment (Figure 1) are given the same reference numerals, and detailed descriptions are omitted. The descriptions omitted below in relation to the third embodiment can be easily understood from the description of the first embodiment (Figure 1).

[0149] Referring to Figures 14A and 14B, the transparent display device according to the third embodiment may include a first substrate 171, a second substrate 172, a first layer 120, a second layer 130, a driver IC 140, a light-emitting element chip 150, and the like.

[0150] The lower surface of the first substrate 171 and the upper surface of the second substrate 172 are arranged to face each other. In this case, the first layer 120 is placed on the lower surface of the first substrate 171, and the second layer 130 is placed on the upper surface of the second substrate 172.

[0151] The first layer 120 may include a first power supply wiring 121, a second power supply wiring 122, etc., and the second layer 130 may include a third power supply wiring 131, a fourth power supply wiring 132, etc.

[0152] The driver IC 140 and the light-emitting chip 150 are arranged on the upper surface of the second substrate 172. The driver IC 140 and the light-emitting chip 150 are arranged between the first substrate 171 and the second substrate 172. The upper side of the driver IC 140 and the upper side of the light-emitting chip 150 can be separated from the lower surface of the first substrate 171, but this is not limited.

[0153] Although not shown in the diagram, a molding section is placed between the first substrate 171 and the second substrate 172. The first substrate 171 and the second substrate 172 are bonded together via the molding section, and the drive IC 140 and the light-emitting element chip 150 are fixed in place.

[0154] On the other hand, a conductive spacer 175 is placed between the first substrate 171 and the second substrate 172. The conductive spacer 175 can be used instead of the first via 111, the second via 112 and via 113 shown in Figure 2, the first via 114, the second via 115 and via 116 shown in Figure 5, and the first via 117 and second via 118 shown in Figure 11.

[0155] For example, as shown in Figure 14B, the first power supply wiring 121 and the fourth power supply wiring 132 are electrically connected via a conductive spacer 175. The conductive spacer 175 can be made of metal or a composite material such as a resin containing metal. A conductive ball containing metal, solder, etc., may be used instead of the conductive spacer 175. As shown in Figure 11, the first power supply wiring 121 and the fourth power supply wiring 132, to which a low potential voltage is supplied, are electrically connected via a conductive spacer 175.

[0156] Although not shown in the diagram, the second power supply wiring 122 and the third power supply wiring 131, to which a high potential voltage is supplied, are further electrically connected via another conductive spacer 175.

[0157] The detailed description above should not be interpreted restrictively in any way, but should be considered illustrative. The scope of the examples should be determined by a reasonable analysis of the attached claims, and all modifications within the equivalent scope of the examples are included within the scope of the examples.

Claims

1. A first layer including a first power supply wiring and a second power supply wiring along a first direction, A second layer is arranged on the first layer and includes a third power supply wiring, a fourth power supply wiring, a first data signal wiring, a second data signal wiring, and a plurality of connecting wirings along the first direction, A drive IC is placed between the third power supply wiring and the fourth power supply wiring, Includes an end-point device disposed between the third power supply wiring and the fourth power supply wiring, The drive IC is electrically connected to the first power supply wiring, the second power supply wiring, the third power supply wiring, the fourth power supply wiring, the first data signal wiring, the second data signal wiring, and the plurality of connecting wirings. The light-emitting element is electrically connected to one of the second power supply wiring and the fourth power supply wiring and to the plurality of connecting wirings. The first power supply wiring and the third power supply wiring overlap vertically. The second power supply wiring and the fourth power supply wiring are arranged vertically on a transparent display device.

2. The transparent display apparatus according to claim 1, further comprising a substrate having a lower surface on which the first layer is arranged and an upper surface on which the second layer is arranged.

3. The first power supply wiring and the second power supply wiring are low-potential wiring. The transparent display device according to claim 2, wherein the third power supply wiring and the fourth power supply wiring are high-potential wiring.

4. The first layer is, A connecting portion that electrically connects the first power supply wiring and the second power supply wiring across the second data signal wiring along the second direction, The transparent display device according to claim 3, further comprising: a connection pattern that electrically connects the third power supply wiring and the fourth power supply wiring via first vias and second vias on the substrate, crossing the first data signal wiring along the second direction.

5. The second power supply wiring is electrically connected to the drive IC and the light-emitting element via vias on the substrate. The transparent display device according to claim 3, wherein the third power supply wiring is electrically connected to the drive IC.

6. The first power supply wiring and the second power supply wiring are high-potential wiring. The transparent display device according to claim 2, wherein the third power supply wiring and the fourth power supply wiring are low-potential wiring.

7. The first layer is, A connecting portion that electrically connects the first power supply wiring and the second power supply wiring across the first data signal wiring along the second direction, The transparent display device according to claim 6, further comprising a connection pattern that electrically connects the third power supply wiring and the fourth power supply wiring via first vias and second vias on the substrate, crossing the second data signal wiring along the second direction.

8. The aforementioned connecting portion is electrically connected to the drive IC via vias on the substrate. The transparent display device according to claim 7, wherein the fourth power supply wiring is electrically connected to the drive IC and the light-emitting element.

9. The first power supply wiring and the fourth power supply wiring are low-potential wiring. The transparent display device according to claim 2, wherein the second power supply wiring and the third power supply wiring are high-potential wiring.

10. The first layer is, A first connecting portion that electrically connects the first power supply wiring and the fourth power supply wiring via a first via on the substrate, crossing the first data signal wiring along the second direction, The transparent display device according to claim 9, further comprising: a second connecting portion that electrically connects the second power supply wiring and the third power supply wiring via a second via on the substrate, crossing the second data signal wiring along the second direction.

11. The third power supply wiring is electrically connected to the drive IC, The transparent display device according to claim 9, wherein the fourth power supply wiring is electrically connected to the drive IC and the light-emitting element.

12. A first substrate having a lower surface on which the first layer is arranged, The present invention further includes a second substrate having an upper surface on which the second layer is arranged, The transparent display device according to claim 1, wherein the drive IC and the light-emitting element are arranged between the first substrate and the second substrate.

13. The transparent display apparatus according to claim 12, further comprising a conductive spacer between the first substrate and the second substrate.

14. The transparent display apparatus according to claim 1, comprising a plurality of light-emitting elements stacked perpendicularly to each other and electrically connected to the plurality of connecting wires.

15. The transparent display device according to claim 1, wherein the light-emitting elements include a plurality of light-emitting elements arranged horizontally to each other along a second direction and connected to the plurality of connecting wires.

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