Semiconductor devices and power devices

Abstract

To provide a semiconductor device that can reduce on-resistance.SOLUTION: A semiconductor device has: a first semiconductor part and a second semiconductor part that are of the same conductivity type as each other and arranged along a first direction; a third semiconductor part that is provided between the first semiconductor part and the second semiconductor part, and has a lower impurity concentration than the first semiconductor part and the second semiconductor part; a fourth semiconductor part that is provided between the second semiconductor part and the third semiconductor part, and has a lower impurity concentration than the first semiconductor part and the second semiconductor part; a gate insulating layer and a gate electrode that are provided side by side with the third semiconductor part in a second direction intersecting the first direction; and a dielectric part that is provided side by side with the fourth semiconductor part in the second direction. The dielectric part is formed of a material having a larger band gap and a larger dielectric constant than a material forming the fourth semiconductor part. When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the fourth semiconductor part.SELECTED DRAWING: Figure 1

Description

Technical Field

[0005] , , ,

[0001] The present invention relates to a semiconductor device and a power device.

Background Art

[0002] Semiconductor nanocolumns are attracting attention for application to various semiconductor devices such as transistors and light sources as a configuration of next-generation nanodevices. For example, by adopting a GAA (Gate All Around) structure in which a semiconductor nanocolumn is surrounded entirely in the circumferential direction by a gate electrode, the channel formation region of the semiconductor nanocolumn can be surrounded by the gate electrode, completely depleted, and the current controllability can be enhanced. According to the GAA structure, it is possible to achieve both steep on-off switching characteristics with respect to time and high density per unit area. For example, Patent Document 1 describes a transistor device including a nanowire, a gate dielectric surrounding the nanowire, and a gate conductor surrounding the gate dielectric.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the transistor device as described above, it is desired to reduce the on-resistance.

Means for Solving the Problems

[0005] One aspect of the semiconductor device according to the present invention is a first semiconductor part and a second semiconductor part that have the same conductivity type as each other and are arranged along a first direction, A third semiconductor portion is provided between the first semiconductor portion and the second semiconductor portion, and has a lower impurity concentration than the first and second semiconductor portions. A fourth semiconductor portion is provided between the second semiconductor portion and the third semiconductor portion, and has a lower impurity concentration than the first semiconductor portion and the second semiconductor portion. A gate insulating layer and a gate electrode are provided in a second direction intersecting the first direction of the third semiconductor portion, The dielectric portion provided in the second direction of the fourth semiconductor portion, It has, The dielectric portion is made of a material with a larger band gap and a higher relative permittivity than the material constituting the fourth semiconductor portion. When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the fourth semiconductor portion.

[0006] One aspect of the power device according to the present invention is: A first semiconductor portion and a second semiconductor portion having the same conductivity type and arranged along a first direction, A third semiconductor portion is provided between the first semiconductor portion and the second semiconductor portion, and has a lower impurity concentration than the first and second semiconductor portions. A fourth semiconductor portion is provided between the second semiconductor portion and the third semiconductor portion, and has a lower impurity concentration than the first semiconductor portion and the second semiconductor portion. A gate insulating layer and a gate electrode are provided in a second direction intersecting the first direction of the third semiconductor portion, The dielectric portion provided in the second direction of the fourth semiconductor portion, It has, The dielectric portion is made of a material with a larger band gap and a higher relative permittivity than the material constituting the fourth semiconductor portion. When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the fourth semiconductor portion. [Brief explanation of the drawing]

[0007] [Figure 1]A schematic cross-sectional view showing the semiconductor device according to this embodiment. [Figure 2] A schematic plan view showing the semiconductor device according to this embodiment. [Figure 3] A schematic cross-sectional view showing the manufacturing process of a semiconductor device according to this embodiment. [Figure 4] A schematic cross-sectional view showing the manufacturing process of a semiconductor device according to this embodiment. [Figure 5] A schematic cross-sectional view showing the manufacturing process of a semiconductor device according to this embodiment. [Figure 6] A schematic cross-sectional view showing a semiconductor device according to a modified example of this embodiment. [Modes for carrying out the invention]

[0008] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. The embodiments described below are not intended to unduly limit the scope of the present invention as described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0009] 1. Semiconductor device First, the semiconductor device according to this embodiment will be described with reference to the drawings. Figure 1 is a schematic cross-sectional view of the semiconductor device 100 according to this embodiment. Figure 2 is a schematic plan view of the semiconductor device 100 according to this embodiment. Note that Figure 1 is a cross-sectional view taken along line II of Figure 2. Also, in Figures 1 and 2, the X-axis, Y-axis, and Z-axis are shown as three mutually orthogonal axes.

[0010] As shown in Figures 1 and 2, the semiconductor device 100 includes a substrate 10, a buffer layer 20, a mask layer 22, a columnar portion 30, an insulating layer 40, a gate insulating layer 50, a gate electrode 60, a dielectric layer 70, and a drain electrode 80. The semiconductor device 100 is, for example, a power device. The semiconductor device 100 is, for example, a vertical metal-oxide-semiconductor field-effect transistor (MOSFET). For convenience, the drain electrode 80 is omitted from the illustration in Figure 2.

[0011] The substrate 10 is, for example, a Si substrate, a GaN substrate, a sapphire substrate, a SiC substrate, or the like.

[0012] As shown in FIG. 1, the buffer layer 20 is provided on the substrate 10. The buffer layer 20 is, for example, an n-type GaN layer or an AlGaN layer doped with Si. The buffer layer 20 functions as a source, for example. The buffer layer 20 is electrically connected to a source pad (not shown), for example. The source pad is electrically connected to the source region 32 of the columnar portion 30 through the buffer layer 20.

[0013] In this specification, in the stacking direction of the channel formation region 34 and the drain region 38 of the columnar portion 30, when the channel formation region 34 is used as a reference, the direction from the channel formation region 34 toward the drain region 38 is referred to as "up", and the direction from the channel formation region 34 toward the source region 32 is referred to as "down" for explanation. In the illustrated example, the stacking direction of the channel formation region 34 and the drain region 38 is the Z-axis direction.

[0014] The mask layer 22 is provided on the buffer layer 20. The mask layer 22 is provided between the buffer layer 20 and the insulating layer 40. The mask layer 22 is, for example, a titanium layer, a silicon oxide layer, a titanium oxide layer, an aluminum oxide layer, or the like. A plurality of openings 24 are provided in the mask layer 22. In the illustrated example, the openings 24 penetrate the mask layer 22 in the Z-axis direction. The columnar portion 30 is located in the openings 24. The mask layer 22 functions as a mask for growing the columnar portion 30.

[0015] The columnar portion 30 is provided on the buffer layer 20. The columnar portion 30 is provided on the substrate 10 via the buffer layer 20. The columnar portion 30 has a columnar shape protruding upward from the buffer layer 20. In other words, the columnar portion 30 protrudes upward from the substrate 10 via the buffer layer 20. The columnar portion 30 is provided between the buffer layer 20 and the drain electrode 80. The columnar portion 30 is also called, for example, a nanocolumn, a nanowire, a nanorod, or a nanopillar. The planar shape of the columnar portion 30 is, for example, a polygon such as a hexagon or a circle. In the example shown in FIG. 2, the planar shape of the columnar portion 30 is a regular hexagon.

[0016] The diameter of the columnar portion 30 is, for example, 50 nm or more and 500 nm or less, preferably 100 nm or more and 300 nm or less. By setting the diameter of the columnar portion 30 to 500 nm or less, a high-quality crystalline columnar portion 30 can be obtained.

[0017] Note that the "diameter of the columnar portion 30" is the diameter when the planar shape of the columnar portion 30 is a circle, and is the diameter of the minimum enclosing circle when the planar shape of the columnar portion 30 is not a circle. For example, when the planar shape of the columnar portion 30 is a polygon, the diameter of the columnar portion 30 is the diameter of the smallest circle that includes the polygon inside, and when the planar shape of the columnar portion 30 is an ellipse, the diameter of the columnar portion 30 is the diameter of the smallest circle that includes the ellipse inside.

[0018] For example, a plurality of columnar portions 30 are provided. By providing a plurality of columnar portions 30, the semiconductor device 100 can achieve a large current, and is preferably used as a power device. The plurality of columnar portions 30 are spaced apart from each other. The interval between adjacent columnar portions 30 is, for example, 10 nm or more and 1 μm or less, preferably 0.5 times or more and 1.5 times or less the diameter of the columnar portion 30, that is, 25 nm or more and 750 nm or less, and more preferably 400 nm or more and 600 nm or less. The plurality of columnar portions 30 are arranged, for example, at a predetermined pitch in a predetermined direction when viewed from the Z-axis direction. The plurality of columnar portions 30 are arranged, for example, in a triangular lattice or a square lattice. In the illustrated example, the plurality of columnar portions 30 are arranged, for example, in a regular triangular lattice.

[0019] The "pitch of the columnar parts 30" refers to the distance between the centers of adjacent columnar parts 30 in a predetermined direction. The "center of the columnar part 30" refers to the center of the circle if the planar shape of the columnar part 30 is a circle, and to the center of the smallest inclusion circle if the planar shape of the columnar part 30 is not a circle. For example, if the planar shape of the columnar part 30 is a polygon, the center of the smallest circle that contains the polygon is the center of the polygon, and if the planar shape of the columnar part 30 is an ellipse, the center of the smallest circle that contains the ellipse is the center of the ellipse.

[0020] As shown in Figure 1, the columnar portion 30 has a source region 32, a channel forming region 34, a drift region 37, and a drain region 38.

[0021] The source region 32 is provided on the buffer layer 20. The source region 32 is provided between the buffer layer 20 and the channel formation region 34. The source region 32 is composed of a semiconductor layer. The material of the source region 32 is, for example, Si-doped n-type GaN or AlGaN. The impurity concentration of the source region 32 may be the same as the impurity concentration of the buffer layer 20.

[0022] The channel formation region 34 is located on the source region 32. The channel formation region 34 is located between the source region 32 and the drift region 37. The channel formation region 34 is composed of a semiconductor layer. The impurity concentration in the channel formation region 34 is lower than that of the source region 32 and the drain region 38. The impurity concentrations of the source region 32, the channel formation region 34, the drift region 37, and the drain region 38 are measured, for example, by atom probe analysis.

[0023] The material of the channel formation region 34 is, for example, UID (unintentionally doped) type GaN or AlGaN, which is not intentionally doped with impurities. Because the diameter of the columnar portion 30 is small, even if the conductivity type of the channel formation region 34 is UID type, the channel formation region 34 can be completely depleted. A channel is formed in the channel formation region 34 when a predetermined voltage is applied to the gate electrode 60. For example, an N channel is formed in the channel formation region 34.

[0024] The drift region 37 is located on the channel formation region 34. The drift region 37 is located between the channel formation region 34 and the drain region 38. The drift region 37 is composed of a semiconductor layer. The conductivity type of the drift region 37 is, for example, the same as that of the source region 32. The material of the drift region 37 is, for example, Si-doped n-type GaN or AlGaN.

[0025] The impurity concentration in the drift region 37 is lower than that in the source region 32 and the drain region 38. Alternatively, the impurity concentration in the drift region 37 may be the same as that in the channel formation region 34. Or, the impurity concentration in the drift region 37 may be higher than that in the channel formation region 34. That is, the impurity concentration in the drift region 37 may be between that of the channel formation region 34 and the drain region 38. By providing the drift region 37, the breakdown voltage of the semiconductor device 100 in the off state can be improved.

[0026] The drain region 38 is located on the drift region 37. The drain region 38 is located between the drift region 37 and the drain electrode 80. The drain region 38 is composed of a semiconductor layer. The conductivity type of the drain region 38 is the same as that of the source region 32. The material of the drain region 38 is, for example, Si-doped n-type GaN or AlGaN.

[0027] The impurity concentration in the drain region 38 is higher than that in the drift region 37. The impurity concentration in the drain region 38 may be the same as that in the source region 32. The source region 32, the channel-forming region 34, the drift region 37, and the drain region 38 are arranged along a first direction. In the illustrated example, the first direction is the +Z axis direction. The source region 32, the channel-forming region 34, the drift region 37, and the drain region 38 are stacked, for example, in the +Z axis direction to form a columnar portion 30.

[0028] The insulating layer 40 is provided on the mask layer 22. The insulating layer 40 is provided between the substrate 10 and the gate electrode 60. The insulating layer 40 is provided between the source regions 32 of adjacent columnar portions 30. When viewed from the Z-axis direction, the insulating layer 40 surrounds the source region 32. The insulating layer 40 is, for example, an SOG (spin on glass) layer.

[0029] The gate insulating layer 50 is provided on the side surface of the channel forming region 34 of the columnar portion 30. The side surface of the channel forming region 34 is, for example, an m-plane. The gate insulating layer 50 is provided in a second direction that intersects with the first direction of the channel forming region 34. In the illustrated example, the second direction is the +Y axis direction and is perpendicular to the first direction, which is the +Z axis direction. The gate insulating layer 50 surrounds the channel forming region 34 when viewed from the Z axis direction. The gate insulating layer 50 is provided between the channel forming region 34 and the gate electrode 60.

[0030] The gate insulating layer 50 is made of a material with a larger band gap than, for example, the material constituting the channel formation region 34. Furthermore, the gate insulating layer 50 is made of a material with a larger relative permittivity than, for example, the material constituting the channel formation region 34. The material of the gate insulating layer 50 is a transition metal oxide such as hafnium oxide (HfO2), tantalum oxide (Ta2O5), yttrium oxide (Y2O3), zirconium oxide (ZrO2), or lanthanum oxide (La2O3), and is preferably hafnium oxide. The material of the gate insulating layer 50 may also be silicon oxide (SiO2).

[0031] The gate electrode 60 is provided on the gate insulating layer 50. The gate electrode 60 is provided in the +Y axis direction of the channel forming region 34. In the illustrated example, the gate electrode 60 surrounds the gate insulating layer 50 when viewed from the Z axis direction. The gate electrode 60 is provided on the insulating layer 40, for example, via an insulating layer 52. The material of the insulating layer 52 is the same as that of the gate insulating layer 50. The gate electrode 60 is provided between the insulating layer 40 and the dielectric layer 70. The gate electrode 60 is provided between the channel forming regions 34 of adjacent columnar portions 30.

[0032] The material of the gate electrode 60 is, for example, polysilicon doped with impurities such as phosphorus or boron, or a metal. The semiconductor device 100 has a GAA structure. The gate electrode 60 is electrically connected to a gate pad (not shown).

[0033] The dielectric layer 70 is provided on the gate insulating layer 50 and the gate electrode 60. The dielectric layer 70 is provided between the gate insulating layer 50 and the gate electrode 60 and the drain electrode 80. The dielectric layer 70 is provided in the +Y axis direction of the drift region 37. In the illustrated example, the dielectric layer 70 surrounds the drift region 37. The dielectric layer 70 is provided between the drift regions 37 of adjacent columnar portions 30.

[0034] The dielectric layer 70 is made of a material with a larger band gap than the material constituting the drift region 37. Furthermore, the dielectric layer 70 is made of a material with a larger relative permittivity than the material constituting the drift region 37. The material of the dielectric layer 70 is, for example, a transition metal oxide such as hafnium oxide, tantalum oxide, yttrium oxide, zirconium oxide, or lanthanum oxide, and is preferably hafnium oxide.

[0035] Because the dielectric layer 70 is made of a material with a larger band gap and higher relative permittivity than the material constituting the drift region 37, when a predetermined voltage is applied to the gate electrode 60, the Dielectric RESURF (Reduced Surface Field) effect is exhibited, and a depletion layer is formed in the drift region 37 by the electric field generated in the dielectric layer 70. The semiconductor device 100 can have a pseudo-superjunction structure due to the Dielectric RESURF effect. The predetermined voltage is the voltage required to turn off the semiconductor device 100.

[0036] The depletion layer formed by the electric field generated in the dielectric layer 70 spreads from the side of the drift region 37 of the columnar portion 30 toward the center of the columnar portion 30, as shown by arrow A1 in Figure 1. Furthermore, as shown by arrow A2, there is also a depletion layer that spreads from the channel formation region 34 toward the drift region 37. In this way, the semiconductor device 100 can spread the depletion layer from both the vertical and horizontal directions, thus exhibiting the Dielectric RESURF effect.

[0037] The drain electrode 80 is provided on the drain region 38 and on the dielectric layer 70. The drain electrode 80 is provided in the +Z axis direction of the drain region 38. The drain region 38 may be in ohmic contact with the drain electrode 80.

[0038] The material of the drain electrode 80 is, for example, polysilicon doped with impurities such as phosphorus or boron, or a metal. The drain electrode 80 is electrically connected to a drain pad (not shown). The drain pad is electrically connected to the drain region 38 via the drain electrode 80.

[0039] The semiconductor device 100 can be used, for example, as a power device and is applied to inverters, chargers, boosters, step-down converters, DC (Direct Current) / DC converters, electric airplanes, electric vehicles, etc. However, the semiconductor device 100 may also be used as a logic device, high-frequency device, etc., instead of a power device.

[0040] The semiconductor device 100 has, for example, the following effects.

[0041] The semiconductor device 100 includes a source region 32 as a first semiconductor part and a drain region 38 as a second semiconductor part, both having the same conductivity type and arranged along the +Z axis; a channel formation region 34 as a third semiconductor part provided between the source region 32 and the drain region 38, having a lower impurity concentration than the source region 32 and the drain region 38; a drift region 37 as a fourth semiconductor layer provided between the channel formation region 34 and the drain region 38, having a lower impurity concentration than the source region 32 and the drain region 38; a gate insulating layer 50 and a gate electrode 60 provided in the +Y axis direction of the channel formation region 34; and a dielectric layer 70 as a dielectric part provided in the +Y axis direction of the drift region 37. The dielectric layer 70 is made of a material with a larger band gap and a higher relative permittivity than the material constituting the drift region 37, and when a predetermined voltage is applied to the gate electrode 60, a depletion layer is formed in the drift region 37 by the electric field generated in the dielectric layer 70.

[0042] Therefore, in the semiconductor device 100, for example, compared to the case where the dielectric constant of the dielectric layer is below the dielectric constant of the drift region, the Dielectric RESURF effect, in which the depletion layer spreads from the side surface of the drift region 37 of the columnar portion 30 toward the center of the columnar portion 30, can be greatly increased, as shown by arrow A1 above. This makes it possible to improve the breakdown voltage. As a result, the impurity concentration in the drift region 37 can be increased, and the on-resistance can be lowered.

[0043] Furthermore, in the semiconductor device 100, for example, the insulating properties of the dielectric layer 70 can be improved compared to the case where the band gap of the dielectric layer is below the band gap of the drift region. This makes it possible to reduce leakage current.

[0044] Furthermore, in the semiconductor device 100, the impurity concentration in the channel formation region 34 is lower than that in the source region 32 and the drain region 38, which allows for increased carrier mobility in the channel formation region 34. For example, when an N channel is formed in the channel formation region 34, the electron mobility in the channel formation region 34 can be increased. This allows for lower on-resistance.

[0045] Furthermore, the semiconductor device 100 can be manufactured more easily compared to the case where a p-type semiconductor layer with a different conductivity type from the source region 32 and drain region 38 is provided instead of the dielectric layer 70. For example, if a superjunction structure is to be formed by providing a p-type semiconductor layer instead of the dielectric layer 70, it becomes necessary to control the impurity concentration of the p-type semiconductor layer with high precision, which complicates the manufacturing process.

[0046] Furthermore, in the semiconductor device 100, in the off state, the potential difference between the gate electrode 60 and the drain region 38 is greater than the potential difference between the gate electrode 60 and the source region 32. Therefore, the dielectric resurface effect can be increased compared to the case where a dielectric layer is provided in the +Y axis direction of the source region.

[0047] In the semiconductor device 100, the source region 32, the channel formation region 34, and the drift region 37 are stacked in the +Z axis direction to form a columnar portion 30. Therefore, in the semiconductor device 100, compared to a case where the source region, channel formation region, and drift region do not form a columnar portion, the possibility of crystal defects caused by the difference in lattice constants between the substrate 10 and the buffer layer 20 reaching the channel formation region 34 and the drift region 37 is reduced because the crystal defects bend at the side surface of the columnar portion 30 in the source region 32. As a result, the channel formation region 34 and the drift region 37 can have high-quality crystallinity. In the illustrated example, the drain region 38 also forms a columnar portion 30, so the drain region 38 can also have high-quality crystallinity.

[0048] In the semiconductor device 100, when viewed from the Z-axis direction, the gate insulating layer 50 surrounds the channel formation region 34, and the gate electrode 60 surrounds the gate insulating layer 50. Therefore, in the semiconductor device 100, the channel formation region 34 can be completely depleted.

[0049] In semiconductor device 100, the dielectric layer 70 is made of a transition metal oxide. Therefore, in semiconductor device 100, it is easier to realize a dielectric layer 70 with a larger band gap and a higher relative permittivity than the drift region 37.

[0050] In the semiconductor device 100, the dielectric layer 70 is made of hafnium oxide. Therefore, in the semiconductor device 100, the dielectric layer 70 can be formed by the ALD (Atomic Layer Deposition) method. This allows the dielectric layer 70 to be formed without the generation of voids, even between adjacent columnar portions 30.

[0051] In the semiconductor device 100, the gate insulating layer 50 is made of a material with a larger band gap and higher relative permittivity than the material constituting the channel formation region 34. Therefore, in the semiconductor device 100, the controllability of the threshold voltage can be improved compared to, for example, a case where the permittivity of the gate insulating layer is less than or equal to the permittivity of the channel formation region. Furthermore, the insulating properties of the gate insulating layer 50 can be improved compared to, for example, a case where the band gap of the gate insulating layer is less than or equal to the band gap of the channel formation region.

[0052] In the semiconductor device 100, the material of the gate insulating layer 50 is a transition metal oxide. Therefore, in the semiconductor device 100, it is easier to realize a gate insulating layer 50 with a larger band gap and a higher dielectric constant than the channel formation region 34.

[0053] In the semiconductor device 100, the material of the gate insulating layer 50 is hafnium oxide. Therefore, in the semiconductor device 100, the gate insulating layer 50 can be formed by the ALD method. This makes it possible to form the gate insulating layer 50 without generating voids, for example, between adjacent columnar portions 30.

[0054] 2. Method for manufacturing semiconductor devices Next, the manufacturing method of the semiconductor device 100 according to this embodiment will be described with reference to the drawings. Figures 3 to 5 are schematic cross-sectional views showing the manufacturing process of the semiconductor device 100 according to this embodiment.

[0055] As shown in Figure 3, a buffer layer 20 is epitaxially grown on the substrate 10. Examples of epitaxial growth methods include MOCVD (Metal Organic Chemical Vapor Deposition) and MBE (Molecular Beam Epitaxy). The buffer layer 20 is grown while doping with impurities.

[0056] Next, a mask layer 22 is formed on the buffer layer 20. The mask layer 22 is formed, for example, by electron beam evaporation or sputtering.

[0057] Next, the mask layer 22 is patterned to form a plurality of openings 24. Patterning is performed, for example, by electron beam lithography and dry etching.

[0058] As shown in Figure 4, the source region 32, channel formation region 34, drift region 37, and drain region 38 are epitaxially grown on the buffer layer 20 in this order, using the mask layer 22 as a mask. Examples of epitaxial growth methods include MOCVD and MBE. The growth of the source region 32 and the drain region 38 is carried out while doping with impurities. Multiple columnar portions 30 can be formed by this process.

[0059] Next, an insulating layer 40 is formed on the mask layer 22 between the source regions 32 of adjacent columnar portions 30. The insulating layer 40 is formed by, for example, the ALD method, the CVD (Chemical Vapor Deposition) method, or the SOG (spin on glass) method.

[0060] As shown in Figure 5, an insulating layer 50a is formed on the insulating layer 40 so as to cover the columnar portion 30. The insulating layer 50a is formed by, for example, the ALD method or the CVD method. In the illustrated example, the insulating layer 50a is formed on the side and top surfaces of the columnar portion 30.

[0061] Next, a gate electrode 60 is formed on the insulating layer 50a. The gate electrode 60 is formed, for example, by CVD, sputtering, or vacuum deposition.

[0062] As shown in Figure 1, a portion of the insulating layer 50a is etched and removed. This forms a gate insulating layer 50 between the channel formation region 34 and the gate electrode 60. This etching exposes the drain region 38.

[0063] Next, a dielectric layer 70 is formed on the gate insulating layer 50 and the gate electrode 60. The dielectric layer 70 is formed by, for example, the ALD method or the CVD method.

[0064] Next, a drain electrode 80 is formed on the drain region 38 and the dielectric layer 70. The drain electrode 80 is formed, for example, by CVD, sputtering, or vacuum deposition.

[0065] By following the above steps, the semiconductor device 100 can be manufactured.

[0066] 3. Modified examples of semiconductor devices Next, a semiconductor device according to a modified example of this embodiment will be described with reference to the drawings. Figure 6 is a schematic cross-sectional view showing a semiconductor device 200 according to a modified example of this embodiment. Hereinafter, in the semiconductor device 200 according to a modified example of this embodiment, components having the same function as the components of the semiconductor device 100 according to the above embodiment will be denoted by the same reference numerals, and their detailed descriptions will be omitted.

[0067] In the semiconductor device 100 described above, as shown in Figure 1, the drain region 38 constituted a columnar portion 30.

[0068] In contrast, in the semiconductor device 200, as shown in Figure 6, the drain region 38 does not constitute a columnar portion 30. The columnar portion 30 is composed of a source region 32, a channel formation region 34, and a drift region 37.

[0069] The drain region 38 is further provided in the +Z axis direction of the dielectric layer 70. The drain region 38 is provided on the drift region 37 and on the dielectric layer 70. The drain region 38 is provided between the drift region 37 and the dielectric layer 70 and the drain electrode 80. The drain region 38 is provided across a plurality of columnar portions 30. Viewed from the stacking direction, the drain region 38 overlaps with the plurality of columnar portions 30. Viewed from the stacking direction, the drain electrode 80 overlaps with the plurality of columnar portions 30.

[0070] The semiconductor device 200 has a drain electrode 80 provided in the +Z axis direction of the drift region 37, and the drain region 38 is further provided in the +Z axis direction of the dielectric layer 70. Therefore, in the semiconductor device 200, the contact area between the drain region 38 and the drain electrode 80 can be increased compared to a case where the drain region is not provided in the +Z axis direction of the dielectric layer. This makes it possible to lower the contact resistance between the drain region 38 and the drain electrode 80. Generally, the contact resistance between a semiconductor layer and a metal electrode is high, so it is important to increase the contact area.

[0071] The embodiments and variations described above are examples only and are not limiting. For example, each embodiment and each variation can be combined as appropriate.

[0072] The present invention includes configurations substantially identical to those described in the embodiments, for example, configurations with the same function, method, and results, or configurations with the same purpose and effect. Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Finally, the present invention includes configurations that add known technology to the configurations described in the embodiments.

[0073] The following can be derived from the embodiments and modifications described above.

[0074] One aspect of a semiconductor device is: A first semiconductor portion and a second semiconductor portion having the same conductivity type and arranged along a first direction, A third semiconductor portion is provided between the first semiconductor portion and the second semiconductor portion, and has a lower impurity concentration than the first and second semiconductor portions. A fourth semiconductor portion is provided between the second semiconductor portion and the third semiconductor portion, and has a lower impurity concentration than the first semiconductor portion and the second semiconductor portion. A gate insulating layer and a gate electrode are provided in a second direction intersecting the first direction of the third semiconductor portion, The dielectric portion provided in the second direction of the fourth semiconductor portion, It has, The dielectric portion is made of a material with a larger band gap and a higher relative permittivity than the material constituting the fourth semiconductor portion. When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the fourth semiconductor portion.

[0075] Such a semiconductor layer allows for lower on-resistance.

[0076] In one aspect of semiconductor devices, The first semiconductor portion, the third semiconductor portion, and the fourth semiconductor portion may be stacked in the first direction to form a columnar portion.

[0077] Such a semiconductor layer reduces the likelihood of crystal defects reaching the third and fourth semiconductor layers.

[0078] In one aspect of semiconductor devices, Viewed from the first direction, the gate insulating layer surrounds the third semiconductor portion, The gate electrode may surround the gate insulating layer.

[0079] Such a semiconductor layer allows for the complete depletion of the third semiconductor portion.

[0080] In one aspect of semiconductor devices, The first semiconductor section constitutes the source region, The second semiconductor portion may constitute a drain region.

[0081] Such a semiconductor layer can significantly enhance the diode resurfacing effect.

[0082] In one aspect of semiconductor devices, The material of the dielectric portion may be a transition metal oxide.

[0083] According to such a semiconductor layer, 4 The band gap is larger than that of the semiconductor part, and the ratio It is easier to create a dielectric part with a high dielectric constant.

[0084] In one aspect of semiconductor devices, The material of the dielectric portion may be hafnium oxide.

[0085] With such a semiconductor layer, the dielectric portion can be formed by the ALD method.

[0086] In one aspect of semiconductor devices, The gate insulating layer may be made of a material with a larger band gap and a higher dielectric constant than the material constituting the third semiconductor portion.

[0087] Such a semiconductor layer can improve the controllability of the threshold voltage.

[0088] In one aspect of semiconductor devices, The material of the gate insulating layer may be a transition metal oxide.

[0089] Such a semiconductor layer makes it easier to realize a gate insulating layer with a larger band gap and higher dielectric constant than the third semiconductor layer.

[0090] In one aspect of semiconductor devices, The material of the gate insulating layer may be hafnium oxide.

[0091] With such a semiconductor layer, the gate insulating layer can be formed by the ALD method.

[0092] In one aspect of semiconductor devices, The second semiconductor portion has electrodes provided in the first direction. The second semiconductor portion may further be provided in the first direction of the dielectric portion.

[0093] Such a semiconductor layer makes it possible to lower the contact resistance between the second semiconductor portion and the electrode.

[0094] One form of a power device is, A first semiconductor portion and a second semiconductor portion having the same conductivity type and arranged along a first direction, A third semiconductor portion is provided between the first semiconductor portion and the second semiconductor portion, and has a lower impurity concentration than the first and second semiconductor portions. A gate insulating layer and a gate electrode are provided in a second direction intersecting the first direction of the third semiconductor portion, A dielectric portion provided in the second direction of the second semiconductor portion, It has, The dielectric portion is made of a material with a larger band gap and a higher relative permittivity than the material constituting the second semiconductor portion. When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the second semiconductor portion by the electric field generated in the dielectric portion.

[0095] Such power devices allow for lower on-resistance. [Explanation of Symbols]

[0096] 10...Substrate, 20...Buffer layer, 22...Mask layer, 24...Aperture, 30...Columnar portion, 32...Source region, 34...Channel formation region, 37...Drift region, 38...Drain region, 40...Insulating layer, 50...Gate insulating layer, 50a, 52...Insulating layer, 60...Gate electrode, 70...Dielectric layer, 80...Drain electrode, 100, 200...Semiconductor device

Claims

1. A first semiconductor portion and a second semiconductor portion having the same conductivity type and arranged along a first direction, A third semiconductor portion is provided between the first semiconductor portion and the second semiconductor portion, and has a lower impurity concentration than the first and second semiconductor portions. A fourth semiconductor portion is provided between the second semiconductor portion and the third semiconductor portion, and has a lower impurity concentration than the first semiconductor portion and the second semiconductor portion. A gate insulating layer and a gate electrode are provided on the second direction side intersecting the first direction of the third semiconductor portion, A dielectric portion provided on the second direction side of the fourth semiconductor portion, It has, The dielectric portion is made of a material with a larger band gap and a higher relative permittivity than the material constituting the fourth semiconductor portion. When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the fourth semiconductor portion. A semiconductor device in which the first semiconductor portion, the third semiconductor portion, and the fourth semiconductor portion are stacked along the first direction to form a columnar portion.

2. In claim 1, Viewed from the first direction, the gate insulating layer surrounds the third semiconductor portion, The gate electrode surrounds the gate insulating layer, which is a semiconductor device.

3. In claim 1 or 2, The first semiconductor section constitutes the source region, The second semiconductor portion is a semiconductor device that constitutes a drain region.

4. In any one of claims 1 to 3, A semiconductor device in which the material of the dielectric portion is a transition metal oxide.

5. In any one of claims 1 to 4, A semiconductor device in which the material of the dielectric part is hafnium oxide.

6. In any one of claims 1 to 5, The semiconductor device wherein the gate insulating layer is made of a material that has a larger band gap and a higher dielectric constant than the material constituting the third semiconductor portion.

7. In any one of claims 1 to 6, A semiconductor device wherein the material of the gate insulating layer is a transition metal oxide.

8. In any one of claims 1 to 7, A semiconductor device wherein the material of the gate insulating layer is hafnium oxide.

9. A first semiconductor portion and a second semiconductor portion having the same conductivity type and arranged along a first direction, A third semiconductor portion is provided between the first semiconductor portion and the second semiconductor portion, and has a lower impurity concentration than the first and second semiconductor portions. A fourth semiconductor portion is provided between the second semiconductor portion and the third semiconductor portion, and has a lower impurity concentration than the first semiconductor portion and the second semiconductor portion. A gate insulating layer and a gate electrode are provided on the second direction side intersecting the first direction of the third semiconductor portion, The dielectric portion provided in the second direction of the fourth semiconductor portion, It has, The dielectric portion is made of a material with a larger band gap and a higher relative permittivity than the material constituting the fourth semiconductor portion. When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the fourth semiconductor portion. The electrode provided on the first direction side of the second semiconductor portion The second semiconductor portion is further provided on the first direction side of the dielectric portion, and is a semiconductor device.

10. A first semiconductor portion and a second semiconductor portion having the same conductivity type and arranged along a first direction, A third semiconductor portion is provided between the first semiconductor portion and the second semiconductor portion, and has a lower impurity concentration than the first and second semiconductor portions. A fourth semiconductor portion is provided between the second semiconductor portion and the third semiconductor portion, and has a lower impurity concentration than the first semiconductor portion and the second semiconductor portion. A gate insulating layer and a gate electrode are provided in a second direction intersecting the first direction of the third semiconductor portion, The dielectric portion provided in the second direction of the fourth semiconductor portion, It has, The dielectric portion is made of a material with a larger band gap and a higher relative permittivity than the material constituting the fourth semiconductor portion. When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the fourth semiconductor portion. A power device in which the first semiconductor portion, the third semiconductor portion, and the fourth semiconductor portion are stacked along the first direction to form a columnar portion.

11. A first semiconductor portion and a second semiconductor portion having the same conductivity type and arranged along a first direction, A third semiconductor portion is provided between the first semiconductor portion and the second semiconductor portion, and has a lower impurity concentration than the first and second semiconductor portions. A fourth semiconductor portion is provided between the second semiconductor portion and the third semiconductor portion, and has a lower impurity concentration than the first semiconductor portion and the second semiconductor portion. A gate insulating layer and a gate electrode are provided in a second direction intersecting the first direction of the third semiconductor portion, The dielectric portion provided in the second direction of the fourth semiconductor portion, It has, The dielectric portion is made of a material with a larger band gap and a higher relative permittivity than the material constituting the fourth semiconductor portion. When a predetermined voltage is applied to the gate electrode, a depletion layer is formed in the fourth semiconductor portion. The electrode provided on the first direction side of the second semiconductor portion The second semiconductor portion is a power device provided on the first direction side of the dielectric portion.

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