Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the semiconductor structure comprising: a first device structure comprising a first substrate and a first device formed on the first substrate, the first device comprising a first channel layer structure on the first substrate, a first device gate structure across the first channel layer structure, and first source / drain doped regions in the first channel layer structure on both sides of the first device gate structure; a second device structure on a front side of the first device structure, comprising a second substrate on the first device structure and a second device formed on the second substrate, the second device comprising a second channel layer structure on the second substrate, a second device gate structure across the second channel layer structure, and second source / drain doped regions in the second channel layer structure on both sides of the second device gate structure; a projection of the second channel layer structure and the first channel layer structure on the first substrate does not vertically intersect. The present application can realize electrical lead-out of the first device.

Description

Semiconductor structure and its formation method Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] In semiconductor manufacturing, with the development trend of very large-scale integrated circuits (VLSI), the feature size of integrated circuits continues to shrink. To adapt to the shrinking feature size, the channel length of MOSFETs is also continuously shortening. However, as the channel length of the device shortens, the distance between the source and drain of the device also shortens, thus reducing the gate's control over the channel and making it increasingly difficult to pinch off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better adapt to the reduction in feature size, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency.

[0004] Among them, the vertically stacked complementary field-effect transistor (CFET) is a revolutionary three-dimensional transistor. In the CFET structure, PMOS transistors and NMOS transistors stacked vertically to each other form complementary devices, which can save area, increase transistor integration density, and thus bring benefits in power consumption and cost performance. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby realizing the electrical lead-out of a first device.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure, comprising: a first device structure including a first substrate and a first device formed on the first substrate, the first device including a first channel layer structure on the first substrate, a first device gate structure spanning the first channel layer structure, and first source / drain doped regions within the first channel layer structure on both sides of the first device gate structure, wherein the surface of the first device structure closest to the top of the first device gate structure is the front side; and a second device structure located on the front side of the first device structure including a second substrate on the first device structure and a second device formed on the second substrate, the second device including a second channel layer structure on the second substrate, a second device gate structure spanning the second channel layer structure, and second source / drain doped regions within the second channel layer structure on both sides of the second device gate structure; wherein the projections of the second channel layer structure and the first channel layer structure onto the first substrate are not perpendicularly intersecting.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: forming a first device structure, including a first substrate and a first device formed on the first substrate, the first device including a first channel layer structure on the first substrate, a first device gate structure spanning the first channel layer structure, and first source / drain doped regions located in the first channel layer structures on both sides of the first device gate structure, wherein the surface of the first device structure near the top of the first device gate structure is the front side; disposing a second substrate on the front side of the first device structure; after disposing the second substrate on the front side of the first device structure, forming a second channel layer structure on the second substrate, wherein the projections of the second channel layer structure and the first channel layer structure on the first substrate are not perpendicularly intersecting; forming a second device gate structure and a second source / drain doped region on the second substrate, the second device gate structure spanning the second channel layer structure, the second source / drain doped region located in the second channel layer structures on both sides of the second device gate structure, the second source / drain doped region, the second device gate structure, and the second channel layer structure are used to form a second device, and the second device and the second substrate are used to constitute the second device structure.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] This invention provides a semiconductor structure comprising a first device structure and a second device structure located on the front side of the first device structure. The first device structure includes a first device, which includes a first channel layer structure and a first device gate structure spanning the first channel layer structure. The second device structure includes a second device, which includes a second channel layer structure and a second device gate structure spanning the second channel layer structure. The projections of the second channel layer structure and the first channel layer structure onto a first substrate are not perpendicularly intersecting, and the projections of the second device gate structure and the first device gate structure onto the first substrate are also not perpendicularly intersecting. Therefore, when a source / drain plug connected to a first source / drain doped region in the first device is formed, or a gate plug connected to the first device structure in the first device is formed, the probability that the formation process of the source / drain plug or the gate plug is blocked by the second device can be reduced, thereby facilitating the electrical lead-out of the first device. Moreover, the first device and the second device are independent of each other, and electrical isolation can still be achieved between the first device and the second device. Attached Figure Description

[0010] Figure 1 is a three-dimensional view of a semiconductor structure;

[0011] Figure 2 is a perspective view of an embodiment of the semiconductor structure of the present invention;

[0012] Figure 3 is a top view of the semiconductor structure shown in Figure 2;

[0013] Figure 4 is a cross-sectional view of the semiconductor structure shown in Figure 2 at the location where the second device is exposed and along the extension direction of the first channel layer structure.

[0014] Figure 5 is a cross-sectional view of the second device structure in the semiconductor structure shown in Figure 2 along the extension direction of the second channel layer structure.

[0015] Figures 6 to 16 are schematic diagrams of the structure corresponding to each step in one embodiment of the method for forming the semiconductor structure of the present invention. Detailed Implementation

[0016] As is known from the background art, the CFET device structure includes PMOS transistors and NMOS transistors stacked vertically on top of each other. However, it is currently difficult to expose the electrical properties of the lower-layer transistors in the CFET device structure.

[0017] We will now analyze, in conjunction with a semiconductor structure, why it is difficult to extract the electrical properties of the lower-level transistors in a CFET device structure.

[0018] Referring to Figure 1, a three-dimensional view of a semiconductor structure is shown.

[0019] The semiconductor structure includes: a first device structure 10, including a first substrate 11 and a first device (not shown) formed on the first substrate 10. The first device includes a first channel layer structure 12 located on the first substrate 11, a first device gate structure 13 spanning the first channel layer structure 12, and first source / drain doped regions (not shown) located in the first channel layer structures 12 on both sides of the first device gate structure 13. The surface of the first device structure 10 near the top of the first device gate structure 13 is the front side (not shown); a second device structure 20 bonded to the front side of the first device structure 10 includes a second substrate 21 bonded to the first device structure 10 and a second device (not shown) formed on the second substrate 21. The second device includes a second channel layer structure 22 located on the second substrate 21, a second device gate structure 23 surrounding the second channel layer structure 22, and second source / drain doped regions (not shown) located in the second channel layer structures 22 on both sides of the second device gate structure 23.

[0020] The first and second source / drain doped regions are formed independently, and the second channel layer structure 22 is parallel to the first channel layer structure 12, as are the second device gate structure 23 and the first device gate structure 13. Specifically, in the direction from the second device structure 20 to the first device structure 10, the second channel layer structure 22 completely blocks the first channel layer structure 12, and the second device gate structure 23 completely blocks the first device gate structure 13. For example, the projection of the first channel layer structure 12 on the first substrate 11 lies within the projection of the second channel layer structure 22 on the substrate 11, and the projections of the second device gate structure 23 and the first device gate structure 13 on the substrate 11 coincide.

[0021] The semiconductor structure needs to simultaneously achieve vertical integration and electrical isolation between the first device and the second device. However, since the second channel layer structure 22 completely blocks the first channel layer structure 12, and the second device gate structure 23 completely blocks the first device gate structure 13, the gate plug and source / drain plug in the first device are blocked by the second device, making it difficult to extract the electrical properties of the first device.

[0022] To address the aforementioned technical problems, embodiments of the present invention provide a semiconductor structure in which the projections of the second channel layer structure and the first channel layer structure onto the first substrate are not perpendicularly intersecting, and the projections of the second device gate structure and the first device gate structure onto the first substrate are also correspondingly not perpendicularly intersecting. Therefore, when a source / drain plug connected to the first source / drain doped region in the first device is formed, or a gate plug connected to the first device structure in the first device is formed, the probability that the formation process of the source / drain plug or the gate plug will be blocked by the second device can be reduced, thereby facilitating the electrical lead-out of the first device. Moreover, the first device and the second device are independent of each other, and electrical isolation can still be achieved between the first device and the second device.

[0023] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0024] Referring to Figures 2 to 5, Figure 2 is a perspective view of an embodiment of the semiconductor structure of the present invention, Figure 3 is a top view of the semiconductor structure shown in Figure 2, Figure 4 is a cross-sectional view of the semiconductor structure shown in Figure 2 at the location where the second device is exposed and along the extension direction of the first channel layer structure, and Figure 5 is a cross-sectional view of the second device structure in the semiconductor structure shown in Figure 2 along the extension direction of the second channel layer structure.

[0025] The semiconductor structure includes: a first device structure 100, including a first substrate 110 and a first device 150 formed on the first substrate 110. The first device 150 includes a first channel layer structure 120 located on the first substrate 110, a first device gate structure 130 spanning the first channel layer structure 120, and first source / drain doped regions 140 located in the first channel layer structures 120 on both sides of the first device gate structure 130. The surface of the first device structure 100 near the top of the first device gate structure 130 is the front surface 101. The second device structure 300 of 101 includes a second substrate 310 located on the first device structure 100 and a second device 350 formed on the second substrate 310. The second device 350 includes a second channel layer structure 320 located on the second substrate 310, a second device gate structure 330 spanning the second channel layer structure 320, and second source / drain doped regions 340 located in the second channel layer structure 320 on both sides of the second device gate structure 330. The projections of the second channel layer structure 320 and the first channel layer structure 120 on the first substrate 110 do not intersect perpendicularly.

[0026] In semiconductor structures, the electrical properties of the first source / drain doped region 140 are typically extracted through a source / drain plug connected to the first source / drain doped region 140, and the electrical properties of the first device gate structure 130 are extracted through a gate plug connected to the first device gate structure 130. In this embodiment, by making the projections of the second channel layer structure 320 and the first channel layer structure 120 onto the first substrate 110 non-perpendicular, the probability of the second device 350 completely obscuring the first device 150 is reduced. When forming the source / drain plug connected to the first source / drain doped region 140, or when forming the gate plug connected to the first device gate structure 130, the probability of the formation process of the source / drain plug or gate plug being blocked by the second device 350 can be reduced. This facilitates the electrical extraction of the first device 150, while maintaining the independence between the first device 150 and the second device 350, and ensuring electrical isolation between them.

[0027] In this embodiment, the semiconductor structure is a complementary field-effect transistor (CFET). Therefore, in the CFET structure, the first device 150 and the second device 350 are stacked vertically, which can save area, increase transistor integration density, and thus bring benefits in terms of power consumption and cost performance.

[0028] Specifically, the first device 150 and the second device 350 have different channel conductivity types, so that the first device 150 and the second device 350, which are stacked perpendicularly to each other, constitute complementary devices.

[0029] In this embodiment, the first device 150 is an NMOS device, and the second device 350 is a PMOS device. In other embodiments, the first device is a PMOS device, and the second device is an NMOS device.

[0030] It should be noted that in other embodiments, depending on the device design requirements, the first and second devices may have the same channel conductivity type, but different device performance types. For example, the first and second devices may have different threshold voltages.

[0031] As an example, both the first device 150 and the second device 350 are fully enclosed gate devices. In other embodiments, the first device may also be a fin field-effect transistor, the second device may also be a fin field-effect transistor, and the structural types of the first and second devices may be different. For example, the first device is a fin field-effect transistor, and the second device is a fully enclosed gate device.

[0032] In this embodiment, the first device structure 100 includes a first substrate 110 and a first device 150 formed on the first substrate 110.

[0033] The first substrate 110 is used to provide a process platform for the formation of the first device 150.

[0034] In this embodiment, the first substrate 110 is a bulk substrate. As an example, the material of the first substrate is silicon. In other embodiments, the first substrate may also be a substrate of other material types. For example, the material of the first substrate may be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, etc. The first substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0035] As an example, the first device structure 100 further includes: a first fin 111 protruding from the first substrate 110, and a first isolation layer 112 located on the first substrate 110 exposed by the first fin 111, the top of the first isolation layer 112 being flush with the top of the first fin 111.

[0036] In this embodiment, the material of the first fin 111 is the same as the material of the first substrate 110.

[0037] The first isolation layer 112 serves as a shallow trench isolation (STI) structure to isolate adjacent transistors. The material of the first isolation layer 112 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the first isolation layer 112 is silicon nitride.

[0038] In this embodiment, the first device 150 includes a first channel layer structure 120, a first device gate structure 130 spanning the first channel layer structure 120, and a first source / drain doped region 140 located in the first channel layer structure 120 on both sides of the first device gate structure 130.

[0039] The first channel layer structure 120 is used to provide a channel for the first device 150.

[0040] In this embodiment, the first channel layer structure 120 is spaced apart from the first substrate 110. Specifically, the first channel layer structure 120 is spaced apart from the first fin 111.

[0041] The first channel layer structure 120 includes one or more first channel layers 125 spaced apart in the normal direction of the surface of the first substrate 110. As an example, the first channel layer structure 120 includes one first channel layer 125.

[0042] In this embodiment, the first device 150 is an NMOS device; therefore, the first channel layer structure 120 is used to provide a channel for the NMOS device, and the material of the first channel layer structure 120 is silicon. In other embodiments, when the first device is a PMOS device, the first channel layer structure is correspondingly used to provide a channel for the PMOS device, and the material of the first channel layer structure is correspondingly germanium or silicon germanide.

[0043] It should be noted that, in other embodiments, when the first device is a fin field-effect transistor, the first channel layer structure is the first fin protruding from the first substrate. Correspondingly, the first isolation layer covers part of the sidewall of the first fin, and the top of the first isolation layer is lower than the top of the first fin.

[0044] Referring to Figure 3, which is a top view of the semiconductor structure shown in Figure 2, Figure 3 only shows the first channel layer structure 120, the first device gate structure 130, the second channel layer structure 320, and the second device gate structure 330 to illustrate the relative positional relationship between the first device 150 and the second device 350.

[0045] In this embodiment, there are multiple first channel layer structures 120 in a direction parallel to the surface of the first substrate 110, and the multiple first channel layer structures 120 are arranged in parallel, with a first pitch P1 between adjacent first channel layer structures 120. The first pitch P1 is the sum of the linewidth of the first channel layer structure 120 and the spacing between adjacent first channel layer structures 120.

[0046] The first device gate structure 130 is located on the first isolation layer 112. The first device gate structure 130 is orthogonal to the first channel layer structure 120. The orthogonal first device gate structure 130, the first channel layer structure 120, and the first source / drain doped regions 140 located on both sides of the first device gate structure 130 are used to form a first device 150.

[0047] The first device gate structure 130 is used to control the opening and closing of the channel of the first device 150.

[0048] In this embodiment, the first device gate structure 130 is a metal gate (MG) structure. By employing a metal gate structure, the leakage current of the semiconductor device is reduced. Accordingly, the first device gate structure 130 includes a first high-k gate dielectric layer (not shown), a first work function layer (not shown) located on the first high-k gate dielectric layer, and a first gate electrode layer (not shown) located on the first work function layer.

[0049] The first high-k gate dielectric layer is made of a high-k dielectric material, where a high-k dielectric material is a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the first high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the first high-k gate dielectric layer is HfO2.

[0050] The first work function layer is used to adjust the threshold voltage of the first device 150. In this embodiment, the first device 150 is an NMOS device, and the first work function layer is correspondingly an N-type work function layer. The material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0051] The first gate electrode layer is used to electrically lead out the gate structure 130 of the first device. In this embodiment, the material of the first gate electrode layer is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0052] The first source / drain doped region 140 serves as the source or drain region of the first device 150. In this embodiment, the first source / drain doped region 140 includes a first epitaxial layer doped with first-type ions, the first type of which has the same conductivity type as the channel conductivity type of the first device 150.

[0053] Specifically, the first device 150 is an NMOS device; therefore, the material of the first epitaxial layer is Si or SiC, and the first type of ion is an N-type ion, which includes P ions, As ions, or Sb ions. As an example, the material of the first source / drain doped region 140 is SiP.

[0054] Referring to FIG4, in this embodiment, the first device structure 100 further includes: a first interlayer dielectric layer 160, located on the first substrate 110 on the side of the first device gate structure 130, and the first interlayer dielectric layer 160 covers the sidewall of the first device gate structure 130.

[0055] The first interlayer dielectric layer 160 is used to isolate adjacent first devices 150. The material of the first interlayer dielectric layer 160 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the first interlayer dielectric layer 160 is silicon oxide.

[0056] In this embodiment, the top of the first interlayer dielectric layer 160 is flush with the top of the first device gate structure 130.

[0057] Referring again to Figure 4, in this embodiment, the semiconductor structure further includes a bottom source / drain plug 210, which penetrates the first interlayer dielectric layer 160 above the first source / drain doped region 140 and is connected to the first source / drain doped region 140.

[0058] The electrical properties of the first source / drain doped region 140 are brought out through the bottom source / drain plug 210.

[0059] In this embodiment, the source / drain plug connected to the first source / drain doped region 140 is used as the first source / drain plug, and the bottom source / drain plug 210 is used as part of the first source / drain plug.

[0060] A second device structure 300 is stacked on the first device structure 100. Correspondingly, a first source / drain plug penetrates the second device structure 300 and the first interlayer dielectric layer 160 above the first source / drain doped region 140. By providing a bottom source / drain plug 210 in the first device structure 100, the first source / drain plug can be formed through two plug formation processes during the formation of the semiconductor structure. That is, after stacking the second device structure 300 on the first device structure 100, a top source / drain plug is formed that penetrates the second device structure 300 and is connected to the bottom source / drain plug 210. The top and bottom source / drain plugs are used to constitute the first source / drain plug, thereby reducing the etching depth of a single plug formation process, which is beneficial to improving the morphological quality and dimensional accuracy of the first source / drain plug.

[0061] In this embodiment, the bottom source / drain plug 210 is flush with the top of the first interlayer dielectric layer 160. In this embodiment, the bottom source / drain plug 210 is made of copper. Copper has low resistivity, which helps improve the signal delay of the subsequent RC circuit, increases the chip's processing speed, and also helps reduce the resistance of the bottom source / drain plug 210, thereby reducing power consumption. In other embodiments, the bottom source / drain plug can also be made of conductive materials such as tungsten or cobalt.

[0062] In this embodiment, the surface of the first device structure 100 near the top of the first device gate structure 130 is the front side 101, and the second device structure 300 is located on the front side 101 of the first device structure 100. That is, the first device 150 and the second device 350 are located on the same side of the first substrate 110. Accordingly, the interconnect layout can be realized on the same side of the first substrate 110, which is beneficial to reduce circuit complexity and reduce the thickness of the semiconductor structure. Moreover, compared with the scheme of stacking the first device and the second device on the same substrate, the first device 150 is formed on the first substrate 110, and the second device 350 is formed on the second substrate 310. The first device 150 and the second device 350 do not share the same device gate structure, so that the first device 150 and the second device 350 are independent of each other, and electrical isolation can still be achieved between the first device 150 and the second device 350. This correspondingly improves the process flexibility when forming the first device 150 and the second device 350, and makes it easier for the first device 150 and the second device 350 to meet their respective performance requirements.

[0063] In this embodiment, the second device structure 300 is bonded to the front side 101 of the first device structure 100. By employing bonding, the finished second substrate 310 can be directly combined with the first device structure 100 during the formation of the semiconductor structure, thereby reducing process complexity and increasing process feasibility.

[0064] Specifically, the semiconductor structure further includes a bonding layer 200 located between the front side 101 of the first device structure 100 and the second substrate 310. The bonding layer 200 facilitates bonding between the second substrate 310 and the first device structure 100, and the bonding strength is high.

[0065] In this embodiment, the bonding layer 200 is made of silicon oxide. By using silicon oxide, the second substrate 310 and the first device structure 100 can be bonded by fusion bonding, which is beneficial to improving bonding efficiency and bonding strength between the first device structure 100 and the second device structure 300; moreover, it is also beneficial to further improve the electrical isolation effect between the first device 150 and the second device 350; in addition, by using silicon oxide, the bonding temperature is lower, thereby reducing the impact on the performance of the first device 150.

[0066] Specifically, the bonding layer 200 includes two stacked sub-bonding layers. One sub-bonding layer is located on the front side 101 of the first device structure 100, and the other sub-bonding layer is located on the surface of the second substrate 310 facing the first device structure 100. Thus, the bonding between the second substrate 310 and the first device structure 100 is achieved through the bonding of the two sub-bonding layers. For example, both sub-bonding layers are made of silicon oxide, thereby achieving silicon oxide-silicon oxide fusion bonding.

[0067] In this embodiment, the second device structure 300 includes a second substrate 310 and a second device 350 formed on the second substrate 310.

[0068] The second substrate 310 is used to provide a process platform for the formation of the second device 350.

[0069] In this embodiment, the second substrate 310 is a substrate that has undergone thinning treatment. The thickness of the second substrate 310 is small, so that the thickness of the second substrate 310 meets the performance requirements.

[0070] For a detailed description of the second substrate 310, please refer to the corresponding description of the first substrate 110 above, which will not be repeated here.

[0071] As an example, the second device structure 300 further includes: a second fin 311 protruding from the second substrate 310, and a second isolation layer 312 located on the second substrate 310 exposed by the second fin 311, the top of the second isolation layer 312 being flush with the top of the second fin 311.

[0072] For a detailed description of the second fin 311 and the second isolation layer 312, please refer to the corresponding descriptions of the first fin 111 and the first isolation layer 112 above, which will not be repeated here.

[0073] In this embodiment, the second device 350 includes a second channel layer structure 320 located on the second substrate 310, a second device gate structure 330 spanning the second channel layer structure 320, and a second source / drain doped region 340 located in the second channel layer structure 320 on both sides of the second device gate structure 330.

[0074] The second channel layer structure 320 is used to provide a channel for the second device 350.

[0075] In this embodiment, the second channel layer structure 320 and the second substrate 310 are spaced apart. Specifically, the second channel layer structure 320 and the second fin 311 are spaced apart.

[0076] The second channel layer structure 320 includes one or more second channel layers 325 spaced apart in the normal direction of the surface of the second substrate 310. As an example, the second channel layer structure 320 includes one second channel layer 325.

[0077] In this embodiment, the second device 350 is a PMOS device. Therefore, the second channel layer structure 320 is used to provide the channel for the PMOS device, and the material of the second channel layer structure 320 is germanium or silicon germanide. By using germanium or silicon germanide, it is beneficial to improve the negative bias temperature instability (NBTI) problem of the PMOS transistor, thereby improving the performance of the PMOS transistor. In other embodiments, when the second device is an NMOS device, the second channel layer structure is correspondingly used to provide the channel for the NMOS device, and the material of the second channel layer structure can be silicon.

[0078] It should be noted that in other embodiments, the second device may also be a fin field-effect transistor, and the second channel layer structure is the second fin protruding from the second substrate. Correspondingly, the second isolation layer covers part of the sidewall of the second fin, and the top of the second isolation layer is lower than the top of the second fin.

[0079] In this embodiment, the projections of the second channel layer structure 320 and the first channel layer structure 120 on the first substrate 110 are not perpendicularly intersecting. Consequently, the projections of the second device gate structure 330 and the first device gate structure 130 on the first substrate 110 are also not perpendicularly intersecting. Moreover, the first source / drain doped region 140 is located within the first channel layer structure 120 on both sides of the first device gate structure 130, and the second source / drain doped region 340 is located within the second channel layer structure 320 on both sides of the first device gate structure 330. Therefore, the probability that the second device 350 completely blocks the first device 150 is low, so that the electrical properties of the first device 150 can be brought out.

[0080] Specifically, the projections of the second channel layer structure 320 and the first channel layer structure 120 on the first substrate 110 are not perpendicular to each other, so that the projection of the second channel layer structure 320 on the first substrate 110 can expose part of the projection of the first channel layer structure 120 on the first substrate 110.

[0081] Correspondingly, the source / drain plug connected to the first source / drain doped region 140 (i.e., the first source / drain plug) can be disposed in the exposed area of ​​the second device 350, and penetrate the second device structure 300 and the first interlayer dielectric layer 160 above the top of the first source / drain doped region 140. Similarly, the gate plug connected to the top of the first device gate structure 130 can also be disposed in the exposed area of ​​the second device 350, and penetrate the second device structure 300 above the top of the first device gate structure 130.

[0082] It should be noted that if the angle between the projections of the second channel layer structure 320 and the first channel layer structure 120 on the first substrate 110 is too large or too small, it will easily increase the area of ​​the second device 350 blocking the first device 150, thereby increasing the difficulty of bringing out the electrical signals of the first device 150. Therefore, in this embodiment, the angle between the projections of the second channel layer structure 320 and the first channel layer structure 120 on the first substrate 110 is between 5 degrees and 85 degrees, so that the projection of the second channel layer structure 320 on the first substrate 110 can expose part of the projection of the first channel layer structure 120 on the first substrate 110.

[0083] As an example, the included angle is 45 degrees, thereby minimizing the area of ​​the second device 350 that is blocked by the first device 150, and providing sufficient process window for forming the source / drain plug connected to the first source / drain doped region 140 and the gate plug connected to the gate structure 130 of the first device.

[0084] Referring again to Figure 3, in this embodiment, in the second device structure 300, there are multiple second channel layer structures 320 in a direction parallel to the surface of the second substrate 310, and the multiple second channel layer structures 320 are arranged in parallel, with a second pitch P2 between adjacent second channel layer structures 320. The second pitch P2 is the sum of the linewidth of the second channel layer structure 320 and the spacing between adjacent second channel layer structures 320.

[0085] In this embodiment, the second pitch P2 and the first pitch P1 are not equal, that is, the second pitch P2 is less than the first pitch P1, or the second pitch P2 is greater than the first pitch P1. By making the second pitch P2 and the first pitch P1 unequal, the occlusion area of ​​the second device 350 on the first device 150 is further reduced.

[0086] It should be noted that the absolute value of the difference between the second pitch P2 and the first pitch P1 should not be too small or too large. If the absolute value of the difference is too small, the second pitch P2 and the first pitch P1 will be too close, which may increase the area of ​​the second device 350 blocking the first device 150, or even lead to the second device 350 completely blocking the first device 150, thereby increasing the difficulty of the process of bringing out the electrical properties of the first device 150. If the absolute value of the difference is too large, the second pitch P2 or the first pitch P1 may be too large, resulting in an excessively large overall area of ​​the semiconductor structure. Moreover, increasing the pitch will lead to an increase in the volume of the epitaxial layer corresponding to the source and drain doped regions. Correspondingly, if the absolute value of the difference is too large, the volume difference between the epitaxial layers corresponding to the first source and drain doped region 140 and the second source and drain doped region 340 may be too large, which may lead to a mismatch in the performance of the first device 150 and the second device 350. Therefore, in this embodiment, the absolute value of the difference between the second pitch P2 and the first pitch P1 is 1 nanometer to 5 nanometers. For example, the absolute value of the difference between the second pitch P2 and the first pitch P1 is 2 nanometers, 3 nanometers, or 4 nanometers.

[0087] The second device gate structure 330 is located on the second isolation layer 312. The second device gate structure 330 is orthogonal to the second channel layer structure 320. The orthogonal second device gate structure 330 and the second channel layer structure 320, as well as the second source and drain doped regions 340 located on both sides of the second device gate structure 330, are used to form a second device 350.

[0088] The gate structure 330 of the second device is used to control the opening and closing of the channel of the second device 350.

[0089] In this embodiment, the second device gate structure 330 is a metal gate structure. The second device gate structure 330 includes a second high-k gate dielectric layer (not shown), a second work function layer (not shown) located on the second high-k gate dielectric layer, and a second gate electrode layer (not shown) located on the second work function layer.

[0090] For a detailed description of the second high-k gate dielectric layer and the second gate electrode layer, please refer to the corresponding descriptions of the first high-k gate dielectric layer and the first gate electrode layer above, which will not be repeated here.

[0091] The second work function layer is used to adjust the threshold voltage of the second device 350. In this embodiment, the second device 350 is a PMOS device, and the second work function layer is a P-type work function layer. The material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN.

[0092] The second source / drain doped region 340 serves as the source or drain region of the second device 350. In this embodiment, the second source / drain doped region 340 includes a second epitaxial layer doped with type II ions, the conductivity type of which is the same as the channel conductivity type of the second device 350.

[0093] Specifically, the second device 350 is a PMOS device; therefore, the material of the second epitaxial layer is Si or SiGe, and the second type of ions is P-type ions, including B ions, Ga ions, or In ions. As an example, the material of the second source / drain doped region 340 is SiGeB.

[0094] Referring to Figures 4 and 5, in this embodiment, the second device structure 300 further includes a second interlayer dielectric layer 360 located on the second substrate 310 on the side of the second device gate structure 330, and the second interlayer dielectric layer 360 covers the sidewall of the second device gate structure 330.

[0095] The second interlayer dielectric layer 360 is used to isolate the adjacent second device 350. In this embodiment, the material of the second interlayer dielectric layer 360 is silicon oxide, and the top of the second interlayer dielectric layer 360 is flush with the top of the gate structure 330 of the second device. For a detailed description of the second interlayer dielectric layer 360, please refer to the corresponding description of the first interlayer dielectric layer 160 above, which will not be repeated here.

[0096] As shown in Figure 4, the semiconductor structure further includes: a top source / drain plug 220, which penetrates the second interlayer dielectric layer 360 and the second substrate 310 above the first source / drain doped region 140 and is connected to the bottom source / drain plug 210. The top source / drain plug 220 and the bottom source / drain plug 210 are used to form the first source / drain plug 230.

[0097] The top source / drain plug 220 is electrically connected to the first source / drain doped region 140 through the bottom source / drain plug 210. Therefore, the first source / drain plug 230 is used to bring out the electrical properties of the first source / drain doped region 140.

[0098] In this embodiment, the top of the top source / drain plug 220 is flush with the top of the second interlayer dielectric layer 360, and the material of the top source / drain plug 220 is copper.

[0099] It should be noted that in other embodiments, the top source drain plug and the bottom source drain plug may also be an integral structure, thereby improving the alignment accuracy when forming the first source drain plug.

[0100] As shown in Figure 5, the semiconductor structure further includes a second source / drain plug 240, which penetrates the second interlayer dielectric layer 360 above the second source / drain doped region 340 and is connected to the second source / drain doped region 340.

[0101] The second source / drain plug 240 is used to electrically bring out the second source / drain doped region 340. In this embodiment, the top of the second source / drain plug 240 is flush with the top of the second interlayer dielectric layer 360, and the material of the second source / drain plug 240 is copper. For a detailed description of the top source / drain plug 220 and the second source / drain plug 240, please refer to the corresponding description of the bottom source / drain plug 210 above, which will not be repeated here.

[0102] Accordingly, the present invention also provides a method for forming a semiconductor structure.

[0103] Figures 6 to 16 are schematic diagrams of the structure corresponding to each step in one embodiment of the method for forming the semiconductor structure of the present invention.

[0104] Referring to Figures 6 and 7, Figure 7 is a top view of Figure 6, forming a first device structure 400, including a first substrate 410 and a first device 450 formed on the first substrate 410. The first device 450 includes a first channel layer structure 420 located on the first substrate 410, a first device gate structure 430 spanning the first channel layer structure 420, and first source / drain doped regions 440 located in the first channel layer structures 420 on both sides of the first device gate structure 430. The surface of the first device structure 400 near the top of the first device gate structure 430 is the front side 401.

[0105] For ease of illustration, Figure 7 only shows the relative positional relationship between the first channel layer structure 420 and the first device gate structure 430.

[0106] In this embodiment, the formation method is used to form a complementary field-effect transistor (CFET). Therefore, a second device structure with a second device is subsequently formed above the first device structure 400, so that the first device 450 and the second device are stacked vertically, thereby saving area, increasing transistor integration density, and thus bringing benefits in terms of power consumption and cost performance.

[0107] The first substrate 410 serves as a process platform for the formation of the first device 450. As an example, the formed first device 450 is a fully enclosed gate transistor.

[0108] In this embodiment, the first substrate 410 is a bulk substrate. As an example, the material of the first substrate is silicon.

[0109] In other embodiments, the first substrate may also be a substrate of other material types. For example, the material of the first substrate may be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium bismuth, etc. The first substrate may also be other types of substrates such as silicon on insulator or germanium on insulator.

[0110] In this embodiment, a first fin 411 and a first isolation layer 412 are also formed on the first substrate 410 exposed on the first substrate 410. The top of the first isolation layer 412 is flush with the top of the first fin 411. For a detailed description of the first substrate 410, the first fin 411 and the first isolation layer 412, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0111] In this embodiment, the first device 450 includes a first channel layer structure 420, a first device gate structure 430 spanning the first channel layer structure 420, and a first source / drain doped region 440 located in the first channel layer structure 420 on both sides of the first device gate structure 430.

[0112] Specifically, referring to FIG7, the first device gate structure 430 is orthogonal to the first channel layer structure 420, and the orthogonal first device gate structure 430, the first channel layer structure 420, and the first source / drain doped regions 440 located on both sides of the first device gate structure 430 are used to form a first device 450.

[0113] The first channel layer structure 420 is used to provide a channel for the first device 450.

[0114] In this embodiment, the first channel layer structure 420 and the first substrate 410 are spaced apart. Specifically, the first channel layer structure 420 and the first fin 411 are spaced apart.

[0115] The first channel layer structure 420 includes one or more first channel layers 425 spaced apart in the normal direction of the surface of the first substrate 410. As an example, the first channel layer structure 420 includes one first channel layer 425.

[0116] In this embodiment, the first device 450 is an NMOS device. Therefore, the first channel layer structure 420 is used to provide the channel for the NMOS device, and the material of the first channel layer structure 420 is silicon.

[0117] In other embodiments, when the first device is a PMOS device, the first channel layer structure is correspondingly used to provide a channel for the PMOS device, and the material of the first channel layer structure can be germanium or silicon germanide.

[0118] Referring again to FIG7, in this embodiment, there are multiple first channel layer structures 420 in a direction parallel to the surface of the first substrate 410, and the multiple first channel layer structures 420 are arranged in parallel, with a first pitch P1 between adjacent first channel layer structures 420.

[0119] The first device gate structure 430 is located on the first isolation layer 412, and the first device gate structure 430 is used to control the opening and closing of the channel of the first device 450.

[0120] In this embodiment, the first device gate structure 430 is a metal gate structure. The first device gate structure 430 includes a first high-k gate dielectric layer (not shown), a first work function layer (not shown) located on the first high-k gate dielectric layer, and a first gate electrode layer (not shown) located on the first work function layer.

[0121] For a detailed description of the first high-k gate dielectric layer, the first work function layer, and the first gate electrode layer, please refer to the corresponding descriptions in the foregoing embodiments, which will not be repeated here.

[0122] In this embodiment, the first source / drain doped region 440 includes a first epitaxial layer doped with a first type of ion, the conductivity type of which is the same as the channel conductivity type of the first device 450. Specifically, the first device 450 is an NMOS device; therefore, the material of the first epitaxial layer is Si or SiC, and the first type of ion is an N-type ion, which includes P ions, As ions, or Sb ions.

[0123] In this embodiment, the first device structure 400 further includes a first interlayer dielectric layer 460 located on the first substrate 410 on the side of the first device gate structure 430, and the first interlayer dielectric layer 460 covers the sidewall of the first device gate structure 430.

[0124] The first interlayer dielectric layer 460 is used to isolate adjacent first devices 450. The material of the first interlayer dielectric layer 460 is an insulating material, which includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the first interlayer dielectric layer 460 is silicon oxide.

[0125] In this embodiment, the top of the first interlayer dielectric layer 460 is flush with the top of the first device gate structure 430.

[0126] In this embodiment, the first device gate structure 430 is formed by forming a high k last metal gate last after forming a high k last gate dielectric layer. Therefore, before the first device gate structure 430 is formed, the position of the first device gate structure 430 is occupied by a first dummy gate structure.

[0127] Specifically, the steps of forming the first device structure 400 include: forming one or more stacked first channel layers on a first substrate 410, each first channel layer including a first sacrificial layer (not shown) and a first channel layer 425 located on the first sacrificial layer; forming a first dummy gate structure spanning the first channel layer, the first dummy gate structure covering part of the top and part of the sidewalls of the first channel layer; forming first source / drain doped regions 440 in the first channel layers on both sides of the first dummy gate structure; forming a first interlayer dielectric layer 460 on the first substrate 410 on the side of the first dummy gate structure, the first interlayer dielectric layer 460 covering the first source / drain doped regions 440; removing the first dummy gate structure to form a first gate opening (not shown) in the first interlayer dielectric layer 460; removing the sacrificial layer exposed by the first gate opening to form a first through-hole (not shown) communicating with the first gate opening; and forming a first device gate structure 430 in the first gate opening and the first through-hole, the first device gate structure 430 surrounding the first channel layer 425.

[0128] Therefore, in this embodiment, the bottommost first channel layer 425 and the first fin 411 are spaced apart.

[0129] In this embodiment, the step of forming the first device structure 400 before forming the first source / drain doped region 440 further includes: forming a first sidewall (not shown) on the sidewall of the first dummy gate structure. The first sidewall is used to protect the sidewall of the first dummy gate structure and also serves as a mask when forming the first source / drain doped region 440. As an example, the material of the first sidewall is silicon nitride.

[0130] In this embodiment, before forming the first source / drain doped region 440, the step of forming the first device structure 400 further includes: using the first sidewall as a mask, etching the first channel stack on both sides of the first pseudo-gate structure, forming a groove in the first channel stack, the groove exposing the sidewall of the first sacrificial layer and the first channel layer 425; correspondingly, the step of forming the first source / drain doped region 440 includes: using an epitaxial process to form a first epitaxial layer in the groove, and during the epitaxial process, in-situ self-doping with type I ions, the first epitaxial layer doped with type I ions serving as the first source / drain doped region 440.

[0131] It should be noted that, after forming the trench and before forming the first source / drain doped region 440, the step of forming the first device structure 400 further includes: laterally etching a portion of the first sacrificial layer exposed by the trench along a direction perpendicular to the sidewall of the dummy gate structure, so that the remaining sidewall of the first sacrificial layer is recessed inward relative to the sidewall of the first channel layer 425 to form a trench, the trench being surrounded by the adjacent first channel layer 425 and the remaining first sacrificial layer, or by the first channel layer 425 closest to the first substrate 410, the first substrate 410, and the remaining first sacrificial layer; and forming a first inner spacer (not shown) in the trench.

[0132] The first inner wall helps to reduce the parasitic capacitance between the first device gate structure 430 and the first source-drain plug, thereby improving device performance. The first source-drain plug refers to the contact plug electrically connected to the first source-drain doped region 440.

[0133] It should be noted that in other embodiments, the first device may also be a fin field-effect transistor, and correspondingly, the first channel layer structure is a first fin protruding from the first substrate. Accordingly, the first isolation layer covers part of the sidewall of the first fin, and the top of the first isolation layer is lower than the top of the first fin.

[0134] In this embodiment, when the first device is a fin field-effect transistor, in the step of forming the first dummy gate structure, the first dummy gate structure spans the first fin and covers part of the top and part of the sidewalls of the first fin, and the gate structure of the first device is formed only in the first gate opening. The steps of forming the fin field-effect transistor are similar to the steps of forming the fully enclosed gate transistor, and will not be described further in this embodiment.

[0135] Referring to Figure 8, the forming method further includes: forming a bottom source / drain plug 510 that penetrates the first interlayer dielectric layer 460 above the first source / drain doped region 440, the bottom source / drain plug 510 being connected to the first source / drain doped region 440.

[0136] The bottom source / drain plug 510 is used to bring out the electrical properties of the first source / drain doped region 440. Specifically, the bottom source / drain plug 510 is used as part of the first source / drain plug.

[0137] Subsequently, a second device structure is stacked on the first device structure 400, and the electrical properties of the first source / drain doped region 440 are brought out through the first source / drain plug. Correspondingly, the first source / drain plug penetrates the second device structure and the first interlayer dielectric layer 460 above the first source / drain doped region 440. Therefore, by first forming the bottom source / drain plug 510, after stacking the second device structure on the first device structure 400, only a top source / drain plug that penetrates the second device structure and is connected to the bottom source / drain plug 510 needs to be formed. The top and bottom source / drain plugs are used to constitute the first source / drain plug. The first source / drain plug is formed through two plug-forming processes to reduce the etching depth of a single plug-forming process. This is beneficial to improving the controllability of each etching process, and thus beneficial to improving the morphological quality and dimensional accuracy of the first source / drain plug.

[0138] Specifically, the first interlayer dielectric layer 460 above the first source / drain doped region 440 is etched to form a contact hole exposing the first source / drain doped region 440; a conductive material is filled into the contact hole; the conductive material is planarized so that the top of the remaining conductive material is flush with the top of the first interlayer dielectric layer 460, and the planarized remaining conductive material serves as the bottom source / drain plug 510.

[0139] In this embodiment, the bottom source / drain plug 510 is made of copper. In other embodiments, the bottom source / drain plug may also be made of conductive materials such as tungsten or cobalt.

[0140] After the first device structure 400 is formed, the surface of the first device structure 400 near the top of the first device gate structure 430 is the front surface 401. As an example, the front surface 401 exposes the top of the first device gate structure 430.

[0141] The front side 401 is used to provide a process platform for the formation of the subsequent second device structure.

[0142] Referring to Figure 9, a second substrate 610 is disposed on the front side 401 of the first device structure 400.

[0143] The second substrate 610 is used to provide a process platform for the subsequent formation of the second device.

[0144] Furthermore, as part of the second device structure, the second substrate 610 is disposed on the front side 401 of the first device structure 400, thereby enabling the second device structure to be stacked on the front side 401 of the first device structure 400.

[0145] Compared to the approach of stacking a first device and a second device on the same substrate, this embodiment, after forming the first device structure 400, places a second substrate 610 on the front side 401 of the first device structure 400. This allows the first device 450 to be fabricated on the first substrate 410 and the second device on the second substrate 610, respectively. The first device 450 and the second device do not share the same gate structure, making them independent of each other while maintaining electrical isolation. This improves the process flexibility in forming the first device 450 and the second device, making it easier for them to meet their respective performance requirements. Furthermore, after the second device is subsequently formed on the second substrate 610, the first device 450 and the second device are located on the same side of the first substrate 410. Consequently, interconnect layout can be implemented on the same side of the first substrate 410, which helps reduce circuit complexity and semiconductor structure thickness.

[0146] For a detailed description of the second substrate 610, please refer to the relevant description of the first substrate 410, which will not be repeated here.

[0147] In this embodiment, the step of forming a second substrate 610 on the front side 401 of the first device structure 400 includes: providing a second substrate 610; and bonding the second substrate 610 to the front side 401 of the first device structure 400.

[0148] By using a bonding method, the second substrate 310 of the finished product can be directly combined with the first device structure 100, thereby reducing the process complexity and having high process feasibility.

[0149] In this embodiment, the second substrate 610 is bonded to the front side 401 of the first device structure 400 using a bonding layer 500. By using the bonding layer 500, it is easy to achieve bonding between the second substrate 610 and the first device structure 400, and the bonding strength is high.

[0150] In this embodiment, the bonding layer 500 is made of silicon oxide. By using silicon oxide, the second substrate 610 and the first device structure 400 can be bonded by fusion bonding, which is beneficial to improving bonding efficiency and bonding strength between the second substrate 610 and the first device structure 400. Moreover, it is also beneficial to further improve the electrical isolation effect between the first device 450 and the second device. In addition, by using silicon oxide, the bonding temperature is lower, thereby reducing the impact on the performance of the first device 450.

[0151] In this embodiment, the second substrate 610 includes a bonding surface 601 for bonding with the first device structure 400. A first sub-bonding layer (not shown) is formed on the front side 401 of the first device structure 400. After a second sub-bonding layer (not shown) is formed on the bonding surface 601, the first and second sub-bonding layers are bonded together, thereby achieving bonding between the second substrate 610 and the first device structure 400. Accordingly, the first and second sub-bonding layers constitute a bonding layer 500 with a stacked structure.

[0152] In this embodiment, both the first sub-bonding layer and the second sub-bonding layer are made of silicon oxide, thereby achieving silicon oxide-silicon oxide fusion bonding.

[0153] In this embodiment, a deposition process (e.g., chemical vapor deposition) is used to form the first sub-bonded layer and the second sub-bonded layer.

[0154] In this embodiment, a channel material layer 605 is also formed on the surface of the second substrate 610 facing away from the bonding surface 601. The channel material layer 605 is used to form a second channel layer structure.

[0155] In this embodiment, the second device subsequently formed is a PMOS device; therefore, the channel material layer 605 is made of germanium or silicon germanide. In other embodiments, when the second device is an NMOS device, the channel material layer can be made of silicon.

[0156] Specifically, one or more stacked channel material layers (not shown) are formed on the second substrate 610, each channel material layer including a sacrificial material layer (not shown) and a channel material layer 605 located on the sacrificial material layer. As an example, the number of channel material layers is one.

[0157] The sacrificial material layer is used to form the second sacrificial layer, and the channel material layer 605 is used to form the second channel layer.

[0158] Therefore, in the actual formation process, a sacrificial material layer is also formed between the second substrate 610 and the channel material layer 605. It should be noted that the sacrificial material layer is not shown in FIG10 in this embodiment.

[0159] In this embodiment, the channel material layer 605 is made of germanium or silicon germanide, and the sacrificial material layer is made of silicon. The etching selectivity between the sacrificial material layer and the channel material layer 605 is high, thereby reducing damage to the second channel layer caused by subsequent processes removing the second sacrificial layer. In other embodiments, when the channel material layer is made of silicon, the sacrificial layer is made of SiGe.

[0160] It should also be noted that a fin material layer (not shown) is also formed on the surface of the second substrate 610, which is used to form the second fin. As an example, the second substrate 610 and the fin material layer are an integral structure.

[0161] In other embodiments, when the formed second device is a fin field-effect transistor, the channel material layer is the fin material layer, which is formed directly on the second substrate. Specifically, the fin material layer and the second substrate can be an integral structure.

[0162] In addition, in this embodiment, the forming method further includes: thinning the second substrate 610.

[0163] The second substrate 610 is provided by a bare wafer, which is typically quite thick. Therefore, by thinning the second substrate 610, the final thickness of the second substrate 610 can meet the performance requirements of the second device. For example, this improves the heat dissipation of the device, facilitates subsequent packaging processes, and reduces the overall thickness of the packaged structure.

[0164] The thinning process can be performed before the second substrate 610 is bonded to the front side 401 of the first device structure 400, or it can be performed after the second substrate 610 is bonded to the front side 401 of the first device structure 400.

[0165] As an example, after the second substrate 610 is bonded to the front surface 401 of the first device structure 400, the side of the second substrate 610 facing away from the bonding surface 601 is thinned.

[0166] In this embodiment, the second substrate 610 and the fin material layer are an integral structure, and the fin material layer has a preset thickness. Correspondingly, the top surface of the fin material layer is thinned. After the thinning process, the thickness of the fin material layer reaches the preset thickness, and the thickness of the second substrate 610 also meets the process requirements.

[0167] Specifically, the thinning process can be carried out by grinding.

[0168] In other embodiments, neutral dopant ions (such as one or both of oxygen and nitrogen ions) may be used to form stop regions within the bare wafer, thereby defining the stop positions for the thinning process.

[0169] In other embodiments, when the second substrate is a silicon-on-insulator substrate or a germanium-on-insulator substrate, the bonding surface of the second substrate may be thinned before bonding the second substrate to the surface of the first device structure, and the thinning process may be stopped at the bottom of the insulating layer.

[0170] Referring to Figure 10, which is a top view, after a second substrate 610 (as shown in Figure 9) is disposed on the front side 401 (as shown in Figure 9) of the first device structure 400 (as shown in Figure 9), a second channel layer structure 620 is formed on the second substrate 610. The projections of the second channel layer structure 620 and the first channel layer structure 420 on the first substrate 410 do not intersect perpendicularly.

[0171] The outline of the first channel layer structure 420 is represented by a dashed box, and for ease of illustration, only the first channel layer structure 420, the second channel layer structure 620, and the second substrate 610 are shown.

[0172] The second channel layer structure 620 is used to provide a channel for the second device.

[0173] In this embodiment, the second channel layer structure 620 and the second substrate 610 are spaced apart.

[0174] Specifically, the steps for forming the second channel layer structure 620 include: patterning the channel material stack, patterning the sacrificial material layer as a second sacrificial layer (not shown), and patterning the channel material layer 605 as a second channel layer 625. Therefore, after patterning the channel material stack, one or more stacked second channel layers are formed, each second channel stack including a second sacrificial layer (not shown) and a second channel layer 625 located on the second sacrificial layer.

[0175] In this embodiment, along the surface normal direction of the second substrate 610, there is one channel material stack and one second channel stack. Therefore, the second channel layer 625 is the second channel layer structure 620.

[0176] In other embodiments, when there are multiple channel material stacks along the surface normal direction of the second substrate, the number of second channel stacks is correspondingly multiple, and the second channel layer structure correspondingly includes multiple second channel layers spaced apart along the surface normal direction of the second substrate. Adjacent second channel layers are isolated by a second sacrificial layer.

[0177] In this embodiment, during the process of patterning the channel material stacking, a fin material layer is also patterned to form a second fin (not shown) located between the top of the second substrate 610 and the bottom of the second channel layer structure 620. Correspondingly, the second channel layer structure 620 and the second fin are spaced apart.

[0178] It should be noted that the second fin is located below the second channel layer structure 620, therefore, the second fin is not shown in Figure 10.

[0179] In other embodiments, when the formed second device is a fin field-effect transistor, the channel material layer is a fin material layer, and the second channel layer structure is correspondingly a second fin protruding from the second substrate.

[0180] It should be noted that after forming the second channel layer structure 620, the forming method further includes: forming a second isolation layer (not shown) on the second substrate 610 exposed by the second channel layer structure 620. In this embodiment, the top of the second isolation layer is flush with the top of the second fin.

[0181] It should be noted that the second isolation layer is not shown in Figure 10.

[0182] In this embodiment, the projections of the second channel layer structure 620 and the first channel layer structure 420 onto the first substrate 410 are not perpendicular to each other.

[0183] A second device gate structure is subsequently formed across the second channel layer structure 620, and second source / drain doped regions are formed within the second channel layer structure 620 on both sides of the second device gate structure. The orthogonal second device gate structure and second channel layer structure 620, as well as the second source / drain doped regions located on both sides of the second device gate structure, constitute a second device. The second device and the second substrate constitute the second device structure. Since the projections of the first device gate structure 430 and the first channel layer structure 420 onto the first substrate 410 are orthogonal, the projections of the second device gate structure and the second channel layer structure 620 onto the second substrate 610 are also orthogonal. This results in the projections of the second device gate structure and the first device gate structure 430 onto the first substrate 410 not intersecting perpendicularly. Therefore, the probability of the second device completely obscuring the first device 450 is low, which facilitates the extraction of the electrical properties of the first device 450.

[0184] Specifically, the projections of the second channel layer structure 620 and the first channel layer structure 420 onto the first substrate 410 are not perpendicularly intersecting, such that the projection of the second channel layer structure 620 onto the first substrate 410 can expose part of the projection of the first channel layer structure 420 onto the first substrate 410.

[0185] Accordingly, when forming the source / drain plug that electrically connects to the first source / drain doped region 440, the source / drain plug can be formed in the exposed area of ​​the second device and penetrate the second device structure and the first interlayer dielectric layer 460 above the top of the first source / drain doped region 440. Similarly, when forming the gate plug connected to the top of the first device gate structure 430, the gate plug can also be disposed in the exposed area of ​​the second device and penetrate the second device structure above the top of the first device gate structure 430.

[0186] It should be noted that if the angle between the projections of the second channel layer structure 620 and the first channel layer structure 420 onto the first substrate 410 is too large or too small, it will easily increase the area of ​​the second device blocking the first device 450, thereby increasing the difficulty of bringing out the electrical components of the first device 450. Therefore, in this embodiment, the angle between the projections of the second channel layer structure 620 and the first channel layer structure 420 onto the first substrate 410 is between 5 degrees and 85 degrees.

[0187] As an example, the included angle is 45 degrees, thereby minimizing the area of ​​the second device blocking the first device 450, and providing sufficient process window for forming the source / drain plug connected to the first source / drain doped region 440 and the gate plug connected to the gate structure 430 of the first device.

[0188] In this embodiment, there are multiple second channel layer structures 620 in a direction parallel to the surface of the second substrate 610, and the multiple second channel layer structures 620 are arranged in parallel, with a second pitch P2 between adjacent second channel layer structures 620. The second pitch P2 is the sum of the linewidth of the second channel layer structure 620 and the spacing between adjacent second channel layer structures 620.

[0189] In this embodiment, the second pitch P2 and the first pitch P1 are not equal. By making the second pitch P2 and the first pitch P1 not equal, the occlusion area of ​​the second device on the first device 450 is further reduced.

[0190] It should be noted that the absolute value of the difference between the second pitch P2 and the first pitch P1 should not be too small or too large. If the absolute value of the difference is too small, the second pitch P2 and the first pitch P1 will be too close, which may increase the area of ​​the second device blocking the first device 450, or even lead to the second device completely blocking the first device 450, thereby increasing the difficulty of the process of bringing out the electrical properties of the first device 450. If the absolute value of the difference is too large, the second pitch P2 or the first pitch P1 may be too large, resulting in an excessively large overall area of ​​the semiconductor structure. Moreover, increasing the pitch will correspondingly increase the volume of the epitaxial layer corresponding to the source and drain doped regions. Correspondingly, if the absolute value of the difference is too large, the volume difference between the first source and drain doped region 440 and the epitaxial layer corresponding to the second source and drain doped region may be too large, which may lead to a mismatch in the performance of the first device 450 and the second device. Therefore, in this embodiment, the absolute value of the difference between the second pitch P2 and the first pitch P1 is 1 nanometer to 5 nanometers.

[0191] Referring to Figures 11 to 14, a second device gate structure 630 and a second source / drain doped region 640 are formed on a second substrate 610. The second device gate structure 630 spans a second channel layer structure 620, and the second source / drain doped regions 640 are located within the second channel layer structures 620 on both sides of the second device gate structure 630. The second source / drain doped regions 640, the second device gate structure 630, and the second channel layer structure 620 are used to form a second device 650. The second device 650 and the second substrate 610 are used to constitute a second device structure 600.

[0192] Figure 11 is a perspective view, Figure 12 is a top view of Figure 11, Figure 13 is a cross-sectional view of Figure 11 at the exposed position of the second device 600 along the extension direction of the first channel layer structure 425, and Figure 14 is a cross-sectional view of the second device structure 600 in Figure 11 along the extension direction of the second channel layer structure 625. Furthermore, to illustrate the relative positional relationship between the first device 450 and the second device 650, Figure 12 only shows the first channel layer structure 420, the first device gate structure 430, the second channel layer structure 620, and the second device gate structure 630.

[0193] The orthogonal second device gate structure 630 and second channel layer structure 620, and the second source / drain doped regions 640 located on both sides of the second device gate structure 630 are used to form a second device 650.

[0194] A second device 650 is formed by forming a second device gate structure 630 and a second source / drain doped region 640 on a second substrate 610, thereby forming a second device 650 stacked above the first device 450. Specifically, the second device gate structure 630 is formed on a second isolation layer 412.

[0195] The second device gate structure 630 is used to control the opening and closing of the channel of the second device 650.

[0196] In this embodiment, the second device gate structure 630 is a metal gate structure. Accordingly, the second device gate structure 630 includes a second high-k gate dielectric layer (not shown), a second work function layer (not shown) located on the second high-k gate dielectric layer, and a second gate electrode layer (not shown) located on the second work function layer. For a detailed description of the second high-k gate dielectric layer and the second gate electrode layer, please refer to the foregoing descriptions of the first high-k gate dielectric layer and the first gate electrode layer, respectively; these will not be repeated here.

[0197] The second work function layer is used to adjust the threshold voltage of the second device 650. In this embodiment, the second device 650 is a PMOS device, and the second work function layer is correspondingly a P-type work function layer. The material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN. In this embodiment, the second source / drain doped region 640 includes a second epitaxial layer doped with type II ions. Specifically, the second device 650 is a PMOS device; therefore, the material of the second epitaxial layer is Si or SiGe, and the type II ions are P-type ions, including B ions, Ga ions, or In ions.

[0198] In this embodiment, the method for forming the semiconductor structure further includes: forming a second interlayer dielectric layer 660 on a second substrate 610, wherein the second interlayer dielectric layer 660 is located on the second substrate 610 on the side of the second device gate structure 630 and covers the sidewall of the second device gate structure 630, and the second interlayer dielectric layer 660, the second device 650 and the second substrate 610 are used to constitute the second device structure 600.

[0199] The second interlayer dielectric layer 660 is used to isolate the adjacent second device 650. In this embodiment, the top of the second interlayer dielectric layer 660 and the gate structure 630 of the second device are flush. For a detailed description of the second interlayer dielectric layer 660, please refer to the corresponding description of the first interlayer dielectric layer 460 above, which will not be repeated here.

[0200] In this embodiment, the second device gate structure 630 is formed by forming a high-k gate dielectric layer and then forming a gate electrode layer. Therefore, before the second device gate structure 630 is formed, the position of the second device gate structure 630 is occupied by the second pseudo-gate structure.

[0201] Specifically, the steps of forming the second device structure 600 include: after forming the second channel stack, forming a second dummy gate structure spanning the second channel stack, the second dummy gate structure covering part of the top and part of the sidewalls of the second channel stack; forming second source / drain doped regions 640 in the second channel stack on both sides of the second dummy gate structure; forming a second interlayer dielectric layer 660 on the second substrate 610 on the side of the second dummy gate structure, the second interlayer dielectric layer 660 covering the second source / drain doped regions 640; removing the second dummy gate structure to form a second gate opening (not shown) in the second interlayer dielectric layer 660; removing the second sacrificial layer exposed by the second gate opening to form a second trench (not shown) connected to the second gate opening; forming a second device gate structure 630 in the second gate opening and the second trench, the second device gate structure 630 surrounding the second channel layer 425.

[0202] Therefore, in this embodiment, the bottommost second channel layer 425 and the second fin 411 are spaced apart.

[0203] In this embodiment, a second sidewall (not shown) is also formed on the sidewall of the second device gate structure 430, and a second inner sidewall is also formed between the second device gate structure 430 and the second source / drain doped region 640 located below the second channel layer 625.

[0204] It should be noted that for a detailed description of the second source / drain doped region 640, the second sidewall, and the second inner sidewall and their formation methods, please refer to the aforementioned descriptions of the first source / drain doped region 440, the first sidewall, and the first inner sidewall, respectively, and will not be repeated here.

[0205] Referring to FIG15, which is a cross-sectional view based on FIG13, after forming the second device structure 600, the forming method further includes: forming a top source / drain plug 520 that penetrates the second interlayer dielectric layer 660 and the second substrate 610 above the first source / drain doped region 440. The top source / drain plug 520 is connected to the bottom source / drain plug 510, and the top source / drain plug 520 and the bottom source / drain plug 510 are used to form the first source / drain plug 530.

[0206] The top source / drain plug 520 is electrically connected to the first source / drain doped region 440 through the bottom source / drain plug 510. Therefore, the first source / drain plug 530 is used to bring out the electrical properties of the first source / drain doped region 440.

[0207] In this embodiment, the top of the top source / drain plug 520 is flush with the top of the second interlayer dielectric layer 660, and the material of the top source / drain plug 520 is copper. Specifically, the top source / drain plug 520 is formed through etching, deposition, and planarization processes. The formation method of the top source / drain plug 520 is similar to the formation method of the bottom source / drain plug 510, and will not be described again in this embodiment.

[0208] Referring to Figure 16, which is a cross-sectional view based on Figure 14, after forming the second device structure 600, the forming method further includes: forming a second source / drain plug 540 that penetrates the second interlayer dielectric layer 660 above the second source / drain doped region 640, and the second source / drain plug 540 is connected to the second source / drain doped region 640.

[0209] The second source / drain plug 540 is used to bring out the electrical properties of the second source / drain doped region 640.

[0210] In this embodiment, the top of the second source / drain plug 540 is flush with the top of the second interlayer dielectric layer 660, and the material of the second source / drain plug 540 is copper. Specifically, the second source / drain plug 540 is formed through etching, deposition, and planarization processes. The formation method of the second source / drain plug 540 is similar to the formation method of the bottom source / drain plug 510, and will not be described again in this embodiment.

[0211] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: A first device structure includes a first substrate and a first device formed on the first substrate. The first device includes a first channel layer structure on the first substrate, a first device gate structure spanning the first channel layer structure, and a first source / drain doped region within the first channel layer structure located on both sides of the first device gate structure. The surface of the first device structure closest to the top of the first device gate structure is the front side. The second device structure located on the front side of the first device structure includes a second substrate on the first device structure and a second device formed on the second substrate. The second device includes a second channel layer structure on the second substrate, a second device gate structure spanning the second channel layer structure, and second source / drain doped regions within the second channel layer structure located on both sides of the second device gate structure. The projections of the second channel layer structure and the first channel layer structure onto the first substrate are not perpendicular to each other.

2. The semiconductor structure as described in claim 1, characterized in that, The angle between the projections of the second channel layer structure and the first channel layer structure onto the first substrate is 5 to 85 degrees.

3. The semiconductor structure as described in claim 2, characterized in that, The angle between the projections of the second channel layer structure and the first channel layer structure onto the first substrate is 45 degrees.

4. The semiconductor structure as described in claim 1, characterized in that, In the first device structure, there are multiple first channel layer structures, and the multiple first channel layer structures are arranged in parallel, with a first pitch between adjacent first channel layer structures; in the second device structure, there are multiple second channel layer structures, and the multiple second channel layer structures are arranged in parallel, with a second pitch between adjacent second channel layer structures, and the second pitch is not equal to the first pitch.

5. The semiconductor structure as described in claim 4, characterized in that, The absolute value of the difference between the second pitch and the first pitch is 1 nanometer to 5 nanometers.

6. The semiconductor structure as described in claim 1, characterized in that, The first device structure further includes: a first interlayer dielectric layer located on the first substrate at the side of the gate structure of the first device, the first interlayer dielectric layer covering the sidewall of the gate structure of the first device; the semiconductor structure further includes: a bottom source / drain plug penetrating the first interlayer dielectric layer above the first source / drain doped region and connected to the first source / drain doped region.

7. The semiconductor structure as described in claim 6, characterized in that, The second device structure further includes: a second interlayer dielectric layer located on a second substrate on the side of the gate structure of the second device, the second interlayer dielectric layer covering the sidewall of the gate structure of the second device; the semiconductor structure further includes: a top source / drain plug penetrating the second interlayer dielectric layer and the second substrate above the first source / drain doped region, and connected to the bottom source / drain plug.

8. The semiconductor structure as described in claim 1, characterized in that, The second device structure is bonded to the front side of the first device structure.

9. The semiconductor structure as described in claim 8, characterized in that, The semiconductor structure further includes a bonding layer located between the front side of the first device structure and the second substrate.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, The bonding layer is made of silicon oxide.

11. The semiconductor structure as claimed in claim 1, characterized in that, The first channel layer structure is a first fin protruding from the first substrate; or, the first channel layer structure is spaced apart from the first substrate, and the first channel layer structure includes one or more first channel layers spaced apart in the normal direction of the surface of the first substrate; the second channel layer structure is a second fin protruding from the second substrate; or, the second channel layer structure is spaced apart from the second substrate, and the second channel layer structure includes one or more second channel layers spaced apart in the normal direction of the surface of the second substrate.

12. The semiconductor structure as claimed in claim 1, characterized in that, The first device is an NMOS device and the second device is a PMOS device; or, the first device is a PMOS device and the second device is an NMOS device.

13. A method for forming a semiconductor structure, characterized in that, include: A first device structure is formed, including a first substrate and a first device formed on the first substrate. The first device includes a first channel layer structure on the first substrate, a first device gate structure spanning the first channel layer structure, and first source / drain doped regions within the first channel layer structure located on both sides of the first device gate structure. The surface of the first device structure closest to the top of the first device gate structure is the front side. A second substrate is disposed on the front side of the first device structure. After the second substrate is disposed on the front side of the first device structure, a second channel layer structure is formed on the second substrate. The projections of the second channel layer structure and the first channel layer structure onto the first substrate are not perpendicularly intersecting. A second device gate structure and a second source / drain doped region are formed on the second substrate. The second device gate structure spans the second channel layer structure. The second source / drain doped region is located in the second channel layer structure on both sides of the second device gate structure. The second source / drain doped region, the second device gate structure, and the second channel layer structure are used to form a second device. The second device and the second substrate are used to constitute a second device structure.

14. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of forming the second channel layer structure on the second substrate, the angle between the projections of the second channel layer structure and the first channel layer structure onto the first substrate is 5 degrees to 85 degrees.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, The angle between the projections of the second channel layer structure and the first channel layer structure onto the first substrate is 45 degrees.

16. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of forming the first device structure, there are multiple first channel layer structures, and the multiple first channel layer structures are arranged in parallel, with a first pitch between adjacent first channel layer structures; in the step of forming the second channel layer structure on the second substrate, there are multiple second channel layer structures, and the multiple second channel layer structures are arranged in parallel, with a second pitch between adjacent second channel layer structures, and the second pitch is not equal to the first pitch.

17. The method for forming a semiconductor structure as described in claim 16, characterized in that, The absolute value of the difference between the second pitch and the first pitch is 1 nanometer to 5 nanometers.

18. The method for forming a semiconductor structure as described in claim 13, characterized in that, In the step of forming the first device structure, the first device structure further includes: a first interlayer dielectric layer located on the first substrate at the side of the first device gate structure, the first interlayer dielectric layer covering the sidewall of the first device gate structure; before bonding the second substrate to the front side of the first device structure, the method of forming the semiconductor structure further includes: forming a bottom source / drain plug through the first interlayer dielectric layer above the first source / drain doped region, the bottom source / drain plug being connected to the first source / drain doped region.

19. The method for forming a semiconductor structure as described in claim 18, characterized in that, The method for forming the semiconductor structure further includes: forming a second interlayer dielectric layer on the second substrate, the second interlayer dielectric layer being located on the second substrate at the side of the gate structure of the second device and covering the sidewall of the gate structure of the second device, the second interlayer dielectric layer, the second device, and the second substrate being used to constitute the second device structure; after forming the second device structure, the method further includes: forming a top source / drain plug penetrating the second interlayer dielectric layer and the second substrate above the first source / drain doped region, the top source / drain plug being connected to the bottom source / drain plug.

20. The method for forming a semiconductor structure as described in claim 13, characterized in that, The step of disposing a second substrate on the front side of the first device structure includes: providing a second substrate; and bonding the second substrate to the front side of the first device structure.

21. The method for forming a semiconductor structure as described in claim 20, characterized in that, Before forming the second channel layer structure on the second substrate, the forming method further includes: thinning the second substrate.

22. The method for forming a semiconductor structure as described in claim 20, characterized in that, The second substrate is bonded to the front side of the first device structure using a bonding layer.

23. The method for forming a semiconductor structure as described in claim 13, characterized in that, The first channel layer structure is a first fin protruding from the first substrate; or, the first channel layer structure is spaced apart from the first substrate, and the first channel layer structure includes one or more first channel layers spaced apart in the normal direction of the surface of the first substrate; the second channel layer structure is a second fin protruding from the second substrate; or, the second channel layer structure is spaced apart from the second substrate, and the second channel layer structure includes one or more second channel layers spaced apart in the normal direction of the surface of the second substrate.

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