Arithmetic processing program and arithmetic processing method

Abstract

To speed up parallel operations of a sparse matrix.SOLUTION: A processor is configured to set, in a mask register used for a mask operation, to each of a plurality of mask bits that indicates a bit corresponding to each element of each row of a sparse matrix, each mask pattern for designating the mask operation. The processor is configured to expand the plurality of mask bits to which the respective mask patterns are set to different areas of a physical register, respectively.SELECTED DRAWING: Figure 1

Description

Technical Field

[0005] ,

[0001] The present invention relates to an arithmetic processing program and an arithmetic processing method.

Background Art

[0002] As a technique for quickly calculating a sparse matrix, SIMD (Single Instruction Multiple Data), which calculates multiple rows at once, is used. When parallelizing by SIMD, when the number of elements is different for each row, parallelization is achieved by using a masking technique.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, in the above technique, since it is necessary to prepare in advance the mask patterns that may occur, a large number of logical registers are used for creating mask patterns, and there is a risk that the logical registers will run out. Although there is also a technique for eliminating the exhaustion of logical registers by assigning physical registers to register numbers using a renamer, when using a renamer, a dependency occurs and the processing speed decreases.

[0005] One objective is to provide a computation program and method that can speed up parallel computation of sparse matrices. [Means for solving the problem]

[0006] In the first proposal, the arithmetic processing program is characterized by causing the computer to perform the following processing: setting a mask pattern that specifies the mask operation for each of the multiple mask bits in the mask register used for the mask operation, each of which represents a bit corresponding to each element of each row of the sparse matrix; and expanding each of the multiple mask bits on which each mask pattern is set into a different area of ​​the physical register. [Effects of the Invention]

[0007] According to one embodiment, parallel processing of sparse matrices can be accelerated. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a functional block diagram showing the functional configuration of the processor of the information processing device according to Embodiment 1. [Figure 2] Figure 2 illustrates the parallel operation of sparse matrices in Example 1. [Figure 3] Figure 3 is a diagram illustrating the mask operation. [Figure 4] Figure 4 is a diagram illustrating the element mask of RISC-V. [Figure 5] Figure 5 illustrates the problems caused by replacing the mask pattern. [Figure 6] Figure 6 illustrates the generation of a mask pattern by right shifting. [Figure 7] Figure 7 illustrates the development of dependencies. [Figure 8] Figure 8 is a diagram illustrating the renaming process. [Figure 9] Figure 9 illustrates an example of resolving dependencies through renaming. [Figure 10]FIG. 10 is a diagram for explaining the renaming process in Example 1. [Figure 11] FIG. 11 is a diagram for explaining the effect according to Example 1. [Figure 12] FIG. 12 is a flowchart for explaining the flow of the renaming process in Example 1. [Figure 13] FIG. 13 is a flowchart for explaining the flow of the release process in Example 1. [Figure 14] FIG. 14 is a diagram for explaining the release determination in the release process. [Figure 15] FIG. 15 is a diagram for explaining an example of the hardware configuration.

Embodiments for Carrying Out the Invention

[0009] Hereinafter, embodiments of the arithmetic processing program and the arithmetic processing method disclosed in the present application will be described in detail based on the drawings. Note that the invention is not limited by this embodiment. Also, each embodiment can be appropriately combined within a non - contradictory range.

Example

[0010] (Description of the Information Processing Apparatus) FIG. 1 is a functional block diagram showing the functional configuration of the processor 10d of the information processing apparatus according to Example 1. The information processing apparatus 10 shown in FIG. 1 is an example of an information processing apparatus such as a computer or a server. The processor 10d of the information processing apparatus speeds up the solution process of a system of linear equations of a sparse matrix (especially a large - scale sparse matrix) by parallelization using SIMD. At that time, the processor 10d changes the processing of the renamer while utilizing the characteristics of the RISC (Reduced Instruction Set Computer) - V mask to eliminate the dependency relationship during parallel execution.

[0011] As shown in FIG. 1, the processor 10d has an instruction processing unit 11, a renamer 12, a sending unit 13, an instruction window 14, an arithmetic circuit 15, and a register file 16.

[0012] It should be noted that there is an error in the original text where the line number "二十七" is used. It is likely a mislabeling. This translation assumes it is a mislabeling and continues with the translation process. If this is not the case, please correct the original text for a more accurate translation. The instruction processing unit 11 is a processing unit that executes an instruction pipeline that divides the execution of one instruction into multiple stages and executes multiple instructions in a pipelined manner. For example, the instruction processing unit 11 executes functions such as a FETCHER that reads an instruction from memory and a DECODER that interprets the read instruction.

[0013] The renamer 12 is a processing unit that performs renaming of the register numbers of the mask registers that hold mask patterns when executing the mask processing of RISC-V. The renamer 12 has a free list 12a, a RMT (Register Map Table) 12b, and a renamer control unit 12c.

[0014] The free list 12a is a database that stores unused register numbers. For example, the register numbers of the freed physical registers are registered in the free list 12a. Since the free list 12a is managed as a FIFO (First In First Out), the freed register numbers are added to the end of the list, and when allocating, an available physical register is taken out from the top of the list.

[0015] The RMT 12b is a table that represents the mapping between logical registers and physical registers. The RMT 12b has entries for the number of logical registers, and one entry corresponds to one logical register. In each entry, the register number of the physical register currently allocated to that logical register is recorded. The register number of the physical register taken out from the free list 12a is registered in the RMT 12b, and when an instruction is committed, the release of the previously allocated physical register is executed.

[0016] The renamer control unit 12c is a processing unit that performs the renaming process when executing the mask processing of SIMD type operations. The details of the renaming process by the renamer control unit 12c will be described later, but to briefly explain, for example, the renamer control unit 12c sets a mask pattern that specifies the mask operation for each of the multiple mask bits that represent the bits corresponding to each element of each row of the sparse matrix in the mask register used for the mask operation. The renamer control unit 12c expands each of the multiple mask bits to which each mask pattern is set into a different area (register number) of the physical register.

[0017] Furthermore, when the renamer control unit 12c computes (operates) each element in each row of the sparse matrix in parallel, it identifies the mask bits to be stored in the area of ​​the physical register corresponding to each element. As a result, the processor 10d performs the mask operation according to the mask pattern set in the identified mask bits.

[0018] Here, we will briefly explain the terminology used in Example 1. Mask bits indicate the corresponding bits of each element in the mask register. Mask patterns indicate the patterns to be set for the corresponding bits, such as {1,0,1,1} or {0,0,1,1}. The mask register is represented as "v0", and the mask bits correspond to the 0th bit of element #0, the 1st bit of element #1, etc. of v0.

[0019] The dispatch unit 13 is a processing unit that executes commands in a waiting state, and for example, it has the function of a DISPATCHER. For example, the dispatch unit 13 executes the command input by the command processing unit 11 after the renaming process by the renamer 12 has been executed.

[0020] The instruction window 14 is a processing unit that inputs instructions executed by the dispatch unit 13 to the arithmetic circuit 15. For example, the instruction window 14 monitors the processing status of the arithmetic circuit 15 and inputs instructions that are in a waiting state to the arithmetic circuit 15 at the appropriate timing.

[0021] The arithmetic circuit 15 is a processing unit that includes a circuit for executing instructions, and performs various operations such as addition and subtraction. The register file 16 is a type of high-speed storage that integrates registers, and is used for storing data when SIMD operations are executed.

[0022] (Explanation of prerequisite technologies) Next, we will describe each process performed by the processor 10d in Example 1. Figure 2 is a diagram illustrating the parallel operation of sparse matrices in Example 1. As shown in Figure 2, when the processor 10d performs a sparse matrix-vector multiplication (SpMV), which is an operation between each element (i) of sparse matrix A and each element (v) of vector x, it performs the operation on multiple rows of sparse matrix A at once.

[0023] For example, processor 10d executes the arithmetic expression "y += Av(col) × x(Ai(col))" in a loop on index "col". That is, processor 10d retrieves "Ai" at index "col" (stride load) and gathers it (x), retrieves "Av" at index "col" (stride load), performs Fma (Fused multiply add) on them and stores them in "y".

[0024] (Mask calculation) When processor 10d executes the arithmetic expression shown in Figure 2 in parallel using SIMD, it performs a mask operation because the number of elements differs from row to row in the sparse matrix A. Figure 3 illustrates the mask operation. As shown in Figure 3, when performing a 4-element parallel operation (parallel computation), from element 10 onwards, the number of elements becomes less than 4, and furthermore, the number of elements differs from row to row. In such cases, processor 10d performs a mask operation. For example, processor 10d uses a mask vector such as {0,1,1,1} and controls the execution of operations on elements that are set to "0" in the mask vector. In the example in Figure 3, processor 10d does not execute the calculation of z(0).

[0025] Here, we will explain the masking process in RISC-V. Figure 4 is a diagram illustrating element masking in RISC-V. As shown in Figure 4, processor 10d uses register 0 "v0", which is a vector register having 32 regions v0 to v31 separated by 64 bits, as the mask register. Then, processor 10d executes "vop.v v1,v2,v3,v0.t". Here, the mask bits to be used are stored in the region corresponding to each element in mask register v0. For example, the mask pattern for element 0 is set in bit 0 of the region of element #0 in mask register v0, the mask pattern for element 1 is set in bit 1 of the region of element #1 in mask register v0, and the mask pattern for element 2 is set in bit 2 of the region of element #2 in mask register v0.

[0026] In this state, processor 10d determines whether the "t-bit" of the t-th element of v0 is "0" or "1" for each element. If it is "0", it performs a mask operation; if it is "1", it performs a normal operation. Note that "vop" is a vector instruction operation, such as addition or subtraction.

[0027] However, the mask calculation described above requires changing the mask pattern as the calculation progresses, and furthermore, the code for creating the mask pattern must be executed in the innermost loop, which significantly slows down the calculation and degrades processing performance. For example, if the mask generation process is increased by 2 cycles within a 100,000-cycle loop, a performance degradation of 200,000 cycles occurs. In addition, since the mask pattern to be replaced as the calculation progresses must be prepared in advance and stored in a logical register, a large number of logical registers are used, and logical registers may be depleted.

[0028] (Implementation examples and problems) Next, we will explain an example of assembly code implementation. Figure 5 illustrates the problems caused by replacing the mask pattern. In Figure 5, each of the 16 lines columnThis is an example of an assembly code implementation that performs rename and mask operations on a sparse matrix with 8 elements. For example, in the assembly code of Figure 5, after a right shift "v0,v21,0" which initializes the mask, the processing content is defined within the innerLabel loop. For example, the stride load "v8,(a1),v11,v0" is an instruction that loads an index into v8, where v8 is a vector register to store the result, a1 is the starting address of the vector data, and v11 is index information indicating multiple addresses. Note that a stride load is a regular load, and a gather load is a random pattern load.

[0029] The assembly code in Figure 5 is explained in detail. Load the index into v8. Rus The first four elements are processed by a stride load (loading matrix values ​​into v9), a gather load (loading vector x into v10), and a sum-of-products operation (Fma). Then, the mask pattern is changed by a right shift, and the index is loaded into v12. Rus The operations on the bottom four elements are performed using a stride load, a stride load that loads the matrix values ​​into v13, a gather load that loads the vector x into v14, and Fma which performs a sum-of-products operation. After that, a right shift (v0, v22, t1) is performed to generate the mask for the next iteration, a subtraction (index -= 4) for the SIMD elements (Sub(t0, t0, 4)) is performed, and an add (t1, t1, 1) is performed to swap the mask patterns.

[0030] Logical register number v21 is a mask pattern for the top four elements (for example, {0x1FFF,0x7FFE,0x3FFC,0x1FF8}), and logical register number v22 is a mask pattern for the bottom four elements (for example, {0x0FFF,0x7FFE,0x1FFC,0x0FF8}).

[0031] In the left diagram of Figure 5, a right shift after processing the top four elements results in a swap of the mask patterns for the next iteration (from v21 to v22), requiring the mask patterns to be prepared in advance, which consumes a large number of logical registers.

[0032] On the other hand, the right-hand diagram in Figure 5 shows an example where the mask pattern is replaced with a single logical register. In this case, the mask pattern is not replaced, but right shifts are performed sequentially. As a result, the same logical register is used, creating a dependency where the shift result of v21 is used.

[0033] Figure 6 illustrates the generation of mask patterns by right shift. As shown in Figure 6, the processor 10d stores the mask pattern for right shift in each bit of each element of the mask register v0, instead of the method described in Figure 4, so that when a right 1-bit shift is performed, the mask pattern to be used is placed in the bit position to be used. For example, bit 0 of element #0 of the mask register v0 is set to the "first mask pattern to be used", bit 1 to the "second mask pattern to be used", bit 2 to the "third mask pattern to be used", and bit 3 to the "fourth mask pattern to be used". Also, bit 1 of element #1 of the mask register v0 is set to the "first mask pattern to be used", bit 2 to the "second mask pattern to be used", bit 3 to the "third mask pattern to be used", and bit 4 to the "fourth mask pattern to be used". Note that "first use" is synonymous with "use after a right 1-bit shift", and "second use" is synonymous with "use after a right 2-bit shift".

[0034] However, this method introduces dependencies during the execution of right shifts. Figure 7 illustrates the occurrence of these dependencies. In Figure 7, the timing of the execution of each instruction is represented by "Ex". As shown in Figure 7, dependencies arise because the "logical register number v21" is shared during right shifts. This results in right shifts being executed sequentially, leading to slower processing.

[0035] (Rename process) In the method described above, processing slows down due to the dependency of the right shift. To resolve this dependency, the processor 10d applies the rename operation by the renamer 12 to the mask register.

[0036] Figure 8 illustrates the renaming process. As shown in Figure 8, the processor 10d executes a renaming process to resolve dependencies by reassigning the program register number x# to the physical register number p#, in order to utilize the physical registers, which have several times the capacity of logical registers.

[0037] In the example in Figure 8, processor 10d identifies an available physical register number in the free list 12a and registers it in RMT12b to convert the operations "I1:mul p20←p12×4", "I2:add x3←x1+1", "I3:sub x1←x5-1", and "I4:and x6←x7&1" into "I1:mul p20←p12×4", "I2:add p23←p11+1", "I3:sub p22←p15-1", and "I4:and p23←p17&1". The right-hand diagram in Figure 8 is an example of registration from the free list 12a to RMT12b and renaming of operations, showing, for example, that p23 in the free list 12a is registered in RMT12b and x3 in I2 is renamed to p23.

[0038] In other words, processor 10d renames the 3 logical register numbers x3 that are dependent on I1 and I2 to physical register numbers p20 and p23, and the 1 logical register number x1 that is dependent on I2 and I3 to physical register numbers p11 and p24, thereby resolving the right-shift dependency and executing I1 to I4 in parallel.

[0039] Figure 9 illustrates an example of resolving dependencies through renaming. Similar to Figure 5, Figure 9 uses 16 rows to show each dependency. columnThis will be explained with an example of assembly code implementation that performs rename and mask operations on a sparse matrix with 8 elements.

[0040] As shown in Figure 9, the processor 10d renames the logical register numbers in the right shifts within the loop after the initial mask right shift performed outside the loop using the renamer 12, etc. For example, the processor 10d renames the logical register number v0 in the first right shift within the loop to the physical register number pv0, and renames the logical register number v0 in the second right shift within the loop to the physical register number pv1, and then performs the operation. As a result, the processor 10d can perform the two right shifts in parallel by rewriting the logical register numbers.

[0041] However, while this renaming process can resolve the right-shift dependency, it still uses a large number of logical registers, making it highly likely that logical registers will be depleted.

[0042] Therefore, in Example 1, the processing by the renamer 12 is improved to achieve both the elimination of the right shift dependency and the reduction of logical register usage. Specifically, the processor 10d decomposes the mask register bit by bit using the renamer 12 and assigns each bit to a separate physical register.

[0043] (Improvements to the renaming process) Figure 10 illustrates the renaming process in Embodiment 1. As shown in Figure 10, the processor 10d sets a mask pattern for each of the multiple mask bits in the mask register used for the mask operation, each of which represents a bit corresponding to each element in each row of the sparse matrix. The processor 10d expands each of the multiple mask bits on which each mask pattern is set into a different area (register number) of the physical register.

[0044] Subsequently, when the processor 10d performs operations on each element of each row of the sparse matrix in parallel, it identifies the mask bits to be stored in the area of ​​the physical register corresponding to each element. The processor 10d then performs the mask operation according to the mask pattern set on the identified mask bits.

[0045] Specifically, as shown in Figure 10, the processor 10d sets the mask pattern in the mask bits of the area corresponding to each element of the mask register v0, similar to Figure 6. For example, the processor 10d sets the "first mask pattern to use" in bit 0 of the area for element #0 of the logical register mask register v0, the "second mask pattern to use" in bit 1, the "third mask pattern to use" in bit 2, and the "fourth mask pattern to use" in bit 3.

[0046] Furthermore, processor 10d provides physical registers pv0, pv1, pv2, pv3, and pv4, and associates the positions of the mask bits (0, 1, 2, 3) with each physical register.

[0047] Then, processor 10d places mask bit 0 of element #0 of mask register v0 into mask bit 0 of element #0 of physical register pv0, and places mask bit 1 of element #0 of mask register v0 into mask bit 0 of element #0 of physical register pv1. Processor 10d then places mask bit 2 of element #0 of mask register v0 into mask bit 0 of element #0 of physical register pv2, and places mask bit 3 of element #0 of mask register v0 into mask bit 0 of element #0 of physical register pv3.

[0048] Similarly, processor 10d expands mask bit 1 of element #1 of mask register v0 into mask bit 1 of element #1 of physical register pv0, and expands mask bit 2 of element #1 of mask register v0 into mask bit 1 of element #1 of physical register pv1. Processor 10d expands mask bit 3 of element #1 of mask register v0 into mask bit 1 of element #1 of physical register pv2, and expands mask bit 4 for element #1 of mask register v0 into mask bit 1 of element #1 of physical register pv3.

[0049] Similarly, processor 10d expands mask bit 2 of element #2 of mask register v0 into mask bit 2 of element #2 of physical register pv0, and expands mask bit 3 of element #2 of mask register v0 into mask bit 2 of element #2 of physical register pv1. Processor 10d expands mask bit 4 of element #2 of mask register v0 into mask bit 2 of element #2 of physical register pv2, and expands mask bit 5 of element #2 of mask register v0 into mask bit 2 of element #2 of physical register pv3.

[0050] Similarly, processor 10d expands the mask bit 3 of element #3 of mask register v0 into the mask bit 3 of element #3 of physical register pv0, and expands the mask bit 4 of element #3 of mask register v0 into the mask bit 3 of element #3 of physical register pv1. Processor 10d expands the mask bit 5 of element #3 of mask register v0 into the mask bit 3 of element #3 of physical register pv2, and expands the mask bit 6 of element #3 of mask register v0 into the mask bit 3 of element #3 of physical register pv3.

[0051] In other words, if the referenced mask bit is bit 0, the processor 10d performs mask processing using each mask pattern specified by each mask bit of pv0, and if the referenced mask bit is bit 1, it performs mask processing using each mask pattern specified by each mask bit of pv1. Similarly, if the referenced mask bit is bit 2, the processor 10d performs mask processing using each mask pattern specified by each mask bit of pv2, and if the referenced mask bit is bit 3, it performs mask processing using each mask pattern specified by each mask bit of pv3.

[0052] Furthermore, processor 10d associates the mask bit positions (0,1,2,3) in RMT12b and also in free list 12a. As a result, processor 10d can manage which physical register is used at which bit position, and can accurately revert to the logical register number when renaming.

[0053] Figure 11 illustrates the effects of Example 1. As shown in Figure 11, after the mask initialization right shift "v0,v21,0", processor 10d can allocate "pv20" as the mask register for the first operation, "pv21" for the next operation, and "pv22" for the next operation. As a result, processor 10d accesses different physical registers even when performing a right shift for each operation, thus eliminating the dependency of the right shift. Furthermore, processor 10d can also reduce the amount of logical registers used.

[0054] Note that the loop processing in the assembly code shown in Figure 11 involves updating addresses and loop counts, and uses a scalar pipeline different from vectors, so parallel execution is possible. For example, an example of address updating is "Add a1,a1,t2", "Add a2,a2,t2", "Add a3,a3,t2", "Add a4,a4,t2", "Add a5,a5,t2", "Add a6,a6,t2", etc. An example of updating the loop count is "Sub t0,t0,4", "Add t1,t1,1".

[0055] (Process flow) Figure 12 is a flowchart illustrating the rename process in Example 1. As shown in Figure 12, the processor 10d executes the rename process described in Figures 10 to 11, which adds bit position information, when this function is ON (S101: Yes), the program counter (PC) is within the set range (S102: Yes), and the logical register is the pre-specified v0 (S103: Yes) (S104). Subsequently, the processor 10d executes the improved rename process while performing arithmetic processing.

[0056] On the other hand, if this function is not ON (S101: No), the program counter PC is outside the set range (S102: No), or the logical register is not the pre-specified v0 (S103: No), the processor 10d performs the normal rename process described in Figures 8 and 9 (S105). After that, the processor 10d performs the normal rename process while also performing arithmetic processing.

[0057] In other words, the processor 10d allows the function according to Example 1 to be set ON or OFF, and the scope of application can be specified by the PC (program counter) so that it operates only within a specific loop. Furthermore, the processor 10d limits the register to be expanded to v0 only, and performs the aforementioned expansion and addition of bit position information only when the above conditions are met.

[0058] Figure 13 is a flowchart illustrating the deallocation process in Example 1. As shown in Figure 13, processor 10d deallocates the physical register used for the renamer if the physical register satisfies the deallocation conditions (S201: Yes), the logical register is v0 (S202: Yes), and all bits satisfy the deallocation conditions (S203: Yes) (S204). Subsequently, processor 10d terminates the deallocation process when it has finished deallocating all physical registers used for the renamer (S205: Yes), and if there are any undeallocated physical registers (S205: No), it repeats steps S201 onwards.

[0059] In other words, processor 10d releases the allocated physical register when it has finished its role as in normal technology. In Example 1, in addition to the normal release determination, processor 10d performs an additional determination as to whether the physical register to which the mask information is assigned satisfies the normal release conditions. For example, if the target for release is v0, processor 10d checks further because the renaming according to Example 1 may have been applied. Specifically, since the information of v0 is spread across multiple physical registers, processor 10d determines whether all of them can be released using the bit position information. If all physical registers associated with logical register v0 that have bit position information can be released, processor 10d releases them.

[0060] Figure 14 is a diagram illustrating the deallocation determination during the deallocation process. The upper part of Figure 14 shows RMT12b after the rename operation according to Example 1 has been performed, and the mask information of mask register v0 has been expanded into pv20 and pv21. Here, pv20 is the mask information shifted 0 bits to the right, and pv21 is the mask information shifted 1 bit to the right.

[0061] Subsequently, as shown in the lower diagram of Figure 14, if the mask information for pv20 has already been calculated and is available for release, but the mask information for pv21 has not yet been calculated, the processor 10d determines that it cannot be released. In other words, the processor 10d suppresses the release of these until the final mask calculation is performed.

[0062] (effect) As described above, processor 10d can perform parallel operations on sparse matrices using physical registers, which have a larger capacity than logical registers. When renaming a mask register used in mask operations, processor 10d can rename it to a physical register. When renaming to a physical register, processor 10d can distribute and expand each mask bit of the mask register across multiple physical registers. As a result, processor 10d can eliminate the dependency of right shifts associated with swapping mask patterns while suppressing the use of unnecessary logical registers, thus achieving both the elimination of the dependency of right shifts and a reduction in the amount of logical registers used.

[0063] Processor 10d releases the physical registers only after the use of each physical register used in the mask calculation is complete. This prevents physical registers from being released during the calculation, reducing the occurrence of calculation errors and unnecessary processing such as re-renaming. [Examples]

[0064] (Numerical values, etc.) The register numbers, mask patterns, mask bits, operations, loop processing, etc., used in the above embodiment are merely examples and can be changed as needed. Furthermore, the processing flow described in each flowchart can be modified as appropriate within a consistent range. Note that the processor 10d is, for example, a CPU (Central Processing Unit) or an MPU (Micro Processor Unit).

[0065] (system) Unless otherwise specified, the processing procedures, control procedures, specific names, and various data and parameters shown in the above documents and drawings may be changed at will.

[0066] Furthermore, the components of each illustrated device are functionally conceptual and do not necessarily need to be physically configured as shown. In other words, the specific forms of distribution and integration of each device are not limited to those shown. That is, all or part of them can be functionally or physically distributed and integrated in any unit according to various loads and usage conditions.

[0067] Furthermore, each processing function performed by each device may be implemented, in whole or in part, by a CPU and a program executed for analysis by that CPU, or by hardware using wired logic.

[0068] (Hardware) Figure 15 illustrates an example of a hardware configuration. As shown in Figure 15, the information processing device 10 includes a communication device 10a, an HDD (Hard Disk Drive) 10b, memory 10c, and a processor 10d. Furthermore, each component shown in Figure 15 is interconnected by a bus or the like.

[0069] The communication device 10a is a network interface card or the like, and communicates with other devices. The HDD 10b stores programs and databases that operate the functions shown in Figure 1.

[0070] The processor 10d operates a process that performs the functions described in Figure 1 by reading a program that performs the same processing as each processing unit shown in Figure 1 from the HDD 10b or the like and loading it into memory 10c. For example, this process performs the same functions as each processing unit of the information processing device 10. Specifically, the processor 10d reads a program that has the same function as the renamer 12 from the HDD 10b or the like. Then, the processor 10d executes a process that performs the same processing as the renamer 12.

[0071] Thus, the information processing device 10 operates as an information processing device that executes an information processing method by reading and executing a program. Furthermore, the information processing device 10 can also achieve the same functionality as the embodiment described above by reading the program from the recording medium using a media reader and executing the read program. Note that the program referred to in this other embodiment is not limited to being executed by the information processing device 10. For example, the above embodiment may also be applied to cases where another computer or server executes the program, or where these computers or servers collaborate to execute the program.

[0072] This program may be distributed via a network such as the Internet. Alternatively, this program may be recorded on a computer-readable recording medium such as a hard disk, flexible disk (FD), CD-ROM, MO (Magneto-Optical disk), or DVD (Digital Versatile Disc), and executed by being read from the recording medium by a computer. [Explanation of Symbols]

[0073] 10 Information Processing Devices 10d processor 11 Instruction Processing Unit 12 Lineage 12a Freelift 12b RMT 12c Renamer Control Unit 13 Shipping Department 14. Instruction Window 15 Arithmetic circuit 16 Register File

Claims

1. On the computer, For each area of ​​the mask register, which is a logical register used for mask calculations, corresponding to each element of each row of the sparse matrix, a mask pattern for right shifting is set for each mask bit in each area of ​​the mask register such that a right shift of one bit brings the mask pattern used for the mask calculation to the bit position used. The positions of the mask bits are associated with each physical register having a region corresponding to each of the aforementioned elements. In each area of ​​each of the aforementioned physical registers, the mask pattern is acquired and set at the position of the corresponding mask bit in the mask register, thereby expanding the mask pattern into the physical register. When performing operations on each element of each row of the aforementioned sparse matrix in parallel, the physical register corresponding to the element to be operated on among the expanded physical registers is referenced during the operation. A arithmetic processing program characterized by executing a process.

2. The aforementioned expansion process is, If the program counter falls within the set range, each of the mask bits is expanded by the physical register. If the program counter does not fall within the set range, the expansion to the physical register is suppressed, and the mask register is renamed to perform the mask operation. The arithmetic processing program according to feature 1.

3. The arithmetic processing program according to claim 1, characterized in that when the mask calculation corresponding to each of the mask bits deployed in different areas of the physical register is completed, the computer is instructed to perform a process to release each of the different areas of the physical register.

4. Computers For each area of ​​the mask register, which is a logical register used for mask calculations, corresponding to each element of each row of the sparse matrix, a mask pattern for right shifting is set for each mask bit in each area of ​​the mask register such that a right shift of one bit brings the mask pattern used for the mask calculation to the bit position used. The positions of the mask bits are associated with each physical register having a region corresponding to each of the aforementioned elements. In each area of ​​each of the aforementioned physical registers, the mask pattern is acquired and set at the position of the corresponding mask bit in the mask register, thereby expanding the mask pattern into the physical register. When performing operations on each element of each row of the aforementioned sparse matrix in parallel, the physical register corresponding to the element to be operated on among the expanded physical registers is referenced during the operation. A method for performing arithmetic operations, characterized by executing a process.

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