Silicon carbide wafers and silicon carbide semiconductor manufacturing equipment using the same

Abstract

To set the trap density of an epitaxial layer to 1.0×1013 cm-3 or less.SOLUTION: A silicon carbide wafer includes a substrate made of SiC, an epitaxial layer made of SiC and arranged on the substrate, a chip formation region in which a semiconductor element is formed, and a peripheral region surrounding the chip formation region, and in the chip formation region, the epitaxial layer has a trap density of 1.0×1013 cm-3 or less at an activation energy of 0.10 to 0.20 eV as determined by the DLTS method, and the substrate has a Ti density and a Cr density of 1.0×1017 cm-3 or less as measured by the SIMS method.SELECTED DRAWING: Figure 4

Description

Technical Field

[0001] The present invention relates to a SiC wafer made of silicon carbide (hereinafter also referred to as SiC) and a SiC semiconductor device using the same.

Background Art

[0002] Conventionally, a SiC semiconductor device has been proposed in which an epitaxial layer of SiC is grown on a substrate made of SiC to form a SiC wafer, and a semiconductor element such as a MOSFET is formed using this SiC wafer. Note that MOSFET is an abbreviation for metal oxide semiconductor field effect transistor.

[0003] For example, a SiC semiconductor device in which a MOSFET is formed has the following configuration. That is, the MOSFET has an n-type substrate, an n-type drift layer disposed on the substrate, a p-type base layer disposed on the drift layer, and an n-type source region formed in the surface layer portion of the base layer. Further, the MOSFET has a trench gate structure formed to penetrate the source region and reach the drift layer, a first electrode electrically connected to the base layer and the source region, and a second electrode connected to the substrate.

[0004] And such a SiC semiconductor device is configured as follows. That is, after a SiC wafer is formed by disposing an n-type epitaxial layer on a wafer-shaped substrate, ion implantation or the like is performed to form a base layer, a source region, etc., and the SiC wafer is divided into chip units for manufacturing. Note that the drift layer is formed of a portion different from the portion constituting the base layer and the source region in the epitaxial layer.

[0005] Incidentally, the SiC semiconductor devices described above are expected to replace existing silicon-based semiconductor devices over a wide voltage range, specifically from 100V to over 10kV. In this case, to make the SiC semiconductor device an ultra-high voltage device with a breakdown voltage exceeding 10kV, a low-concentration epitaxial layer (i.e., drift layer) is required to obtain a conductivity modulation effect. For example, Non-Patent Literature 1 states that to obtain an ultra-high voltage device, the impurity concentration of the epitaxial layer should be 1.0 × 10⁻⁶. 14 cm -3 The following has been proposed: [Prior art documents] [Patent Documents]

[0006] [Non-Patent Document 1] Materials Science Forum Vol924,pp 568-572 [Overview of the Initiative] [Problems that the invention aims to solve]

[0007] The inventors diligently studied techniques for fabricating an epitaxial layer (i.e., a drift layer) applicable to all of the above voltage ranges. Specifically, they diligently studied techniques for intentionally controlling the impurity concentration of the epitaxial layer. The inventors then determined that the impurity concentration of the epitaxial layer should be 1.0 × 10⁻⁶ 14 cm -3 To achieve the following, we focused on the need to reduce the influence of trap density in the epitaxial layer. In particular, it is known that when Ti (i.e., titanium) and Cr (i.e., chromium) are incorporated into the epitaxial layer, they form energy levels shallow from the conduction band and behave as n-type impurities, affecting the breakdown voltage of SiC semiconductor devices. Therefore, in order to make the trap density of the epitaxial layer less likely to affect the breakdown voltage, it is preferable to lower the trap density of the epitaxial layer by about 10% compared to the impurity concentration of the epitaxial layer. In other words, the impurity concentration of the epitaxial layer should be 1.0 × 10⁻⁶14 cm -3 When the following conditions are met, it is preferable that the trap density of the epitaxial layer be 1.0×10 13 cm -3 or less. In the case of a device with a lower breakdown voltage, for example, about 1 kV, the impurity concentration of the epitaxial layer is 0.5 to 5.0×10 16 cm -3 In this case, since the impurity concentration control tends to be easier, if the trap density of the epitaxial layer can be made 1.0×10 13 cm -3 or less, it will also include epitaxial layers for fabricating devices in different voltage ranges.

[0008] In view of the above points, the present invention aims to provide a SiC wafer and a SiC semiconductor device in which the trap density of the epitaxial layer is 1.0×10 13 cm -3 or less.

Means for Solving the Problems

[0011] Claim 6 is a SiC semiconductor device comprising the substrate and epitaxial layer described in Claim 1, wherein a semiconductor element is formed that conducts current along the stacking direction between the substrate and the epitaxial layer.

[0012] According to this, it is possible to create a SiC semiconductor device, which is an ultra-high voltage resistant device.

[0013] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]

[0014] [Figure 1] This is a cross-sectional view of a SiC semiconductor device according to the first embodiment. [Figure 2] This figure shows the relationship between temperature and the signal obtained by the DLTS method. [Figure 3] This is a plan view of a SiC wafer. [Figure 4] This figure shows the relationship between the Ti density in the substrate measured by the SIMS method and the Ti trap density in the epitaxial layer obtained by the DLTS method. [Modes for carrying out the invention]

[0015] The embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0016] (First Embodiment) The first embodiment will be described with reference to the drawings. In this embodiment, a SiC semiconductor device 1 on which a MOSFET (abbreviation for Metal Oxide Semiconductor Field Effect Transistor) is formed as a semiconductor element will be used as an example. The SiC semiconductor device 1 has a cell region and a peripheral region formed to surround the cell region, although these are not specifically shown in the drawings. The MOSFET shown in Figure 1 is formed in the cell region of the SiC semiconductor device 1.

[0017] The SiC semiconductor device 1 is made of n + It is constructed using a substrate 10 of type n. An epitaxial layer 20 made of SiC is arranged on the surface of the substrate 10. The epitaxial layer 20 in this embodiment is n - Buffer layer 21 of type n - The configuration consists of a p-type drift layer 22 and a p-type base layer 23 arranged in that order.

[0018] In this embodiment, the epitaxial layer 20 has a thickness of approximately 4 to 300 μm, where the length along the direction normal to the surface direction of the substrate 10 is the thickness, and the impurity concentration is 5.0 × 10⁻¹⁶. 13 ~1.0×10 19 cm -3 The structure is said to have a part that is described as follows. Furthermore, as will be described in more detail later, the epitaxial layer 20 has a trap density of Ti and Cr within an activation energy of 0.10 to 0.20 eV, as measured by DLTS (Deep Level Transient Spectroscopy), which is 1.0 × 10⁻¹⁶ 13 cm -3 The following is stated:

[0019] The surface layer of the base layer 23 is n + A source region 24 of type n is formed. The source region 24 is formed by either ion implantation on the surface of the base layer 23, or by forming grooves in the base layer 23 and placing an n-type epitaxial layer in those grooves.

[0020] The substrate 10 is, for example, made of a material with a resistivity of 30 mΩ·cm or less (for example, 20 mΩ·cm), a surface that is a (0001)Si plane, and an off-angle of 0.5 to 5° relative to the (0001)Si plane. Furthermore, as will be described in more detail later, the substrate 10 has a Ti density and Cr density of 1.0 × 10¹⁶ as measured by the SIMS method (Secondary Ion Mass Spectrometry). 17 cm -3 The following is stated. In this embodiment, the substrate 10 constitutes the drain layer of the MOSFET.

[0021] The buffer layer 21 has, for example, an n-type impurity concentration of 1.0 × 10 16 ~1.0×10 19 cm -3 It is stated that the drift layer 22 has an n-type impurity concentration of 1.0 × 10⁻⁶ to make it an ultra-high voltage resistant device. 14 cm -3 The following is stated:

[0022] The base layer 23 is the region where the channel region is formed, for example, when the p-type impurity concentration is 3.0 × 10 17 cm -3 The thickness is set to approximately 0.5 to 2 μm. The source region 24 has a higher impurity concentration than the drift layer 22; for example, the n-type impurity concentration in the surface layer is 2.5 × 10⁻⁶. 18 ~1.0×10 19 cm -3 The thickness is considered to be approximately 0.5 to 2 μm. However, the film thickness of the drift layer 22, base layer 23, and source region 24 is arbitrary and not limited to the above.

[0023] Furthermore, a trench 30 is formed so as to penetrate the base layer 23 and the source region 24 and reach the drift layer 22. The base layer 23 and the source region 24 are arranged so as to be in contact with the side surface of this trench 30. Although only one trench 30 is shown in Figure 1, the actual trenches 30 are formed in a stripe pattern with multiple trenches arranged at equal intervals in the left-right direction of the paper.

[0024] A gate insulating film 31 is formed on the inner wall surface of the trench 30. A gate electrode 32 made of doped poly-Si is formed on the surface of the gate insulating film 31. The trench 30 is then completely filled with these gate insulating film 31 and gate electrode 32. In this embodiment, the trench gate structure is configured in this way.

[0025] An upper electrode 41, which serves as a source electrode, is arranged on the epitaxial layer 20, insulated from the gate electrode 32 and connected to the base layer 23 and the source region 24. In this embodiment, the upper electrode 41 is composed of multiple metals, such as Ni / Al. The portion of the multiple metals that contacts the portion constituting the n-type SiC (i.e., the source region 24) is composed of a metal that can make ohmic contact with the n-type SiC. Furthermore, at least the portion of the multiple metals that contacts the p-type SiC (i.e., the base layer 23) is composed of a metal that can make ohmic contact with the p-type SiC.

[0026] A lower electrode 42, which serves as a drain electrode electrically connected to the substrate 10, is formed on the back side of the substrate 10. In this embodiment, this structure constitutes an n-channel inverting trench gate MOSFET. A cell region is formed by arranging multiple such MOSFETs.

[0027] The above describes the basic configuration of the SiC semiconductor device 1 in this embodiment. In such a SiC semiconductor device 1, when a predetermined gate voltage is applied to the gate electrode 32, an inversion layer is formed in the portion of the base layer 23 that is in contact with the trench 30, and a current flows between the upper electrode 41 and the lower electrode 42. In other words, a current flows along the stacking direction of the substrate 10 and the epitaxial layer 20.

[0028] Furthermore, as described above, when the SiC semiconductor device 1 has an ultra-high voltage withstand capability of 10kV or more, the impurity concentration of the drift layer 22 should be 1.0 × 10 14 cm -3 The following is desirable. And the impurity concentration of the drift layer 22 should be 1.0 × 10⁻⁶. 14 cm -3 In the following case, the trap density of the drift layer 22 (i.e., epitaxial layer 20) should be set to 1.0 × 10⁻¹⁰ to minimize the impact on pressure resistance. 13 cm -3 The following is desired:

[0029] Currently, the SIMS method is commonly used to analyze trap density, but the SIMS method is 1.0 × 10⁻⁶ 14 cm -3 It has been reported that it is difficult to detect trap densities below 1.0 × 10⁻⁶. Therefore, the inventors of this invention have found that 1.0 × 10⁻⁶ trap densities are difficult to detect. 11 cm -3 We investigated evaluating the trap density of the epitaxial layer 20 using the DLTS method, which is capable of evaluating trap densities down to a certain extent, and obtained the results shown in Figure 2.

[0030] As shown in Figure 2, the DLTS method confirmed the presence of a defect peak I1 around 90K. Based on this defect peak I1, the activation energy is calculated to be 0.1–0.2 eV. Therefore, the epitaxial layer 20 has a defect peak I1 at an activation energy of 0.10–0.20 eV measured by the DLTS method. This defect peak I1 corresponds to the defect levels of Ti and Cr. Thus, the defect peak I1 is attributed to Ti and Cr. Note that peak I2 in Figure 2 is a peak attributed to carbon vacancies. Figure 2 also shows the results of evaluation after forming a Schottky electrode on a SiC wafer 100 (described later), with a DLTS interval of 19.2 ms. In this case, the Schottky electrode may be formed uniformly throughout the SiC wafer 100 (described later), or it may be formed as a TEG.

[0031] The reasons for the incorporation of Ti and Cr into the epitaxial layer 20 are thought to be the influence of each component used in growing the epitaxial layer 20, the raw material gas, and the underlying substrate 10. Specifically, the SiC semiconductor device 1 described above is manufactured as follows. First, a wafer-shaped substrate 10 is prepared, and an epitaxial layer 20 is grown on the substrate 10 to manufacture a SiC wafer 100 having multiple chip formation regions RA and an outer peripheral region RB surrounding the chip formation regions RA, as shown in Figure 3. Each chip formation region RA is demarcated by a dicing line DL. The SiC semiconductor device 1 is then manufactured by performing a predetermined semiconductor manufacturing process, such as ion implantation, on each chip formation region RA to form semiconductor elements having a source region 24, etc., and then dividing each chip formation region RA into chip units along the dicing line DL.

[0032] The outer peripheral region RB is defined, for example, as 3 mm from the edge in the planar direction of the SiC wafer 100. Furthermore, the thickness and impurity concentration of the buffer layer 21 and drift layer 22 (i.e., epitaxial layer 20) are the same as those of the SiC wafer 100.

[0033] In this case, the SiC wafer 100 is manufactured by placing the substrate 10 on a base located inside a chamber that constitutes a reaction chamber, and growing an epitaxial layer 20 on the substrate 10 by introducing a reaction gas such as silane or propane into the chamber while controlling the temperature inside the chamber.

[0034] Furthermore, in order to improve the crystal quality of the epitaxial layer 20, the components such as the chamber and the reaction gas used to grow the epitaxial layer 20 are usually made of the highest possible purity material. For example, the components such as the chamber are made of extremely high-purity carbon material or are covered with a high-purity carbon coating film. Therefore, it is thought that when the epitaxial layer 20 is grown on the substrate 10, the Ti and Cr contained in the substrate 10 are incorporated into the epitaxial layer 20 as degass. The inventors then diligently investigated the relationship between the Ti density in the substrate 10 and the Ti trap density formed in the epitaxial layer 20 and obtained the results shown in Figure 4. The Ti density in the substrate 10 was measured by the SIMS method, and the Ti trap density in the epitaxial layer 20 was measured by the DLTS method.

[0035] As shown in Figure 4, it is confirmed that the Ti trap density in the epitaxial layer 20 increases as the Ti density in the substrate 10 increases. 13 cm -3 To achieve the following, the Ti density in substrate 10 must be 1.0 × 10⁻⁶. 17 cm -3 It is confirmed that the following is sufficient. Note that although Ti density was explained here, the results are almost the same for Cr. Therefore, in this embodiment, the Ti density and Cr density of the substrate 10 are 1.0 × 10⁻⁶. 17 cm -3 The following is stated:

[0036] Furthermore, when manufacturing the SiC wafer 100 as described above, the edge portion becomes the outer peripheral region RB where semiconductor elements are not formed. Therefore, the epitaxial layer 20 has a trap density of Ti and Cr of at least 1.0 × 10⁻¹⁶ in the chip formation region RA. 13 cm -3 The following should suffice.

[0037] Furthermore, in order to suppress a decrease in yield when constructing the SiC semiconductor device 1, it is preferable that the carrier concentration distribution deviation along the plane direction of the substrate 10 is within 15%. In this case, more specifically, it is preferable that the carrier concentration distribution deviation along the plane direction of the epitaxial layer 20 located in each chip formation region RA is within 15%.

[0038] The substrate 10 is usually obtained by cutting a SiC ingot. Specifically, SiC ingots are obtained by high-temperature CVD (chemical vapor deposition) or sublimation. More specifically, SiC ingots are manufactured by placing a seed substrate made of SiC in a chamber, controlling the temperature inside the chamber with heating devices placed around the chamber, and introducing reaction gases such as silane or propane into the chamber to grow an epitaxial layer on the seed substrate. When manufacturing SiC ingots, Ti and Cr are also incorporated into the epitaxial layer from the seed substrate as degass. Therefore, even in the seed substrate used to manufacture SiC ingots, the Ti density and Cr density are 1.0 × 10⁻⁶. 17 cm -3 By using the following, the Ti density and Cr density can be increased to 1.0 × 10⁻⁶ 17 cm -3 The following SiC ingots (i.e., substrate 10) can be manufactured.

[0039] According to the embodiment described above, the Ti density and Cr density of the substrate 10 are 1.0 × 10 17 cm -3The following is stated. Therefore, the trap density due to Ti and Cr in the epitaxial layer 20 is 1.0 × 10⁻⁶. 13 cm -3 The following can be achieved, resulting in a SiC wafer 100 capable of manufacturing ultra-high voltage devices. Furthermore, before growing the epitaxial layer 20 on the substrate 10, the Ti density and Cr density of the substrate 10 are measured by SIMS to be 1.0 × 10⁻⁶. 17 cm -3 It is sufficient to check whether the following conditions are met, and a highly reliable SiC semiconductor device 1 can be obtained without significantly increasing the manufacturing process. Similarly, after growing the epitaxial layer 20 on the substrate 10, the trap density of Ti and Cr in the epitaxial layer 20 is measured by DLTS and the trap density is 1.0 × 10⁻⁶. 13 cm -3 It is sufficient to check whether the following conditions are met, and a highly reliable SiC semiconductor device can be obtained without significantly increasing the manufacturing process. Alternatively, the requirements for the substrate 10 and the epitaxial layer 20 may be checked after the epitaxial layer 20 has been grown. Furthermore, when checking these requirements, CV measurements may be performed to confirm the effective impurity concentration.

[0040] (1) In this embodiment, the epitaxial layer 20 on the SiC wafer 100 has a carrier concentration distribution deviation of 15% or less along the plane direction of the substrate 10. Therefore, it is possible to suppress a decrease in yield when manufacturing the SiC semiconductor device 1.

[0041] (2) In this embodiment, the epitaxial layer 20 has an impurity concentration of 5.0 × 10 13 ~1.0×10 19 cm -3 It has a portion that is described as having a thickness of 4 to 300 μm. In addition, the buffer layer 21 is 1.0 × 10 16 ~1.0×10 19 cm -3 It is stated that the drift layer 22 is 1.0 × 10 14 cm -3 The following is stated. Therefore, it is possible to create an ultra-high voltage MOSFET.

[0042] (Other embodiments) This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and idea of ​​this disclosure.

[0043] For example, in each of the above embodiments, a SiC semiconductor device 1 on which a MOSFET is formed was described. However, the SiC semiconductor device 1 may also have a Schottky diode or a pn diode.

[0044] Furthermore, in each of the above embodiments, a SiC semiconductor device 1 was described in which a MOSFET with an n-channel trench gate structure, where the first conductivity type is n-type and the second conductivity type is p-type, was formed. However, the SiC semiconductor device 1 may also be a p-channel trench gate structure MOSFET in which the conductivity types of each component are reversed compared to the n-channel type. Moreover, the SiC semiconductor device 1 may also have an IGBT with a similar structure in addition to the MOSFET. In the case of an IGBT, the n in the first embodiment is + The substrate 10 of type p + Aside from changing to the type substrate 10, it is the same as the MOSFET described in the first embodiment above.

[0045] (Features of the present invention)

[0046] [Claim 1] A silicon carbide wafer composed of silicon carbide, A substrate (10) made of silicon carbide, The device comprises an epitaxial layer (20) made of silicon carbide and disposed on the substrate, It has a chip formation region (RA) where semiconductor elements are formed, and an outer peripheral region (RB) surrounding the chip formation region. The epitaxial layer has a trap density at an activation energy of 0.10 to 0.20 eV derived by the DLTS method of 1.0×10 13 cm -3 or less in the chip formation region, The substrate is a silicon carbide wafer in which the Ti density and the Cr density measured by the SIMS method are each 1.0×10 17 cm -3 or less.

[0047] [Claim 2] The silicon carbide wafer according to claim 1, wherein the epitaxial layer has a deviation in carrier concentration distribution along the surface direction of the substrate of 15% or less.

[0048] [Claim 3] The silicon carbide wafer according to claim 1 or 2, wherein the epitaxial layer has a portion with an impurity concentration of 5.0×10 13 ~1.0×10 19 cm -3 or less.

[0049] [Claim 4] The silicon carbide wafer according to any one of claims 1 to 3, wherein the epitaxial layer has a film thickness of 4 to 300 μm.

[0050] [Claim 5] The epitaxial layer has a buffer layer (21) located on the substrate side and a drift layer (22) located on the buffer layer, The buffer layer has a density of 1.0×10 16 ~1.0×10 19 cm -3 or less, the silicon carbide wafer according to claim 4.

[0051] [Claim 6] A silicon carbide semiconductor device, comprising the substrate and the epitaxial layer according to any one of claims 1 to 5, A silicon carbide semiconductor device having a semiconductor element formed that conducts current along the stacking direction between the substrate and the epitaxial layer. [Explanation of symbols]

[0052] 10 circuit boards 20 Epitaxial Layer RA chip formation area RB outer area

Claims

1. A silicon carbide wafer composed of silicon carbide, An n-type substrate (10) made of silicon carbide, The invention comprises an epitaxial layer (20) composed of silicon carbide and having an n-type portion disposed on the substrate, It has a chip formation region (RA) where semiconductor elements are formed, and an outer peripheral region (RB) surrounding the chip formation region. The epitaxial layer has a trap density of 1.0 × 10⁻¹⁰ at an activation energy of 0.10 to 0.20 eV, as derived by the DLTS method, in the chip formation region. １３ cm －３ The following is stated: The substrate has Ti density and Cr density of 1.0 × 10⁻⁶, respectively, as measured by the SIMS method. １７ cm －３ The silicon carbide wafers are as follows:

2. The silicon carbide wafer according to claim 1, wherein the epitaxial layer has a carrier concentration distribution deviation along the planar direction of the substrate of 15% or less.

3. The epitaxial layer has an impurity concentration of 5.0 × 10⁻⁶ １３ ~1.0 x 10 １９ cm －３ A silicon carbide wafer according to claim 1 or 2, having a portion that is defined as such.

4. The silicon carbide wafer according to claim 1, wherein the epitaxial layer has a film thickness of 4 to 300 μm.

5. The epitaxial layer comprises a buffer layer (21) located on the substrate side and a drift layer (22) located on the buffer layer. The buffer layer has an impurity concentration of 1.0×10 １６ to 1.0×10 １９ cm －３ The silicon carbide wafer according to claim 3, which is so configured.

6. A silicon carbide semiconductor device, The substrate and epitaxial layer described in claim 1 are provided, A silicon carbide semiconductor device having a semiconductor element formed that conducts current along the stacking direction between the substrate and the epitaxial layer.

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