Oscillator, oscillator, and control method for the oscillator

Abstract

To provide an oscillation circuit that can reduce the possibility of abnormal oscillation even if there is a variation in the characteristics of an oscillator to be connected thereto.SOLUTION: An oscillation circuit comprises a circuit for oscillation that is connected to an oscillator, and a control circuit that controls the circuit for oscillation. The circuit for oscillation has a normal operation mode for oscillating in a state where a negative resistance value is a first value, and a start-up mode from a state where the circuit for oscillation stops oscillation until a transition to the normal operation mode. The control circuit performs control, in the start-up mode, so as to increase the negative resistance value from a second value smaller than the first value.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to an oscillator circuit, an oscillator, and a method for controlling an oscillator circuit. [Background technology]

[0002] Patent Document 1 describes an oscillation circuit that includes a control circuit that increases the load capacitance of the oscillation circuit only when oscillation is started, so that the growth coefficient of the main oscillation at the time of oscillation startup becomes larger than the growth coefficient of the spurious oscillation. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Utility Model Publication No. 62-109511 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, if the oscillator circuit is configured to have different load capacitances during startup and at other times, as described in Patent Document 1, there is a risk that normal oscillation cannot be guaranteed due to variations in the characteristics of the oscillator. In other words, if an oscillator is used that does not resonate with either the main oscillation or spurious oscillations at the load capacitance during oscillation startup, but resonates with both the main oscillation and spurious oscillations at the load capacitance during normal operation, there is a risk of abnormal oscillation. [Means for solving the problem]

[0005] One embodiment of the oscillator circuit according to the present invention is: An oscillator circuit connected to the vibrator, The system includes a control circuit for controlling the oscillation circuit, The oscillation circuit has a normal operating mode in which it oscillates when the negative resistance value is a first value, The system includes a startup mode from the state in which the oscillation circuit has stopped oscillating until it transitions to the normal operation mode, The aforementioned control circuit is In the startup mode, the negative resistance value is controlled to increase from a second value that is smaller than the first value.

[0006] One embodiment of the oscillator according to the present invention is: One embodiment of the oscillator circuit, The system comprises the aforementioned vibrator and

[0007] One aspect of the control method for an oscillator circuit according to the present invention is: A control method for an oscillator circuit, comprising an oscillator circuit connected to an oscillator, wherein the oscillator circuit has a normal operating mode in which it oscillates with a negative resistance value of a first value, and a startup mode in which it transitions from a state in which it has stopped oscillating to the normal operating mode, In the startup mode, the negative resistance value is controlled to increase from a second value that is smaller than the first value. [Brief explanation of the drawing]

[0008] [Figure 1] A perspective view of the oscillator of this embodiment. [Figure 2] A cross-sectional view of the oscillator of this embodiment. [Figure 3] A bottom view of the oscillator of this embodiment. [Figure 4] Functional block diagram of the oscillator according to the first embodiment. [Figure 5] A diagram showing an example of the configuration of an oscillator circuit. [Figure 6] A diagram showing an example configuration of a variable current source. [Figure 7] A diagram showing an example of current adjustment data. [Figure 8] A diagram showing an example of capacity adjustment data. [Figure 9] A diagram showing other configuration examples of a variable capacitance circuit. [Figure 10] A waveform diagram showing an example of the sequence in the first embodiment. [Figure 11] A waveform diagram showing another example of the sequence in the first embodiment. [Figure 12]A flowchart illustrating an example of the procedure for controlling an oscillator circuit. [Figure 13] A flowchart illustrating an example of the startup procedure in the first embodiment. [Figure 14] A flowchart illustrating another example of the startup procedure in the first embodiment. [Figure 15] A waveform diagram showing an example of a sequence in the second embodiment. [Figure 16] A flowchart illustrating an example of the startup procedure in the second embodiment. [Figure 17] A diagram showing an example of the configuration of a voltage control circuit in the third embodiment. [Figure 18] A waveform diagram showing an example of a sequence in the third embodiment. [Figure 19] A flowchart illustrating an example of the startup procedure in the third embodiment. [Figure 20] A waveform diagram showing an example of a sequence in the fourth embodiment. [Figure 21] A flowchart illustrating an example of the startup procedure in the fourth embodiment. [Figure 22] Functional block diagram of the oscillator according to the fifth embodiment. [Figure 23] A diagram showing an example of the configuration of an oscillation detection circuit. [Figure 24] A waveform diagram showing an example of a sequence in the fifth embodiment. [Figure 25] A flowchart illustrating an example of the startup procedure in the fifth embodiment. [Figure 26] A diagram showing an example of the control circuit configuration in the sixth embodiment. [Figure 27] A diagram showing an example of a delay circuit configuration. [Figure 28] A diagram showing an example of the waveform for each bit of current adjustment data. [Figure 29] A diagram showing an example configuration of a variable current source in the seventh embodiment. [Figure 30] A figure showing an example of current adjustment data in the seventh embodiment. [Modes for carrying out the invention]

[0009] Preferred embodiments of the present invention will be described in detail below with reference to the drawings. The embodiments described below are not intended to unduly limit the scope of the present invention as described in the claims. Furthermore, not all of the configurations described below are necessarily essential components of the present invention.

[0010] 1. First Embodiment 1-1. Oscillator Configuration Figures 1, 2, and 3 show an example of the structure of the oscillator 1 of this embodiment. Figure 1 is a perspective view of the oscillator 1. Figure 2 is a cross-sectional view of AA in Figure 1. Figure 3 is a bottom view of the oscillator 1.

[0011] As shown in Figures 1, 2, and 3, the oscillator 1 includes an oscillation circuit 2, a resonator 3, a package 4, a lid 5, and a plurality of external terminals 6. In this embodiment, the resonator 3 is a quartz crystal resonator using quartz as the substrate material, such as an AT-cut quartz crystal resonator or a tuning fork type quartz crystal resonator. The resonator 3 may also be a SAW (Surface Acoustic Wave) resonator or a MEMS (Micro Electro Mechanical Systems) resonator. SAW is an abbreviation for Surface Acoustic Wave, and MEMS is an abbreviation for Micro Electro Mechanical Systems. As the substrate material for the resonator 3, in addition to quartz, piezoelectric single crystals such as lithium tantalate and lithium niobate, piezoelectric ceramics such as lead zirconate titanate, or silicon semiconductor materials can be used. As the excitation means for the resonator 3, a piezoelectric effect may be used, or electrostatic driving by Coulomb force may be used. In this embodiment, the oscillation circuit 2 is realized as a single-chip integrated circuit. However, the oscillator circuit 2 may be composed of discrete components, at least in part.

[0012] Package 4 houses the oscillator circuit 2 and the resonator 3 in the same space. Specifically, package 4 has a recess, and by covering the recess with the lid 5, it becomes a housing chamber 7. Inside package 4 or on the surface of the recess, there are wirings (not shown) for electrically connecting the two terminals of the oscillator circuit 2, specifically the XI and XO terminals in Figure 4 (described later), and the two excitation electrodes 3a and 3b of the resonator 3, respectively. In addition, inside package 4 or on the surface of the recess, there are wirings (not shown) for electrically connecting each terminal of the oscillator circuit 2 to each external terminal 6 provided on the bottom surface of package 4. Note that package 4 is not limited to a configuration in which the oscillator circuit 2 and the resonator 3 are housed in the same space. For example, it may be a so-called H-type package in which the oscillator circuit 2 is mounted on one side of the package substrate and the resonator 3 is mounted on the other side.

[0013] The oscillator 3 has metal excitation electrodes 3a and 3b on its front and back surfaces, respectively, and oscillates at a desired frequency depending on the shape and mass of the oscillator 3, including the excitation electrodes 3a and 3b.

[0014] As shown in Figure 3, the oscillator 1 of this embodiment has four external terminals 6 on its bottom surface, specifically on the back surface of the package 4: external terminal VDD1 which is a power supply terminal, external terminal VSS1 which is a ground terminal, external terminal VC1 which is a terminal to which a signal controlling the frequency of the oscillation circuit 2 is input, and external terminal OUT1 which is an output terminal to which the oscillation signal is output. The power supply voltage is supplied to external terminal VDD1, and external terminal VSS1 is grounded.

[0015] Figure 4 is a functional block diagram of the oscillator 1 of the first embodiment. As shown in Figure 4, the oscillator 1 of this embodiment includes an oscillation circuit 2 and a vibrator 3. The oscillation circuit 2 has VDD terminal, VSS terminal, OUT terminal, VC terminal, XI terminal and XO terminal as external connection terminals. The VDD terminal, VSS terminal, OUT terminal and VC terminal are electrically connected to the four external terminals 6 of the oscillator 1 shown in Figure 3, which are external terminal VDD1, external terminal VSS1, external terminal OUT1 and external terminal VC1, respectively. The XI terminal is electrically connected to the excitation electrode 3a, which is one end of the vibrator 3, and the XO terminal is electrically connected to the excitation electrode 3b, which is the other end of the vibrator 3.

[0016] In this embodiment, the oscillation circuit 2 includes an oscillation circuit 10, a power supply circuit 20, a power-on reset circuit 30, a control circuit 40, a reference voltage generation circuit 50, an output circuit 60, and a memory circuit 70. The oscillation circuit 2 may also be configured by omitting or modifying some of these elements, or by adding other elements.

[0017] The power supply circuit 20 generates various voltages, including the power supply voltage Vdd of the logic circuit 42, based on the external power supply voltage input from the external terminal VDD1 and supplied via the VDD terminal, and supplies the generated voltages to each circuit. In addition, a ground voltage Vss is supplied to each circuit via the VSS terminal.

[0018] When power is supplied to oscillator 1, the power supply voltage Vdd output from power supply circuit 20 rises from 0V to a predetermined voltage value. When the power supply voltage Vdd reaches a predetermined threshold voltage, power-on reset circuit 30 generates a power-on reset signal POR, which remains high for a certain period of time. The power-on reset signal POR initializes logic circuit 42 to a desired state. When the power-on reset signal POR changes from high level to low level, logic circuit 42 starts operating.

[0019] The oscillation circuit 10 is connected to the oscillator 3 via terminals XI and XO, and is a circuit that amplifies the signal output from the oscillator 3 using an amplifying element and supplies it to the oscillator 3, causing the oscillator 3 to oscillate. The amplifying element may be, for example, a bipolar transistor, a MOS transistor, or a CMOS inverter. MOS stands for Metal Oxide Semiconductor, and CMOS stands for Complementary Metal Oxide Semiconductor. The oscillation circuit 10 is adjusted so that the oscillation frequency becomes the target frequency based on various setting signals supplied from the logic circuit 42.

[0020] The output circuit 60 buffers and outputs the oscillation signal CK output by the oscillation circuit 10. The oscillation signal CKO output from the output circuit 60 is output to the outside of the oscillator 1 via the OUT terminal and the external terminal OUT1. The output circuit 60 may also output differential oscillation signals. That is, the output circuit 60 may output an oscillation signal XCKO, which is the oscillation signal CKO with its polarity inverted. In this case, the oscillation circuit 2 further has an XOUT terminal for outputting the oscillation signal XCKO, and the oscillator 1 further has an external terminal XOUT1 for outputting the oscillation signal XCKO.

[0021] The control circuit 40 controls the oscillation circuit 10. In this embodiment, the control circuit 40 includes a voltage control circuit 41 and a logic circuit 42.

[0022] The voltage control circuit 41 generates a control voltage to change the oscillation frequency of the oscillation circuit 10 according to the voltage level of the frequency control signal supplied from the external terminal VC1 via the VC terminal, and supplies it to the oscillation circuit 10. In other words, the frequency of the oscillation signal CKO output from the external terminal OUT1 changes according to the voltage level of the frequency control signal input from the external terminal VC1.

[0023] The logic circuit 42 outputs an oscillation enable signal en_osc to the oscillation circuit 10 and controls the operation of the oscillation circuit 10. Specifically, the logic circuit 42 causes the oscillation circuit 10 to oscillate by setting the oscillation enable signal en_osc to a high level, and stops the oscillation of the oscillation circuit 10 by setting the oscillation enable signal en_osc to a low level. In addition, the logic circuit 42 outputs various setting signals to the oscillation circuit 10 and controls the oscillation frequency of the oscillation circuit 10. Furthermore, the logic circuit 42 outputs an output enable signal en_out to the output circuit 60 and controls the operation of the output circuit 60. Specifically, the logic circuit 42 controls the output circuit 60 to output the oscillation signal CKO by setting the output enable signal en_out to a high level, and controls the output circuit 60 to stop outputting the oscillation signal CKO by setting the output enable signal en_out to a low level.

[0024] The reference voltage generation circuit 50 generates various reference voltages based on the voltage output from the power supply circuit 20 and outputs them to the oscillation circuit 10.

[0025] The memory circuit 70 is a circuit for storing various types of information and includes a non-volatile memory 71 and a register 72. The non-volatile memory 71 may be, for example, a FAMOS, MONOS type memory, or EEPROM. FAMOS is an abbreviation for Floating gate Avalanche injection Metal Oxide Semiconductor. MONOS is an abbreviation for Metal Oxide Nitride Oxide Silicon. EEPROM is an abbreviation for Electrically Erasable Programmable Read-Only Memory. During the manufacturing process of the oscillator 1, various types of information are stored in the non-volatile memory 71. When power is supplied to the oscillator 1, the various types of information stored in the non-volatile memory 71 are transferred to the register 72, and the various types of information stored in the register 72 are supplied to each circuit as appropriate. For example, information for adjusting the oscillation frequency, transferred from the non-volatile memory 71 to the register 72, is supplied to the oscillation circuit 10 as various setting signals via the logic circuit 42. The information used to adjust the oscillation frequency includes current adjustment data and capacitance adjustment data, which will be described later.

[0026] 1-2. Configuration of the Oscillator Circuit Figure 5 shows an example configuration of the oscillation circuit 10. In the example in Figure 5, the oscillation circuit 10 includes an amplifying element 11, a variable current source 12, a resistor 13, a variable capacitance circuit 14, a variable capacitance circuit 15, a variable capacitance circuit 16, and a variable capacitance circuit 17. The oscillation circuit 10 also includes 10 CMOS inverters 100, 101, 102, 103, 104, 110, 111, 112, 113, and 114.

[0027] The amplification element 11 is an NPN bipolar transistor, with its base terminal connected to the XI terminal, its collector terminal connected to the XO terminal, and its emitter terminal grounded. Furthermore, a resistor 13 is connected between the base terminal and the collector terminal of the amplification element 11. The oscillation stage current Iosc is supplied to the collector terminal of the amplification element 11 from the variable current source 12, and the signal at the collector terminal is output as the oscillation signal CK. Note that a MOS transistor or a CMOS inverter may be used as the amplification element 11.

[0028] The variable current source 12 generates an oscillation stage current Iosc of a magnitude corresponding to the 5-bit current adjustment data trimI[4:0] supplied as a setting signal from the logic circuit 42, based on the voltage Vreg generated by the reference voltage generation circuit 50. The variable current source 12 then supplies the oscillation stage current Iosc to the amplification element 11. Note that the number of bits in the current adjustment data trimI is not limited to 5.

[0029] Figure 6 shows an example configuration of the variable current source 12. In the example in Figure 6, the variable current source 12 includes six current sources 120, 121, 122, 123, 124, and 130, five switching elements 125, 126, 127, 128, and 129, and two P-channel MOS transistors 131 and 132.

[0030] P-channel MOS transistor 131 has its gate and drain connected, and a voltage Vreg is supplied to its source. P-channel MOS transistor 132 has its gate connected to the gate of P-channel MOS transistor 131, a voltage Vreg is supplied to its source, and its drain is connected to the collector of the amplification element 11 in Figure 5.

[0031] The current source 130 has one end connected to the drain of the P-channel MOS transistor 131 and the other end connected to ground, and a constant bias current I bA current flows through the current sources. One end of the current source 120 is connected to the drain of the P-channel MOS transistor 131 via a switch element 125, and the other end is grounded. A constant current I0 flows when the switch element 125 is conducting. One end of the current source 121 is connected to the drain of the P-channel MOS transistor 131 via a switch element 126, and the other end is grounded. A current twice the magnitude of I0 flows when the switch element 126 is conducting. One end of the current source 122 is connected to the drain of the P-channel MOS transistor 131 via a switch element 127, and the other end is grounded. A current four times the magnitude of I0 flows when the switch element 127 is conducting. One end of the current source 123 is connected to the drain of the P-channel MOS transistor 131 via a switch element 128, and the other end is grounded. A current eight times the magnitude of I0 flows when the switch element 128 is conducting. The current source 124 has one end connected to the drain of a P-channel MOS transistor 131 via a switch element 129, and the other end is grounded. When the switch element 129 is conducting, a current 16 times the magnitude of I0 flows. For example, current sources 120, 121, 122, 123, 124, and 130 may be constructed using depletion-type N-channel MOS transistors or using current mirror circuits.

[0032] Switch element 125 conducts when data trimI[0] (bit 0 of current adjustment data trimI[4:0]) is input to its control terminal, and deconducts when data trimI[0] is high level and deconducts when data trimI[0] is low level. Switch element 126 conducts when data trimI[1] (bit 1 of current adjustment data trimI[4:0]) is input to its control terminal, and deconducts when data trimI[1] is high level and deconducts when data trimI[1] is low level. Switch element 127 conducts when data trimI[2] (bit 2 of current adjustment data trimI[4:0]) is input to its control terminal, and deconducts when data trimI[2] is high level and deconducts when data trimI[2] is low level. Switch element 128 conducts when data trimI[3] (bit 3 of current adjustment data trimI[4:0]) is input to its control terminal, and deconducts when data trimI[3] is high level, and deconducts when data trimI[3] is low level. Switch element 129 conducts when data trimI[4] (bit 4 of current adjustment data trimI[4:0]) is input to its control terminal, and deconducts when data trimI[4] is high level, and deconducts when data trimI[4] is low level. For example, switch elements 125, 126, 127, 128, and 129 may be N-channel MOS transistors or transmission gates.

[0033] Figure 7 shows the relationship between the decimal representation of the current adjustment data trimI[4:0] and the binary representation of each bit of the current adjustment data trimI[4:0]. A 0 in each bit corresponds to a low level, and a 1 in each bit corresponds to a high level. For example, if the current adjustment data trimI[4:0] is 1, then bit 0 is 1, and bits 1, 2, 3, and 4 are 0. Therefore, the switch element 125 conducts and current I0 flows to the current source 120. Also, for example, if the current adjustment data trimI[4:0] is 2, then bit 1 is 1, and bits 0, 2, 3, and 4 are 0. Therefore, the switch element 126 conducts and a current twice the magnitude of current I0 flows to the current source 121.

[0034] A bias current I is present between the source and drain of the P-channel MOS transistor 131. b A current flows through the source-drain of the P-channel MOS transistor 131, which is the sum of the currents flowing through each of the current sources 120, 121, 122, 123, and 124. For example, when the current adjustment data trimI[4:0] is 1, current I0 flows through current source 120, and the currents flowing through current sources 121, 122, 123, and 124 are zero, so a bias current I flows between the source and drain of the P-channel MOS transistor 131. b A current flows when current I0 is added to it. Also, for example, current adjustment data trim When I[4:0] is 1, twice the current I0 flows through current source 121, and the currents flowing through current sources 120, 122, 123, and 124 are zero. Therefore, the bias current I flows between the source and drain of the P-channel MOS transistor 131. b The current I0 is twice the current A current flows when the currents are added together. Then, a current mirror circuit, composed of two P-channel MOS transistors 131 and 132, causes a current of a predetermined magnitude, equal to the current flowing between the source and drain of P-channel MOS transistor 131, to flow between the source and drain of P-channel MOS transistor 132. This current is supplied to the amplification element 11 as the oscillation stage current Iosc. Therefore, the magnitude of the oscillation stage current Iosc changes according to the value of the current adjustment data trimI[4:0]. Specifically, the larger the value of the current adjustment data trimI[4:0], the larger the oscillation stage current Iosc becomes.

[0035] In the manufacturing process of oscillator 1, the value of current adjustment data trimI[4:0], which is used to set the oscillation stage current Iosc to a desired value corresponding to the resonant frequency of the oscillator 3, is written to the non-volatile memory 71.

[0036] Returning to the explanation of Figure 5, CMOS inverter 100 outputs data trimCN1[0], which is the logical inversion of data trimC1[0], bit 0 of the 5-bit capacitance adjustment data trimC1[4:0] supplied as a setting signal from logic circuit 42. CMOS inverter 101 outputs data trimCN1[1], which is the logical inversion of data trimC1[1], bit 1 of the capacitance adjustment data trimC1[4:0]. CMOS inverter 102 outputs data trimCN1[2], which is the logical inversion of data trimC1[2], bit 2 of the capacitance adjustment data trimC1[4:0]. CMOS inverter 103 outputs data trimCN1[3], which is the logical inversion of data trimC1[3], bit 3 of the capacitance adjustment data trimC1[4:0]. The CMOS inverter 104 outputs data trimCN1[4], which is the logical inversion of data trimC1[4], which is bit 4 of the capacitance adjustment data trimC1[4:0].

[0037] The variable capacitance circuit 14 is a capacitance circuit having a capacitance value C1 of a magnitude corresponding to the capacitance adjustment data trimCN1[4:0] obtained by logically inverting each bit of the capacitance adjustment data trimC1[4:0] by the CMOS inverters 100, 101, 102, 103, and 104. The variable capacitance circuit 14 includes five capacitance elements 140, 141, 142, 143, and 144, and five switch elements 145, 146, 147, 148, and 149.

[0038] Capacitive element 140 has one end connected to terminal XI and the other end grounded via switch element 145, and its capacitance value is C0. Capacitive element 141 has one end connected to terminal XI and the other end grounded via switch element 146, and its capacitance value is twice that of C0. Capacitive element 142 has one end connected to terminal XI and the other end grounded via switch element 147, and its capacitance value is four times that of C0. Capacitive element 143 has one end connected to terminal XI and the other end grounded via switch element 148, and its capacitance value is eight times that of C0. Capacitive element 144 has one end connected to terminal XI and the other end grounded via switch element 149, and its capacitance value is sixteen times that of C0. For example, capacitive elements 140, 141, 142, 143, and 144 may be MIM type capacitive elements using metal for both electrodes, or PIP type capacitive elements using polysilicon for both electrodes. MIM stands for Metal Insulator Metal, and PIP stands for Poly Insulator Poly.

[0039] Switch element 145 conducts when data trimCN1[0] (bit 0 of capacitance adjustment data trimCN1[4:0]) is input to its control terminal, and deconducts when data trimCN1[0] is high level and deconducts when data trimCN1[0] is low level. Switch element 146 conducts when data trimCN1[1] (bit 1 of capacitance adjustment data trimCN1[4:0]) is input to its control terminal, and deconducts when data trimCN1[1] is high level and deconducts when data trimCN1[1] is low level. Switch element 147 conducts when data trimCN1[2] (bit 2 of capacitance adjustment data trimCN1[4:0]) is input to its control terminal, and deconducts when data trimCN1[2] is low level. Switch element 148 conducts when data trimCN1[3] (bit 3 of capacitance adjustment data trimCN1[4:0]) is input to its control terminal, and deconducts when data trimCN1[3] is high level, and deconducts when data trimCN1[3] is low level. Switch element 149 conducts when data trimCN1[4] (bit 4 of capacitance adjustment data trimCN1[4:0]) is input to its control terminal, and deconducts when data trimCN1[4] is high level, and deconducts when data trimCN1[4] is low level. For example, switch elements 145, 146, 147, 148, and 149 may be N-channel MOS transistors or transmission gates.

[0040] Figure 8 shows the relationship between the decimal value of the capacitance adjustment data trimC1[4:0] and the binary value of each bit of the capacitance adjustment data trimCN1[4:0], which is obtained by logically inverting the capacitance adjustment data trimC1[4:0]. A 0 in each bit corresponds to a low level, and a 1 in each bit corresponds to a high level. For example, if the capacitance adjustment data trimC1[4:0] is 1, then bits 1, 2, 3, and 4 of the capacitance adjustment data trimCN1[4:0] are 1, and bit 0 is 0. Therefore, switch elements 146, 147, 148, and 149 conduct, and the other ends of the capacitance elements 141, 142, 143, and 144 are grounded. Also, for example, if the capacitance adjustment data trimC1[4:0] is 2, then bits 0, 2, 3, and 4 of the capacitance adjustment data trimCN1[4:0] are 1, and bit 1 is 0. Therefore, the switching elements 145, 147, 148, and 149 conduct, and the other ends of the capacitive elements 140, 142, 143, and 144 are grounded.

[0041] The capacitance value C1 of the variable capacitance circuit 14 is the sum of the capacitance values ​​of the capacitance elements 140, 141, 142, 143, and 144, whose other ends are grounded due to the conduction of the switch elements 145, 146, 147, 148, and 149. For example, when the capacitance adjustment data trimC1[4:0] is 1, the other ends of the capacitance elements 141, 142, 143, and 144 are grounded, and the other end of the capacitance element 140 is not grounded, so the capacitance value C1 of the variable capacitance circuit 14 is 2C0 + 4C0 +8C0 + 16C0 = 30C0. Also, for example, the capacity adjustment data trimC1[4 When :0] is 2, the other ends of capacitive elements 140, 142, 143, and 144 are grounded, and the other end of capacitive element 141 is not grounded, so the capacitance value C1 of the variable capacitance circuit 14 is C0 + 4C0 +8C0 + 16C0 = 29C0. Thus, the capacitance value C1 of the variable capacitance circuit 14 is It changes according to the value of the capacitance adjustment data trimC1[4:0]. Specifically, the larger the value of the capacitance adjustment data trimC1[4:0], the smaller the capacitance value C1 of the variable capacitance circuit 14 becomes.

[0042] CMOS inverter 110 outputs data trimCN2[0], which is the logical inversion of data trimC2[0], bit 0 of the 5-bit capacitance adjustment data trimC2[4:0] supplied as a setting signal from the logic circuit 42. CMOS inverter 111 outputs data trimCN2[1], which is the logical inversion of data trimC2[1], bit 1 of the capacitance adjustment data trimC2[4:0]. CMOS inverter 112 outputs data trimCN2[2], which is the logical inversion of data trimC2[2], bit 2 of the capacitance adjustment data trimC2[4:0]. CMOS inverter 113 outputs data trimCN2[3], which is the logical inversion of data trimC2[3], bit 3 of the capacitance adjustment data trimC2[4:0]. CMOS inverter 114 outputs data trimCN2[4], which is the logical inversion of data trimC2[4], bit 4 of the capacitance adjustment data trimC2[4].

[0043] The variable capacitance circuit 15 is a capacitance circuit having a capacitance value C2 of a magnitude corresponding to the capacitance adjustment data trimCN2[4:0] obtained by logically inverting each bit of the capacitance adjustment data trimC2[4:0] by the CMOS inverters 110, 111, 112, 113, 114. The variable capacitance circuit 15 includes five capacitance elements 150, 151, 152, 153, 154 and five switch elements 155, 156, 157, 158, 159.

[0044] Capacitive element 150 has one end connected to the XO terminal and the other end grounded via switch element 155, and its capacitance value is C0. Capacitive element 151 has one end connected to the XO terminal and the other end grounded via switch element 156, and its capacitance value is twice that of C0. Capacitive element 152 has one end connected to the XO terminal and the other end grounded via switch element 157, and its capacitance value is four times that of C0. Capacitive element 153 has one end connected to the XO terminal and the other end grounded via switch element 158, and its capacitance value is eight times that of C0. Capacitive element 154 has one end connected to the XO terminal and the other end grounded via switch element 159, and its capacitance value is sixteen times that of C0. For example, capacitive elements 150, 151, 152, 153, and 154 may be MIM-type capacitive elements using metal for two electrodes, or PIP-type capacitive elements using polysilicon for two electrodes. MIM stands for Metal Insulator Metal, and PIP stands for Poly Insulator Poly.

[0045] Switch element 155 conducts when data trimCN2[0] (bit 0 of capacitance adjustment data trimCN2[4:0]) is input to its control terminal, and deconducts when data trimCN2[0] is high level and deconducts when data trimCN2[0] is low level. Switch element 156 conducts when data trimCN2[1] (bit 1 of capacitance adjustment data trimCN2[4:0]) is input to its control terminal, and deconducts when data trimCN2[1] is high level and deconducts when data trimCN2[1] is low level. Switch element 157 conducts when data trimCN2[2] (bit 2 of capacitance adjustment data trimCN2[4:0]) is input to its control terminal, and deconducts when data trimCN2[2] is high level and deconducts when data trimCN2[2] is low level. Switch element 158 ​​conducts when data trimCN2[3] (bit 3 of capacitance adjustment data trimCN2[4:0]) is input to its control terminal, and deconducts when data trimCN2[3] is high level, and deconducts when data trimCN2[3] is low level. Switch element 159 conducts when data trimCN2[4] (bit 4 of capacitance adjustment data trimCN2[4:0]) is input to its control terminal, and deconducts when data trimCN2[4] is high level, and deconducts when data trimCN2[4] is low level. For example, switch elements 155, 156, 157, 158, and 159 may be N-channel MOS transistors or transmission gates.

[0046] The relationship between the decimal value of the capacitance adjustment data trimC2[4:0] and the binary value of each bit of the capacitance adjustment data trimCN2[4:0], which is obtained by logically inverting the capacitance adjustment data trimC2[4:0], is the same as the relationship between the decimal value of the capacitance adjustment data trimC1[4:0] and the binary value of each bit of the capacitance adjustment data trimCN1[4:0] shown in Figure 8, so its illustration is omitted. For example, if the capacitance adjustment data trimC2[4:0] is 1, then bits 1, 2, 3, and 4 of the capacitance adjustment data trimCN2[4:0] are 1, and bit 0 is 0. Therefore, switch elements 156, 157, 158, and 159 conduct, and the other ends of the capacitance elements 151, 152, 153, and 154 are grounded. Furthermore, for example, if the capacitance adjustment data trimC2[4:0] is 2, then bits 0, 2, 3, and 4 of the capacitance adjustment data trimCN2[4:0] are 1, and bit 1 is 0. Therefore, the switch elements 155, 157, 158, and 159 conduct, and the other ends of the capacitance elements 150, 152, 153, and 154 are grounded.

[0047] The capacitance value C2 of the variable capacitance circuit 15 is the sum of the capacitance values ​​of the capacitance elements 150, 151, 152, 153, and 154, whose other ends are grounded due to the conduction of the switch elements 155, 156, 157, 158, and 159, respectively. For example, when the capacitance adjustment data trimC2[4:0] is 1, the other ends of the capacitance elements 151, 152, 153, and 154 are grounded, and the other end of the capacitance element 150 is not grounded, so the capacitance value C2 of the variable capacitance circuit 15 is 2C0 + 4C0 +8C0 + 16C0 = 30C0. Also, for example, the capacity adjustment data trimC2[4 When :0] is 2, the other ends of capacitive elements 150, 152, 153, and 154 are grounded, and the other end of capacitive element 151 is not grounded, so the capacitance value C2 of the variable capacitance circuit 15 is C0 + 4C0 +8C0 + 16C0 = 29C0. Thus, the capacitance value C2 of the variable capacitance circuit 15 is It changes according to the value of the capacitance adjustment data trimC2[4:0]. Specifically, the larger the value of the capacitance adjustment data trimC2[4:0], the smaller the capacitance value C2 of the variable capacitance circuit 15 becomes.

[0048] The variable capacitance circuit 14 is connected to the excitation electrode 3a of the oscillator 3 via terminal XI, and the variable capacitance circuit 15 is connected to the excitation electrode 3b of the oscillator 3 via terminal XO. In other words, the variable capacitance circuits 14 and 15 are connected to the node connected to the oscillator 3 and become part of the load capacitance of the oscillator 3. In the manufacturing process of the oscillator 1, the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0], which are used to set the frequency of the oscillation signal CK output from the oscillation circuit 10 to the target frequency, are written to the non-volatile memory 71.

[0049] The variable capacitance circuit 16 is a capacitance circuit having a capacitance value C3 whose magnitude corresponds to the control voltage Vcnt1 supplied from the voltage control circuit 41. The variable capacitance circuit 16 includes a variable capacitance element 160. For example, the variable capacitance element 160 is a varactor with the source and drain of an NMOS transistor connected, the gate of the NMOS transistor connected to the XI terminal, the ground voltage Vss supplied to the back gate, and the control voltage Vcnt1 supplied to the source and drain. The larger the control voltage Vcnt1, the smaller the capacitance value C3 of the variable capacitance circuit 16.

[0050] The variable capacitance circuit 17 is a capacitance circuit having a capacitance value C4 whose magnitude corresponds to the control voltage Vcnt2 supplied from the voltage control circuit 41. The variable capacitance circuit 17 includes a variable capacitance element 170. For example, the variable capacitance element 170 is a varactor with the source and drain of an NMOS transistor connected, the gate of the NMOS transistor connected to the XO terminal, the ground voltage Vss supplied to the back gate, and the control voltage Vcnt2 supplied to the source and drain. The larger the control voltage Vcnt2, the smaller the capacitance value C4 of the variable capacitance circuit 17.

[0051] Figure 9 shows another example configuration of the variable capacitance circuits 16 and 17. In the example in Figure 9, the variable capacitance circuit 16 includes n variable capacitance elements 161-1 to 161-n, n capacitance elements 162-1 to 162-n, and n capacitance elements 163-1 to 163-n, where n is an integer greater than or equal to 2. For each integer i between 1 and n, the variable capacitance element 161-i is a varactor connected to the source and drain of an NMOS transistor. The source and drain of the NMOS transistor are connected to the XI terminal via capacitance element 163-i, a ground voltage Vss is supplied to the back gate, and the gate is grounded via capacitance element 162-i. In addition, a reference voltage Vref1-i generated by the reference voltage generation circuit 50 is supplied to the gate of the NMOS transistor, and a control voltage Vcnt1 is supplied to the source and drain. The larger the control voltage Vcnt1, the smaller the capacitance value C3 of the variable capacitance circuit 16.

[0052] Furthermore, the variable capacitance circuit 17 includes n variable capacitance elements 171-1 to 171-n, n capacitance elements 172-1 to 172-n, and n capacitance elements 173-1 to 173-n. n is an integer greater than or equal to 2. For each integer i between 1 and n, the variable capacitance element 171-i is a varactor connected to the source and drain of an NMOS transistor. The source and drain of the NMOS transistor are connected to terminal XI via capacitance element 173-i, a ground voltage Vss is supplied to the back gate, and the gate is grounded via capacitance element 172-i. In addition, a reference voltage Vref2-i generated by the reference voltage generation circuit 50 is supplied to the gate of the NMOS transistor, and a control voltage Vcnt2 is supplied to the source and drain. The larger the control voltage Vcnt2, the smaller the capacitance value C4 of the variable capacitance circuit 17 becomes.

[0053] In both Figure 5 and Figure 9, the variable capacitance circuit 16 is connected to the excitation electrode 3a of the oscillator 3 via terminal XI, and the variable capacitance circuit 17 is connected to the excitation electrode 3b of the oscillator 3 via terminal XO. That is, the variable capacitance circuits 16 and 17 are connected to the node connected to the oscillator 3 and become part of the load capacitance of the oscillator 3. The capacitance values ​​C3 and C4 of the variable capacitance circuits 16 and 17 are These voltages change according to the control voltages Vcnt1 and Vcnt2, and the control voltages Vcnt1 and Vcnt2 change according to the voltage level of the frequency control signal input from the external terminal VC1 via the VC terminal. Therefore, the oscillation frequency of the oscillation circuit 10 can be changed by the frequency control signal input from the external terminal VC1. In this embodiment, the voltage control circuit 41 generates control voltages Vcnt1 and Vcnt2 according to the voltage level of the frequency control signal input from the external terminal VC1, but the voltage control circuit 41 may also be a temperature compensation circuit, and the control voltages Vcnt1 and Vcnt2 may be temperature compensation voltages.

[0054] Note that Figure 5 omits the diagram of the circuit for stopping oscillation when the oscillation enable signal en_osc is low level. This circuit could be, for example, a switch circuit that cuts off the supply of the oscillation stage current Iosc to the amplification element 11 when the oscillation enable signal en_osc is low level.

[0055] 1-3. Startup Sequence In this embodiment, the oscillator circuit 2 has multiple operating modes, including a normal operating mode and a startup mode. The normal operating mode is an operating mode in which the oscillator circuit 10 oscillates when its negative resistance value |nR|, which is the absolute value of its negative resistance, is a predetermined first value |nR1|. The startup mode is an operating mode from when the oscillator circuit 10 has stopped oscillating until it transitions to the normal operating mode. For example, the startup mode is the operating mode from when power is applied to the oscillator 1 until it transitions to the normal operating mode. Furthermore, if the oscillator circuit 2 has a standby mode as an operating mode in which the oscillation of the oscillator circuit 10 stops when power is applied to the oscillator 1, the operating mode from the standby mode to the normal operating mode is also a startup mode.

[0056] In this embodiment, the oscillator 3 is a quartz crystal oscillator and is capable of resonance in either the principal or secondary oscillation. When the polarization of the oscillation along the X, Y, and Z axes is illustrated, the Y and Z axes are cosine waves, and if the number of peaks is p, q, and r respectively, the oscillation mode is expressed as (pqr). For example, if the oscillator 3 is an AT-cut quartz crystal oscillator, the principal oscillation is a thickness principal oscillation with oscillation mode (1.0.0). This thickness principal oscillation is a pure slip oscillation with only displacement in the X-axis direction and has a constant polarization in the Z-axis direction. Also, for example, the secondary oscillation is a thickness secondary oscillation with oscillation mode (3.1.0), (5.1.0), or (7.1.0). This thickness secondary oscillation is a slip oscillation only in the X-axis direction, but has an odd number of sinusoidal polarizations in the X-axis direction, and the signs of adjacent extreme values ​​are opposite. Alternatively, the secondary vibration may be a thickness secondary vibration with vibration mode (1.1.1) or (1.1.2). This thickness secondary vibration is close to the main thickness vibration and intervenes between the main thickness vibration and a thickness secondary vibration with vibration mode (3.1.0), (5.1.0), or (7.1.0), having one sinusoidal polarization in the X-axis direction and one or two cosinusoidal polarizations in the Z-axis direction, with adjacent extrema having opposite signs. Alternatively, the secondary vibration may be a secondary vibration due to a higher-order contour vibration with vibration mode (21.0.0). This secondary vibration due to a higher-order contour vibration has an odd number of sinusoidal polarizations in the X-axis direction, with adjacent extrema having opposite signs, and has a nearly constant polarization in the Z-axis direction. Alternatively, the secondary vibration may be a secondary vibration due to a higher-order contour vibration with vibration mode (0.0.33). The secondary vibrations due to this higher-order contour vibration have an odd number of sinusoidal polarizations in the Z-axis direction, with adjacent extrema having opposite signs, and a nearly constant polarization in the X-axis direction. Alternatively, the secondary vibrations may be due to higher-order contour vibrations with vibration modes (40.1.0), (42.1.0), or (12.1.0). These secondary vibrations due to this higher-order contour vibration have an odd number of sinusoidal polarizations in the X-axis direction, with adjacent extrema having opposite signs.

[0057] The value of the series resistance R under load when oscillator 3 resonates in its primary vibration. Lm In this case, oscillator 3 is in secondary vibration The value of the series resistance R under load when resonance occurs.Ls is smaller than. In other words, the vibration with the smallest value of the series resistance during load is the main vibration. In the normal operation mode, if the vibrator 3 resonates at the main vibration, the oscillation circuit 10 oscillates normally and the oscillation signal CK of the target frequency can be obtained. However, if the vibrator 3 resonates at the sub-vibration, the oscillation circuit 10 oscillates abnormally and the oscillation signal CK of the target frequency cannot be obtained. In the normal operation mode, in order to stably oscillate the oscillation circuit 10 at the main vibration, the negative resistance value |nR| is set to a first value |nR1| that is sufficiently larger than R Specifically, the logic circuit 42 of the control circuit 40 supplies the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] transferred from the non-volatile memory 71 to the register 72 to the oscillation circuit 10, and controls the negative resistance value |nR| of the oscillation circuit 10 to be the first value |nR1| determined by the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0]. Lm is set to a first value |nR1| that is sufficiently larger than R. Specifically 的には、制御回路40のロジック回路42が、不揮発性メモリー71からレジスター72に転送された電流調整データtrimI[4:0]及び容量調整データtrimC1[4:0],trimC2[4:0]を発振用回路10に供給し、発振用回路10の負性抵抗値|nR|が、電流調整データtrimI[4:0]及び容量調整データtrimC1[4:0],trimC2[4:0]によって決まる第1の値|nR1|となるように制御する。

[0058] However, since the first value |nR1| is sufficiently larger than R, as a result, it becomes larger than R Lm よりも十分に大きいため、結果的にR L s よりも大きくなってしまう。そうすると、第1の値|nR1|がR Ls よりも大きいた め、発振用回路10の発振が停止している状態からすぐに負性抵抗値|nR|を第1の値|nR1|に設定すると、条件によっては振動子3が副振動で共振し、発振用回路10が異常発振を起こすおそれがある。そこで、本実施形態では、発振用回路10が異常発振を起こすおそれを低減させるために、制御回路40のロジック回路42は、起動モードにおいて、発振用回路10の負性抵抗値|nR|が第1の値|nR1|よりも小さい第2の値|nR2|から増加するように制御する。

[0059] Here, as described above, the first value |nR1| is the value of the series resistance during load when the vibrator 3 resonates at the main vibration R LmLarger than and when oscillator 3 resonates with secondary vibrations under load Column resistor vR Ls It is a value greater than . Also, the second value |nR2| is at least . The value of the series resistance R under load when the rotor 3 resonates due to secondary vibration. Ls A value smaller than, i.e., The negative resistance value is such that oscillator 3 cannot resonate in secondary vibrations. The second value |nR2| is the series resistance value R under load when oscillator 3 resonates in primary vibrations. Lm It can be even smaller than that. It can be large. For example, even considering the variation in the characteristics of the oscillator 3 connected to the oscillation circuit 2, the second value |nR2| is reliably R Ls The second value |nR2| is set to be smaller than R Lm It can be made even smaller.

[0060] Thus, in this embodiment, the logic circuit 42 controls the negative resistance value |nR| of the oscillation circuit 10 in the startup mode to increase from a second value |nR2|, which prevents the oscillator 3 from resonating at least in sub-vibrations. As a result, the negative resistance value |nR| is always R Lm Larger than, and R Ls There exists a state smaller than this, and this state In this state, the oscillator 3 can resonate with the main vibration but cannot resonate with the secondary vibration. Therefore, the oscillator 3 resonates with the main vibration before it resonates with the secondary vibration, and the oscillation circuit 10 oscillates normally based on the resonance with the main vibration.

[0061] Here, in the oscillation circuit 10 shown in Figure 5, the transconductance of the amplification element 11 is set to g. m The capacitance value connected to terminal XI is C XI The capacitance value connected to the XO terminal is C XO , If the oscillation frequency of the oscillation circuit 10 is f = ω / 2π, then the theoretical formula for the negative resistance value |nR| of the oscillation circuit 10 is given by equation (1).

[0062]

number

[0063] Furthermore, the transconductance of the amplification element 11 is g m This is expressed by equation (2). In equation (2), q is the charge of the electron, k is the Boltzmann constant, and T is the absolute temperature.

[0064]

number

[0065] From equation (1), the transconductance of the amplification element 11 is given by g. m The larger g is, the larger the negative resistance |nR|. In equation (2), q, k, and T are constants, so the larger the oscillation stage current Iosc, the larger the transconductance g m The negative resistance |nR| increases as the oscillation stage current Iosc increases.

[0066] Therefore, in this embodiment, the logic circuit 42 of the control circuit 40 increases the negative resistance value |nR| of the oscillation circuit 10 from the second value |nR2| by increasing the value of the oscillation stage current Iosc in the startup mode. Specifically, in the startup mode, the logic circuit 42 controls the negative resistance value |nR| to increase in a step manner by changing the value of the current adjustment data trimI[4:0] output to the oscillation circuit 10 to increase the value of the oscillation stage current Iosc in a step manner.

[0067] Figure 10 is a waveform diagram showing an example of the sequence from when power is supplied to the oscillator circuit 2 until it transitions to the normal operating mode. In the example in Figure 10, when power is supplied to the oscillator 1, the reset period T1 begins, the power supply voltage Vdd rises from 0V to a predetermined voltage value, the power-on reset signal POR changes from a low level to a high level, and the logic circuit 42 is initialized. Subsequently, the reset period T1 ends as the power-on reset signal POR changes from a high level to a low level, and the memory load period T2 begins.

[0068] During the memory load period T2, various pieces of information stored in the non-volatile memory 71 are transferred to the register 72. After this transfer is complete, the logic circuit 42 changes the oscillation enable signal en_osc from a low level to a high level, ending the memory load period T2 and starting the startup period T3.

[0069] During the startup period T3, the logic circuit 42 gradually increases the current adjustment data trimI[4:0] from the start value to the end value by arbitrary values, and the value of the oscillation stage current Iosc increases in stages accordingly. The start and end values ​​of the current adjustment data trimI[4:0] can be set to arbitrary values, for example, by writing them in advance to the non-volatile memory 71. In the example in Figure 10, the logic circuit 42 gradually increases the current adjustment data trimI[4:0] from the start value of 0 to 1, and the value of the oscillation stage current Iosc increases in stages accordingly. b It increases by I0 each time. As a result, during the startup period T3, The negative resistance value |nR| of the oscillation circuit 10 increases in a step-like manner from the second value |nR2|. Negative resistance |nR| is R Lm Larger than, and R Ls When it is smaller than, oscillator 3 The oscillator begins to resonate with the main oscillation, and the amplitude of the current I_xtal output from oscillator 3 increases. When the amplitude of current I_xtal exceeds a predetermined threshold, a pulse is generated in the oscillation signal CK. Subsequently, the current adjustment data trimI[4:0] increases, and the negative resistance value |nR| becomes R Ls It becomes larger than that, but at that point, the oscillation is due to resonance in the main vibration of oscillator 3. Since the oscillation of circuit 10 has grown sufficiently, resonance does not occur in the secondary oscillation of oscillator 3. When the current adjustment data trimI[4:0] increases further and reaches the final value of 31, the value of the oscillation stage current Iosc becomes I b The value becomes +31I0. After that, logic circuit 42 adjusts the current. The value of trimI[4:0] is changed stepwise from the end value to the set value in normal operation mode by any value. In the example in Figure 10, the logic circuit 42 gradually decreases the value of the current adjustment data trimI[4:0] from the end value of 31 by 1, and when the set value of the current adjustment data trimI[4:0] in normal operation mode reaches 20, which is the value transferred to register 72 during the memory load period T2, the value of the oscillation stage current Iosc is changed to I b It becomes +20I0. The negative resistance value |nR| becomes the first value |nR1|. Then, the logic circuit 42 holds the value of the current adjustment data trimI[4:0] at 20 and changes the output enable signal en_out from a low level to a high level, ending the startup period T3 and starting the normal operation period T4.

[0070] During the normal operating period T4, the output enable signal en_out is at a high level, so the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0071] In the example shown in Figure 10, the operating mode during the startup period T3 is the startup mode, and the operating mode during the normal operating period T4 is the normal operating mode. Alternatively, the operating mode during the reset period T1, the memory load period T2, and the startup period T3 is the startup mode.

[0072] In the example shown in Figure 10, the logic circuit 42 increases the current adjustment data trimI[4:0] from the minimum value to the maximum value in the startup mode, and then decreases it to the set value in the normal operation mode, resulting in a longer startup period T3. In contrast, other sequences that shorten the startup period T3 are also conceivable.

[0073] Figure 11 is a waveform diagram showing another example of the sequence from when power is applied to the oscillator circuit 2 to when it transitions to the normal operating mode. In the example in Figure 11, during the startup period T3, the logic circuit 42 gradually increases the current adjustment data trimI[4:0] from the starting value to the set value in the normal operating mode by an arbitrary value, and the value of the oscillator stage current Iosc increases in stages accordingly. The starting value of the current adjustment data trimI[4:0] may be set to an arbitrary value, for example, by writing it in advance to the non-volatile memory 71. In the example in Figure 11, the logic circuit 42 gradually increases the current adjustment data trimI[4:0] from the starting value of 0 to 20, which is the set value in the normal operating mode by 1, and the value of the oscillator stage current Iosc increases in stages accordingly. b From I b It increases by 10 up to +20I0. As a result, during the startup period T3, the negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner from the second value |nR2| to the first value |nR1|. Then, the logic circuit 42 However, by holding the value of the current adjustment data trimI[4:0] to 20 and changing the output enable signal en_out from a low level to a high level, the startup period T3 ends and the normal operation period T4 begins.

[0074] In the example in Figure 11, the logic circuit 42 does not need to increase the current adjustment data trimI[4:0] from the start value to the end value, so the startup period T3 is shortened. Also, in the example in Figure 11, the first value |nR1|, which is the set value of the negative resistance value |nR| in the normal operating mode, is greater than or equal to the maximum value of the negative resistance value |nR| during the startup period T3. That is, during the startup period T3, the negative resistance value |nR| does not become greater than the first value |nR1|, so the negative resistance value |nR| is equal to the value of the series resistance under load when the oscillator 3 resonates in sub-vibration R Ls twist The time during which the value is large is short, making resonance in the secondary vibrations of oscillator 3 less likely to occur.

[0075] In the example in Figure 11, the operating mode during the startup period T3 is the startup mode, and the operating mode during the normal operating period T4 is the normal operating mode. Alternatively, the operating mode during the reset period T1, the memory load period T2, and the startup period T3 is the startup mode.

[0076] 1-4. Control Method for Oscillator Circuits Figure 12 is a flowchart illustrating an example of the control procedure for the oscillator circuit 2. As shown in Figure 12, when power is supplied to the oscillator 1, the oscillator circuit 2 first performs a reset process S1. Specifically, in the reset process S1, the power-on reset circuit 30 initializes the logic circuit 42 by changing the power-on reset signal POR from a low level to a high level. Then, the power-on reset circuit 30 changes the power-on reset signal POR from a high level to a low level, ending the reset process S1. The duration of the reset process S1 corresponds to the reset period T1 in Figure 10 or Figure 11.

[0077] Next, the oscillator circuit 2 performs the memory load process S2. Specifically, in the memory load process S2, the memory circuit 70 transfers various information stored in the non-volatile memory 71 to the register 72. After the transfer is complete, the logic circuit 42 sets the oscillation enable signal en_osc to a high level, and the memory load process S2 ends. The duration of the memory load process S2 corresponds to the memory load period T2 in Figure 10 or Figure 11.

[0078] Next, the oscillator circuit 2 performs the startup process S3. Specifically, in the startup process S3, the logic circuit 42 sets the oscillation enable signal en_osc to a high level, and the negative resistance value |nR| of the oscillator circuit 10 increases from a second value |nR2| which is smaller than the first value |nR1|. The system is controlled to do so. Then, the logic circuit 42 changes the output enable signal en_out from a low level to a high level, and the startup process S3 ends. The duration of the startup process S3 corresponds to the startup period T3 in Figure 10 or Figure 11.

[0079] Finally, the oscillator circuit 2 performs the normal operation process S4. Specifically, in the normal operation process S4, the oscillator circuit 10 oscillates with its negative resistance value |nR| set to a second value |nR2|, and the oscillation signal CKO output from the output circuit 60 is output from the external terminal OUT1 of the oscillator 1 via the OUT terminal. The duration of the normal operation process S4 corresponds to the normal operation period T4 in Figure 10 or Figure 11.

[0080] The operating mode in the startup process S3 is the startup mode, and the operating mode in the normal operation process S4 is the normal operation mode. Alternatively, the operating mode in the reset process S1, memory load process S2, and startup process S3 is the startup mode.

[0081] Figure 13 is a flowchart showing an example of the procedure for the startup process S3 in Figure 12 in the first embodiment. The procedure shown in Figure 13 corresponds to the operation of the startup period T3 in Figure 10. As shown in Figure 13, first, in process S31, the logic circuit 42 sets the current adjustment data trimI[4:0] to a starting value. In the example of Figure 10, the starting value is 0. By setting the current adjustment data trimI[4:0] to a starting value, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0082] Next, when a predetermined time has elapsed in step S32, in step S33, the logic circuit 42 determines whether the value of the current adjustment data trimI[4:0] matches the end value. In the example in Figure 10, the final value is 20.

[0083] If the value of the current adjustment data trimI[4:0] in step S33 does not match the final value, in step S34, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to increase the oscillation stage current Iosc.

[0084] Processes S32, S33, and S34 are repeated until the value of the current adjustment data trimI[4:0] matches the end value. Once the value of the current adjustment data trimI[4:0] matches the end value, in process S35, the logic circuit 42 changes the current adjustment data trimI[4:0] to the set value in normal operation mode.

[0085] Then, in step S36, the logic circuit 42 sets the output enable signal en_out to a high level, and the startup step S3 ends.

[0086] Figure 14 is a flowchart showing another example of the procedure for the startup process S3 in Figure 12 in the first embodiment. The procedure shown in Figure 14 corresponds to the operation of the startup period T3 in Figure 11. As shown in Figure 14, first, in step S101, the logic circuit 42 sets the current adjustment data trimI[4:0] to a starting value. In the example of Figure 11, the starting value is 0. By setting the current adjustment data trimI[4:0] to a starting value, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0087] Next, after a predetermined time has elapsed in step S102, in step S103, the logic circuit 42 determines whether the value of the current adjustment data trimI[4:0] matches the set value in the normal operation mode. The set value of the current adjustment data trimI[4:0] in the normal operation mode is the value stored in the non-volatile memory 71.

[0088] If the value of the current adjustment data trimI[4:0] in step S103 does not match the set value in normal operation mode, in step S104 the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to increase the oscillation stage current Iosc.

[0089] Then, steps S102, S103, and S104 are repeated until the value of the current adjustment data trimI[4:0] matches the set value in normal operation mode. When the value of the current adjustment data trimI[4:0] matches the set value in normal operation mode, in step S105, the logic circuit 42 sets the output enable signal en_out to a high level, and the startup step S3 ends.

[0090] 1-5. Effects In the oscillator 1 of the first embodiment described above, in the oscillation circuit 2, during the startup mode from a state in which the oscillation circuit 10 has stopped oscillating to a normal operating mode in which the oscillation circuit 10 oscillates when its negative resistance value |nR| becomes a first value |nR1|, the negative resistance value |nR| of the oscillation circuit 10 starts from a second value |nR2| which is smaller than the first value |nR1|. It increases. The value of the series resistance R under load when oscillator 3 resonates in its primary vibration. Lm The oscillator 3 is The value of the series resistance R under load when resonance occurs due to secondary vibrations. Ls Since it is smaller than, the oscillation circuit 10 The negative resistance value |nR| increases from the second value |nR2|, R Lm Larger than, and R Ls The value becomes smaller than this. Therefore, in the startup mode, the common in the main oscillation of oscillator 3 Oscillation based on vibration develops before oscillation based on resonance in the sub-vibrations of the oscillator 3. Therefore, according to the oscillator 1 of the first embodiment, the risk of abnormal oscillation can be reduced even if there are variations in the characteristics of the oscillator 3.

[0091] In particular, in the oscillator 1 of the first embodiment, in the startup mode, by increasing the value of the oscillation stage current Iosc, the negative resistance value |nR| of the oscillation circuit 10 gradually increases in a step-like manner from the second value |nR2|, so R Lm Larger than, and R Ls The value is smaller than The time required for this process becomes longer. As a result, oscillation based on resonance in the main vibration of the oscillator 3 develops before oscillation based on resonance in the secondary vibration of the oscillator 3. Therefore, according to the oscillator 1 of the first embodiment, the risk of abnormal oscillation can be reduced even if there are variations in the characteristics of the oscillator 3.

[0092] Furthermore, according to the oscillator 1 of the first embodiment, the variable current source 12 used to set the oscillation stage current Iosc to a desired value corresponding to the resonant frequency of the oscillator 3 in the normal operating mode can also be used to increase the negative resistance value |nR| of the oscillation circuit 10 in the startup mode.

[0093] 2. Second Embodiment In the following description of the oscillator 1 of the second embodiment, the same reference numerals are used for components similar to those in the first embodiment, and descriptions similar to those in the first embodiment are omitted or simplified. The main focus will be on the differences from the first embodiment.

[0094] The configuration of the oscillator 1 in the second embodiment is the same as in Figures 1 to 4, so its illustration and description are omitted. Also, the configuration of the oscillation circuit 10 in the second embodiment is the same as in Figure 5, so its illustration and description are omitted. The oscillator 1 in the second embodiment differs from the oscillator 1 in the first embodiment in its operation in the startup mode.

[0095] From equation (1) above, the capacity value C XI ,C XO The smaller at least one of them becomes, the more negative resistance The resistance value |nR| becomes large. Therefore, in the second embodiment, the logic circuit 42 of the control circuit 40, in the startup mode, sets at least one of the capacitance values ​​C1, C2 of the variable capacitance circuits 14, 15. By decreasing the coefficient, the negative resistance value |nR| of the oscillation circuit 10 is increased from the second value |nR2|. Specifically, in startup mode, the logic circuit 42 changes the value of at least one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] output to the oscillation circuit 10 to step at least one of the capacitance values ​​C1 and C2 of the variable capacitance circuits 14 and 15. By increasing it in a stepwise manner, the negative resistance value |nR| is controlled to increase in a stepwise manner.

[0096] The other components of the oscillator 1 in the second embodiment are the same as those in the first embodiment, so their illustration and description are omitted.

[0097] Figure 15 is a waveform diagram showing an example of the sequence from when power is supplied to the oscillator circuit 2 to when it transitions to the normal operating mode in the second embodiment. In the example in Figure 15, when power is supplied to the oscillator 1, the reset period T1 begins, the power supply voltage Vdd rises from 0V to a predetermined voltage value, the power-on reset signal POR changes from a low level to a high level, and the logic circuit 42 is initialized. Subsequently, the reset period T1 ends as the power-on reset signal POR changes from a high level to a low level, and the memory load period T2 begins.

[0098] During the memory load period T2, various pieces of information stored in the non-volatile memory 71 are transferred to the register 72. After this transfer is complete, the logic circuit 42 changes the oscillation enable signal en_osc from a low level to a high level, ending the memory load period T2 and starting the startup period T3.

[0099] During the startup period T3, the logic circuit 42 gradually increases the capacitance adjustment data trimC1[4:0] and trimC2[4:0] from the starting value to the set value in the normal operation mode by arbitrary values, and the capacitance values ​​C1 and C2 increase in stages accordingly. The starting values ​​of the data trimC1[4:0] and trimC2[4:0] can be set to any value, for example, by writing them in advance to the non-volatile memory 71. In the example in Figure 15, the logic circuit 42 gradually increases the capacitance adjustment data trimC1[4:0] and trimC2[4:0] by 1 from the starting value of 0, and accordingly the capacitance values ​​C1 and C2 decrease by C0 from 31C0. As a result, During the dynamic period T3, the negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner from the second value |nR2|. Lm Larger than, and R Ls Smaller than At that time, oscillator 3 begins to resonate with the main oscillation, and the amplitude of the current I_xtal output from oscillator 3 increases. When the amplitude of current I_xtal exceeds a predetermined threshold, a pulse is generated in the oscillation signal CK. Subsequently, the capacitance adjustment data trimC1[4:0] and trimC2[4:0] increase, and the negative resistance value |nR| becomes R Ls It will be larger than that, At this point, the oscillation of the oscillation circuit 10 due to resonance in the main oscillation of oscillator 3 has grown sufficiently, so resonance in the secondary oscillation of oscillator 3 does not occur. When the capacitance adjustment data trimC1[4:0] and trimC2[4:0] further increase and reach 20, which is the value transferred to register 72 during the memory load period T2, the capacitance values ​​C1 and C2 each become 11C0, and negative The resistance value |nR| becomes the first value |nR1|. Then, the logic circuit 42 holds the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] at 20 and changes the output enable signal en_out from a low level to a high level, thereby ending the startup period T3 and starting the normal operation period T4.

[0100] During the normal operating period T4, the output enable signal en_out is at a high level, so the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0101] Furthermore, during the startup period T3, both capacity values ​​C1 and C2 are decreased by increasing both the capacity adjustment data trimC1[4:0] and trimC2[4:0], Alternatively, one of the capacity adjustment data, trimC1[4:0], trimC2[4:0], may be fixed and the other increased, thereby fixing one of the capacity values ​​C1 and C2 and decreasing the other.

[0102] In the example in Figure 15, the first value |nR1|, which is the set value of the negative resistance |nR| in the normal operating mode, is greater than or equal to the maximum value of the negative resistance |nR| during the startup period T3. That is, during the startup period T3, the negative resistance |nR| does not become greater than the first value |nR1|, so the negative resistance |nR| is equal to the value of the series resistance under load when the oscillator 3 resonates in sub-vibration R. Ls The time during which the value is greater than this is shorter, and resonance in the sub-vibrations of oscillator 3 is less likely to occur. .

[0103] In the example shown in Figure 15, the operating mode during the startup period T3 is the startup mode, and the operating mode during the normal operating period T4 is the normal operating mode. Alternatively, the operating mode during the reset period T1, the memory load period T2, and the startup period T3 is the startup mode.

[0104] Although the sequence diagram is omitted, during the startup period T3, the logic circuit 42 may gradually increase at least one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] from the start value to the end value by any value, and then gradually decrease it by any value to the set value in the normal operation mode.

[0105] The flowchart showing the procedure for controlling the oscillator circuit 2 in the second embodiment is the same as in Figure 12, so its illustration and description are omitted. However, in the second embodiment, the procedure of the startup step S3 in Figure 12 differs from that of the first embodiment.

[0106] Figure 16 is a flowchart showing an example of the procedure for the startup process S3 in Figure 12 in the second embodiment. The procedure shown in Figure 16 corresponds to the operation of the startup period T3 in Figure 15. As shown in Figure 16, first, in process S201, the logic circuit 42 sets the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to their respective starting values. In the example of Figure 15, the starting values ​​are both 0. By setting the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to their respective starting values, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0107] Next, after a predetermined time has elapsed in step S202, in step S203, the logic circuit 42 determines whether the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the set values ​​in the normal operation mode. The set values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] in the normal operation mode are the values ​​stored in the non-volatile memory 71.

[0108] If, in step S203, the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] do not match the set values ​​in normal operation mode, then in step S204, the logic circuit 42 changes the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to decrease the capacitance values ​​C1 and C2.

[0109] Then, steps S202, S203, and S204 are repeated until the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the set values ​​in the normal operating mode. Once the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the set values ​​in the normal operating mode, in step S205, the logic circuit 42 sets the output enable signal en_out to a high level, and the startup step S3 ends.

[0110] Furthermore, the logic circuit 42 fixes one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] values ​​and changes the other value, thereby controlling one of the capacitance values ​​C1 and C2. You may fix one parameter and decrease the other.

[0111] In the oscillator 1 of the second embodiment described above, in the startup mode, by decreasing the capacitance values ​​C1 and C2 of the variable capacitance circuits 14 and 15, the negative resistance value |nR| of the oscillation circuit 10 is Since it gradually increases in a step-like manner from the second value |nR2|, the series resistance value R under load when oscillator 3 resonates in its main vibration is... Lm When it is larger than and the oscillator 3 resonates in secondary vibrations The value of the series resistance R under load Ls The time during which the value is smaller than this becomes longer. Therefore, the vibration Oscillation based on resonance in the main vibration of the rotor 3 develops before oscillation based on resonance in the secondary vibration of the oscillator 3. Therefore, according to the oscillator 1 of the second embodiment, the risk of abnormal oscillation can be reduced even if there is variation in the characteristics of the oscillator 3.

[0112] Furthermore, according to the oscillator 1 of the second embodiment, the variable capacitance circuits 14 and 15 used to set the oscillation frequency of the oscillation circuit 10 to a target frequency in the normal operation mode can also be used to increase the negative resistance value |nR| of the oscillation circuit 10 in the startup mode.

[0113] 3. Third Embodiment Hereinafter, regarding the oscillator 1 of the third embodiment, the same reference numerals will be used for components similar to those in any of the above embodiments, descriptions similar to those in any of the above embodiments will be omitted or simplified, and the description will mainly focus on aspects that differ from any of the above embodiments.

[0114] The configuration of the oscillator 1 in the third embodiment is the same as in Figures 1 to 4, so its illustration and description are omitted. Also, the configuration of the oscillation circuit 10 in the third embodiment is the same as in Figure 5, so its illustration and description are omitted. The oscillator 1 in the third embodiment differs from the oscillator 1 in each of the above embodiments in its operation in the startup mode.

[0115] From equation (1) above, the capacity value C XI ,C XO The smaller at least one of them becomes, the more negative resistance The resistance value |nR| becomes larger. Therefore, in the third embodiment, the voltage control circuit 41 of the control circuit 40 controls at least one of the capacitance values ​​C3 and C4 of the variable capacitance circuits 16 and 17 in the startup mode. By decreasing the value, the negative resistance value |nR| of the oscillation circuit 10 is increased from the second value |nR2|. Specifically, in the startup mode, the voltage control circuit 41 changes the value of at least one of the control voltages Vcnt1 and Vcnt2 output to the oscillation circuit 10, thereby continuously increasing at least one of the capacitance values ​​C3 and C4 of the variable capacitance circuits 16 and 17, thereby increasing the negative resistance value Control |nR| to increase continuously.

[0116] Figure 17 shows an example of the configuration of the voltage control circuit 41 in the third embodiment. As shown in Figure 17, the voltage control circuit 41 includes a control voltage generation circuit 200, a filter circuit 210, a switch circuit 220, a filter circuit 230, a switch circuit 240, a resistor 250, and a resistor 260.

[0117] In normal operation mode, the control voltage generation circuit 200 generates control voltages Vcnt1X and Vcnt2X to change the oscillation frequency of the oscillation circuit 10 according to the voltage level of the frequency control signal supplied from the external terminal VC1 via the VC terminal. In startup mode, the control voltage generation circuit 200 also outputs control voltages Vcnt1X and Vcnt2X in response to the control from the logic circuit 42. Control voltage Vcnt1X is input to the filter circuit 210, and control voltage Vcnt2X is input to the filter circuit 230.

[0118] The filter circuit 210 is a low-pass filter circuit that includes a resistor 211 and a capacitive element 212, and outputs a control voltage Vcnt1f with a gentle rise or fall of the control voltage Vcnt1.

[0119] The switch circuit 220, in response to control from the logic circuit 42, selects and outputs a control voltage Vcnt1X in normal operation mode and a control voltage Vcnt1f in startup mode. The voltage output from the switch circuit 220 is supplied to the variable capacitance circuit 16 in Figure 5 as a control voltage Vcnt1 via the resistor 250.

[0120] The filter circuit 230 is a low-pass filter circuit that includes a resistor 231 and a capacitive element 232, and outputs a control voltage Vcnt2f with a gentle rise or fall of the control voltage Vcnt2.

[0121] The switch circuit 240, in response to control from the logic circuit 42, selects and outputs a control voltage Vcnt2X in normal operation mode and a control voltage Vcnt2f in startup mode. The voltage output from the switch circuit 240 is supplied to the variable capacitance circuit 17 in Figure 5 as a control voltage Vcnt2 via the resistor 260.

[0122] The other components of the oscillator 1 in the third embodiment are the same as those in the embodiments described above, and therefore their illustration and description are omitted.

[0123] Figure 18 is a waveform diagram showing an example of the sequence from when power is supplied to the oscillator circuit 2 to when it transitions to the normal operating mode in the third embodiment. In the example in Figure 18, when power is supplied to the oscillator 1, the reset period T1 begins, the power supply voltage Vdd rises from 0V to a predetermined voltage value, the power-on reset signal POR changes from a low level to a high level, and the logic circuit 42 is initialized. Subsequently, the reset period T1 ends and the memory load period T2 begins as the power-on reset signal POR changes from a high level to a low level.

[0124] During the memory load period T2, various pieces of information stored in the non-volatile memory 71 are transferred to the register 72. After this transfer is complete, the logic circuit 42 changes the oscillation enable signal en_osc from a low level to a high level, ending the memory load period T2 and starting the startup period T3.

[0125] During the startup period T3, under the control of the logic circuit 42, the control voltage generation circuit 200 in the voltage control circuit 41 sets the control voltages Vcnt1X and Vcnt2X to the starting value V start from End value V end The switch circuits 220 and 240 are powered up to the filter circuit 210, The control voltages Vcnt1f and Vcnt2f output from 230 are selected and output. This makes the rise of the control voltages Vcnt1 and Vcnt2 gradual, causing them to increase continuously, and consequently the capacitance values ​​C3 and C4 to increase continuously. It decreases gradually. As a result, during the startup period T3, the negative resistance value |nR| of the oscillation circuit 10 increases continuously from the second value |nR2|. Lm Larger than Kiku, katsu, R Ls When it is smaller than this, oscillator 3 begins to resonate with its principal oscillation, and oscillator 3 The amplitude of the output current I_xtal increases. When the amplitude of current I_xtal exceeds a predetermined threshold, a pulse is generated in the oscillation signal CK. Subsequently, the control voltages Vcnt1 and Vcnt2 increase, and the negative resistance value |nR| increases. Ls It will be larger than that, At this point, the oscillation of the oscillation circuit 10 due to resonance in the main oscillation of oscillator 3 has grown sufficiently, so resonance in the secondary oscillation of oscillator 3 does not occur. The control voltages Vcnt1 and Vcnt2 increase further until the final value V end When it reaches this point, the capacity values ​​C3 and C4 each become predetermined values, and the negative The resistance value |nR| becomes the first value |nR1|. For example, the end value V end From the VC terminal The input frequency control signal voltage value may also be used. Then, the logic circuit 42 changes the output enable signal en_out from a low level to a high level, ending the startup period T3 and starting the normal operation period T4. Note that the starting value V start or end Value V end For example, by writing to the non-volatile memory 71 in advance, It may be possible to set it to any value.

[0126] During the normal operating period T4, the output enable signal en_out is at a high level, so the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0127] Furthermore, during the startup period T3, both control voltages Vcnt1 and Vcnt2 are increased, thereby decreasing both capacitance values ​​C3 and C4. By fixing one of them and increasing the other, one of the capacity values ​​C3 and C4 is fixed and the other is increased. It may be reduced.

[0128] In the example shown in Figure 18, the operating mode during the startup period T3 is the startup mode, and the operating mode during the normal operating period T4 is the normal operating mode. Alternatively, the operating mode during the reset period T1, the memory load period T2, and the startup period T3 is the startup mode.

[0129] Although the sequence diagram is omitted, during the startup period T3, at least one of the control voltages Vcnt1 and Vcnt2 is set to the starting value V start From the final value V end It was continuously increased up to that point. Afterwards, the final value V end From there, continuously up to the voltage value of the frequency control signal input from the VC terminal. It may be changed. For example, the minimum and maximum values ​​of the variable range of the control voltages Vcnt1 and Vcnt2 may be changed from the starting value V start and the final value V end That is also acceptable.

[0130] The flowchart showing the procedure for controlling the oscillator circuit 2 in the third embodiment is the same as in Figure 12, so its illustration and description are omitted. However, in the third embodiment, the procedure of the startup step S3 in Figure 12 differs from that of the above embodiments.

[0131] Figure 19 is a flowchart showing an example of the procedure for the startup process S3 in Figure 12 in the third embodiment. The procedure shown in Figure 19 corresponds to the operation of the startup period T3 in Figure 18. As shown in Figure 19, first, in step S301, the logic circuit 42 sets the switch circuits 220 and 240 of the voltage control circuit 41 to select the output voltages of the filter circuits 210 and 230.

[0132] Next, in step S302, the logic circuit 42 and the control voltage generation circuit 200 of the voltage control circuit 41 set the control voltages Vcnt1X and Vcnt2X to a starting value V start From the final value V end The control is set to change up to this point. This allows the control voltages Vcnt1 and Vcnt2 to It changes continuously from the starting value to the ending value.

[0133] Then, when a predetermined time has elapsed in step S303, in step S304, the logic circuit 42 sets the output enable signal en_out to a high level, and the startup step S3 ends. For example, the predetermined time is when the control voltages Vcnt1 and Vcnt2 are at the starting value V start From the final value V end This is a longer time than the time it takes for it to change, and the filter circuit 210,2 It is determined appropriately based on the time constant of 30.

[0134] Furthermore, the logic circuit 42 fixes one of the control voltages Vcnt1X and Vcnt2X and changes the other, thereby fixing one of the capacitance values ​​C1 and C2 and decreasing the other. That's good too.

[0135] In the oscillator 1 of the third embodiment described above, in the startup mode, by decreasing the capacitance values ​​C3 and C4 of the variable capacitance circuits 16 and 17, the negative resistance value |nR| of the oscillation circuit 10 is Since it increases continuously and gradually from the second value |nR2|, the value of the series resistance under load when oscillator 3 resonates in its main vibration is R Lm Larger than and when oscillator 3 resonates in secondary vibration The value of the series resistance under load R Ls The time during which the value is smaller than this becomes longer. Therefore, the oscillator Oscillation based on resonance in the main vibration of oscillator 3 develops before oscillation based on resonance in the secondary vibration of oscillator 3. Therefore, according to the oscillator 1 of the third embodiment, the risk of abnormal oscillation can be reduced even if there is variation in the characteristics of oscillator 3.

[0136] Furthermore, according to the oscillator 1 of the third embodiment, the variable capacitance circuits 16 and 17 used to change the oscillation frequency of the oscillation circuit 10 by a frequency control signal input from the external terminal VC1 in the normal operation mode can also be used to increase the negative resistance value |nR| of the oscillation circuit 10 in the startup mode.

[0137] 4. Fourth Embodiment Hereinafter, regarding the oscillator 1 of the fourth embodiment, the same reference numerals will be used for components similar to those in any of the above embodiments, descriptions similar to those in any of the above embodiments will be omitted or simplified, and the description will mainly focus on aspects that differ from any of the above embodiments.

[0138] The configuration of the oscillator 1 in the fourth embodiment is the same as in Figures 1 to 4, so its illustration and description are omitted. Also, the configuration of the oscillation circuit 10 in the fourth embodiment is the same as in Figure 5, so its illustration and description are omitted. The oscillator 1 in the fourth embodiment differs from the oscillator 1 in each of the above embodiments in its operation in the startup mode.

[0139] In the fourth embodiment, the logic circuit 42 of the control circuit 40 increases the value of the oscillation stage current Iosc and decreases the capacitance values ​​C1 and C2 of the variable capacitance circuits 14 and 15 in the startup mode. Even without this, decreasing one of them increases the negative resistance value |nR| from the second value |nR2|. For example, in the startup mode, logic circuit 42 changes the value of the oscillation stage current Iosc from the third value to a value greater than the third value without changing the capacitance values ​​C1 and C2 of the variable capacitance circuits 14 and 15. After increasing the value to 4, decrease at least one of the capacitance values ​​C1 and C2 and oscillate. The control to change the value of the stage current Iosc to a third value may be repeated. For example, in startup mode, the logic circuit 42 first holds the value of at least one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] output to the oscillation circuit 10 as the starting value, and then changes the value of the current adjustment data trimI[4:0] output to the oscillation circuit 10 from the starting value to the ending value, thereby increasing the value of the oscillation stage current Iosc in steps from the third value to the fourth value, thereby controlling the negative resistance value |nR| to increase in steps. Next, after changing the value of the current adjustment data trimI[4:0] to the starting value, the logic circuit 42 changes the value of at least one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] and holds it, thereby decreasing at least one of the capacitance values ​​C1 and C2 by one step, and adjusting the current The logic circuit 42 controls the negative resistance value |nR| to increase in a stepwise manner by changing the value of the adjustment data trimI[4:0] from the start value to the end value, thereby increasing the value of the oscillation stage current Iosc in a stepwise manner from the third value to the fourth value. The logic circuit 42 repeats the same control while changing the value of at least one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0]. Finally, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to the start value, and then changes the value of at least one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to the end value and holds it, thereby increasing the capacitance values ​​C1 and C2 in one step. The negative resistance value |nR| is controlled to increase stepwise by decreasing the value of the current adjustment data trimI[4:0] from the start value to the end value, thereby increasing the value of the oscillation stage current Iosc in a stepwise manner from the third value to the fourth value.

[0140] The other components of the oscillator 1 in the fourth embodiment are the same as those in the embodiments described above, and therefore their illustration and description are omitted.

[0141] Figure 20 is a waveform diagram showing another example of the sequence from when power is supplied to the oscillator circuit 2 to when it transitions to the normal operating mode in the fourth embodiment. In the example in Figure 20, when power is supplied to the oscillator 1, the reset period T1 begins, the power supply voltage Vdd rises from 0V to a predetermined voltage value, the power-on reset signal POR changes from a low level to a high level, and the logic circuit 42 is initialized. Subsequently, the reset period T1 ends and the memory load period T2 begins as the power-on reset signal POR changes from a high level to a low level.

[0142] During the memory load period T2, various pieces of information stored in the non-volatile memory 71 are transferred to the register 72. After this transfer is complete, the logic circuit 42 changes the oscillation enable signal en_osc from a low level to a high level, ending the memory load period T2 and starting the startup period T3.

[0143] During the startup period T3, the logic circuit 42 first sets the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to their respective starting values ​​and holds them, then gradually increases the current adjustment data trimI[4:0] from its starting value to its ending value by an arbitrary amount, and the value of the oscillation stage current Iosc increases in stages accordingly. The starting values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0], and the starting and ending values ​​of the current adjustment data trimI[4:0] can be set to arbitrary values, for example, by writing them in advance to the non-volatile memory 71. In the example in Figure 20, the logic circuit 42 sets the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to their respective starting values ​​of 0 and holds them, then gradually increases the current adjustment data trimI[4:0] from its starting value of 0 to its ending value of 31 by 1. As a result, oscillation occurs when the capacitance values ​​C1 and C2 are both 31C0. The stage current Iosc is the third value I b The fourth value is I b Stepped up to +31I0 As it increases, the negative resistance value |nR| of the oscillation circuit 10 increases in a step-like manner from the second value |nR2|.

[0144] Next, the logic circuit 42 changes the current adjustment data trimI[4:0] to its starting value of 0, and then increases the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] by an arbitrary amount. In the example in Figure 20, the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are set to 1, which is the value obtained by increasing them by 1 from 0, and are held there. Then, the current adjustment data trimI[4:0] is increased step by step from the starting value of 0 to the ending value of 31. As a result, the capacitance values ​​C1 and C2 each decrease to 30C0. In this state, the oscillation stage current Iosc is the third value I b The fourth value is I b +31I0 The negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner until it reaches a certain value.

[0145] Next, the logic circuit 42 changes the current adjustment data trimI[4:0] to its starting value of 0, and then increases the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] by an arbitrary amount. In the example in Figure 20, the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are set to 2, which is the value obtained by increasing them by 1 from 1, and are held there. Then, the current adjustment data trimI[4:0] is increased step by step from the starting value of 0 to the ending value of 31. As a result, the capacitance values ​​C1 and C2 each decrease to 29C0. In this state, the oscillation stage current Iosc is the third value I b The fourth value is I b +31I0 The negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner until it reaches R. Lm Larger than, and R Ls When it is smaller than, Oscillator 3 begins to resonate with its primary oscillation, and the amplitude of the current I_xtal output from oscillator 3 increases. When the amplitude of current I_xtal exceeds a predetermined threshold, a pulse is generated in the oscillation signal CK. Subsequently, the capacitance adjustment data trimC1[4:0] and trimC2[4:0] increase, and the negative resistance value |nR| becomes R Ls It will be larger than that, but at that point it will be Because the oscillation of the oscillation circuit 10 due to resonance during the main vibration of the rotor 3 has grown sufficiently, resonance does not occur during the secondary vibration of the oscillator 3.

[0146] Subsequently, when the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] each reach the termination value of 31, and the value of the current adjustment data trimI[4:0] also reaches the termination value of 31, the logic circuit 42 gradually changes the value of the current adjustment data trimI[4:0] from the termination value to the set value in the normal operation mode by any value. The termination values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] may be set to any value by, for example, writing them in advance to the non-volatile memory 71. In the example in Figure 20, the logic circuit 42 gradually decreases the value of the current adjustment data trimI[4:0] from the termination value of 31 by 1. Then, when the value of the current adjustment data trimI[4:0] reaches 24, which is the value transferred to the register 72 during the memory load period T2, the logic circuit 42 holds the value of the current adjustment data trimI[4:0] at 24, and the value of the oscillation stage current Iosc is set to I b This results in +24I0. Furthermore, logic circuit 42 receives capacitance adjustment data. The values ​​of trimC1[4:0] and trimC2[4:0] are changed stepwise from the end value to the set value in normal operation mode by an arbitrary value. In the example in Figure 20, the logic circuit 42 gradually decreases the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] from the end value of 31 by 1 each. When the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] reach 26, which is the value transferred to register 72 during the memory load period T2, the logic circuit 42 holds the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] at 26, and the capacitance values ​​C1 and C2 are Each will be 5C0. The value of the oscillation stage current Iosc is I b It becomes +24I0, and the capacity value As C1 and C2 each become 5C0, the negative resistance value |nR| becomes the first value |nR1 Then, the logic circuit 42 changes the output enable signal en_out from a low level to a high level, ending the startup period T3 and starting the normal operation period T4.

[0147] During the normal operating period T4, the output enable signal en_out is at a high level, so the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0148] Furthermore, during the startup period T3, both capacity values ​​C1 and C2 are decreased by increasing both the capacity adjustment data trimC1[4:0] and trimC2[4:0], Alternatively, one of the capacity adjustment data, trimC1[4:0], trimC2[4:0], may be fixed and the other increased, thereby fixing one of the capacity values ​​C1 and C2 and decreasing the other.

[0149] In the example shown in Figure 20, the operating mode during the startup period T3 is the startup mode, and the operating mode during the normal operating period T4 is the normal operating mode. Alternatively, the operating mode during the reset period T1, the memory load period T2, and the startup period T3 is the startup mode.

[0150] Although the sequence diagram is omitted, in order to shorten the startup period T3, the logic circuit 42 may terminate the startup period T3 by decreasing the value of the current adjustment data trimI[4:0] to the set value in normal operation mode when the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] reach their respective set termination values, and the value of the current adjustment data trimI[4:0] also reaches its termination value. For example, the termination values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] may be the set values ​​in normal operation mode.

[0151] The flowchart showing the procedure for controlling the oscillator circuit 2 in the fourth embodiment is the same as that in Figure 12, so its illustration and description are omitted. However, in the fourth embodiment, the procedure of the startup step S3 in Figure 12 differs from that of the above embodiments.

[0152] Figure 21 is a flowchart showing an example of the procedure for the startup process S3 in Figure 12 in the fourth embodiment. The procedure shown in Figure 21 corresponds to the operation of the startup period T3 in Figure 20. As shown in Figure 21, first, in process S401, the logic circuit 42 sets the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] to starting values. In the example of Figure 20, the starting value of the current adjustment data trimI[4:0] is 0, and the starting values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] are 0. By setting the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] to starting values, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0153] Next, when a predetermined time has elapsed in step S402, in step S403, the logic circuit 42 determines whether the value of the current adjustment data trimI[4:0] matches the end value. In the example in Figure 20, the end value of the current adjustment data trimI[4:0] is 31.

[0154] If the value of the current adjustment data trimI[4:0] in step S403 does not match the final value, in step S404, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to increase the oscillation stage current Iosc.

[0155] Processes S402, S403, and S404 are repeated until the value of the current adjustment data trimI[4:0] matches the end value. Once the value of the current adjustment data trimI[4:0] matches the end value, in process S405, the logic circuit 42 determines whether the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the end value. In the example in Figure 20, the end values ​​for both the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are 31.

[0156] If the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] do not match the end value in step S405, the logic circuit 42 sets the current adjustment data trimI[4:0] to the start value in step S406. Furthermore, in step S407, the logic circuit 42 changes the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to decrease the capacitance values ​​C1 and C2, respectively.

[0157] Processes S402, S403, S404, S405, S406, and S407 are repeated until the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the end value. Once the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the end value, in process S408, the logic circuit 42 changes the current adjustment data trimI[4:0] to the set value in normal operation mode. Furthermore, in process S409, the logic circuit 42 changes the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to the set value in normal operation mode.

[0158] Then, in step S410, the logic circuit 42 sets the output enable signal en_out to a high level, and the startup step S3 ends.

[0159] Furthermore, the logic circuit 42 fixes one of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] values ​​and changes the other value, thereby controlling one of the capacitance values ​​C1 and C2. You may fix one parameter and decrease the other.

[0160] In the oscillator 1 of the fourth embodiment described above, in the startup mode, the value of the oscillation stage current Iosc is increased and the capacitance values ​​C1 and C2 of the variable capacitance circuits 14 and 15 are decreased. As a result, the negative resistance value |nR| of the oscillation circuit 10 gradually increases in a step-like manner from the second value |nR2|, so the series resistance value R under load when the oscillator 3 resonates in its main oscillation. Lm Rather The value of the series resistance R under load when the series resistance is large and the oscillator 3 resonates in secondary vibration.Ls Smaller than The time during which the value is high becomes longer. As a result, oscillation based on resonance in the main vibration of the oscillator 3 grows faster than oscillation based on resonance in the secondary vibration of the oscillator 3. Therefore, according to the oscillator 1 of the fourth embodiment, the risk of abnormal oscillation can be reduced even if there is variation in the characteristics of the oscillator 3.

[0161] In particular, in the oscillator 1 of the fourth embodiment, the logic circuit 42 increases the value of the oscillation stage current Iosc from a third value to a fourth value while changing the capacitance values ​​C1 and C2 of the variable capacitance circuits 14 and 15. The control to apply the current is repeated. Therefore, according to the oscillator 1 of the fourth embodiment, if the capacitance values ​​C1 and C2 of the variable capacitance circuits 14 and 15 are too large, or if the value of the oscillation stage current Iosc is too small, This reduces the risk that the oscillation circuit 10 may not oscillate due to excessive pressure. Furthermore, the logic circuit 42 increases the value of the oscillation stage current Iosc from the third value to the fourth value, and then changes the value of the oscillation stage current Iosc back to the third value before decreasing the capacitance values ​​C1 and C2. When capacitance values ​​C1 and C2 are decreased, the negative resistance value |nR| increases rapidly, and oscillator 3 This reduces the risk of resonance due to secondary vibrations.

[0162] Furthermore, according to the oscillator 1 of the fourth embodiment, the variable current source 12 for setting the oscillation stage current Iosc to a desired value corresponding to the resonant frequency of the oscillator 3 in the normal operating mode, and the variable capacitance circuits 14 and 15 for setting the oscillation frequency of the oscillation circuit 10 to a target frequency, can be used concurrently to increase the negative resistance value |nR| of the oscillation circuit 10 in the startup mode.

[0163] 5. Fifth Embodiment In the following description of the oscillator 1 of the fifth embodiment, components similar to those in any of the above embodiments will be denoted by the same reference numerals, descriptions similar to those in any of the above embodiments will be omitted or simplified, and the description will mainly focus on aspects that differ from any of the above embodiments.

[0164] The structure of the oscillator 1 in the fifth embodiment is the same as in Figures 1 to 3, so its illustration and description are omitted.

[0165] Figure 22 is a functional block diagram of the oscillator 1 of the fifth embodiment. As shown in Figure 22, the oscillator 1 of the fifth embodiment includes an oscillation circuit 2 and a resonator 3, similar to the embodiments described above. The oscillation circuit 2 includes an oscillation circuit 10, a power supply circuit 20, a power-on reset circuit 30, a control circuit 40, a reference voltage generation circuit 50, an output circuit 60, and a memory circuit 70, similar to the embodiments described above, but unlike the embodiments described above, it also includes an oscillation detection circuit 80. Note that the oscillation circuit 2 may have some of these elements omitted or modified, or other elements added.

[0166] In startup mode, the oscillation detection circuit 80 detects when the signal output from the oscillator 3 exceeds a predetermined amplitude and outputs a detection signal DET.

[0167] The logic circuit 42 of the control circuit 40 sets the negative resistance value |nR| of the oscillation circuit 10 to a first value |nR1| based on the detection signal DET.

[0168] Figure 23 shows an example configuration of the oscillation detection circuit 80. In the example in Figure 23, the oscillation detection circuit 80 includes a current source 300, three capacitive elements 301, 314, and 315, three variable resistors 302, 303, and 304, six N-channel MOS transistors 305, 306, 307, 308, 309, and 313, a comparator 310, and two CMOS inverters 311 and 312.

[0169] The current source 300 has a voltage Vreg supplied to one end and the other end connected to the drain of an N-channel MOS transistor 305.

[0170] The gate of N-channel MOS transistor 305 is connected to the gates of N-channel MOS transistor 307 and N-channel MOS transistor 309, and the sources of N-channel MOS transistors 305, 307, and 309 are grounded.

[0171] The drain of N-channel MOS transistor 307 is connected to the source of N-channel MOS transistor 306, and the drain of N-channel MOS transistor 309 is connected to the source of N-channel MOS transistor 308.

[0172] The variable resistor 304 has a voltage Vreg supplied to one end and the other end connected to one end of the variable resistor 303. The other end of the variable resistor 303 is connected to one end of the variable resistor 302, and the other end of the variable resistor 302 is grounded.

[0173] Capacitive element 301 has one end connected to terminal XI, and the other end connected to the other end of variable resistor 303, one end of variable resistor 302, and the gate of N-channel MOS transistor 306. The signal output from oscillator 3 is input to terminal XI.

[0174] The gate of the N-channel MOS transistor 308 is connected to the other end of the variable resistor 304 and one end of the variable resistor 303, and a voltage Vreg is supplied to the drains of the N-channel MOS transistors 306 and 308.

[0175] Comparator 310 has an inverting input terminal connected to the source of an N-channel MOS transistor 308 and one end of a capacitive element 315, and a non-inverting input terminal connected to the source of an N-channel MOS transistor 306 and one end of a capacitive element 314. The other end of capacitive element 314 and the other end of capacitive element 315 are grounded.

[0176] The output terminal of the comparator 310 is connected to the input terminal of the CMOS inverter 311 and the gate of the N-channel MOS transistor 313, and the output terminal of the CMOS inverter 311 is connected to the input terminal of the CMOS inverter 312. The source and drain of the N-channel MOS transistor 313 are connected to one end and the other end of the variable resistor 303, respectively.

[0177] In the oscillation detection circuit 80 configured as described above, a voltage V2 = Vreg×(R1 + R2) / (R1 + R2 + R3) obtained by dividing the voltage Vreg by the variable resistors 302, 303, and 304 is input to the gate of the N-channel MOS transistor 306. R1, R 2, and R3 are the resistance values of the variable resistors 302, 303, and 304, respectively. Also, a voltage V1 obtained by adding a voltage Vreg×R1 / (R1 + R2 + R3) obtained by dividing the voltage Vreg by the variable resistors 302, 303, and 304 and an AC component obtained by removing the DC component of the signal input from the XI terminal by the capacitive element 3 01 is input to the gate of the N-channel MOS transistor 306. Therefore, a voltage V2 - V is input to the inverting input terminal of the comparator 310, and a voltage V1 - V gs2 is input to the non-inverting input terminal of the comparator 310. V gs 1. V gs1 is the voltage between the gate and source of the N-channel MOS transistor 306, and V is the voltage between the gate and source of the N-channel MOS transistor 308. gs2 is the voltage between the gate and source of the N-channel MOS transistor 308. is the voltage between the gate and source of the N-channel MOS transistor 308.

[0178] The comparator 310 outputs a low-level signal when the voltage V1 - V gs1 is lower than the voltage V2 - V<000​​​​​​​​Outputs a high-level signal. The output signal of comparator 310 is inverted in logic level by CMOS inverter 311 and further inverted in logic level by CMOS inverter 312. Then, since the output signal of CMOS inverter 312 is output to logic circuit 42 as detection signal DET, the logic level of detection signal DET is the same as the logic level of the output signal of comparator 310. Therefore, detection signal DET is at a low level when voltage V1-V gs1 is lower than voltage V2-V gs2 and is at a high level when voltage V1-V gs1 is higher than voltage V2-V gs2 . At the start point of the startup mode , since the amplitude of the signal output from oscillator 3 and input from terminal XI is zero, voltage V1-V gs1 is lower than voltage V2-V gs2 , so detection signal DET is at a low level . As the amplitude of the signal input from terminal XI increases, the DC level of voltage V1-V gs1 increases while the instantaneous voltage fluctuation is suppressed by capacitive elements 314 and 315 . Then, when voltage V1-V gs1 becomes higher than voltage V2-V gs2 , the output signal of comparator -310 changes to a high level, and detection signal DET also changes to a high level. When detection signal DET changes from a low level to a high level, logic circuit 42 sets the negative resistance value |nR| of oscillation circuit 10 to the first value |nR1|. Also, when the output signal of comparator 310 becomes high level, the drain-source of N-channel MOS transistor 313 conducts, the difference between voltage V1 and voltage V2 disappears, the output signal of comparator 310 maintains a high level, and detection signal DET also maintains a high level.

[0179] According to this oscillation detection circuit 80, voltages V1 and V2 are those of variable resistors 302, 303, and 304 Since it is determined by the ratio rather than the absolute values of the resistance values R1, R2, and R3 instead of the absolute value, the variable resistor 30 The errors of the voltages V1 and V2 due to the manufacturing errors of 2,303,304 are small, and from the vibrator 3 The amplitude of the signal output can be detected with high accuracy.

[0180] Since the other configurations of the oscillator 1 of the fifth embodiment are the same as those of the above embodiments, the illustration and description thereof are omitted.

[0181] FIG. 24 is a waveform diagram showing another example of a sequence for shifting to the normal operation mode after the power is turned on in the oscillation circuit 2 in the fifth embodiment. In the example of FIG. 24, when the power is turned on to the oscillator 1, the reset period T1 starts, the power supply voltage Vdd rises from 0V to a predetermined voltage value, the power-on reset signal POR changes from the low level to the high level, and the logic circuit 42 is initialized. Thereafter, when the power-on reset signal POR changes from the high level to the low level, the reset period T1 ends and the memory load period T2 starts.

[0182] During the memory load period T2, various types of information stored in the non-volatile memory 71 are transferred to the register 72. After this transfer is completed, the logic circuit 42 changes the oscillation enable signal en_osc from the low level to the high level, so that the memory load period T2 ends and the startup period T3 starts.

[0183] During the startup period T3, the logic circuit 42 first sets the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to their respective starting values ​​and holds them, then gradually increases the current adjustment data trimI[4:0] from its starting value to its ending value by an arbitrary amount, and the value of the oscillation stage current Iosc increases in stages accordingly. The starting values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0], and the starting and ending values ​​of the current adjustment data trimI[4:0] can be set to arbitrary values, for example, by writing them in advance to the non-volatile memory 71. In the example in Figure 24, the logic circuit 42 sets the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to their respective starting values ​​of 0 and holds them, then gradually increases the current adjustment data trimI[4:0] from its starting value of 0 to its ending value of 31 by 1. As a result, with capacitance values ​​C1 and C2 each at 31C0, oscillation occurs. The stage current Iosc is the third value I b The fourth value is I b Stepped up to +31I0 As it increases, the negative resistance value |nR| of the oscillation circuit 10 increases in a step-like manner from the second value |nR2|.

[0184] Next, the logic circuit 42 changes the current adjustment data trimI[4:0] to its starting value of 0, and then increases the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] by an arbitrary amount. In the example in Figure 24, the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are set to 1, which is the value obtained by increasing them by 1 from 0, and are held there. Then, the current adjustment data trimI[4:0] is increased step by step from the starting value of 0 to the ending value of 31. As a result, the capacitance values ​​C1 and C2 each decrease to 30C0. In this state, the oscillation stage current Iosc is the third value I b The fourth value is I b +31I0 The negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner until it reaches a certain value.

[0185] Next, the logic circuit 42 changes the current adjustment data trimI[4:0] to its starting value of 0, and then increases the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] by an arbitrary amount. In the example in Figure 24, the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are set to 2, which is the value obtained by increasing them by 1 from 1, and are held there. Then, the current adjustment data trimI[4:0] is increased step by step from the starting value of 0 to the ending value of 31. As a result, the capacitance values ​​C1 and C2 each decrease to 29C0. In this state, the oscillation stage current Iosc is the third value I b The fourth value is I b +31I0 The negative resistance value |nR| of the oscillation circuit 10 increases in a stepwise manner until it reaches R. Lm Larger than, and R Ls When it is smaller than, When oscillator 3 begins to resonate with its primary oscillation, the amplitude of the current I_xtal output from oscillator 3 increases. When the amplitude of current I_xtal exceeds a predetermined threshold, a pulse is generated in the oscillation signal CK. Furthermore, when the amplitude of current I_xtal output from oscillator 3 reaches a predetermined value, for example, when the value of the current adjustment data trimI[4:0] is 9 and the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are both 2, the detection signal DET changes from a low level to a high level.

[0186] Next, in response to the detection signal DET becoming high, the logic circuit 42 gradually changes the value of the current adjustment data trimI[4:0] in increments of an arbitrary value up to the set value in normal operation mode. In the example in Figure 24, the value of the current adjustment data trimI[4:0] when the detection signal DET becomes high is 9, so the logic circuit 42 gradually increases the value of the current adjustment data trimI[4:0] from 9 in increments of 1. Then, when the value of the current adjustment data trimI[4:0] reaches 24, which is the value transferred to the register 72 during the memory load period T2, the logic circuit 42 holds the value of the current adjustment data trimI[4:0] at 24, and the value of the oscillation stage current Iosc becomes I b This results in +24I0. Furthermore, the logic Circuit 42 gradually changes the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] in increments of an arbitrary value up to the set value in the normal operating mode. In the example in Figure 24, when the detection signal DET becomes high level, the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are each 2, so logic circuit 42 gradually increases the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] from 2 in increments of 1. When the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] reach 26, which is the value transferred to register 72 during the memory load period T2, logic circuit 42 holds the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] at 26, and the capacitance values ​​C1 and C2 become 5C0, respectively. Oscillation The value of the stage current Iosc is I b The result is +24I0, and the capacitance values ​​C1 and C2 are each 5C0. As a result, the negative resistance |nR| becomes the first value |nR1|. Ls It will be larger than that, but at that point the oscillator 3 Because the oscillation of the oscillation circuit 10 due to resonance in the main oscillation has grown sufficiently, resonance does not occur in the secondary oscillation of the oscillator 3. Then, the logic circuit 42 changes the output enable signal en_out from a low level to a high level, ending the startup period T3 and starting the normal operation period T4.

[0187] During the normal operating period T4, the output enable signal en_out is at a high level, so the oscillation signal CK is buffered and a pulse is generated in the oscillation signal CKO.

[0188] Furthermore, during the startup period T3, both capacity values ​​C1 and C2 are decreased by increasing both the capacity adjustment data trimC1[4:0] and trimC2[4:0], Alternatively, one of the capacity adjustment data, trimC1[4:0], trimC2[4:0], may be fixed and the other increased, thereby fixing one of the capacity values ​​C1 and C2 and decreasing the other.

[0189] In the example shown in Figure 24, the operating mode during the startup period T3 is the startup mode, and the operating mode during the normal operating period T4 is the normal operating mode. Alternatively, the operating mode during the reset period T1, the memory load period T2, and the startup period T3 is the startup mode.

[0190] The flowchart showing the procedure for controlling the oscillator circuit 2 in the fifth embodiment is the same as that in Figure 12, so its illustration and description are omitted. However, in the fifth embodiment, the procedure of the startup step S3 in Figure 12 differs from that of the above embodiments.

[0191] Figure 25 is a flowchart showing an example of the procedure for the startup process S3 in Figure 12 in the fifth embodiment. The procedure shown in Figure 25 corresponds to the operation of the startup period T3 in Figure 24. As shown in Figure 25, first, in process S501, the logic circuit 42 sets the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] to starting values. In the example of Figure 24, the starting value of the current adjustment data trimI[4:0] is 0, and the starting values ​​of the capacitance adjustment data trimC1[4:0], trimC2[4:0] are 0. By setting the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] to starting values, the negative resistance value |nR| of the oscillation circuit 10 becomes the second value |nR2|.

[0192] Next, when a predetermined time has elapsed in step S502, if the detection signal DET is at a low level in step S503, the logic circuit 42 determines in step S504 whether the value of the current adjustment data trimI[4:0] matches the end value. In the example in Figure 24, the end value of the current adjustment data trimI[4:0] is 31.

[0193] If the value of the current adjustment data trimI[4:0] in step S504 does not match the final value, in step S505, the logic circuit 42 changes the value of the current adjustment data trimI[4:0] to increase the oscillation stage current Iosc.

[0194] As long as the detection signal DET is at a low level in step S503, steps S502, S504, and S505 are repeated until the value of the current adjustment data trimI[4:0] matches the end value. When the value of the current adjustment data trimI[4:0] matches the end value, in step S506, the logic circuit 42 determines whether the values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the end value. In the example in Figure 24, the end values ​​of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] are both 31.

[0195] In step S506, if the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] do not match the end values, in step S507, the logic circuit 42 sets the current adjustment data trimI[4:0] to the start value. Further, in step S508, the logic circuit 42 changes the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to decrease the capacitance values C1 and C2 respectively.

[0196] As long as the detection signal DET is at the low level in step S503, steps S502, S504, S505, S506, S507, and S508 are repeated until the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] match the end values.

[0197] If the detection signal DET is at the high level in step S503, or if the values of the capacitance adjustment data trimC 1[4:0] and trimC2[4:0] match the end values in step S506, in step S509, the logic circuit 42 changes the current adjustment data trimI[4:0] to the set value in the normal operation mode. Further, in step S510, the logic circuit 42 changes the capacitance adjustment data trimC1[4:0] and trimC2[4:0] to the set values in the normal operation mode.

[0198] Then, in step S511, the logic circuit 42 sets the output enable signal en_out to the high level, and the startup step S3 ends.

[0199] Note that the logic circuit 42 may fix one of the values of the capacitance adjustment data trimC1[4:0] and trimC2[4:0] and change the other value to fix one of the capacitance values C1 and C2 and decrease the other. and decrease the other.

[0200] Figures 24 and 25 correspond to the sequence and flowchart when an oscillation detection circuit 80 is added to the oscillator 1 of the fourth embodiment. Although the sequence and flowchart are not shown here, an oscillation detection circuit 80 may also be added to the oscillator 1 of the first to third embodiments.

[0201] In the oscillator 1 of the fifth embodiment described above, in the startup mode, when the oscillation detection circuit 80 detects that the signal output from the oscillator 3 has reached a predetermined amplitude or higher, it sets the negative resistance value |nR| to a first value |nR1| and transitions to the normal operation mode, thereby shortening the startup time.

[0202] 6. Sixth Embodiment Hereinafter, regarding the oscillator 1 of the sixth embodiment, the same reference numerals will be used for components similar to those in any of the above embodiments, descriptions similar to those in any of the above embodiments will be omitted or simplified, and the description will mainly focus on aspects that differ from any of the above embodiments.

[0203] The configuration of the oscillator 1 in the sixth embodiment is the same as in Figures 1 to 4, so its illustration and description are omitted. Similarly, the configuration of the oscillation circuit 10 in the fourth embodiment is the same as in Figure 5, so its illustration and description are omitted.

[0204] In each of the above embodiments, in the startup mode, the negative resistance value |nR| of the oscillation circuit 10 is controlled based on weighted multi-bit control data output from the control circuit 40.

[0205] For example, in the first or fourth embodiment, in startup mode, the negative resistance value |nR| is controlled by the current adjustment data trimI[4:0], which is control data where larger bits have greater weight. For example, when the logic level of trimI[0] is inverted, the oscillation stage current Iosc increases or decreases by I0, whereas when the logic level of trimI[4] is inverted, the oscillation stage current Iosc increases or decreases by 16 × I0. Therefore, for example, when the current adjustment data trimI[4:0] changes from 15 to 16, if trimI[4] changes from a high level to a low level before trimI[0], trimI[1], trimI[2], and trimI[3] each change from a high level to a low level, the oscillation stage current Iosc will instantaneously increase by 16 × I0. As a result, the negative resistance value |nR| becomes the value of the series resistance under load R when the oscillator 3 resonates in sub-vibration. Ls When it becomes larger than that, oscillator 3 sub The risk of abnormal oscillation occurring due to resonance caused by vibration increases.

[0206] Furthermore, in the second or fourth embodiment, for example, in the startup mode, the negative resistance value |nR| is controlled by the capacitance adjustment data trimC1[4:0] and trimC2[4:0], where larger bits have greater weight. For example, when the logic levels of trimC1[0] and trimC2[0] are inverted, the capacitance values ​​C1 and C2 increase or decrease by C0, respectively. In contrast, when the logical levels of trimC1[4] and trimC2[4] are reversed, the capacity values ​​C1 and C2 increase or decrease by 16 × C0, respectively. Therefore, for example, capacity adjustment data t When rimC1[4:0] and trimC2[4:0] change from 15 to 16, if trimC1[4] changes from a high level to a low level before trimC1[0], trimC1[1], trimC1[2], and trimC1[3] each change from a high level to a low level, the capacity value C1 will instantaneously increase by 16 × C0. Therefore, the negative resistance value |nR| is the same as the series resistance value R under load when oscillator 3 resonates in secondary vibration. LsIf the value becomes larger than this, the risk of oscillator 3 resonating due to secondary vibrations and causing abnormal oscillation increases. The same can be said for the volume adjustment data trimC2[4:0].

[0207] Therefore, in the sixth embodiment, in order to reduce the risk of abnormal oscillation, the control circuit 40 is configured such that, in the startup mode, the control data for controlling the negative resistance value |nR| of the oscillation circuit 10 changes the logic level faster for bits with smaller weighting.

[0208] Figure 26 shows an example of the configuration of the control circuit 40 in the sixth embodiment. Figure 26 shows an example of the configuration of the control circuit 40 when the control data for controlling the negative resistance value |nR| of the oscillation circuit 10 in startup mode is the current adjustment data trimI[4:0]. In the example of Figure 26, the control circuit 40 includes a logic circuit 42 and 10 delay circuits 411, 421, 422, 431, 432, 433, 441, 442, 443, and 444. As with the embodiments described above, the control circuit 40 also includes a voltage control circuit 41, but it is not shown in Figure 26.

[0209] The logic circuit 42 outputs current adjustment data trimIX[4:0]. trimIX[0] is output as trimI[0]. trimIX[1] is output as trimI[1] after propagating through the delay circuit 411. trimIX[2] is output as trimI[2] after propagating through the delay circuits 421 and 422. trimIX[3] is output as trimI[3] after propagating through the delay circuits 431, 432, and 433. trimIX[4] is output as trimI[4] after propagating through delay circuits 441, 442, 443, and 444.

[0210] The delay circuits 411, 421, 422, 431, 432, 433, 441, 442, 443, and 444 are circuits in which four CMOS inverters 401, 402, 403, and 404 are connected in series, as shown in Figure 27, for example. Note that the number of CMOS inverters is not limited to four; any even number is acceptable.

[0211] Figure 28 shows an example of the waveforms of each bit in the current adjustment data trimIX[4:0] and trimI[4:0]. In the example in Figure 28, the waveforms of each bit are shown when the current adjustment data trimIX[4:0] changes from 15 to 16.

[0212] In the example in Figure 28, the logic level of each bit in the current adjustment data trimIX[4:0] changes simultaneously at time t1. Specifically, trimIX[0], trimIX[1], trimIX[2], and trimIX[3] each change from high to low levels, while trimIX[4] changes from low to high levels.

[0213] Since trimIX[0] is output as trimI[0] without propagating through the delay circuit, at time t1, trimI[0] changes from a high level to a low level. Also, after time t1, the low level of trimIX[1] propagates through delay circuit 411, and at time t2, trimI[1] changes from a high level to a low level. Also, after time t1, the low level of trimIX[2] propagates through delay circuits 421 and 422, and at time t3, trimI[2] changes from a high level to a low level. Also, after time t1, the low level of trimIX[3] propagates through delay circuits 431, 432, and 433, and at time t4, trimI[3] changes from a high level to a low level. Furthermore, after time t1, the high level of trimIX[4] propagates through delay circuits 441, 442, 443, and 444, and at time t5, trimI[4] then changes from a low level to a high level.

[0214] Thus, the current adjustment data trimI[4:0] output to the oscillation circuit 10 changes in the order of trimI[0], trimI[1], trimI[2], trimI[3], trimI[4], meaning that the logic level changes faster for bits with smaller weights.

[0215] Although not shown in the diagram, the control circuit 40 in the startup mode, when the control data for controlling the negative resistance value |nR| of the oscillation circuit 10 is the capacitance adjustment data trimC1[4:0], trimC2[4:0], is configured in the same way as in Figure 26.

[0216] The other components of the oscillator 1 in the sixth embodiment are the same as those in the embodiments described above, and therefore their illustration and description are omitted.

[0217] In the oscillator 1 of the sixth embodiment described above, when the negative resistance value |nR| of the oscillation circuit 10 is increased in the startup mode, the logic level of the current adjustment data trimI[4:0] and the capacitance adjustment data trimC1[4:0], trimC2[4:0] changes faster for bits with smaller weighting. Therefore, according to the oscillator 1 of the sixth embodiment, when the negative resistance value |nR| of the oscillation circuit 10 is increased, the negative resistance value |nR| does not increase rapidly transiently, thus reducing the risk of abnormal oscillation due to the growth of oscillation based on resonance in the sub-vibration of the oscillator 3.

[0218] 7. Seventh Embodiment Hereinafter, regarding the oscillator 1 of the seventh embodiment, the same reference numerals will be used for components similar to those in any of the above embodiments, descriptions similar to those in any of the above embodiments will be omitted or simplified, and the main focus will be on aspects that differ from any of the above embodiments.

[0219] The configuration of the oscillator 1 in the seventh embodiment is the same as in Figures 1 to 4, so its illustration and description are omitted.

[0220] In each of the above embodiments, in the startup mode, the negative resistance value |nR| of the oscillation circuit 10 is controlled based on weighted multi-bit control data output from the control circuit 40. Therefore, as mentioned above, except for the sixth embodiment, the risk of abnormal oscillation occurring due to resonance of the oscillator 3 in sub-vibrations increases.

[0221] Therefore, in the seventh embodiment, in order to reduce the risk of abnormal oscillation, in the startup mode, the negative resistance value |nR| of the oscillation circuit 10 is controlled based on unweighted multi-bit control data output from the control circuit 40. The unweighted multi-bit control data may be data represented by a thermometer code.

[0222] For example, in startup mode, the negative resistance value |nR| may be controlled by controlling the oscillation stage current Iosc output from the variable current source 12 of the oscillation circuit 10 based on unweighted 32-bit current adjustment data trimI[31:0]. Also, for example, in startup mode, the capacitance values ​​C1, C2 of the variable capacitance circuits 14, 15 of the oscillation circuit 10 may be controlled. However, the negative resistance value |nR| may be controlled by being controlled based on unweighted 32-bit capacitance adjustment data trimC1[31:0], trimC2[31:0].

[0223] Figure 29 shows an example configuration of a variable current source 12 controlled by unweighted 32-bit current adjustment data trimI[31:0]. In the example in Figure 29, the variable current source 12 includes a current source 135, 32 current sources 136-0 to 136-31, 32 switch elements 137-0 to 137-31, and two P-channel MOS transistors 133 and 134.

[0224] P-channel MOS transistor 133 has its gate and drain connected, and a voltage Vreg is supplied to its source. P-channel MOS transistor 134 has its gate connected to the gate of P-channel MOS transistor 133, a voltage Vreg is supplied to its source, and its drain is connected to the collector of the amplification element 11 in Figure 5.

[0225] The current source 135 has one end connected to the drain of the P-channel MOS transistor 133 and the other end connected to ground, and a constant bias current I b A current flows. For each integer i between 0 and 31, the current source 136-i has one end connected to the drain of a P-channel MOS transistor 133 via a switch element 137-i, and the other end is grounded, and a constant current I0 flows when the switch element 137-i is conducting. For example, the current sources 135, 136-0 to 136-31 may be constructed using depletion-type N-channel MOS transistors, or they may be constructed using current mirror circuits.

[0226] For each integer i between 0 and 31, the switch element 137-i conducts when the data trimI[i] of bit i of the current adjustment data trimI[31:0] is input to its control terminal, and deconducts when the data trimI[i] is high level, and deconducts when the data trimI[i] is low level. For example, the switch elements 137-0 to 137-31 may be N-channel MOS transistors or transmission gates.

[0227] Figure 30 shows the relationship between the values ​​of each bit in the current adjustment data trimI[31:0] and the value of the oscillation stage current Iosc output from the variable current source 12 shown in Figure 29. A value of 0 in each bit corresponds to a low level, and a value of 1 in each bit corresponds to a high level. For example, if bit 0 of the current adjustment data trimI[31:0] is 1 and bits 1 to 31 are 0, then only the switch element 137-0 conducts and the oscillation stage current Iosc = I b It becomes +I0. Also, for example... For example, if bits 0 and 1 of the current adjustment data trimI[31:0] are 1 and bits 2 through 31 are 0, then only the two switch elements 137-0 and 137-1 conduct, and the oscillation stage current Iosc = I b This becomes +2I0. In general, the current adjustment data trimI[31:0 If N is the number of bits with a value of 1 among the 32 bits of [ ] and 32-N is the number of bits with a value of 0, then the oscillation stage current Iosc = I b It becomes +N×I0. The code shown in Figure 30 is bit The values ​​of bits 0 through 31 are all 0, or the values ​​of bits 0 through 31 are all 1, or for any integer j between 0 and 30 (inclusive), the values ​​of bits 0 through j are all 1 and the values ​​of bits j+1 through 31 are all 0. Such a code is called a thermometer code.

[0228] Although not shown in the diagram, in startup mode, the capacitance values ​​C1 and C2 of the variable capacitance circuits 14 and 15 of the oscillator circuit 10 are adjusted using unweighted 32-bit capacitance adjustment data trimC1. The variable capacitance circuits 14 and 15, and the codes for the capacitance adjustment data trimC1[31:0] and trimC2[31:0], when controlled based on [31:0] and trimC2[31:0], are configured in the same way as in Figures 29 and 30.

[0229] The other components of the oscillator 1 in the seventh embodiment are the same as those in the embodiments described above, and therefore their illustration and description are omitted.

[0230] In the oscillator 1 of the seventh embodiment described above, when the negative resistance value |nR| of the oscillation circuit 10 is increased in the startup mode, the current adjustment data trimI[31:0] and the capacitance adjustment data trimC1[31:0], trimC2[31:0] are unweighted data, for example, data represented by thermometer codes. Therefore, according to the oscillator 1 of the seventh embodiment, when the negative resistance value |nR| of the oscillation circuit 10 is increased, the negative resistance value |nR| does not increase rapidly transiently, thus reducing the risk of abnormal oscillation due to the growth of oscillation based on resonance in the sub-vibration of the oscillator 3.

[0231] 8. Variations In the oscillator 1 of the first or fourth embodiment described above, the logic circuit 42 controls the negative resistance value |nR| to increase in a step-like manner by increasing the value of the oscillation stage current Iosc in a step-like manner during the startup mode. However, the negative resistance value |nR| may also be controlled to increase continuously by continuously increasing the value of the oscillation stage current Iosc.

[0232] Furthermore, in the oscillator 1 of the second or fourth embodiment described above, the logic circuit 42, in startup mode, sets at least one of the capacitance values ​​C1 and C2 of the variable capacitance circuits 14 and 15 to a static state. By increasing it in a step-like manner, the negative resistance value |nR| is controlled to increase in a step-like manner, but at least one of the capacitance values ​​C1 and C2 of the variable capacitance circuits 14 and 15 is continuously increased. By doing so, the negative resistance value |nR| may be controlled to increase continuously.

[0233] Furthermore, the oscillator 1 in each of the above embodiments is an oscillator having a frequency control function such as a VCXO (Voltage Controlled Crystal Oscillator), but it may also be an oscillator having a temperature compensation function such as a TCXO (Temperature Compensated Crystal Oscillator), an oscillator having both a temperature compensation function and a frequency control function such as a VC-TCXO (Voltage Controlled Temperature Compensated Crystal Oscillator), a simple oscillator without a temperature compensation function and a frequency control function such as an SPXO (Simple Packaged Crystal Oscillator), or an oscillator having a temperature control function such as an OCXO (Oven Controlled Crystal Oscillator). VCXO is an abbreviation for Voltage Controlled Crystal Oscillator. TCXO is an abbreviation for Temperature Compensated Crystal Oscillator. VC-TCXO is an abbreviation for Voltage Controlled Temperature Compensated Crystal Oscillator. SPXO is an abbreviation for Simple Packaged Crystal Oscillator. OCXO stands for Oven Controlled Crystal Oscillator. If oscillator 1 is an oscillator with a temperature compensation function or an oscillator with both a temperature compensation function and a frequency control function, in startup mode, the temperature compensation circuit may increase the negative resistance value by decreasing the capacitance value of the variable capacitance circuit.

[0234] The present invention is not limited to this embodiment, and various modifications can be implemented within the scope of the gist of the present invention.

[0235] The embodiments and variations described above are examples only and are not limited thereto. For example, each embodiment and each variation can be combined as appropriate.

[0236] The present invention includes configurations substantially identical to those described in the embodiments, for example, configurations with the same function, method, and results, or configurations with the same purpose and effect. Furthermore, the present invention includes configurations in which non-essential parts of the configurations described in the embodiments are replaced. Furthermore, the present invention includes configurations that produce the same effects or achieve the same purpose as those described in the embodiments. Finally, the present invention includes configurations that add known technology to the configurations described in the embodiments.

[0237] The following can be derived from the embodiments and modifications described above.

[0238] One embodiment of an oscillator circuit is: An oscillator circuit connected to the vibrator, The system includes a control circuit for controlling the oscillation circuit, The oscillation circuit has a normal operating mode in which it oscillates when the negative resistance value is a first value, The system includes a startup mode from the state in which the oscillation circuit has stopped oscillating until it transitions to the normal operation mode, The aforementioned control circuit is In the startup mode, the negative resistance value is controlled to increase from a second value that is smaller than the first value.

[0239] In this oscillator circuit, during the startup mode, from the state where the oscillator circuit has stopped oscillating to the normal operating mode where it oscillates with the negative resistance value of the oscillator circuit at a first value, the negative resistance value of the oscillator circuit increases from a second value which is smaller than the first value. The value of the series resistance under load when the oscillator resonates in its main oscillation is R. Lm This is the load when the oscillator resonates in a secondary vibration. Series resistance at time of time, ERR Ls Since it is smaller than the second value, the negative resistance value of the oscillation circuit increases from the second value. And, R Lm Larger than, and R Ls It will be a smaller value than that. Therefore, the startup mode In this configuration, oscillation based on resonance in the oscillator's primary vibration develops before oscillation based on resonance in the oscillator's secondary vibration. Therefore, this oscillation circuit can reduce the risk of abnormal oscillation even if there are variations in the characteristics of the connected oscillators.

[0240] In one embodiment of the oscillator circuit, The aforementioned control circuit is In the startup mode, the negative resistance value may be controlled to increase in a step-like manner.

[0241] In this oscillator circuit, in the startup mode, the negative resistance value of the oscillator circuit increases stepwise from the second value, so R Lm Larger than, and R Ls Time that is smaller than The duration becomes longer. As a result, oscillations based on resonance in the oscillator's primary vibration grow faster than oscillations based on resonance in the oscillator's secondary vibration. Therefore, this oscillation circuit can reduce the risk of abnormal oscillations even if there are variations in the characteristics of the connected oscillators.

[0242] In one embodiment of the oscillator circuit, The aforementioned control circuit is In the startup mode, the negative resistance value may be controlled to increase continuously.

[0243] In this oscillator circuit, in the startup mode, the negative resistance value of the oscillator circuit increases continuously from the second value, so R Lm Larger than, and R Ls The time when the value is smaller than The oscillation becomes longer. As a result, oscillation based on resonance in the oscillator's primary oscillation grows faster than oscillation based on resonance in the oscillator's secondary oscillation. Therefore, this oscillation circuit can reduce the risk of abnormal oscillation even if there are variations in the characteristics of the connected oscillators.

[0244] In one embodiment of the oscillator circuit, The first value may be greater than or equal to the maximum value of the negative resistance in the startup mode.

[0245] According to this oscillator circuit, in the startup mode, the negative resistance value of the oscillator circuit does not exceed the first value, so the negative resistance value of the oscillator circuit is equal to the series resistance value R under load when the oscillator resonates in sub-vibration. Ls The time for which the value is greater than this is short, and the resonance in the oscillator's sub-vibrations is good. It is less likely to happen.

[0246] In one embodiment of the oscillator circuit, The oscillation circuit includes an amplifying element and a variable current source that supplies current to the amplifying element. The control circuit may increase the negative resistance value by increasing the value of the current in the startup mode.

[0247] With this oscillation circuit, for example, a variable current source used to set the current supplied to the amplifying element to a desired value corresponding to the resonant frequency of the oscillator in the normal operating mode can also be used to increase the negative resistance value of the oscillation circuit in the startup mode.

[0248] In one embodiment of the oscillator circuit, The oscillation circuit includes a variable capacitance circuit connected to a node connected to the oscillator, and the control circuit may increase the negative resistance value by decreasing the capacitance value of the variable capacitance circuit in the startup mode.

[0249] With this oscillator circuit, for example, the variable capacitance circuit used to set the oscillation frequency of the oscillator circuit to a target frequency in the normal operating mode can also be used to increase the negative resistance value of the oscillator circuit in the startup mode.

[0250] In one embodiment of the oscillator circuit, The oscillation circuit includes an amplifying element, a variable current source that supplies current to the amplifying element, and a variable capacitance circuit connected to a node connected to the oscillator. The control circuit may increase the negative resistance value in the startup mode by increasing the value of the current and decreasing the capacitance value of the variable capacitance circuit.

[0251] This oscillator circuit allows, for example, a variable current source used to set the current supplied to the amplifying element to a desired value corresponding to the resonant frequency of the oscillator in the normal operating mode, and a variable capacitance circuit used to set the oscillation frequency of the oscillator circuit to a target frequency, to be used concurrently to increase the negative resistance value of the oscillator circuit in the startup mode. Furthermore, this oscillator circuit increases the value of the current supplied to the amplifying element and decreases the capacitance value of the variable capacitance circuit in the startup mode, thereby reducing the risk that the oscillator circuit will not oscillate due to the capacitance value of the variable capacitance circuit being too large or the value of the current supplied to the amplifying element being too small.

[0252] In one embodiment of the oscillator circuit, The control circuit may, in the startup mode, repeatedly perform a control that increases the current value from a third value to a fourth value greater than the third value without changing the capacitance value, and then decreases the capacitance value and changes the current value to the third value.

[0253] In this oscillation circuit, during startup mode, the control repeatedly increases the value of the current supplied to the amplifying element from a third value to an upper limit while changing the capacitance value of the variable capacitor circuit. This reduces the risk that the oscillation circuit will not oscillate due to the capacitance value of the variable capacitor circuit being too large or the value of the current supplied to the amplifying element being too small. Furthermore, in this oscillation circuit, after the control circuit increases the value of the current supplied to the amplifying element from a third value to a fourth value, it changes the value of the current supplied to the amplifying element back to a third value before decreasing the capacitance value of the variable capacitor circuit. This reduces the risk that the negative resistance value will increase sharply when the capacitance value of the variable capacitor circuit is decreased, causing the oscillator to resonate with secondary vibrations.

[0254] One embodiment of the oscillator circuit is: In the startup mode, the system includes an oscillation detection circuit that detects when the signal output from the oscillator exceeds a predetermined amplitude and outputs a detection signal. The control circuit may set the negative resistance value to the first value based on the detection signal.

[0255] According to this oscillator circuit, when the oscillator circuit oscillates in startup mode, the negative resistance value is set to a first value and the system transitions to normal operation mode, thus shortening the startup time.

[0256] In one embodiment of the oscillator circuit, The negative resistance value is controlled based on weighted multi-bit control data. The control data may change in logic level faster for bits with smaller weights.

[0257] With this oscillation circuit, when the negative resistance value of the oscillation circuit is increased, the negative resistance value does not increase rapidly transiently, thus reducing the risk of abnormal oscillation due to the growth of oscillation based on resonance in the sub-vibrations of the oscillator.

[0258] In one embodiment of the oscillator circuit, The negative resistance value may be controlled based on unweighted multi-bit control data.

[0259] With this oscillation circuit, when the negative resistance value of the oscillation circuit is increased, the negative resistance value does not increase rapidly transiently, thus reducing the risk of abnormal oscillation due to the growth of oscillation based on resonance in the sub-vibrations of the oscillator.

[0260] In one embodiment of the oscillator circuit, The control data may be data represented by a thermometer code.

[0261] One form of oscillator is, One embodiment of the oscillator circuit, The system comprises the aforementioned vibrator and

[0262] In this oscillator, during the startup mode from when the oscillator circuit is stopped oscillating to the normal operating mode in which the negative resistance value of the oscillator circuit becomes a first value, the negative resistance value of the oscillator circuit increases from a second value which is smaller than the first value. The value of the series resistance under load when the oscillator resonates in its main oscillation is R. Lm This is because the oscillator is co-oscillating. The value of the series resistance R under load when vibration occurs. Ls Since it is smaller than, the negative resistance value of the oscillation circuit is Increasing from the second value, R Lm Larger than, and R Ls It will be a smaller value than that. Therefore, in startup mode, oscillations based on resonance in the oscillator's primary oscillation grow faster than oscillations based on resonance in the oscillator's secondary oscillation. Consequently, this oscillator can reduce the risk of abnormal oscillations even if there are variations in the oscillator's characteristics.

[0263] One method for controlling an oscillator circuit is: A control method for an oscillator circuit, comprising an oscillator circuit connected to an oscillator, wherein the oscillator circuit has a normal operating mode in which it oscillates with a negative resistance value of a first value, and a startup mode in which it transitions from a state in which it has stopped oscillating to the normal operating mode, In the startup mode, the negative resistance value is controlled to increase from a second value that is smaller than the first value.

[0264] In this control method for the oscillator circuit, during the startup mode, from a state where the oscillator circuit has stopped oscillating to a normal operating mode where the negative resistance value of the oscillator circuit becomes a first value and oscillates, the negative resistance value of the oscillator circuit increases from a second value which is smaller than the first value. The value of the series resistance under load when the oscillator resonates in its main oscillation is R. Lm This is when the oscillator resonates with secondary vibrations. The value of the series resistance R under load Ls Since it is smaller than the second, the negative resistance value of the oscillation circuit is the second The value increases, R LmLarger than, and R Ls It will be a smaller value than that. Therefore, In startup mode, oscillations based on resonance in the oscillator's primary oscillation grow faster than oscillations based on resonance in the oscillator's secondary oscillation. Therefore, this control method for the oscillation circuit can reduce the risk of abnormal oscillations even if there are variations in the characteristics of the connected oscillators. [Explanation of symbols]

[0265] 1...Oscillator, 2...Oscillator circuit, 3...Vibrator, 3a...Excitation electrode, 3b...Excitation electrode, 4...Package, 5...Lid, 6...External terminal, 7...Housing chamber, 10...Oscillator circuit, 11...Amplifier element, 12...Variable current source, 13...Resistor, 14...Variable capacitance circuit, 15...Variable capacitance circuit, 16...Variable capacitance circuit, 17...Variable capacitance circuit, 20...Power supply circuit, 30...Power-on reset circuit, 40...Control circuit, 41...Voltage control circuit, 42...Logic circuit, 50...Reference voltage generation circuit, 60...Output circuit, 70...Memory circuit, 71...Non-volatile memory, 72...Register, 80...Oscillator detection circuit, 10 0, 101, 102, 103, 104, 110, 111, 112, 113, 114…CMOS inverter, 120, 121, 122, 123, 124…current source, 125, 126, 127, 128, 129…switch element, 130…current source, 131, 132…P-channel MOS transistor, 133, 134…P-channel MOS transistor, 135…current source, 136-0~136-31…current source, 137-0~137-31…switch element, 140, 141, 142, 143, 144…capacitance element, 145, 146, 147, 148, 149…s Switch elements, 150, 151, 152, 153, 154… Capacitor elements, 155, 156, 157, 158, 159… Switch elements, 160… Variable capacitance elements, 161-1~161-n… Variable capacitance elements, 162-1~162-n… Capacitor elements, 163-1~163-n… Capacitor elements, 170… Variable capacitance elements, 171-1~171-n… Variable capacitance elements, 172-1~172-n… Capacitor elements, 173-1~173-n… Capacitor elements, 200… Control voltage generation circuit, 210… Filter circuit, 211… Resistor, 212… Capacitor element, 220… Switch circuit, 230… Filter circuit 231... Resistor, 232... Capacitive element, 240... Switch circuit, 250... Resistor, 260... Resistor, 300... Current source, 301... Capacitive element, 302, 303, 304... Variable resistor, 305, 306, 307, 308, 309... N-channel MOS transistor, 310... Comparator, 311, 312... CMOS inverter, 313... N-channel MOS transistor, 314, 315... Capacitive element, 401, 402, 403, 404... CMOS inverter, 411, 421, 422, 431, 432, 433, 441, 442, 443, 444... Delay circuit

Claims

1. An oscillator circuit connected to the vibrator, The system includes a control circuit for controlling the oscillation circuit, The oscillation circuit has a normal operating mode in which it oscillates when the negative resistance value is a first value, The system includes a startup mode from the state in which the oscillation circuit has stopped oscillating until it transitions to the normal operation mode, The oscillation circuit includes an amplifying element, a variable current source that supplies current to the amplifying element, and a variable capacitance circuit connected to a node connected to the oscillator. The aforementioned control circuit is In the startup mode, the current value is increased and the capacitance value of the variable capacitance circuit is decreased, thereby controlling the negative resistance value to increase from a second value that is smaller than the first value. In the startup mode, the current value is increased from a third value to a fourth value greater than the third value without changing the capacity value, and then the control is repeatedly performed to decrease the capacity value and change the current value to the third value. The first series resistance under load when the oscillator resonates with the primary vibration is smaller than the second series resistance under load when the oscillator resonates with the secondary vibration. The oscillation circuit wherein the second value is smaller than the second series resistance under load.

2. The aforementioned control circuit is The oscillation circuit according to claim 1, wherein in the startup mode, the negative resistance value is controlled to increase in a step-like manner.

3. The aforementioned control circuit is The oscillation circuit according to claim 1, wherein in the startup mode, the negative resistance value is controlled to increase continuously.

4. The oscillation circuit according to any one of claims 1 to 3, wherein the first value is greater than or equal to the maximum value of the negative resistance in the startup mode.

5. In the startup mode, the system includes an oscillation detection circuit that detects when the signal output from the oscillator exceeds a predetermined amplitude and outputs a detection signal. The oscillation circuit according to any one of claims 1 to 4, wherein the control circuit sets the negative resistance value to the first value based on the detection signal.

6. The negative resistance value is controlled based on weighted multi-bit control data. The oscillator circuit according to any one of claims 1 to 5, wherein the logic level of the control data changes faster for bits with smaller weights.

7. The oscillator circuit according to any one of claims 1 to 5, wherein the negative resistance value is controlled based on unweighted multi-bit control data.

8. The oscillation circuit according to claim 7, wherein the control data is data represented by a thermometer code.

9. An oscillator circuit according to any one of claims 1 to 8, An oscillator comprising the aforementioned vibrator and

10. A control method for an oscillator circuit, comprising an oscillator circuit connected to an oscillator, wherein the oscillator circuit has a normal operating mode in which it oscillates with a negative resistance value of a first value, and a startup mode in which it transitions from a state in which it has stopped oscillating to the normal operating mode, The oscillation circuit includes an amplifying element, a variable current source that supplies current to the amplifying element, and a variable capacitance circuit connected to a node connected to the oscillator. In the startup mode, the current value is increased and the capacitance value of the variable capacitance circuit is decreased, thereby controlling the negative resistance value to increase from a second value that is smaller than the first value. In the startup mode, the current value is increased from a third value to a fourth value greater than the third value without changing the capacity value, and then the control is repeatedly performed to decrease the capacity value and change the current value to the third value. A control method for an oscillator circuit, wherein the first series resistance under load when the oscillator resonates with the main vibration is smaller than the second series resistance under load when the oscillator resonates with the secondary vibration, and the second value is smaller than the second series resistance under load.

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