Semiconductor integrated circuits

Abstract

To reduce a leak current when a native element for a low voltage is used in a high-voltage region.SOLUTION: A semiconductor integrated circuit 100 includes a basic circuit 110 including a first transistor M1 and a second transistor M2. The first transistor M1 is constituted of an N-channel native element having a first withstanding voltage VBD1 and has a source grounded. The second transistor M2 has a source connected to a drain of the first transistor M1, and is constituted of an N-channel normal element having a second withstanding voltage VBD2 higher than the first withstanding voltage VBD1. When a gate threshold voltage of the second transistor M2 is VGS(th), a gate voltage of the second transistor M2 can be changed between an ON level VON satisfying VON-VGS(th)<VBD1 and an OFF level VOFF at which the second transistor M2 is turned off.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This disclosure relates to semiconductor integrated circuits. [Background technology]

[0002] An important characteristic of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), which make up semiconductor integrated circuits, is the gate threshold voltage V. GS(th) There is a gate threshold voltage V GS(th) MOSFETs can be divided into two types based on their size: normal MOSFETs (called normal elements) with a threshold voltage of approximately 0.4 to 0.7V, and native MOSFETs with a smaller value (for example, 0.2V or lower). Native elements include depletion transistors, which have a negative threshold voltage. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2008-60911 [Overview of the project] [Problems that the invention aims to solve]

[0004] The inventors of the present invention have recognized that using native elements at the input of a differential amplifier (operational amplifier) ​​has advantages such as suppressing variations in input offset voltage and saving space compared to using normal elements, but a disadvantage is that when the differential amplifier is off, the leakage current in the path composed of native elements increases.

[0005] The advantages and disadvantages mentioned above become even more pronounced, especially in native devices designed for low voltages (e.g., with a voltage rating of 1.2-2V).

[0006] This disclosure has been made in such circumstances, and one of its exemplary purposes is to reduce leakage current when using native elements for low voltage in a high voltage region.

Means for Solving the Problems

[0007] A semiconductor integrated circuit according to an aspect of the present disclosure includes a first transistor composed of an N-channel native element having a first breakdown voltage and having a source grounded, and a second transistor composed of an N-channel normal element having a source connected to the drain of the first transistor and having a second breakdown voltage greater than the first breakdown voltage. When the gate threshold voltage of the second transistor is V GS(th) and the first breakdown voltage is V BD1 , the gate voltage of the second transistor can be switched between an on-level V ON - V GS(th) < V BD1 that satisfies the condition and an off-level V ON at which the second transistor turns off.

[0008] Another aspect of the present disclosure is also a semiconductor integrated circuit. This semiconductor integrated circuit includes a first transistor composed of a P-channel native element having a first breakdown voltage and having a source connected to a positive power supply line, and a second transistor composed of a P-channel normal element having a source connected to the drain of the first transistor and having a second breakdown voltage greater than the first breakdown voltage. When the voltage of the positive power supply line is V LV , the gate threshold voltage of the second transistor is V GS(th) , and the first breakdown voltage is V BD1 , the gate voltage of the second transistor can be switched between an on-level V LV - (V ON + V GS(th) ) < V BD1 that satisfies the condition and an off-level V ON at which the second transistor turns off.

[0009] ​​​​Furthermore, any combination of the above components, or any substitution of components or expressions between methods, apparatus, systems, etc., are also valid as embodiments of the present invention or this disclosure. Moreover, the description in this section (means for solving the problem) does not describe all the indispensable features of the present invention, and therefore, subcombinations of these described features may also constitute the present invention. [Effects of the Invention]

[0010] According to one aspect of this disclosure, leakage current can be reduced when using a native element designed for low voltage in a high-voltage region. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 is a circuit diagram of a semiconductor integrated circuit according to Embodiment 1. [Figure 2] Figure 2 is a circuit diagram showing an example of a gate controller configuration. [Figure 3] Figure 3 is a circuit diagram of a semiconductor integrated circuit according to Example 1. [Figure 4] Figure 4 is a circuit diagram of a modified example of the semiconductor integrated circuit shown in Figure 3. [Figure 5] Figure 5 is a circuit diagram of a semiconductor integrated circuit according to Example 2. [Figure 6] Figure 6 is a circuit diagram of the semiconductor integrated circuit according to Example 3. [Figure 7] Figure 7 is a circuit diagram of the semiconductor integrated circuit according to Example 4. [Figure 8] Figure 8 is a circuit diagram of a semiconductor integrated circuit according to Embodiment 2. [Figure 9] Figure 9 is a circuit diagram of a semiconductor integrated circuit according to Example 4. [Figure 10] Figure 10 is a circuit diagram of a semiconductor integrated circuit. [Modes for carrying out the invention]

[0012] (Summary of the embodiment) This section outlines some exemplary embodiments of the present disclosure. This outline is intended to provide a basic understanding of the embodiments and to simplify some concepts of one or more embodiments, serving as a prelude to the more detailed descriptions that follow. It is not intended to limit the scope of the invention or disclosure. This outline is not a comprehensive overview of all possible embodiments, nor is it intended to identify essential elements of all embodiments or to delineate the scope of some or all aspects. For convenience, “one embodiment” may be used to refer to one or more embodiments (examples or variations) disclosed herein.

[0013] A semiconductor integrated circuit according to one embodiment comprises a first transistor composed of an N-channel native element having a first breakdown voltage and having its source grounded, and a second transistor composed of an N-channel normal element having a source connected to the drain of the first transistor and having a second breakdown voltage greater than the first breakdown voltage. The gate threshold voltage of the second transistor is set to V GS(th) , the first withstand voltage is V BD1 In this case, the gate voltage of the second transistor is V ON -V GS(th) <V BD1 On-level V that satisfies ON Then, the second transistor turns off at the off-level V. OFF It can be switched between the two.

[0014] According to this embodiment, in the operating state of the semiconductor integrated circuit, the drain voltage of the first transistor is clamped by the second transistor, thereby preventing the drain-source voltage of the first transistor from exceeding its breakdown voltage. In the stopped state of the semiconductor integrated circuit, the leakage current flowing through the first transistor can be cut off by turning off the second transistor, thereby reducing the power consumption of the semiconductor integrated circuit.

[0015] In one embodiment, the semiconductor integrated circuit may further include a differential amplifier composed of the same native elements as the first transistor. The first and second transistors may be provided in an output stage that amplifies the output of the differential amplifier.

[0016] In one embodiment, the output stage may include two sets of a first transistor and a second transistor, and further include a current mirror circuit that balances the current flowing through the two sets.

[0017] In one embodiment, the output stage may further include a first switch connected between the input transistor of the current mirror circuit and the power supply line, and a second switch connected between the output transistor of the current mirror circuit and the power supply line.

[0018] In one embodiment, the output stage may further include a switch connected between the gates of the input and output transistors of the current mirror circuit and the power supply line.

[0019] In one embodiment, the semiconductor integrated circuit may further include a third transistor, which is composed of an N-channel native element having a first breakdown voltage. The gate of the third transistor is connected to the gate of the first transistor, the source of the third transistor is connected to the source of the first transistor, and the gate and drain of the third transistor may be connected. In this case, the third transistor and the first transistor constitute a current mirror circuit.

[0020] In one embodiment, the semiconductor integrated circuit may further include a constant current source connected to the drain of the third transistor. This allows the current generated by the constant current source to be copied.

[0021] A semiconductor integrated circuit according to one embodiment comprises a first transistor composed of a P-channel native element having a first breakdown voltage, with its source connected to a positive power line, and a second transistor composed of a P-channel normal element having a source connected to the drain of the first transistor and a second breakdown voltage greater than the first breakdown voltage. The voltage of the positive power line is V LV The gate threshold voltage of the second transistor is set to V GS(th) , the first withstand voltage is V BD1 In this case, the gate voltage of the second transistor is V LV -(V ON +V GS(th) ) <V BD1 On-level V that satisfies ON Then, the second transistor turns off at the off-level V. OFF It can be switched between the two.

[0022] In one embodiment, the semiconductor integrated circuit may further comprise a third transistor comprising a P-channel native element having a first breakdown voltage. The gate of the third transistor is connected to the gate of the first transistor, the source of the third transistor is connected to a positive power line, and the gate and drain of the third transistor may be connected.

[0023] In one embodiment, the semiconductor integrated circuit may further include a constant current source connected to the drain of the third transistor.

[0024] (Embodiment) Preferred embodiments will be described below with reference to the drawings. The same or equivalent components, members, and processes shown in each drawing will be denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Furthermore, the embodiments are illustrative and not limiting to the disclosure and invention, and not all features or combinations thereof described in the embodiments are necessarily essential to the disclosure and invention.

[0025] In this specification, "member A connected to member B" includes not only cases where member A and member B are directly connected physically, but also cases where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection or impair the functions or effects produced by their combination.

[0026] Similarly, "the state in which member C is connected (provided) between member A and member B" includes not only cases where member A and member C, or member B and member C, are directly connected, but also cases where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the function or effect produced by their combination.

[0027] (Embodiment 1) Figure 1 is a circuit diagram of a semiconductor integrated circuit 100 according to Embodiment 1. The semiconductor integrated circuit 100 is supplied with a first power supply voltage V LV And a second power supply voltage V which is higher than that. MV It operates based on two power supply voltages. The semiconductor integrated circuit 100 operates on the first power supply voltage V LV The first region 102 operates at the second power supply voltage V MV It includes a second region 104 that operates in the same manner as above.

[0028] For example, the first power supply voltage V LV The voltage is 1.6V, and the second power supply voltage is V MV The voltage is 3.3V. As an example, in the semiconductor integrated circuit 100, analog circuits that mainly handle small signals are formed in the first region 102, and analog circuits that mainly handle large signals are formed in the second region 104. In another example, the semiconductor integrated circuit 100 may be an analog-digital mixed-signal circuit, in which case digital circuits and analog circuits that handle small signals are formed in the first region 102, and analog circuits that handle large signals may be integrated in the second region 104.

[0029] The semiconductor integrated circuit 100 includes a basic circuit 110. As will be described later, this basic circuit 110 does not have any function on its own, but rather, in combination with other circuit elements, it forms functional circuits such as a common-gate amplifier and a current mirror circuit.

[0030] The basic circuit 110 can be used within the second region 104 and at the boundary with the first region 102. In other words, the basic circuit 110 has the second power supply voltage V MV This is supplied. This basic circuit 110 comprises a first transistor M1 and a second transistor M2. The first transistor M1 has a first withstand voltage V BD1 It consists of N-channel native elements with a source grounded. For example, the gate threshold voltage V of the native element GS(th) The voltage is approximately 0.1-0.3V. First withstand voltage V BD1 The first power supply voltage V LV This is a voltage level that ensures normal operation and reliability when used within the first region 102 to which the voltage is supplied. The gate of the first transistor M1 is supplied with a control voltage V from the first region 102. G1 The following is entered.

[0031] As described above, the first transistor M1 operates under the first power supply voltage V LV Withstand voltage V usable in the first region 102 BD1 It only has, and when the first transistor M1 is used in the second region 104, the drain-source distance is the breakdown voltage V BD1 It must not exceed this limit. To that end, a second transistor M2, which is provided as a clamping element, is connected to the drain of the first transistor M1.

[0032] The second transistor M2 has a first breakdown voltage V BD1 Larger second voltage V BD2 It consists of an N-channel normal element having [a certain characteristic]. The source of the second transistor M2 is connected to the drain of the first transistor M1. The second breakdown voltage V BD2 The second power supply voltage V MVThis is a voltage level that ensures normal operation and reliability when used within the second region 104 where the voltage is supplied.

[0033] Gate voltage V of the second transistor M2 G2 The two voltage levels V depend on the operating state of the semiconductor integrated circuit 100. ON ,V OFF It is switchable. The semiconductor integrated circuit 100 has a gate voltage V of the second transistor M2. G2 It can be equipped with a gate controller 150 to control it.

[0034] The gate threshold voltage of the second transistor M2 is V GS(th) Let's assume the gate voltage of the second transistor M2 is the on-level V. ON It is determined such that it satisfies inequality (1). V ON -V GS(th) <V BD1 …(1) When deformed, on-level V ON This satisfies inequality (2). V ON <V BD1 +V GS(th) …(2)

[0035] For example, on-level V ON The first power supply voltage V LV This allows the voltage to be equal to the given value, thereby simplifying the circuit configuration for generating the gate voltage of the second transistor M2.

[0036] Also, the gate voltage V of the second transistor M2 G2 Off-level V OFF This is the level at which the second transistor M2 turns off. For example, the off level V OFF This can be the source voltage of the first transistor M1, i.e., the ground voltage (0V). This simplifies the circuit configuration for generating the gate voltage of the second transistor M2.

[0037] Figure 2 is a circuit diagram showing an example configuration of the gate controller 150. The gate controller 150 includes switches SW11 and SW12. When switch SW11 is ON and switch SW12 is OFF, an ON voltage V is applied to the gate of the second transistor M2. ON As such, the power supply voltage V MV This is supplied. Conversely, when switch SW11 is off and switch SW12 is on, the gate of the second transistor M2 is supplied with an off voltage V. OFF As such, the ground voltage V GND A power supply is provided. Switches SW11 and SW12 may be CMOS inverters. The gate controller 150 may complementarily switch switches SW11 and SW2 on and off in response to the enable signal EN.

[0038] The above describes the configuration of the semiconductor integrated circuit 100. Next, its operation will be explained.

[0039] During normal operation of the semiconductor integrated circuit 100, the gate of the second transistor M2 has an on-level V ON This is supplied. At this time, the second transistor M2 functions as a clamp circuit, and the drain voltage V of the first transistor M1 is supplied. D1 (that is, the drain-source voltage V DS1 ) is V ON -V GS(th) It is clamped so as not to exceed a certain value. As a result, inequality (3) holds. V D1 =V DS1 <V ON -V GS(th) …(3)

[0040] From inequalities (1) and (3), inequality (4) holds. V D1 =V DS1 <V BD1 …(4) In other words, the drain-source voltage V of the first transistor M1 DS1 The voltage resistance V BD1 It can be kept within a lower range.

[0041] In the stopped state of the semiconductor integrated circuit 100 (which may include, for example, a standby state, a sleep state, a partial function stop state, etc.), the gate voltage V of the first transistor M1 G1 becomes 0V, and the first transistor M1 is turned off. However, since the first transistor M1 is a native device, the gate threshold voltage V GS(th) is low. Therefore, even when the gate-source voltage is 0V, a non-negligible leakage current flows between the drain and source.

[0042] In this stopped state, the gate voltage V of the second transistor M2 G2 is switched to the off level V OFF . Since the second transistor M2 is a normal device having a large gate threshold voltage V GS(th) , if the gate-source voltage is set to 0V, it will surely turn off and the current path can be blocked. Thereby, the leakage current of the first transistor M1 can be blocked by the second transistor M2, and the power consumption of the basic circuit 110 in the stopped state can be reduced.

[0043] Hereinafter, a specific embodiment of the semiconductor integrated circuit 100 will be described.

[0044] (Embodiment 1) FIG. 3 is a circuit diagram of the semiconductor integrated circuit 100A according to Embodiment 1. The semiconductor integrated circuit 100A includes an operational amplifier. The operational amplifier includes a first-stage differential amplifier 120 and a second-stage output stage (also referred to as an amplification stage)​It is composed of native elements having the following characteristics. Specifically, the differential amplifier 120 includes an input differential pair 122, a load circuit 124, a tail current source 126, and switches SW1 to SW3. The input differential pair 122 includes transistors M11 and M12. The load circuit 124 includes transistors M13 and M14. The tail current source 126 includes M15. The first switch SW1 is on when the operational amplifier is operating and off when the operational amplifier is stopped. The second switch SW2 and the third switch SW3 are off when the operational amplifier is operating and on when the operational amplifier is stopped.

[0045] The output stage 130 includes two basic circuits 110_1 and 110_2, a current mirror circuit 132, and switches SW4 and SW5. The two basic circuits 110_1 and 110_2 each include a first transistor M1 and a second transistor M2, and have the same configuration as the basic circuit 110 in Figure 1. One of the differential signals from the differential amplifier 120 is input to the gate of the first transistor M1 of basic circuit 110_1, and the other of the differential signals from the differential amplifier 120 is input to the gate of the first transistor M1 of basic circuit 110_2.

[0046] The current mirror circuit 132 includes transistors M21 and M22. Transistors M21 and M22, like the second transistor M2, have a breakdown voltage of V BD2 It is composed of normal elements having the following properties. Note that since the current in the path including transistors M21 and M22 can be interrupted by switches SW4 and SW5, transistors M21 and M22 may be composed of native elements.

[0047] Focusing on basic circuit 110_1, the combination of transistors M1 and M21 can be understood as a common-source amplifier. Similarly, focusing on basic circuit 110_2, the combination of transistors M1 and M22 can be understood as a common-source amplifier.

[0048] The connection node of the second transistor M2 of the basic circuit 110_2 and the transistor M22 serves as the output of the operational amplifier. When the operational amplifier has a differential output, the connection node of the second transistor M2 of the basic circuit 110_1 and the transistor M21 also serves as an output. The fourth switch SW4 and the fifth switch SW5 are on in the operating state of the operational amplifier and off in the stopped state of the operational amplifier.

[0049] The above is the configuration of the semiconductor integrated circuit 100A. In this semiconductor integrated circuit 100A, in the stopped state of the operational amplifier, since the fourth switch SW4 and the fifth switch SW5 are off, the leakage current flowing from the power supply terminal (power supply line) V MV can be blocked. However, only the fourth switch SW4 and the fifth switch SW5 cannot block the leakage current flowing in from the output terminal OUT of the operational amplifier. Therefore, by turning off the second transistor M2 provided as a clamp circuit, the leakage current flowing in from the output terminal can be blocked.

[0050] FIG. 4 is a circuit diagram of a modified example of the semiconductor integrated circuit 100A in FIG. 3. The semiconductor integrated circuit 100A in FIG. is provided with a switch SW4b instead of the switches SW4 and SW5 in FIG. This switch SW4b is connected between the gate and source of the transistor M, and is on in the stopped state of the operational amplifier. With this configuration, the number of switches can be reduced by one compared to the semiconductor integrated circuit 100A in FIG. 3.

[0051] (Embodiment 2) Figure 5 is a circuit diagram of semiconductor integrated circuit 100B according to Embodiment 2. Like semiconductor integrated circuit 100A in Figure 3, semiconductor integrated circuit 100B also includes an operational amplifier, a differential amplifier 120, and an output stage 130. In this embodiment, the load circuit 124 is a current mirror circuit. The output stage 130 includes one basic circuit 110, a current source 134, and a switch SW5. The gate of the first transistor M1 of the basic circuit 110 is supplied with the voltage from the connection node between transistors M12 and M14 of the differential amplifier 120. The current source 134 includes a transistor M22 that is biased to supply a constant current. The same effects as those of semiconductor integrated circuit 100A in Figure 3 can be obtained with this operational amplifier. In other words, the specific configuration of the operational amplifier is not limited to those shown in Figures 3 and 5.

[0052] In Figure 5, switch SW5 is omitted, and power line V MV Alternatively, a switch SW5b may be placed between the gate of transistor M22 and the op-amp so that the switch SW5b is turned on when the op-amp is stopped.

[0053] (Example 3) Figure 6 is a circuit diagram of the semiconductor integrated circuit 100C according to Embodiment 3. In addition to the basic circuit 110, the semiconductor integrated circuit 100C includes a reference current source 140, a switch SW6, a third transistor M3, a current mirror circuit 142, and a switch SW7.

[0054] The third transistor M3, like the first transistor M1, has a breakdown voltage V BD1 It is composed of native elements having N channels. The third transistor M3, together with the first transistor M1, constitutes a current mirror circuit 144. Specifically, the gate and drain of the third transistor M3 are connected, and the gate voltage of the third transistor M3 is supplied to the gate of the first transistor M1. A reference current source 140 is connected to the drain of the third transistor M3 via a switch SW6. The reference current I generated by the reference current source 140 REFThis is copied and folded by the current mirror circuit 144, and the reference current I is passed to the first transistor M1 and the second transistor M2. REF A constant current Ic, proportional to the bias current I, flows. The current mirror circuit 142 includes transistors M31 and M32, which copy and fold back the constant current Ic. The output current of the current mirror circuit 142 is equal to the bias current I. BIAS This is then supplied to a circuit block (not shown) in the second region 104. For example, transistor M32 can be associated with transistor M22 (current source 134) in Figure 5. Switch SW7 is connected between the gate and source of transistor M31.

[0055] In the operating state of the semiconductor integrated circuit 100C, switch SW6 is ON and switch SW7 is OFF. As a result, the reference current I generated by the reference current source 140 of the first region 102 REF A bias current I proportional to BIAS This can be used within the second region 104.

[0056] When the semiconductor integrated circuit 100C is stopped, switch SW6 is off and switch SW7 is on.

[0057] (Example 4) Figure 7 is a circuit diagram of the semiconductor integrated circuit 100D according to Embodiment 4. The semiconductor integrated circuit 100D includes a resistor R1 in place of the current mirror circuit 142 and switch SW7 of the semiconductor integrated circuit 100C in Figure 6.

[0058] Resistor R1 is connected to the basic circuit 110 and the power line V MV It is placed on the path of the constant current Ic between them. Resistor R1 may be a diffusion resistor or a MOS resistor. A voltage drop of Ic × R1 occurs across resistor R1. The voltage V between resistor R1 and the connection node of the basic circuit 110 REG V MV -Ic × R1. Since Ic × R1 is a constant voltage, the voltage V REG is the power supply voltage V MV This results in a constant voltage that is lower by a predetermined voltage range.

[0059] (Embodiment 2) Figure 8 is a circuit diagram of a semiconductor integrated circuit 200 according to Embodiment 2. In Embodiment 1 and related Embodiments 1 to 3, the first transistor M1 and the second transistor M2 were N-channel MOSFETs, but in Embodiment 2, they are composed of P-channel MOSFETs.

[0060] The semiconductor integrated circuit 200 is powered by a positive supply voltage V LV , negative power supply voltage -V DD and ground voltage V GND Based on.

[0061] The semiconductor integrated circuit 200 is powered by a positive supply voltage V LV The first region 202 operates with a negative power supply voltage -V DD It includes a second region 204 that operates with a negative power supply. The second region 204 is provided with a negative power supply block 206 that operates with a negative power supply.

[0062] For example, a positive power supply voltage V LV The voltage is 1.6V, and the negative power supply voltage is -V DD is -V DD =-V LV = 1.6V.

[0063] The semiconductor integrated circuit 200 includes a basic circuit 210. Similar to Embodiment 1, the basic circuit 210 does not have any function on its own, but rather, in combination with other circuit elements, constitutes a functional circuit such as a gate-grounded amplifier or a current mirror circuit.

[0064] The basic circuit 210 can be located within the second region 204 and used at the boundary between the negative power supply block 206 and the first region 202. In other words, the basic circuit 210 can be located on the positive power supply line V LV and the negative power line -V DD It is provided between them. This basic circuit 210 includes a first transistor M1 and a second transistor M2. The first transistor M1 has a first withstand voltage V BD1It consists of a P-channel native element having a source connected to a positive power line V LV It is connected to the first withstand voltage V BD1 This is a positive power supply voltage V LV This is a voltage level that ensures normal operation and reliability when used within the first region 202 to which the voltage is supplied. The gate of the first transistor M1 is supplied with a control voltage V from the first region 202. G1 The following is entered.

[0065] The drain of the first transistor M1 is connected to the second transistor M2 as a clamping element. The second transistor M2 has a first breakdown voltage V BD1 Larger second voltage V BD2 It consists of a P-channel normal element having [a specific characteristic]. The source of the second transistor M2 is connected to the drain of the first transistor M1. The second breakdown voltage V BD2 This is a positive power supply voltage V LV and the negative power supply voltage -V DD Potential difference V LV +V DD This is the voltage level at which normal operation is guaranteed and reliability is ensured when a voltage equivalent to this is applied.

[0066] Gate voltage V of the second transistor M2 G2 The two voltage levels V depend on the operating state of the semiconductor integrated circuit 200. ON ,V OFF It can be switched. The gate threshold voltage of the second transistor M2 is set to V GS(th) Let's assume the gate voltage of the second transistor M2 is the on-level (also called on-level) V. ON It is determined such that it satisfies inequality (5). V LV -(V ON +V GS(th) ) <V BD1 …(5) When deformed, on-level V ON This satisfies inequality (6). V ON >V LV -V GS(th) -V BD1…(6)

[0067] For example, on-level V ON The ground voltage V GND This allows for a simplification of the circuit configuration for generating the gate voltage of the second transistor M2.

[0068] Also, the gate voltage V of the second transistor M2 G2 Off-level V OFF This is the level at which the second transistor M2 turns off. For example, the off level V OFF This is a positive power supply voltage V LV This allows for a simplification of the circuit configuration for generating the gate voltage of the second transistor M2.

[0069] The above describes the configuration of the semiconductor integrated circuit 200. Next, we will explain its operation.

[0070] During normal operation of the semiconductor integrated circuit 200, the gate of the second transistor M2 has an on-level V ON This is supplied. At this time, the second transistor M2 functions as a clamp circuit, and the drain voltage V of the first transistor M1 is supplied. D1 V ON +V GS(th) It is clamped to prevent it from getting any lower. As a result, the drain-source voltage V of the first transistor M1 DS1 V LV -(V ON +V GS(th) The wire is clamped so as not to exceed ), and in this case, inequality (7) holds. V DS1 <V LV -(V ON +V GS(th) ) …(7)

[0071] From inequalities (5) and (7), inequality (7) holds. V D1 <V BD1 …(7) In other words, the drain-source voltage V of the first transistor M1 DS1 The voltage resistance VBD1 It can be kept within a lower range.

[0072] In a stopped state of the semiconductor integrated circuit 200 (which may include, for example, a standby state, a sleep state, or a partially disabled state), the gate voltage V of the first transistor M1 G1 The power supply voltage is V LV As a result, the first transistor M1 is in the off state. However, since the first transistor M1 is a native element, the gate threshold voltage V GS(th) The voltage is low. Therefore, even if the gate-source voltage is 0V, a non-negligible leakage current flows between the drain and source.

[0073] In this stopped state, the gate voltage V of the second transistor M2 G2 is off-level V OFF It can be switched to. The second transistor M2 has a large gate threshold voltage V GS(th) Since it is a normal element having [a certain characteristic], if the gate-source voltage is set to 0V, it will reliably turn off and the current path can be interrupted. As a result, the leakage current of the first transistor M1 can be interrupted by the second transistor M2, and the power consumption of the basic circuit 210 in the stopped state can be reduced.

[0074] The following describes a specific example of the semiconductor integrated circuit 200.

[0075] (Example 4) Figure 9 is a circuit diagram of the semiconductor integrated circuit 200A according to Example 4. This semiconductor integrated circuit 200A can be understood as having the same configuration as the semiconductor integrated circuit 100C in Figure 6, but inverted.

[0076] In addition to the basic circuit 210, the semiconductor integrated circuit 200A includes a reference current source 240, a switch SW6, a third transistor M3, a current mirror circuit 242, and a switch SW7.

[0077] The third transistor M3, like the first transistor M1, has a breakdown voltage V BD1It is composed of a P-channel native element having [a specific configuration]. The third transistor M3, together with the first transistor M1, constitutes a current mirror circuit 244. Specifically, the gate and drain of the third transistor M3 are connected, and the gate voltage of the third transistor M3 is supplied to the gate of the first transistor M1. A reference current source 240 is connected to the drain of the third transistor M3 via a switch SW6. The reference current I generated by the reference current source 240 REF This is copied and folded by the current mirror circuit 244, and the reference current I is passed to the first transistor M1 and the second transistor M2. REF A constant current Ic proportional to the value flows. This constant current Ic is supplied to the negative power supply block 206.

[0078] The negative power supply block 206 includes a current mirror circuit 242 and a functional block 208. The current mirror circuit 242 includes transistors M31 and M32, which copy and fold back the constant current Ic. The output current of the current mirror circuit 242 is the bias current Ic. BIAS It is supplied to the functional block 208. Switch SW7 is connected between the gate and source of transistor M31.

[0079] In the operating state of the semiconductor integrated circuit 200A, switch SW6 is ON and switch SW7 is OFF. As a result, the reference current I generated by the reference current source 240 of the first region 202 REF A bias current I proportional to BIAS This can be used within the second region 204.

[0080] When the semiconductor integrated circuit 100C is stopped, switch SW6 is off and switch SW7 is on.

[0081] (Application) Figure 10 is a circuit diagram of the semiconductor integrated circuit 300. The semiconductor integrated circuit 300 is a power management IC (Integrated Circuit) and includes power supply circuits 310_1 to 310_3 for multiple channels (in this case, 3 channels) CH1 to CH3, an interface circuit 312, an internal regulator 314, a sequencer 316, a reference current source 318, etc. The power supply circuits 310_1 and 310_2 for the first channel CH1 and the second channel CH2 are step-down converters, and the power supply circuit 310_3 for the third channel CH3 is an LDO (Low Drop Output), i.e., a linear regulator.

[0082] The semiconductor integrated circuit 300 is supplied with an analog power supply voltage AVDD, for example, 3.3V. This power supply voltage AVDD is related to the V described above. MV This voltage corresponds to a certain value and is supplied to the second region 304 of the semiconductor integrated circuit 300, which includes blocks that handle large signals. Specifically, the blocks that handle large signals include the output stages of power supply circuits 310_1 to 310_3.

[0083] The interface circuit 312 and the sequencer 316 are digital circuits, and the low power supply voltage V LV A first region 302 is formed in which the current is supplied. A reference current source 318 is also located in the first region 302. The internal regulator 314 receives the power supply voltage AVDD and a low power supply voltage V, for example, 1.6V. LV It is generated and supplied to the first region 302.

[0084] Interface circuit 312 is I 2 It uses a C interface or SPI (Serial Peripheral Interface) and connects to an external host controller, enabling communication with the host controller. The host controller controls the startup and shutdown of the semiconductor integrated circuit 300, as well as the individual on / off states of each channel.

[0085] The sequencer 316 controls the starting and stopping of multiple channel power supply circuits 310_1 to 310_3 in response to instructions from the host controller.

[0086] The architecture described for the semiconductor integrated circuit 100 of Embodiment 1 can be used for the semiconductor integrated circuit 300.

[0087] For example, the power supply circuit 310_# (#=1~3) has an output voltage V OUT# The feedback signal and reference voltage V shown REF It includes an operational amplifier (error amplifier) ​​that amplifies the error. This operational amplifier can be configured with the architecture shown in Figure 3. That is, the differential amplifier preceding the operational amplifier can be formed in the first region 302, and the amplification stage following the operational amplifier can be configured in the second region 304.

[0088] Furthermore, in the power supply circuit 310_#(#=1~3), a constant bias current I BIAS This may be necessary. In this case, the reference current I generated by the reference current source 318 located in the first region 302 REF This can then be copied using the circuit configuration shown in Figure 6 and supplied to the power supply circuit 310_#.

[0089] Those skilled in the art will understand that the embodiments are illustrative, and that various modifications exist for each component and combination of processing steps, and that such modifications are also included within the scope of this disclosure or the present invention. [Explanation of symbols]

[0090] 100 Semiconductor Integrated Circuits 102 1st area 104 Second area 110 Basic circuit M1 First Transistor M2 Second Transistor M3 Third Transistor 120 Differential Amplifier 122 Input Differential Pair 124 Load circuit 126 Tail current source 130 Output Stages 134 Current source 140 Reference current source 142 Current Mirror Circuit 200 Semiconductor Integrated Circuits 202 1st area 204 Second area 206 Negative Power Block 208 Functional Blocks 210 Basic circuit 240 Reference current source 242 Current Mirror Circuit 300 Semiconductor Integrated Circuits 302 1st area 304 Second area 310 Power supply circuit 312 Interface Circuit 314 Internal Regulator 316 Sequencer

Claims

1. A first transistor is composed of an N-channel native element having a first drain-source breakdown voltage, with its source grounded. A second transistor is composed of an N-channel normal element having a source connected to the drain of the first transistor and a second drain-source breakdown voltage greater than the first drain-source breakdown voltage, Equipped with, The gate threshold voltage of the second transistor is set to V ＧＳ（ｔｈ） , the first drain-source breakdown voltage is V ＢＤ１ In this case, the gate voltage of the second transistor is V ＯＮ -V ＧＳ（ｔｈ） <V ＢＤ１ On-level V that satisfies ＯＮ Then, the off-level V that turns off the second transistor occurs. ＯＦＦ A semiconductor integrated circuit that can be switched between two modes.

2. The differential amplifier further comprises a native element having the same first drain-source breakdown voltage as the first transistor, The semiconductor integrated circuit according to claim 1, wherein the first transistor and the second transistor are provided in an output stage that amplifies the output of the differential amplifier.

3. The output stage comprises two sets of the first transistor and the second transistor, and further comprises a current mirror circuit. The semiconductor integrated circuit according to claim 2, wherein the input side of the current mirror circuit is connected to the drain of the second transistor included in one of the two sets, and the output side of the current mirror circuit is connected to the drain of the second transistor included in the other of the two sets.

4. The aforementioned output stage is A first switch connected between the input transistor of the current mirror circuit and the power line, A second switch is connected between the output transistor of the current mirror circuit and the power line, The semiconductor integrated circuit according to claim 3, further comprising:

5. The semiconductor integrated circuit according to claim 3, wherein the output stage further comprises a switch connected between the gates of the input and output transistors of the current mirror circuit and a power line.

6. The system further comprises a third transistor composed of an N-channel native element having the first drain-source breakdown voltage, The semiconductor integrated circuit according to claim 1, wherein the gate of the third transistor is connected to the gate of the first transistor, the source of the third transistor is connected to the source of the first transistor, and the gate of the third transistor and the drain of the third transistor are connected.

7. The semiconductor integrated circuit according to claim 6, further comprising a constant current source connected to the drain of the third transistor.

8. The semiconductor integrated circuit according to claim 7, further comprising a resistor connected in series with the second transistor.

9. A first transistor comprising a P-channel native element having a first drain-source breakdown voltage, with its source connected to a positive power line, A second transistor is a P-channel normal element having a source connected to the drain of the first transistor and a second drain-source breakdown voltage greater than the first drain-source breakdown voltage, Equipped with, Let the voltage of the positive power supply line be V ＬＶ , let the gate threshold voltage of the second transistor be V ＧＳ（ｔｈ） , let the breakdown voltage between the first drain and source be V ＢＤ１ . When, the gate voltage of the second transistor is V ＬＶ -(V ＯＮ + V ＧＳ（ｔｈ） ) < V ＢＤ１ satisfies the on-level V ＯＮ and the off-level V at which the second transistor turns off ＯＦＦ , a semiconductor integrated circuit that can be switched between them.

10. The third transistor is further composed of a P-channel native element having the first drain-source breakdown voltage, The semiconductor integrated circuit according to claim 9, wherein the gate of the third transistor is connected to the gate of the first transistor, the source of the third transistor is connected to the positive power line, and the gate of the third transistor and the drain of the third transistor are connected.

11. The semiconductor integrated circuit according to claim 10, further comprising a constant current source connected to the drain of the third transistor.

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