amplifier

Abstract

In an example, an amplifier is provided. The amplifier comprises a first transistor. A drain of the first transistor is connected to a first node of the amplifier, a source of the first transistor is connected to a first input node of the amplifier, and a gate of the first transistor is connected to a first gate bias voltage. The first input node is for receiving a first input current signal of an input signal. The amplifier also comprises a second transistor. A drain of the second transistor is connected to a second node of the amplifier, a source of the second transistor is connected to a second input node of the amplifier, and a gate of the second transistor is connected to a second gate bias voltage. The second input node is for receiving a second input current signal of the input signal. The amplifier also comprises a first current source configured to provide a first bias current at the first input node, and a second current source configured to provide a second bias current at the second input node. The amplifier further comprises a first capacitor connected between the first input node and a control node of the second current source, and a second capacitor connected between the second input node and a control node of the first current source.

Description

[0001] AMPLIFIER

[0002] Technical Field

[0003] Example embodiments of this disclosure relate to an amplifier, for example configured to mitigate the effects of a common mode signal in a differential input signal.

[0004] Background

[0005] In modern integrated circuit (IC) processes, there is difficulty associated with usage of devices with a voltage tolerance higher than voltage tolerance of the main core type devices, which is typically less than one volt. However, interface requirements may still require output signal levels well above this. This can be achieved by using specialized transistors with higher voltage tolerance for input / output (I / O) blocks. I / O cells with this level of performance are available or digital interfaces, but are less common for analog interfaces. One possible solution for analog interfaces is to add a cascode transistor as the output stage. The cascode will protect the internal sensitive core voltage transistors from the higher voltage seen at the I / O pins.

[0006] Low voltage design typically uses differential signals to increase voltage swing while leaving supply voltage intact. A problem with differential signals is that non ideal behaviors in the signal chain can convert some of the differential signal into a common mode signal.

[0007] Sometimes, an independent common mode signal is also picked up through capacitive or inductive cross talk mechanisms. This unwanted common mode signal must be removed or at least suppressed later in the signal chain. Typically, a Common Mode Rejection Ratio (CMRR) is defined to characterize and quantify the extent of suppression provided by a specific design.

[0008] There are many ways common mode signal removal or suppression has been done historically. Typically, amplifiers have a separate control loop to set the common mode voltage to the desired level. An example of this can be seen in Figure 6 of CN 109004911A, where the current bias in the gain stage is regulated to achieve the desired common mode (CM) voltage in the output. The drawback of this approach is that the CM loop bandwidth (BW) will be limited by the delay introduced in each step of the loop. This will be a limit for high frequency CM content. Another approach is to measure the CM signal using a separate copy of the input stage and then use the measured value to control the current in the output stage. An example of this can be found in Figure 2 of RU2319287C1. There will be a loss of accuracy compared with a closed loop method.

[0009] There are also designs of input stages that have a degree of intrinsic common mode rejection. For instance, a differential input pair with a floating common source node will have a high degree of common mode rejection. In Figure 3 of JPS5857806A, an example can be seen where the output cascode gates are locked towards the input pair common source using a Zener diode. With suitably selected component values, it should be possible to achieve a significantly lower common mode gain compared to the differential gain.

[0010] In another example, shown in Figure 3 of M. Hossain et al, “A 19-GHz Broadband Amplifier Using a gm-Boosted Cascode in 0.18- pm CMOS,” IEEE Custom Integrated Circuits Conference 2006, 10-13 September 2006, where a gm-boosted cascode is described. The gm-boost will only apply to the differential signal, whereas the common mode signal will only see the intrinsic gm. Thanks to this, a 6 dB lower common mode gain can be expected compared with the differential gain.

[0011] To summarize, if the frequency of the common mode signal is in the GHz range, it is difficult to design a common mode control loop with sufficient bandwidth.

[0012] The cascode stage is ubiquitous in Radio Frequency (RF) amplifier design, but in its fundamental form it has no common mode (CM) rejection. If CM rejection is a requirement, either an additional stage with CM rejection needs to be added before or after the cascode stage, or the cascode stage needs to be modified to suppress the CM component in the input signal.

[0013] Introducing additional stages before or after risks deteriorating signal quality and is best avoided unless needed for additional reasons, such as to provide additional gain. Many published CM rejection designs rely on closed loop amplifiers to suppress the CM component. This may work well at low and moderate frequencies, but becomes increasingly harder to design as frequencies go up. Summary

[0014] One or more embodiments of this disclosure may have one or more advantages. For example, improvements in CM rejection in embodiments of this disclosure may allow a cascode impedance transforming stage to be used even if the RF signal source payload signal also contains a significant unwanted common mode component that cannot be avoided, and / or even if the common mode component has a high frequency, such as in the GHz range.

[0015] One aspect of the present disclosure provides an amplifier comprising a first transistor. A drain of the first transistor is connected to a first node of the amplifier, a source of the first transistor is connected to a first input node of the amplifier, and a gate of the first transistor is connected to a first gate bias voltage. The first input node is for receiving a first input current signal of an input signal. The amplifier also comprises a second transistor. A drain of the second transistor is connected to a second node of the amplifier, a source of the second transistor is connected to a second input node of the amplifier, and a gate of the second transistor is connected to a second gate bias voltage. The second input node is for receiving a second input current signal of the input signal. The amplifier also comprises a first current source configured to provide a first bias current at the first input node, and a second current source configured to provide a second bias current at the second input node. The amplifier further comprises a first capacitor connected between the first input node and a control node of the second current source, and a second capacitor connected between the second input node and a control node of the first current source.

[0016] Another aspect of the present disclosure provides an amplifier comprising a first transistor. A drain of the first transistor is connected to a first node of the amplifier, a source of the first transistor is connected to a first input node of the amplifier, and a gate of the first transistor is connected to a first gate bias voltage. The first input node is for receiving a first input current signal of an input signal. The amplifier also comprises a second transistor. A drain of the second transistor is connected to a second node of the amplifier, a source of the second transistor is connected to a second input node of the amplifier, and a gate of the second transistor is connected to a second gate bias voltage. The second input node is for receiving a second input current signal of the input signal. The amplifier also comprises a first current source configured to provide a first bias current at the first input node, and a second current source configured to provide a second bias current at the second input node. The amplifier further comprises a gain stage configured to receive a signal representing an input common mode signal in the input signal and to provide a first current signal to the first node and / or a second current signal to the second node. The first current signal and / or the second current signal at least partially cancel a current due to the input common mode signal at the first node and / or the second node.

[0017] A further aspect of the present disclosure provides an amplifier comprising a first transistor. A drain of the first transistor is connected to a first node of the amplifier, and a source of the first transistor is connected to a first input node of the amplifier. The first input node is for receiving a first input current signal of an input signal. The amplifier also comprises a second transistor. A drain of the second transistor is connected to a second node of the amplifier, and a source of the second transistor is connected to a second input node of the amplifier. The second input node is for receiving a second input current signal of the input signal. A gate of the first transistor and a gate of the second transistor are connected via at least one impedance to a seventh reference voltage. The amplifier also comprises a first current source configured to provide a first bias current at the first input node, and a second current source configured to provide a second bias current at the second input node.

[0018] An additional aspect of the present disclosure provides an amplifier comprising a first transistor. A drain of the first transistor is connected to a first node of the amplifier, a source of the first transistor is connected to a first input node of the amplifier, and a gate of the first transistor is connected to a first gate bias voltage. The first input node is for receiving a first input current signal of an input signal. The amplifier also comprises a second transistor. A drain of the second transistor is connected to a second node of the amplifier, a source of the second transistor is connected to a second input node of the amplifier, and a gate of the second transistor is connected to a second gate bias voltage. The second input node is for receiving a second input current signal of the input signal. The amplifier also comprises a first current source configured to provide a first bias current at the first input node, and a second current source configured to provide a second bias current at the second input node. The amplifier further comprises a buffer stage configured to receive a signal representing an input common mode signal in the input signal and to provide a current source control signal based on the input common mode signal to a control node of the first current source and a control node of the second current source.

[0019] Brief Description of the Drawings

[0020] For a better understanding of examples of the present disclosure, and to show more clearly how the examples may be carried into effect, reference will now be made, by way of example only, to the following drawings in which: Figure 1 is a circuit diagram of a circuit including an example of a cascode amplifier;

[0021] Figure 2 is a circuit diagram of an example of a cascode amplifier;

[0022] Figure 3A is a circuit diagram of an example of an amplifier according to an example of this disclosure;

[0023] Figure 3B is a circuit diagram of an example implementation of the amplifier of Figure 3A;

[0024] Figure 3C is a circuit diagram of another example of an amplifier according to an example of this disclosure;

[0025] Figure 4A is a circuit diagram of another example of an amplifier according to an example of this disclosure;

[0026] Figure 4B is a circuit diagram of another example of an amplifier according to an example of this disclosure;

[0027] Figure 4C is a circuit diagram of another example of an amplifier according to an example of this disclosure;

[0028] Figure 5A is a circuit diagram of an example implementation of the amplifier of Figure 4C;

[0029] Figure 5B is a circuit diagram of another example implementation of the amplifier of Figure 4C;

[0030] Figure 6A is a circuit diagram of another example of an amplifier according to an example of this disclosure;

[0031] Figure 6B is a circuit diagram of an example implementation of the amplifier of Figure 6A;

[0032] Figure 7 is a circuit diagram of another example of an amplifier according to an example of this disclosure;

[0033] Figure 8 illustrates an example of an integrated circuit according to an example of this disclosure; and

[0034] Figure 9 illustrates an example of an electronic apparatus according to an example of this disclosure.

[0035] Detailed Description

[0036] The following sets forth specific details, such as particular embodiments or examples for purposes of explanation and not limitation. It will be appreciated by one skilled in the art that other examples may be employed apart from these specific details. A cascode stage has many advantages, such as providing current-to-voltage conversion with high linearity. A disadvantage is that there is no intrinsic common mode (CM) rejection in a basic differential cascode stage. In examples of this disclosure, additional circuitry has been added to an amplifier, such as a cascode amplifier, to mitigate the effects of any CM component in the input signal at the output. Some examples may combine several different methods to achieve a sufficient overall CM suppression.

[0037] Figure 1 is a circuit diagram of a circuit including an example of a cascode amplifier 100. In this circuit, the output of a differential low voltage current output radio frequency-digital to analog converter (RF-DAC) 102 cannot be sent directly to a load, due to the possible large voltages seen across the load. Instead, the RF-DAC 102 provides a differential current signal to input nodes 104 and 106 of the amplifier 100 via capacitors 108 and 110 respectively. That is, a first signal of the differential current signal is provided to input node 104, and a second signal of the differential current signal is provided to input node 106. The input node 104 is connected to the source of a first cascode transistor 112, and the input node 106 is connected to the source of a second cascode transistor 114. In this embodiment, first cascode transistor 112 and second cascode transistor 114 may be n-type transistors. The drains of the transistors 112 and 114 are connected together via a pair of series connected 50 ohm resistors 116 and 118 (or alternatively a single 100 ohm resistor). The drains of the transistors 112 and 114 are the output nodes 120 and 122 respectively of the amplifier 100, which provide a differential output signal.

[0038] The amplifier 100 also includes a third transistor 124 and a fourth transistor 126. The third transistor 124 has a drain connected to the first input node 104 and a source connected to a second reference voltage, such as for example ground, a lower supply voltage, V-, Vss, zero volts etc. In this embodiment, third transistor 124 and the fourth transistor 114 may be n- type transistors. The fourth transistor 126 has a drain connected to the second input node 106 and a source connected to the second reference voltage. The gates of the transistors 124 and 126 are connected to the gate and drain of a fifth transistor 128, which has its source connected to the second reference voltage. In this embodiment, fifth transistor 128 may be n-type. A bias current 130 is provided to the drain of the fifth transistor 128, and thus the bias current is mirrored by transistors 124 and 126.

[0039] The circuit includes an external load 132, such as an antenna, RF choke, balun and / or transformer. The external load 132 is represented by a pair of inductors 134 and 136 connected in series between the output nodes 120 and 122 of the amplifier 100, with a midpoint between the inductors 134 and 136 connected to a first reference voltage, such as for example a power supply voltage, a positive supply voltage, V+, Vdd etc. The load 132 is also represented by a 100 ohm resistance 138 connected between the output nodes 120 and 122 of the amplifier 100, and hence the antenna 132 is a matched load to the 50 ohm resistors 116 and 118 of the amplifier 100. In this embodiment, the first reference voltage may be applied to the external load 132, such as an antenna. In other embodiments, the first reference voltage may be applied directly to a load network which may be internal or external.

[0040] Thus the amplifier 100 converts a low impedance, low voltage RF signal to a 50 Ohm standard output. The amplifier 100 protects the RF-DAC 102 from the high voltages that will occur over the 50 ohm loads when sufficient power is transmitted to the output (e.g. by the load 132).

[0041] The cascode amplifier 200 is shown in isolation in Figure 2. Here, like components are given like reference numerals as for Figure 1. In the amplifier 200 of Figure 2, the input nodes 104 and 106 may receive a differential input current signal (e.g. from a DAC) via capacitors 108 and 110. A first current source 202 provides a first bias current at the first input node 104, and a second current source 204 provides a second bias current at the second input nodes 106. In some examples, the current sources 202 and 204 may be implemented by transistors 124, 126 and 128. The output nodes 120 and 122 of the amplifier 200 may be connected to a load (e.g. an antenna, RF choke, balun and / or transformer). The output nodes 120 and 122 may be also connected via resistors to the first reference voltage.

[0042] In the amplifiers 100 and 200, the input current signal is generating a voltage at the drain of the common gate (CG) cascode stage, i.e. at the output nodes 120 and 122. This design provides no rejection of an input common mode current signal.

[0043] Figure 3 is a circuit diagram of an example of an amplifier 300 according to an example of this disclosure. The amplifier comprises a first transistor 302. A drain of the first transistor 302 is connected to a first node 304 of the amplifier, a source of the first transistor 302 is connected to a first input node 306 of the amplifier, and a gate of the first transistor 302 is connected to a first gate bias voltage. The first input node 306 is for receiving a first input current signal of an input signal, for example via a capacitor 332. The differential input signal may in some examples be received from a DAC, such as a low voltage RF-DAC. In this embodiment, as well as all other examples of this disclosure, all transistors may be n- type transistors, although in other embodiments any one or more of the transistors may be p- type.

[0044] The amplifier 300 also comprises a second transistor 308. A drain of the second transistor 308 is connected to a second node 310 of the amplifier, a source of the second transistor 308 is connected to a second input node 312 of the amplifier, and a gate of the second transistor 308 is connected to a second gate bias voltage. The second input node 312 is for receiving a second input current signal of the input signal, for example via capacitor 334.

[0045] In some examples, the first gate bias voltage and the second gate bias voltage (provided to the gates of the transistors 302 and 308 respectively) may be the same reference voltage, and may for example both be a first reference voltage such as for example a power supply voltage, a positive supply voltage, V+, Vdd etc. However, in other examples, the first and second gate bias voltages may be connected in other ways, such as for example to a second gate voltage (e.g. ground, a lower supply voltage, V-, Vss, zero volts etc.), to different voltages, or where features of the amplifier 300 are combined with features from other examples, such as those in the amplifier 600 or 650 described below with reference to Figure 6A or 6B.

[0046] The amplifier 300 includes a first current source 340 configured to provide a first bias current at the first input node 306, a second current source 342 configured to provide a second bias current at the second input node 312.

[0047] The amplifier 300 further comprises a first capacitor 322 connected between the first input node 306 and a control node 348 of the second current source 342, and a second capacitor 324 connected between the second input node 312 and a control node 346 of the first current source 340. Thus for example the first current source 340 and second current source 342 may adjust the current provided to nodes 306 and 312 respectively based on the second input current signal and first input current signal respectively. In the example shown in Figure 3A, a third resistor 326 is connected between the control node 346 of the first current source 340 and a node 330 (referred to below as a gate bias voltage provisioning node 330), and a fourth resistor 328 is connected between the control node 348 of the second current source 342 and the node 330.

[0048] The capacitors 322 and 324 (and, in some examples, resistors 326 and 328) of the amplifier 300 may be referred to in some examples as a cross-connection arrangement. The cross- connection may effectively implement a cross-modulation. Thus, in the amplifier 300, the cascode bias point (that is, the bias point of the first transistor 302 and second transistor 308, which may be for example the operating point in the absence of signal) may in some examples be modulated by the input signal to increase the ratio between differential and common mode gain, effectively increasing the common mode rejection.

[0049] This approach to common mode rejection does not significantly change the current consumption of the amplifier 300 as compared to for example the amplifier 200 shown in Figure 2. In operation, in examples of the amplifier 300, some of the voltage swing at the cascode inputs (i.e. at the input nodes 306 and 312) is converted into additional swings of bias current through transistors 308 and 302 respectively by modulation of the bias current sources. As a result, the gain for a common mode signal is effectively reduced. In other words, in this embodiment, an operating point of the cascode transistors 302 and 308 depends on the input current signal at input nodes 306 and 312 in such a way that a common mode gain is attenuated and the differential gain is increased. This causes a mitigation and or attenuation of the common mode signal impact at the drain of cascode transistors 302 and 310. A value of the gain of this mechanism may in some examples be adjusted in such a way so as to not overcome a first threshold, above which the circuit may start to oscillate. It is known to the person skilled in the art how to avoid such oscillations. One drawback of this circuit is that there is some degradation in linearity in some examples. The improvement in common mode suppression is around 1.5 dB according to simulations of examples of the amplifier 300.

[0050] Figure 3B is a circuit diagram of an amplifier 350 that is an example implementation of the amplifier of Figure 3A. In Figure 3B, like components are given like reference numerals as for Figure 3A. In the amplifier 350 of Figure 3B, the current sources 340 and 342 are implemented by a third transistor 318 and fourth transistor 320 respectively.

[0051] The third transistor 318 has a source connected to a second reference voltage (e.g. ground, a lower supply voltage, V-, Vss, zero volts etc.), and a drain of the third transistor 318 is configured to receive the first input current signal (e.g. is connected to the first input node 306). The third transistor 318 is configured to cause the first bias current at the first input node 306.

[0052] The fourth transistor 320 has a source connected to the second reference voltage, and a drain of the fourth transistor 320 is configured to receive the second input current signal (e.g. is connected to the second input node 312). The fourth transistor is configured to cause the second bias current at the second input node 312. The first capacitor 322 is connected between the first input node 306 and a gate of the fourth transistor 320, and the second capacitor 324 connected between the second input node 312 and a gate of the third transistor 318. The third resistor 326 is connected between the gate of the third transistor 318 and the gate voltage provisioning node 330, and the fourth resistor 328 is connected between the gate of the fourth transistor 320 and the gate voltage provisioning node 330.

[0053] As indicated above, the third transistor 318 is configured to cause a first bias current at the first input node 306, and the fourth transistor is configured to cause a second bias current at the second input node 312. This may be achieved for example using a fifth transistor 336, with a source connected to the first reference voltage or the second reference voltage (in the example amplifier 300 of Figure 3, the source of the fifth transistor 336 is connected to the second reference voltage). A gate of the fifth transistor 336 is connected to a drain of the fifth transistor 336. The drain of the fifth transistor 336 is configured to receive a bias current, and the gate of the fifth transistor 336 comprises the gate voltage provisioning node 330.

[0054] In the example shown in Figure 3B, the amplifier 350 includes a load network 344 between the first reference voltage(e.g. a power supply voltage, a positive supply voltage, V+, Vdd etc.) and the first 304 and second 310 nodes. In the example shown, the load network comprises a first resistor 314 connected between the drain of the first transistor 302 and the first reference voltage, and a second resistor 316 connected between the drain of the second transistor 308 and the first reference voltage. Generally, the load network 344 comprises at least one of the following: a resistive load, inductive load, transistor-based load and capacitive load.

[0055] Figure 3C is a circuit diagram of another example of an amplifier 370 according to an example of this disclosure. In Figure 3C, like components are given like reference numerals as for Figure 3A. The amplifier 370 of Figure 3C includes a buffer stage 372. The buffer stage 372 is configured to receive a signal representing an input common mode signal in the input signal. This signal representing the input common mode signal in the input signal may be determined in some examples in a manner similar to that shown in Figure 40, 5A or 5B and described below, e.g. the signal representing the input common mode signal may in some examples be provided by apparatus 426 in the amplifier 370. The buffer stage 372 is also configured to provide a current source control signal based on the input common mode signal to a control node 346 of the first current source 340 and a control node 348 of the second current source 342. In the example shown in Figure 3C, this signal is provided via capacitor 376.

[0056] Similar to the amplifiers 300 and 350 described above, the buffer stage 372 may in some examples provide the current source control signal such that the cascode bias point (that is, the bias point of the first transistor 302 and second transistor 308, which may be for example the operating point in the absence of signal) may be modulated by the input signal to increase the ratio between differential and common mode gain, effectively increasing the common mode rejection.

[0057] In the example shown in Figure 3C, the amplifier 370 includes a third resistor 378 connected between the gate bias voltage provisioning node 330 and the control nodes 346 and 348 of the current sources 340 and 342. In some examples, the first current source 340 comprises a third transistor 318, wherein a source of the third transistor 318 is connected to a second reference voltage, and a drain of the third transistor 318 is connected to the first input node 306, wherein the third transistor 318 is configured to provide the first bias current at the first input node 306. Also, in some examples, the second current source 342 comprises a fourth transistor 320, wherein a source of the fourth transistor is connected to the second reference voltage, and a drain of the fourth transistor 320 is connected to the second input node 312 wherein the fourth transistor is configured to provide the second bias current at the second input node 312. Also in some examples, the amplifier 370 comprises a fifth transistor, wherein a source of the fifth transistor is connected to the first reference voltage or the second reference voltage, and a gate of the fifth transistor is connected to a drain of the fifth transistor, wherein the drain of the fifth transistor is configured to receive a bias current, and the gate of the fifth transistor comprises a gate bias voltage provisioning node 330. The third resistor 378 may thus in some examples be connected between the gate bias voltage provisioning node 330 and the gates of the third transistor 318 and fourth transistor 320.

[0058] The buffer stage 372 in some examples is configured to provide the current source control signal to the gates of the third transistor 318 and fourth transistor 320.

[0059] Figure 4A is a circuit diagram of another example of an amplifier 400 according to an example of this disclosure. The amplifier 400 comprises a first transistor 402. A drain of the first transistor 402 is connected to a first node 404 of the amplifier, a source of the first transistor 402 is connected to a first input node 406 of the amplifier, and a gate of the first transistor 402 is connected to a first gate bias voltage. The first input node 406 is for receiving a first input current signal of an input signal, for example via a capacitor 432. The differential input signal may in some examples be received from a DAC, such as a low voltage RF-DAC.

[0060] The amplifier 400 also comprises a second transistor 408. A drain of the second transistor 408 is connected to a second node 410 of the amplifier, a source of the second transistor 408 is connected to a second input node 412 of the amplifier, and a gate of the second transistor 408 is connected to a second gate bias voltage. The second input node 412 is for receiving a second input current signal of the input signal, for example via a capacitor 434.

[0061] In some examples, the first gate bias voltage and the second gate bias voltage (provided to the gates of the transistors 402 and 408 respectively) may the same reference voltage, and may both be a first reference voltage such as for example a power supply voltage, a positive supply voltage, V+, Vdd etc. However, in other examples, the first and second gate voltages may be connected in other ways, such as for example to a second gate voltage (e.g. ground, a lower supply voltage, V-, Vss, zero volts etc.), may be different voltages, or where features of the amplifier 400 are combined with features from other examples, such as those in the amplifier 600 or 650 described below with reference to Figure 6A or 6B.

[0062] The amplifier 400 also includes a gain stage 422 configured to receive a signal 424 representing an input common mode signal in the input signal, and to provide a first current signal to the first node 404 and / or a second current signal to the second node 410. The first current signal and / or the second current signal at least partially cancel a current due to the input common mode signal at the first node 404 and / or the second node 410. For example, the first current signal may be provided to the first node 404 to at least partially cancel a first common mode current at the first node 404 due to the input common mode signal. Additionally or alternatively, the second current signal may be provided to the second node 410 to at least partially cancel a second common mode current at the second node 410 due to the input common mode signal.

[0063] In some examples, the gain of the gain stage 422 may be configurable so as to configure an amplitude of the first current signal and / or the second current signal. This configurable gain can be configured so as to ensure that the amplitude of the first and second current signals is the same or substantially the same as the first and second common mode currents respectively. The gain of the gain stage may be configured in some examples on manufacture of a device including the amplifier 400, or alternatively may be dynamically configurable in some examples, for example based on frequency of the input signal. The signal 424 representing an input common mode signal in the input signal can thus in some examples be used to generate a current (the first current signal and second current signal referred to above) inverse to the common mode current going through transistors 402 and 408. This inverse common mode current (comprising the first current signal and second current signal) is then provided to the output of transistors 402 and 408, i.e. the nodes 404 and 410. If the inverse common mode current (comprising the first current signal and second current signal) is substantially the same magnitude as the current at these nodes due to the common mode signal, but with opposite sign, the net common mode at the output of the amplifier 400 can be reduced or cancelled completely.

[0064] Thus, in some examples the amplifier 400 of Figure 4A at least partially cancels the common mode signal at the output of the cascode, i.e. at the outputs of the transistors 402 and 408.

[0065] Figure 4B is a circuit diagram of another example of an amplifier 430 according to an example of this disclosure. In Figure 4B, like components are given like reference numerals as for Figure 4A. However, in Figure 4B, the outputs of the gain stage 422 are connected to the first input node 406 and second input node 412 instead of the first node 404 and second node 410 respectively.

[0066] Figure 4C is a circuit diagram of another example of an amplifier 450 according to an example of this disclosure. In Figure 4C, like components are given like reference numerals as for Figure 4A. The amplifier 450 of Figure 4C includes apparatus 426 configured to determine the signal 424 representing the input common mode signal in the input signal and to provide the signal 424 representing the input common mode signal to the gain stage 422. In the example shown in Figure 4C, the nodes 406 and 412 of the amplifier 450 are provided as inputs to the apparatus 426.

[0067] In some examples, the apparatus 426 comprises a filter configured to filter the input signal to provide the input common mode signal. The reason this is possible in some examples is that a cascode arrangement using a common gate configuration, as in some examples of Figure 4C, typically has a finite input impedance. For example, the transistors 402 and 408 may be a cascode arrangement with a common gate configuration. In a first approximation, this input impedance may for example be 1 / gm. A current flowing through this impedance will create a corresponding voltage on the cascode input (i.e. the source terminal). If the cascode is configured as a differential pair, as in Figure 4A, then any common mode component in the input current will create a common mode voltage on the cascode differential input. It is this voltage that serves as the input for the filter capturing the common mode signal.

[0068] The filter can be implemented in several ways, but from reasons of speed at RF frequencies and not really any need for gain and linearity, the source follower was selected as shown for example in Figures 5A and 5B and described below. By summing the positive and negative side source follower outputs, in some examples, the signal representing the input common mode signal may be created without disturbing the input signal.

[0069] In some examples, the signal representing the input common mode signal may then be converted into current using a transconductance stage. The current created may be added to the output current from the transistors 402 and 408. By configuring the configurable gain in the transconductance stage, the common mode signal output from the transistors 402 and 408 can be cancelled out to a high degree. This arrangement may increase current consumption as compared to for example the amplifier 200 of Figure 2, as both the gain stage 422 and the apparatus 426 (e.g. source follower) may consume current.

[0070] Figure 5A is a circuit diagram of an amplifier 500 that is an example implementation of the amplifier of Figure 4C. In Figure 5A, like components are given like reference numerals as for Figure 4C. In the amplifier 500 of Figure 5A, the apparatus 426 comprises a sixth transistor 502, wherein a drain of the sixth transistor 502 is connected to a third reference voltage, and a gate of the sixth transistor 502 is connected to the first input node 306. The apparatus 426 also comprises a seventh transistor 504, wherein a drain of the seventh transistor 504 is connected to the third reference voltage, and a gate of the seventh transistor 504 is connected to the second input node 412. The apparatus 426 also comprises a third current source 540 configured to provide a first apparatus bias current at the sources of the sixth transistor 502 and the seventh transistor 504.

[0071] In the amplifier 500, the gain stage 422 comprises an eighth transistor 508. The gate of the eighth transistor 508 is connected (in the example shown, via a fifth capacitor 520) to a node configured to receive the signal 424 representing an input common mode signal, which in the example shown is the sources of the transistors 502 and 504. A drain of the eighth transistor 508 is connected to the first node 404. A fourth current source 542 is configured to provide a second apparatus bias current at the source of the eighth transistor 508.

[0072] The gain stage 422 also comprises a ninth transistor 512, wherein a gate of the ninth transistor 512 is connected to the gate of the eighth transistor 508, and a drain of the ninth transistor 512 is connected to the second node 410. A fifth current source 544 is configured to provide a third apparatus bias current at the source of the ninth transistor 512.

[0073] The gain stage 422 also comprises a third capacitor 516 connected between the source of the eighth transistor 508 and a fourth reference voltage, and a fourth capacitor 518 connected between the source of the ninth transistor 512 and a fifth reference voltage. An impedance 522 (in this example, a resistor) is connected between the gate of the eighth transistor 508 and a sixth reference voltage.

[0074] The fourth reference voltage may be for example the same reference voltage as the fifth reference voltage. Additionally or alternatively, in some examples, the third reference voltage, the fourth reference voltage, the fifth reference voltage and / or the sixth reference voltage comprises the first reference voltage or the second reference voltage referred to above.

[0075] In some alternative examples, the sources of the eighth transistor 508 and ninth transistor 512 may be connected together. In such examples, there may be one current source providing a bias current to the eighth transistor 508 and ninth transistor 512, and one capacitor connected between the source of the eighth transistor 508 and the fourth reference voltage (and thus the capacitor is also connected between source of the eighth transistor 508 and the fourth reference voltage). Therefore, in some examples, the gain stage 422 comprises an eighth transistor 508, wherein a gate of the eighth transistor 508 is connected to a node configured to receive the signal 424 representing an input common mode signal, and a drain of the eighth transistor 508 is connected to the first node 404. The gain stage 422 also comprises a ninth transistor 512, wherein a gate of the ninth transistor 512 is connected to the gate of the eighth transistor 508, a drain of the ninth transistor 512 is connected to the second node 410, and a source of the ninth transistor 512 is connected to a source of the eighth transistor 508. The gain stage 422 also comprises a fourth current source configured to provide a third apparatus bias current at the source of the ninth transistor 512, a third capacitor connected between the source of the eighth transistor 508 and a fourth reference voltage, and an impedance 522 connected between the gate of the eighth transistor (508) and a sixth reference voltage. In some of these examples, the third reference voltage, the fourth reference voltage and / or the sixth reference voltage may comprise the first reference voltage or the second reference voltage. In some of these examples, the fourth current source comprises an eleventh transistor, wherein a source of the eleventh transistor is connected to the second reference voltage, and a drain of the eleventh transistor is connected to a source of the eighth transistor 508 (and therefore also the source of the ninth transistor 512).

[0076] In some examples, a gain of the eighth transistor 508 and / or a gain of the ninth transistor 512 are configurable, such that the gain of the gain stage 422 is configurable.

[0077] Figure 5B is a circuit diagram of an amplifier 550 that is another example implementation of the amplifier of Figure 4C. In the amplifier 550, the first current source 440 in Figure 5A is implemented as a third transistor 418. A source of the third transistor 418 is connected to a second reference voltage, and a drain of the third transistor 418 is configured to receive the first input current signal (e.g. is connected to the first input node 406). The third transistor 418 is configured to provide the first bias current at the first input node 406;

[0078] In the amplifier 550, the second current source 442 is implemented as a fourth transistor 420. A source of the fourth transistor 420 is connected to the second reference voltage, and a drain of the fourth transistor 420 is configured to receive the second input current signal (e.g. is connected to the second input node 412). The fourth transistor is configured to provide the second bias current at the second input node 412.

[0079] The third transistor 418 and fourth transistor 420 may be configured to cause the respective bias currents in some examples as follows. The amplifier 550 includes a fifth transistor 422, wherein a source of the fifth transistor 422 is connected to the first reference voltage or the second reference voltage, and a gate of the fifth transistor 422 is connected to a drain of the fifth transistor 422. The drain of the fifth transistor 422 is configured to receive a bias current, and the gate of the fifth transistor 422 is connected to a gate of the third transistor 418 and a gate of the fourth transistor 420. Thus, the current through transistor 422 may be mirrored by transistors 418 and 420.

[0080] In the amplifier 550, the third current source 540 is implemented as a tenth transistor 506, wherein a source of the tenth transistor 506 is connected to the second reference voltage, and a drain of the tenth transistor 506 is connected to a source of the sixth transistor 502 and a source of the seventh transistor 504. A gate of the tenth transistor 506 is connected to the gate of the fifth transistor 422, and thus in some examples the current through transistor 422 may be mirrored by transistor 506.

[0081] Also in the amplifier 550, the fourth current source 542 is implemented as an eleventh transistor 510, wherein a source of the eleventh transistor 510 is connected to the second reference voltage, and a drain of the eleventh transistor 510 is connected to a source of the eighth transistor 508. The fifth current source 544 is implemented as a twelfth transistor 514, wherein a source of the twelfth transistor 514 is connected to the second reference voltage, and a drain of the twelfth transistor 514 is connected to a source of the ninth transistor 512. A gate of the eleventh transistor 510 and a gate of the twelfth transistor 514 are connected to the gate of the fifth transistor 422, and thus in some examples the current through transistor 422 may be mirrored by transistors 510 and 514.

[0082] The amplifier 550 also includes a load network 530 between the first reference voltage and the first 404 and second 410 nodes. In the example shown in Figure 5B, the load network comprises a first resistor 414 connected between the drain of the first transistor 402 and a first reference voltage, and a second resistor 416 connected between the drain of the second transistor 408 and the first reference voltage. Generally, the load network 530 may in some examples comprise at least one of the following: a resistive load, inductive load, transistor-based load and capacitive load.

[0083] In the above examples, the first gate bias voltage may in some examples comprise a seventh reference voltage, and the second gate bias voltage may comprise the seventh reference voltage. The seventh reference voltage may in some examples be the same as any of the other reference voltages, such as for example the first or second reference voltage.

[0084] In an alternative example, the sources of the eighth transistor 508 and ninth transistor 512 may be connected together in a manner suggested above for some examples of the amplifier 500 of Figure 5A. In such examples, the fourth capacitor 518 and twelfth transistor 514 may be omitted.

[0085] In alternative examples of the amplifiers of Figures 4G, 5A and 5B, either or both of the outputs of the gain stage 422 may be connected to the first input node 406 and second input node 412 instead of the first node 404 and second node 410 respectively, as in Figure 4B. Therefore, for example, the drain of the eighth transistor 508 may be connected to the first input node 406, and / or the drain of the ninth transistor 512 may be connected to the second input node 412.

[0086] Figure 6A is a circuit diagram of another example of an amplifier 600 according to an example of this disclosure. The amplifier 600 includes a first transistor 602. A drain of the first transistor 602 is connected to a first node 604 of the amplifier, and a source of the first transistor 602 is connected to a first input node 606 of the amplifier. The first input node 606 is for receiving a first input current signal of an input signal.

[0087] The amplifier also comprises a second transistor 608. A drain of the second transistor 608 is connected to a second node 610 of the amplifier, and a source of the second transistor 608 is connected to a second input node 612 of the amplifier. The second input node 612 is for receiving a second input current signal of the input signal.

[0088] In the amplifier 600, a gate of the first transistor 602 and a gate of the second transistor 608 are connected via at least one impedance 614 (e.g. a resistor) to a seventh reference voltage. The impedance 614 may be a resistor or an inductor or other passive or active impedance or combinations thereof. In one embodiment the impedance 614 has a high impedance value, that is an impedance in the same order of or higher than an impedance provided at the gate of the first and second transistors 602 or 608, in such a way that the gates of the first and second transistors 602 and 608 are substantially AC-floating, while being connected together. A first current source 630 is configured to provide a first bias current at the first input node 606, and a second current source 632 configured to provide a second bias current at the second input node 612.

[0089] The amplifier of Figure 6A thus includes a way to suppress the common mode signal in the input signal by allowing the gates of transistors 602 and 608 to track the input common mode voltage. In Figure 6A, this is done by AC-floating the gates of the transistors 602 and 608. By connecting the gate of one of the transistors 602 and 608 to the gate of the other, differential input signals will cancel but a common mode signal will collectively make the common gates track the common mode signal. A high degree of cancellation may be dependent for example on high and matched coupling through the gate-source capacitance (Cgs) on each cascode. However, in some examples with additional parasitic couplings to ground or elsewhere, perfect tracking may not be achievable. Simulations returned about 16 dB of common mode rejection in the amplifier 600 of Figure 6A. A particular advantage of the amplifier 600 of Figure 6A is that there is little or no impact on the current consumption as compared for example to the amplifier 200 shown in Figure 2.

[0090] Figure 6B is a circuit diagram of an amplifier 650 that is an example implementation of the amplifier of Figure 6A. In the amplifier 650, the first current source 630 is implemented as a third transistor 620, wherein a source of the third transistor 620 is connected to a second reference voltage, and a drain of the third transistor 620 is configured to receive the first input current signal (e.g. is connected to the first input node 606). The third transistor 620 is configured to provide the first bias current at the first input node 606. The second current source 632 is implemented as a fourth transistor 622, wherein a source of the fourth transistor 622 is connected to the second reference voltage, and a drain of the fourth transistor 622 is configured to receive the second input current signal (e.g. is connected to the second input node 612). The fourth transistor 622 is configured to provide the second bias current at the second input node 612.

[0091] The amplifier 650 of Figure 6B also includes a fifth transistor 628. A source of the fifth transistor 628 is connected to the first reference voltage or the second reference voltage, and a gate of the fifth transistor 628 is connected to a drain of the fifth transistor 628, wherein the drain of the fifth transistor 628 is configured to receive a bias current. The gate of the fifth transistor 628 is connected to a gate of the third transistor 620 and a gate of the fourth transistor 622. Thus, in some examples, the current through transistor 628 may be mirrored through transistors 620 and 622.

[0092] The amplifier 650 also comprises a load network 634 between a first reference voltage and the first 604 and second 610 nodes. In the example shown in Figure 6B, the load network 634 comprises a first resistor 616 connected between the drain of the first transistor 602 and a first reference voltage, and a second resistor 618 connected between the drain of the second transistor 608 and the first reference voltage. More generally, in some examples, the load network 634 may comprise at least one of the following: a resistive load, inductive load, transistor-based load and capacitive load.

[0093] An amplifier according to examples of this disclosure may combine features of one or more amplifiers as described herein. For example, the amplifier according to Figure 3A or 3B that includes cross-coupled capacitors 322 and 324 may include the gain stage 422 of Figure 4A, 4B, 4C, 5A or 5B, and may also include the apparatus 426 of Figure 4B, 4C, 5A or 5B. Additionally or alternatively, the amplifier according to Figure 3A or 3B may include the arrangement for biasing transistors 602 and 608 of Figure 6A or 6B, i.e. may include the impedance 614 to bias transistors 302 and 308. Similarly, the amplifier according to Figure 4A, 4B, 4C, 5A or 5B may include the cross-coupled capacitors of Figure 3A or 3B, and may also include the resistors 326 and 328 of Figure 3B. Additionally or alternatively, the amplifier according to Figure 4A, 4B, 4C, 5A or 5B may include the arrangement for biasing transistors 602 and 608 of Figure 6A or 6B, i.e. may include the impedance 614 to bias transistors 402 and 408. Similarly, the amplifier according to Figure 6A or 6B may include features from Figure 3A or 3B, and / or from Figure 4A, 4B, 4C, 5A or 5B. Figure 7 is a circuit diagram of another example of an amplifier 700 according to an example of this disclosure. The amplifier 700 includes features from Figures 3B, 5B and 6B. Thus, the amplifier 700 includes cross-coupled capacitors 322 and 324 and resistors 326 and 328, apparatus 426 and gain stage 422, and impedance 614 for biasing the gates of transistors 302 and 308. A simulation of the amplifier 700 of Figure 7 indicated that it is possible to achieve a total of 30 dB common mode suppression.

[0094] In the examples described herein, “connected to” may mean connected directly, with no additional components in between, or alternatively may mean connected via one or more additional components not shown in the Figures, such as for example cascode transistors, other transistors, resistors, capacitors, inductors and / or other electronic components.

[0095] Figure 8 illustrates an example of an integrated circuit 800 comprising an amplifier 802 according to examples of this disclosure, such as for example the amplifier 300, 350, 370, 400, 430, 450, 500, 550, 600, 650 or 700 shown in Figure 3A, 3B, 3C, 4A, 4B, 4C, 5A, 5B, 6A, 6B or 7 respectively. Figure 9 illustrates an example of an electronic apparatus 900 comprising an amplifier 902 according to examples of this disclosure, such as for example the amplifier 300, 350, 370, 400, 430, 450, 500, 550, 600, 650 or 700 shown in Figure 3A, 3B, 3C, 4A, 4B, 4C, 5A, 5B, 6A, 6B or 7 respectively. The electronic apparatus may in some examples be a communication apparatus. For example, the communication apparatus may be a wireless communication device for a cellular communications system. Alternatively, for example, the communication apparatus may be a base station for a cellular communications system.

[0096] It should be noted that the above-mentioned examples illustrate rather than limit the invention, and that those skilled in the art will be able to design many alternative examples without departing from the scope of the appended statements. The word “comprising” does not exclude the presence of elements or steps other than those listed in a claim, “a” or “an” does not exclude a plurality, and a single processor or other unit may fulfil the functions of several units recited in the statements below. Where the terms, “first”, “second” etc. are used they are to be understood merely as labels for the convenient identification of a particular feature. In particular, they are not to be interpreted as describing the first or the second feature of a plurality of such features (i.e. , the first or second of such features to occur in time or space) unless explicitly stated otherwise. Steps in the methods disclosed herein may be carried out in any order unless expressly otherwise stated. Any reference signs in the statements shall not be construed so as to limit their scope.

Claims

Claims1. An amplifier (300, 350, 700) comprising: a first transistor (302), wherein a drain of the first transistor (302) is connected to a first node (304) of the amplifier, a source of the first transistor (302) is connected to a first input node (306) of the amplifier, and a gate of the first transistor (302) is connected to a first gate bias voltage, wherein the first input node (306) is for receiving a first input current signal of an input signal; a second transistor (308), wherein a drain of the second transistor (308) is connected to a second node (310) of the amplifier, a source of the second transistor (308) is connected to a second input node (312) of the amplifier, and a gate of the second transistor (308) is connected to a second gate bias voltage, wherein the second input node (312) is for receiving a second input current signal of the input signal; a first current source (340) configured to provide a first bias current at the first input node (306); and a second current source (342) configured to provide a second bias current at the second input node (312); wherein the amplifier further comprises: a first capacitor (322) connected between the first input node (306) and a control node (348) of the second current source (342); a second capacitor (324) connected between the second input node (312) and a control node (346) of the first current source (340).

2. The amplifier of claim 1 , comprising a load network (344) between a first reference voltage and the first (304) and second (310) nodes.

3. The amplifier of claim 2, wherein the load network comprises: a first resistor (314) connected between the drain of the first transistor (302) and a first reference voltage; and a second resistor (316) connected between the drain of the second transistor (308) and the first reference voltage.

4. The amplifier of claim 2 or 3, wherein the load network (344) comprises at least one of the following: a resistive load, inductive load, transistor-based load and capacitive load.

5. The amplifier of any of claims 1 to 4, wherein:the first current source (340) comprises a third transistor (318), wherein a source of the third transistor (318) is connected to a second reference voltage, and a drain of the third transistor (318) is connected to the first input node (306) wherein the third transistor (318) is configured to provide the first bias current at the first input node (306); and / or the second current source (342) comprises a fourth transistor (320), wherein a source of the fourth transistor is connected to the second reference voltage, and a drain of the fourth transistor (320) is connected to the second input node (312), wherein the fourth transistor is configured to provide the second bias current at the second input node (312).

6. The amplifier of claim 5, wherein: the first capacitor (322) is connected between the first input node (306) and a gate of the fourth transistor (320); and the second capacitor (324) is connected between the second input node (312) and a gate of the third transistor (318).

7. The amplifier of claim 5 or 6, further comprising: a fifth transistor (336), wherein a source of the fifth transistor (336) is connected to the first reference voltage or the second reference voltage, and a gate of the fifth transistor (336) is connected to a drain of the fifth transistor (336), wherein the drain of the fifth transistor (336) is configured to receive a bias current, and the gate of the fifth transistor (336) comprises a gate bias voltage provisioning node (330); a third resistor (326) connected between the gate of the third transistor (318) and the gate bias voltage provisioning node; and a fourth resistor (328) connected between the gate of the fourth transistor and the gate bias voltage provisioning node.

8. The amplifier of any of claims 1 to 7, further comprising a gain stage (422) configured to receive a signal (424) representing an input common mode signal in the input signal and to provide a first current signal to the first node (404) or the first input node (406) and / or a second current signal to the second node (410) or the second input node (412), and wherein the first current signal and / or the second current signal at least partially cancel a current, due to the input common mode signal, at the first node (404) or the first input node (406) and / or at the second node (410) or the second input node (412).

9. The amplifier of claim 8, further comprising apparatus (426) configured to determine the signal (424) representing the input common mode signal in the input signal and to provide the signal (424) representing the input common mode signal to the gain stage (422).

10. The amplifier of claim 9, wherein the apparatus (426) comprises a filter configured to filter the input signal to provide the input common mode signal.

11. The amplifier of any of claim 9 or 10, wherein the apparatus (426) comprises: a sixth transistor (502), wherein a drain of the sixth transistor (502) is connected to a third reference voltage, and a gate of the sixth transistor (502) is connected to the first input node (306); a seventh transistor (504), wherein a drain of the seventh transistor (504) is connected to the third reference voltage, and a gate of the seventh transistor (504) is connected to the second input node (312); and a third current source (540) configured to provide a first apparatus bias current at the sources of the sixth transistor (502) and the seventh transistor (504).

12. The amplifier of claim 11 , wherein the third current source (540) comprises a tenth transistor (506), wherein a source of the tenth transistor (506) is connected to the second reference voltage, and a drain of the tenth transistor (506) is connected to a source of the sixth transistor (502) and a source of the seventh transistor (504);13. The amplifier of claim 12 when dependent on claim 7, wherein a gate of the tenth transistor (506) is connected to the gate of the fifth transistor (336, 422).

14. The amplifier of any of claims 8 to 13, wherein: the first current signal is provided to the first node (404) or the first input node (406) to at least partially cancel a first common mode current at the first node (404) or the first input node (406) due to the input common mode signal; and / or the second current signal is provided to the second node (410) or the second input node (412) to at least partially cancel a second common mode current at the second node (410) or the second input node (412) due to the input common mode signal.

15. The amplifier of any of claims 8 to 14, wherein a gain of the gain stage (422) is configurable so as to configure an amplitude of the first current signal and / or the second current signal.

16. The amplifier of any of claims 8 to 15, wherein the gain stage (422) comprises: an eighth transistor (508), wherein a gate of the eighth transistor (508) is connected to a node configured to receive the signal (424) representing an input common mode signal,and a drain of the eighth transistor (508) is connected to the first node (404) or the first input node (406); a fourth current source (542) configured to provide a second apparatus bias current at the source of the eighth transistor (508); a ninth transistor (512), wherein a gate of the ninth transistor (512) is connected to the gate of the eighth transistor (508), and a drain of the ninth transistor (512) is connected to the second node (410) or the second input node (412); a fifth current source (544) configured to provide a third apparatus bias current at the source of the ninth transistor (512); a third capacitor (516) connected between the source of the eighth transistor (508) and a fourth reference voltage; a fourth capacitor (518) connected between the source of the ninth transistor (512) and a fifth reference voltage; and an impedance (522) connected between the gate of the eighth transistor (508) and a sixth reference voltage.

17. The amplifier of claim 16, wherein: the fourth reference voltage is the same reference voltage as the fifth reference voltage; and / or the third reference voltage, the fourth reference voltage, the fifth reference voltage and / or the sixth reference voltage comprises the first reference voltage or the second reference voltage.

18. The amplifier of claim 16 or 17, wherein: the fourth current source (542) comprises an eleventh transistor (510), wherein a source of the eleventh transistor (510) is connected to the second reference voltage, and a drain of the eleventh transistor (510) is connected to a source of the eighth transistor (508); and / or the fifth current source (544) comprises a twelfth transistor (514), wherein a source of the twelfth transistor (514) is connected to the second reference voltage, and a drain of the twelfth transistor (514) is connected to a source of the ninth transistor (512).

19. The amplifier of claim 18 when dependent on claim 7, wherein a gate of the eleventh transistor (510) and a gate of the twelfth transistor (514) are connected to the gate of the fifth transistor (336, 422).

20. The amplifier of any of claims 8 to 15, wherein the gain stage (422) comprises:an eighth transistor (508), wherein a gate of the eighth transistor (508) is connected to a node configured to receive the signal (424) representing an input common mode signal, and a drain of the eighth transistor (508) is connected to the first node (404) or the first input node (406); a ninth transistor (512), wherein a gate of the ninth transistor (512) is connected to the gate of the eighth transistor (508), a drain of the ninth transistor (512) is connected to the second node (410) or the second input node (412), and a source of the ninth transistor (512) is connected to a source of the eighth transistor (508); a fourth current source configured to provide a third apparatus bias current at the source of the ninth transistor (512); a third capacitor connected between the source of the eighth transistor (508) and a fourth reference voltage; and an impedance (522) connected between the gate of the eighth transistor (508) and a sixth reference voltage.

21. The amplifier of any of claims 16 to 20, comprising a fifth capacitor (520), wherein the gate of the eighth transistor (508) is connected, via the fifth capacitor (520), to the node configured to receive the signal (424) representing the input common mode signal.

22. The amplifier of any of claims 16 to 21 , wherein a gain of the eighth transistor (508) and / or a gain of the ninth transistor (512) are configurable.

23. The amplifier of any of claims 1 to 22, wherein: the first gate bias voltage comprises a seventh reference voltage, and the second gate bias voltage comprises the seventh reference voltage; and / or the gate of the first transistor (302) and the gate of the second transistor (308) are connected via at least one resistor (614) to the seventh reference voltage.

24. The amplifier of any of claims 1 to 23, wherein the first reference voltage comprises a first power supply voltage, and the second reference voltage comprises a second power supply voltage, zero volts, or ground.

25. An amplifier (400, 430, 450, 500, 550, 700) comprising: a first transistor (402), wherein a drain of the first transistor (402) is connected to a first node (404) of the amplifier, a source of the first transistor (402) is connected to a first input node (406) of the amplifier, and a gate of the first transistor (402) is connected to a firstgate bias voltage, wherein the first input node (406) is for receiving a first input current signal of an input signal; a second transistor (408), wherein a drain of the second transistor (408) is connected to a second node (410) of the amplifier, a source of the second transistor (408) is connected to a second input node (412) of the amplifier, and a gate of the second transistor (408) is connected to a second gate bias voltage, wherein the second input node (412) is for receiving a second input current signal of the input signal; a first current source (440) configured to provide a first bias current at the first input node (406); and a second current source (442) configured to provide a second bias current at the second input node (412); wherein the amplifier further comprises: a gain stage (422) configured to receive a signal (424) representing an input common mode signal in the input signal and to provide a first current signal to the first node (404) or the first input node (406), and / or a second current signal to the second node (410) or the second input node (412), and wherein the first current signal and / or the second current signal at least partially cancel a current due to the input common mode signal at the first node (404) or the first input node (406), and / or at the second node (410) or the second input node (412).

26. The amplifier of claim 25, comprising a load network (530) between a first reference voltage and the first (404) and second (410) nodes.

27. The amplifier of claim 26, wherein the load network comprises: a first resistor (414) connected between the drain of the first transistor (402) and a first reference voltage; and a second resistor (416) connected between the drain of the second transistor (408) and the first reference voltage.

28. The amplifier of claim 26 or 27, wherein the load network (530) comprises at least one of the following: a resistive load, inductive load, transistor-based load and capacitive load.

29. The amplifier of any of claims 25 to 28, wherein: the first current signal is provided to the first node (404) or the first input node (406) to at least partially cancel a first common mode current at the first node (404) or the first input node (406) due to the input common mode signal; and / orthe second current signal is provided to the second node (410) or the second input node (412) to at least partially cancel a second common mode current at the second node (410) or the first input node (412) due to the input common mode signal.

30. The amplifier of any of claims 25 to 29, wherein a gain of the gain stage (422) is configurable so as to configure an amplitude of the first current signal and / or the second current signal.

31. The amplifier of any of claims 25 to 30, wherein: the first current source (440) comprises a third transistor (418), wherein a source of the third transistor (418) is connected to a second reference voltage, and a drain of the third transistor is connected to the first input node (406), wherein the third transistor is configured to provide the first bias current at the first input node (406); and / or the second current source (442) comprises a fourth transistor (420), wherein a source of the fourth transistor (420) is connected to the second reference voltage, and a drain of the fourth transistor (420) is connected to the second input node (412), wherein the fourth transistor is configured to provide the second bias current at the second input node (412).

32. The amplifier of claim 31 , further comprising a fifth transistor (422), wherein a source of the fifth transistor (422) is connected to the first reference voltage or the second reference voltage, and a gate of the fifth transistor (422) is connected to a drain of the fifth transistor (422), wherein the drain of the fifth transistor (422) is configured to receive a bias current, and the gate of the fifth transistor (422) is connected to a gate of the third transistor (418) and a gate of the fourth transistor (420).

33. The amplifier of any of claims 25 to 32, wherein the amplifier further comprises: a first capacitor (322) connected between the first input node (406) and a control node (348) of the second current source; and a second capacitor (324) connected between the second input node (412) and a control node (346) of the first current source.

34. The amplifier of claim 33, further comprising: a fifth transistor (336), wherein a source of the fifth transistor (336) is connected to the first reference voltage or the second reference voltage, and a gate of the fifth transistor (336) is connected to a drain of the fifth transistor (336), wherein the drain of the fifthtransistor (336) is configured to receive a bias current, and the gate of the fifth transistor (336) comprises a gate bias voltage provisioning node (330); a third resistor (326) connected between the gate of the third transistor (318) and the gate bias voltage provisioning node (330); and a fourth resistor (328) connected between the gate of the fourth transistor (320) and the gate bias voltage provisioning node (330).

35. The amplifier of any of claims 25 to 34, further comprising apparatus (426) configured to determine the signal (424) representing the input common mode signal in the input signal and to provide the signal (424) representing the input common mode signal to the gain stage (422).

36. The amplifier of claim 35, wherein the apparatus (426) comprises a filter configured to filter the input signal to provide the input common mode signal.

37. The amplifier of any of claim 35 or 36, wherein the apparatus (426) comprises: a sixth transistor (502), wherein a drain of the sixth transistor (502) is connected to a third reference voltage, and a gate of the sixth transistor (502) is connected to the first input node (406); a seventh transistor (504), wherein a drain of the seventh transistor (504) is connected to the third reference voltage, and a gate of the seventh transistor (504) is connected to the second input node (412); and a third current source (540) configured to provide a first apparatus bias current at the sources of the sixth transistor (502) and the seventh transistor (504).

38. The amplifier of claim 37, wherein the third current source (540) comprises a tenth transistor (506), wherein a source of the tenth transistor (506) is connected to the second reference voltage, and a drain of the tenth transistor (506) is connected to a source of the sixth transistor (502) and a source of the seventh transistor (504);39. The amplifier of claim 38 when dependent on claim 32 or 34, wherein a gate of the tenth transistor (506) is connected to the gate of the fifth transistor (336, 422).

40. The amplifier of any of claims 25 to 39, wherein the gain stage (422) comprises: an eighth transistor (508), wherein a gate of the eighth transistor (508) is connected to a node configured to receive the signal (424) representing an input common mode signal,and a drain of the eighth transistor (508) is connected to the first node (404) or the first input node (406); a fourth current source (542) configured to provide a second apparatus bias current at the source of the eighth transistor (508); a ninth transistor (512), wherein a gate of the ninth transistor (512) is connected to the gate of the eighth transistor (508), and a drain of the ninth transistor (512) is connected to the second node (410) or the second input node (412); a fifth current source (544) configured to provide a third apparatus bias current at the source of the ninth transistor (512); a third capacitor (516) connected between the source of the eighth transistor (508) and a fourth reference voltage; a fourth capacitor (518) connected between the source of the ninth transistor (512) and a fifth reference voltage; and an impedance (522) connected between the gate of the eighth transistor (508) and a sixth reference voltage.

41. The amplifier of claim 40, wherein: the fourth reference voltage is the same reference voltage as the fifth reference voltage; and / or the third reference voltage, the fourth reference voltage, the fifth reference voltage and / or the sixth reference voltage comprises the first reference voltage or the second reference voltage.

42. The amplifier of claim 40 or 41 , wherein: the fourth current source (542) comprises an eleventh transistor (510), wherein a source of the eleventh transistor (510) is connected to the second reference voltage, and a drain of the eleventh transistor (510) is connected to a source of the eighth transistor (508); and / or the fifth current source (544) comprises a twelfth transistor (514), wherein a source of the twelfth transistor (514) is connected to the second reference voltage, and a drain of the twelfth transistor (514) is connected to a source of the ninth transistor (512).

43. The amplifier of claim 42 when dependent on claim 32 or 34, wherein a gate of the eleventh transistor (510) and a gate of the twelfth transistor (514) are connected to the gate of the fifth transistor (422).

44. The amplifier of any of claims 25 to 39, wherein the gain stage (422) comprises:30 an eighth transistor (508), wherein a gate of the eighth transistor (508) is connected to a node configured to receive the signal (424) representing an input common mode signal, and a drain of the eighth transistor (508) is connected to the first node (404) or the first input node (406); a ninth transistor (512), wherein a gate of the ninth transistor (512) is connected to the gate of the eighth transistor (508), a drain of the ninth transistor (512) is connected to the second node (410) or the second input node (412), and a source of the ninth transistor (512) is connected to a source of the eighth transistor (508); a fourth current source configured to provide a third apparatus bias current at the source of the ninth transistor (512); a third capacitor connected between the source of the eighth transistor (508) and a fourth reference voltage; and an impedance (522) connected between the gate of the eighth transistor (508) and a sixth reference voltage.

45. The amplifier of any of claims 40 to 44, comprising a fifth capacitor (520), wherein the gate of the eighth transistor (508) is connected, via the fifth capacitor (520), to the node configured to receive the signal (424) representing the input common mode signal.

46. The amplifier of any of claims 40 to 45, wherein a gain of the eighth transistor (508) and / or a gain of the ninth transistor (512) are configurable.

47. The amplifier of any of claims 25 to 46, wherein: the first gate bias voltage comprises a seventh reference voltage, and the second gate bias voltage comprises the seventh reference voltage; and / or the gate of the first transistor (402) and the gate of the second transistor (408) are connected via at least one resistor (614) to the seventh reference voltage.

48. The amplifier of any of claims 25 to 47, wherein the first reference voltage comprises a first power supply voltage, and the second reference voltage comprises a second power supply voltage, zero volts, or ground.

49. An amplifier (600, 650, 700) comprising: a first transistor (602), wherein a drain of the first transistor (602) is connected to a first node (604) of the amplifier, and a source of the first transistor (602) is connected to a first input node (606) of the amplifier, wherein the first input node (606) is for receiving a first input current signal of an input signal;31 a second transistor (608), wherein a drain of the second transistor (608) is connected to a second node (610) of the amplifier, and a source of the second transistor (608) is connected to a second input node (612) of the amplifier, wherein the second input node (612) is for receiving a second input current signal of the input signal, and wherein a gate of the first transistor (602) and a gate of the second transistor (608) are connected via at least one impedance (614) to a seventh reference voltage; a first current source (630) configured to provide a first bias current at the first input node (606); and a second current source (632) configured to provide a second bias current at the second input node (612).

50. The amplifier of claim 49, comprising a load network (634) between a first reference voltage and the first (604) and second (610) nodes.

51. The amplifier of claim 50, wherein the load network (634) comprises: a first resistor (616) connected between the drain of the first transistor (602) and a first reference voltage; and a second resistor (618) connected between the drain of the second transistor (608) and the first reference voltage.

52. The amplifier of claim 50 or 51 , wherein the load network (634) comprises at least one of the following: a resistive load, inductive load, transistor-based load and capacitive load.

53. The amplifier of any of claims 49 to 52, wherein: the first current source (630) comprises a third transistor (620), wherein a source of the third transistor (620) is connected to a second reference voltage, and a drain of the third transistor (620) is connected to the first input node (606), wherein the third transistor (620) is configured to provide the first bias current at the first input node (606); and / or the second current source (632) comprises a fourth transistor (622), wherein a source of the fourth transistor (622) is connected to the second reference voltage, and a drain of the fourth transistor (622) is connected to the second input node (612), wherein the fourth transistor (622) is configured to provide the second bias current at the second input node (612).

54. The amplifier of claim 53, further comprising a fifth transistor (628), wherein a source of the fifth transistor (628) is connected to the first reference voltage or the second reference32 voltage, and a gate of the fifth transistor (628) is connected to a drain of the fifth transistor (628), wherein the drain of the fifth transistor (628) is configured to receive a bias current, and the gate of the fifth transistor (628) is connected to a gate of the third transistor (620) and a gate of the fourth transistor (622).

55. The amplifier of any of claims 49 to 54, wherein the amplifier further comprises: a first capacitor (322) connected between the first input node (306) and a control node (348) of the second current source; and a second capacitor (324) connected between the second input node (310) and a control node (346) of the first current source.

56. The amplifier of claim 55, further comprising: a fifth transistor (336), wherein a source of the fifth transistor (336) is connected to the first reference voltage or the second reference voltage, and a gate of the fifth transistor (336) is connected to a drain of the fifth transistor (628), wherein the drain of the fifth transistor (336) is configured to receive a bias current, and the gate of the fifth transistor (336) comprises a gate bias voltage provisioning node (330); a third resistor (326) connected between the gate of the third transistor (318) and the gate bias voltage provisioning node (330); and a fourth resistor (328) connected between the gate of the fourth transistor (320) and the gate bias voltage provisioning node (330).

57. The amplifier of any of claims 49 to 56, wherein the amplifier further comprises a gain stage (422) configured to receive a signal (424) representing an input common mode signal in the input signal and to provide a first current signal to the first node (404) or the first input node (406) and / or a second current signal to the second node (410) or the second input node (412), and wherein the first current signal and / or the second current signal at least partially cancel a current due to the input common mode signal at the first node (404) or the first input node (406) and / or at the second node (410) or the second input node (412).

58. The amplifier of claim 57, further comprising apparatus (426) configured to determine the signal (424) representing the input common mode signal in the input signal and to provide the signal (424) representing the input common mode signal to the gain stage (422).

59. The amplifier of claim 58, wherein the apparatus (426) comprises a filter configured to filter the input signal to provide the input common mode signal.3360. The amplifier of any of claim 58 or 59, wherein the apparatus (426) comprises: a sixth transistor (502), wherein a drain of the sixth transistor (502) is connected to a third reference voltage, and a gate of the sixth transistor (502) is connected to the first input node (306); a seventh transistor (504), wherein a drain of the seventh transistor (504) is connected to the third reference voltage, and a gate of the seventh transistor (504) is connected to the second input node (312); and a third current source (540) configured to provide a first apparatus bias current at the sources of the sixth transistor (502) and the seventh transistor (504).

61. The amplifier of claim 60, wherein the third current source (540) comprises a tenth transistor (506), wherein a source of the tenth transistor (506) is connected to the second reference voltage, and a drain of the tenth transistor (506) is connected to a source of the sixth transistor (502) and a source of the seventh transistor (504);62. The amplifier of claim 61 when dependent on claim 52 or 54, wherein a gate of the tenth transistor (506) is connected to the gate of the fifth transistor (336, 422).

63. The amplifier of any of claims 57 to 62, wherein: the first current signal is provided to the first node (404) or the first input node (406) to at least partially cancel a first common mode current at the first node (404) or the first input node (406) due to the input common mode signal; and / or the second current signal is provided to the second node (410) or the second input node (412) to at least partially cancel a second common mode current at the second node (410) or the second input node (412) due to the input common mode signal.

64. The amplifier of any of claims 57 to 63, wherein a gain of the gain stage (422) is configurable so as to configure an amplitude of the first current signal and / or the second current signal.

65. The amplifier of any of claims 57 to 64, wherein the gain stage (422) comprises: an eighth transistor (508), wherein a gate of the eighth transistor (508) is connected to a node configured to receive the signal (424) representing an input common mode signal, and a drain of the eighth transistor (508) is connected to the first node (404) or the first input node (406); a fourth current source (542) configured to provide a second apparatus bias current at the source of the eighth transistor (508);34 an ninth transistor (512), wherein a gate of the ninth transistor (512) is connected to the gate of the eighth transistor (508), and a drain of the ninth transistor (512) is connected to the second node (410) or the second input node (412); a fifth current source (544) configured to provide a third apparatus bias current at the source of the ninth transistor (512); a third capacitor (516) connected between the source of the eighth transistor (508) and a fourth reference voltage; a fourth capacitor (518) connected between the source of the ninth transistor (512) and a fifth reference voltage; and a resistor (522) connected between the gate of the eighth transistor (508) and a sixth reference voltage.

66. The amplifier of claim 65, wherein: the fourth reference voltage is the same reference voltage as the fifth reference voltage; and / or the third reference voltage, the fourth reference voltage, the fifth reference voltage and / or the sixth reference voltage comprises the first reference voltage or the second reference voltage.

67. The amplifier of claim 65 or 66, wherein: the fourth current source (542) comprises an eleventh transistor (510), wherein a source of the eleventh transistor (510) is connected to the second reference voltage, and a drain of the eleventh transistor (510) is connected to a source of the eighth transistor (508); and / or the fifth current source (544) comprises a twelfth transistor (514), wherein a source of the twelfth transistor (514) is connected to the second reference voltage, and a drain of the twelfth transistor (514) is connected to a source of the ninth transistor (512).

68. The amplifier of claim 67 when dependent on claim 54 or 56, wherein a gate of the tenth transistor (506), a gate of the eleventh transistor (510) and a gate of the twelfth transistor (514) are connected to the gate of the fifth transistor (422, 628).

69. The amplifier of any of claims 57 to 64, wherein the gain stage (422) comprises: an eighth transistor (508), wherein a gate of the eighth transistor (508) is connected to a node configured to receive the signal (424) representing an input common mode signal, and a drain of the eighth transistor (508) is connected to the first node (404) or the first input node (406);35 a ninth transistor (512), wherein a gate of the ninth transistor (512) is connected to the gate of the eighth transistor (508), a drain of the ninth transistor (512) is connected to the second node (410) or the second input node (412), and a source of the ninth transistor (512) is connected to a source of the eighth transistor (508); a fourth current source configured to provide a third apparatus bias current at the source of the ninth transistor (512); a third capacitor connected between the source of the eighth transistor (508) and a fourth reference voltage; and an impedance (522) connected between the gate of the eighth transistor (508) and a sixth reference voltage.

70. The amplifier of any of claims 65 to 69, comprising a fifth capacitor (520), wherein the gate of the eighth transistor (508) is connected, via the fifth capacitor (520), to the node configured to receive the signal (424) representing the input common mode signal.

71. The amplifier of any of claims 65 to 70, wherein a gain of the eighth transistor (508) and / or a gain of the ninth transistor (512) are configurable.

72. The amplifier of any of claims 49 to 71 , wherein the first reference voltage comprises a first power supply voltage, and the second reference voltage comprises a second power supply voltage, zero volts, or ground.

73. An amplifier (370) comprising: a first transistor (302), wherein a drain of the first transistor (302) is connected to a first node (304) of the amplifier, a source of the first transistor (302) is connected to a first input node (306) of the amplifier, and a gate of the first transistor (302) is connected to a first gate bias voltage, wherein the first input node (306) is for receiving a first input current signal of an input signal; a second transistor (308), wherein a drain of the second transistor (308) is connected to a second node (310) of the amplifier, a source of the second transistor (308) is connected to a second input node (312) of the amplifier, and a gate of the second transistor (308) is connected to a second gate bias voltage, wherein the second input node (312) is for receiving a second input current signal of the input signal; a first current source (340) configured to provide a first bias current at the first input node (306); and a second current source (342) configured to provide a second bias current at the second input node (312);36 wherein the amplifier further comprises: a buffer stage (372) configured to receive a signal (424) representing an input common mode signal in the input signal and to provide a current source control signal based on the input common mode signal to a control node (346) of the first current source (340) and a control node (348) of the second current source (342).

74. The amplifier of claim 73, wherein the buffer stage (372) is configured to provide the current source control signal via a capacitance (376) to the control node (346) of the first current source (340) and the control node (348) of the second current source (342).

75. The amplifier of claim 73 or 74, comprising a load network (344) between a first reference voltage and the first (304) and second (310) nodes.

76. The amplifier of claim 75, wherein the load network comprises: a first resistor (314) connected between the drain of the first transistor (302) and a first reference voltage; and a second resistor (316) connected between the drain of the second transistor (308) and the first reference voltage.

77. The amplifier of claim 75 or 76, wherein the load network (344) comprises at least one of the following: a resistive load, inductive load, transistor-based load and capacitive load.

78. The amplifier of any of claims 73 to 77, wherein: the first current source (340) comprises a third transistor (318), wherein a source of the third transistor (318) is connected to a second reference voltage, and a drain of the third transistor (318) is connected to the first input node (306) wherein the third transistor (318) is configured to provide the first bias current at the first input node (306); and / or the second current source (342) comprises a fourth transistor (320), wherein a source of the fourth transistor is connected to the second reference voltage, and a drain of the fourth transistor (320) is connected to the second input node (312) wherein the fourth transistor is configured to provide the second bias current at the second input node (312).

79. The amplifier of any of claims 73 to 78, comprising: a fifth transistor, wherein a source of the fifth transistor is connected to the first reference voltage or the second reference voltage, and a gate of the fifth transistor is37 connected to a drain of the fifth transistor, wherein the drain of the fifth transistor is configured to receive a bias current, and the gate of the fifth transistor comprises a gate bias voltage provisioning node (330); and a third resistor (378) connected between the gate bias voltage provisioning node (330) and the gates of the third transistor (318) and fourth transistor (320); wherein the buffer stage (372) is configured to provide the current source control signal to the gates of the third transistor (318) and fourth transistor (320).

80. The amplifier of any of claims 73 to 79, wherein the first reference voltage comprises a first power supply voltage, and the second reference voltage comprises a second power supply voltage, zero volts, or ground.

81. The amplifier of any of claims 73 to 80, wherein: the first gate bias voltage comprises a seventh reference voltage, and the second gate bias voltage comprises the seventh reference voltage; and / or the gate of the first transistor (302) and the gate of the second transistor (308) are connected via at least one impedance (614) to the seventh reference voltage.

82. An integrated circuit (800) comprising the amplifier (300, 350, 370, 400, 430, 450, 500, 550, 600, 650, 700, 802) of any one of claims 1 to 81.

83. An electronic apparatus (900) comprising the amplifier (300, 350, 370, 400, 430, 450, 500, 550, 600, 650, 700, 902) of any one of claims 1 to 81.

84. The electronic apparatus of claim 83, wherein the electronic apparatus (900) is a communication apparatus.

85. The electronic apparatus of claim 84, wherein the communication apparatus is a wireless communication device for a cellular communications system.

86. The electronic apparatus of claim 84, wherein the communication apparatus is a base station for a cellular communications system.

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