An amplifier and its manufacturing method

Abstract

An amplifier includes a transistor, an input circuit coupled between an amplifier input and a transistor input terminal, and an output circuit coupled between a transistor output and a transistor output terminal. The input circuit includes an input-side harmonic termination circuit having a first inductor and a first capacitor connected in series between the transistor input terminal and ground. The output circuit includes a second inductor, an output-side harmonic termination circuit, and a parallel inductor network. The second inductor is coupled between the transistor output terminal and the amplifier output. The output-side harmonic termination circuit includes a third inductor and a second capacitor connected in series between the amplifier output and ground. The parallel inductor network includes a fourth inductor and a third capacitor connected in series between the amplifier output and ground. The input-side and output-side harmonic termination circuits resonate at harmonic frequencies of the amplifier's operating fundamental frequency.

Description

Technical Field

[0001] The embodiments of the subject matter described herein generally relate to radio frequency (RF) amplifiers, and more specifically, to broadband power transistor devices and amplifiers, as well as methods of manufacturing such devices and amplifiers. Background Technology

[0002] Wireless communication systems employ power amplifiers to amplify the power of radio frequency (RF) signals. For example, in a cellular base station, a Dougherty power amplifier can form part of the final amplification stage in the transmit chain before the amplified signal is supplied to the antenna for radiation through the air interface. The desired characteristics of power amplifiers in such wireless communication systems are high gain, high linearity, stability, and a high level of power-adding efficiency.

[0003] In the field of power amplifier device design, there is an increasing desire for parallel multi-band, wideband amplification. To successfully design wideband power amplifier devices for parallel multi-band, wideband operation in Dougherty power amplifier circuits, it is desirable to achieve, for example, good broadband fundamental matching (e.g., exceeding 20% ​​fractional bandwidth) to properly handle harmonic frequency interactions, and to achieve wide video bandwidth. However, achieving these goals continues to present challenges for power amplifier device designers. Summary of the Invention

[0004] According to one aspect of the present invention, an amplifier is provided, comprising: an amplifier input; an amplifier output; a transistor having a transistor input terminal and a transistor output terminal; an input circuit coupled between the amplifier input and the transistor input terminal, wherein the input circuit includes an input-side harmonic termination circuit having a first inductor and a first capacitor connected in series between the transistor input terminal and a ground reference node, wherein the input-side harmonic termination circuit resonates at a harmonic frequency of the fundamental operating frequency of the amplifier; and an output circuit coupled to the transistor output terminal, wherein the output circuit includes a second inductor coupled between the transistor output terminal and the amplifier output, an output-side harmonic termination circuit including a third inductor and a second capacitor connected in series between the amplifier output and the ground reference node, wherein the output-side harmonic termination circuit resonates at the harmonic frequency; and a parallel inductor network including a fourth inductor and a third capacitor connected in series between the amplifier output and the ground reference node.

[0005] According to some embodiments, the first, second, third and fourth inductor elements respectively include a first group, a second group, a third group and a fourth group of bonding wires.

[0006] According to some embodiments, the first capacitor is implemented in a first integrated passive device, and the second and third capacitors are implemented in a second integrated passive device.

[0007] According to some embodiments, the input circuit further includes an input impedance matching circuit, which includes a fifth inductor coupled between the amplifier input and the first node, a sixth inductor coupled between the first node and the transistor input, and a fourth capacitor coupled between the first node and the ground reference node.

[0008] According to some embodiments, the fifth and sixth inductor elements respectively include a fifth group and a sixth group of bonding wires; and the fourth capacitor is implemented in the first integrated passive device.

[0009] According to some embodiments, the second inductor element, the output-side harmonic termination circuit, and the intrinsic output capacitance of the transistor form a parallel inductor / capacitor (LC) circuit that resonates at or near the second harmonic frequency to effectively create a high impedance to signal energy at the second harmonic frequency.

[0010] According to some embodiments, the parallel inductor network resonates at a frequency lower than the operating fundamental frequency of the amplifier.

[0011] According to some embodiments, the parallel inductor network resonates at an odd multiple of the desired signal bandwidth.

[0012] According to some embodiments, the amplifier further includes a video bandwidth circuit coupled to a connection node between the fourth inductor and the third capacitor, wherein the video bandwidth circuit includes a plurality of components, wherein the plurality of components include an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the connection node and the ground reference node.

[0013] According to some embodiments, the video bandwidth circuit also includes a bypass capacitor that is coupled in parallel across one or more of the plurality of components of the video bandwidth circuit.

[0014] According to some embodiments, a bypass capacitor is coupled in parallel across the envelope inductor, and the envelope inductor and the bypass capacitor form a parallel resonant circuit near the center operating frequency of the amplifier.

[0015] According to some embodiments, the transistor is a gallium nitride transistor.

[0016] According to some embodiments, the transistor has a drain-source capacitance of less than 0.2 picofarads per watt.

[0017] According to some embodiments, a transistor, an input circuit, and an output circuit form part of a first amplification path, and the amplifier further includes: a second amplification path; a power divider having an input configured to receive a radio frequency (RF) signal, a first output coupled to the input of the first amplification path, and a second output coupled to the input of the second amplification path, wherein the power divider is configured to divide the RF signal into a first RF signal provided to the first amplification path via the first output and a second RF signal provided to the second amplification path via the second output; and a combining node configured to receive and combine the amplified RF signals generated by the first and second amplification paths.

[0018] According to some embodiments, the amplifier is a Dougherty power amplifier.

[0019] According to another aspect of the present invention, a packaged radio frequency (RF) amplifier device is provided, comprising: a device substrate; an input lead coupled to the device substrate; an output lead coupled to the device substrate; a transistor die coupled to the device substrate, wherein the transistor die includes a transistor, a transistor input terminal coupled to the input lead, and a transistor output terminal coupled to the output lead; an input circuit coupled between the input lead and the transistor input terminal, wherein the input circuit includes an input-side harmonic termination circuit having a first capacitor coupled to the device substrate and a first set of bonding wires coupled between the transistor input terminal and the first capacitor, wherein... An input-side harmonic termination circuit resonates at a harmonic frequency of the operating fundamental frequency of the RF amplifier; and an output circuit coupled to the transistor output terminal and the output lead, wherein the output circuit includes a second set of bonding lines coupled between the transistor output terminal and the first output lead; an output-side harmonic termination circuit including a second capacitor coupled to the device substrate and a third set of bonding lines coupled between the output lead and the second capacitor, wherein the output-side harmonic termination circuit resonates at the harmonic frequency; and a parallel inductor network including a third capacitor coupled to the device substrate and a fourth set of bonding lines coupled between the output lead and the third capacitor.

[0020] According to some embodiments, the packaged RF amplifier device further includes: a first integrated passive device coupled to the device substrate, wherein the first capacitor forms part of the first integrated passive device; and a second integrated passive device coupled to the device substrate, wherein the second and third capacitors form part of the second integrated passive device.

[0021] According to some embodiments, the packaged RF amplifier device further includes: a video bandwidth circuit coupled to a connection node between the fourth set of bonding lines and the third capacitor, wherein the video bandwidth circuit includes a plurality of components, wherein the plurality of components include an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the connection node and the ground reference node.

[0022] According to some embodiments, the packaged RF amplifier device further includes an input impedance matching circuit comprising a fifth set of bonding lines coupled between the input lead and the first node, a sixth set of bonding lines coupled between the first node and the transistor input terminal, and a fourth capacitor coupled to the device substrate.

[0023] According to another aspect of the present invention, a method for manufacturing an RF amplifier device is provided, comprising the steps of: coupling an input lead to a device substrate; coupling an output lead to the device substrate; coupling a transistor die to the device substrate between the input and output leads, wherein the transistor die includes a transistor, a transistor input terminal, and a transistor output terminal; coupling first, second, third, and fourth capacitors to the device substrate; forming an input-side harmonic termination circuit by connecting a first set of bonding wires between the transistor input terminal and the first capacitor, wherein the input-side harmonic termination circuit resonates at a harmonic frequency of the operating fundamental frequency of the RF amplifier device; forming an input-side impedance matching circuit by connecting a second set of bonding wires between the transistor input terminal and the second capacitor and a third set of bonding wires between the input lead and the second capacitor; connecting a third set of bonding wires between the transistor output terminal and the output lead; forming an output-side harmonic termination circuit by connecting a fourth set of bonding wires between the output lead and the third capacitor, wherein the output-side harmonic termination circuit resonates at the harmonic frequency; and forming a parallel inductor network by connecting a fifth set of bonding wires between the output lead and the fourth capacitor. Attached Figure Description

[0024] Considering the following figures, and with reference to the detailed description and claims, a more complete understanding of the subject matter can be obtained. Similar reference numerals are used throughout the figures to refer to similar elements.

[0025] Figure 1 This is a schematic circuit diagram of a power amplifier circuit according to an example embodiment;

[0026] Figures 2A to 2F Various example embodiments of video bandwidth circuitry are shown;

[0027] Figure 3 This is a simplified schematic diagram of a Dougherty power amplifier according to an example embodiment;

[0028] Figure 4 This is a top view of a packaged RF power amplifier device including two parallel amplification paths according to an example embodiment;

[0029] Figure 5 This is a top view of a portion of a packaged RF power amplifier device according to an example embodiment, the portion including a portion of a power transistor and an input impedance matching circuit;

[0030] Figure 6 According to the example embodiment Figure 5 The portion of the RF power amplifier device is shown in a cross-sectional side view along line 6-6;

[0031] Figure 7 This is a top view of a portion of a packaged RF power amplifier device according to an example embodiment, the portion including a portion of a power transistor and an output impedance matching circuit;

[0032] Figure 8 According to the example embodiment Figure 7 The portion of the RF power amplifier device is shown in a cross-sectional side view along line 8-8; and

[0033] Figure 9 This is a flowchart of a method for manufacturing a packaged RF power amplifier device according to an example embodiment. Detailed Implementation

[0034] An embodiment of the amplifier includes an amplifier input, an amplifier output, a transistor, an input circuit, and an output circuit. The transistor has a transistor input terminal and a transistor output terminal. The input circuit is coupled between the amplifier input and the transistor input terminal, and includes an input-side harmonic termination circuit comprising a first inductor and a first capacitor connected in series between the transistor input terminal and a ground reference node. The input-side harmonic termination circuit resonates at a harmonic frequency of the amplifier's operating fundamental frequency. The output circuit is coupled to the transistor output terminal. The output circuit includes a second inductor coupled between the transistor output terminal and the amplifier output, an output-side harmonic termination circuit, and a parallel inductor network. The output-side harmonic termination circuit includes a third inductor and a second capacitor connected in series between the amplifier output and the ground reference node, and resonates at the harmonic frequency. The parallel inductor network includes a fourth inductor and a third capacitor connected in series between the amplifier output and the ground reference node.

[0035] In another embodiment, the first, second, third, and fourth inductor elements each include a first group, a second group, a third group, and a fourth group of junction lines, respectively. In yet another embodiment, the first capacitor is implemented in a first integrated passive device, and the second and third capacitors are implemented in a second integrated passive device. In yet another embodiment, the input circuit further includes an input impedance matching circuit, which includes a fifth inductor element coupled between the amplifier input and the first node, a sixth inductor element coupled between the first node and the transistor input, and a fourth capacitor coupled between the first node and a ground reference node. In yet another embodiment, the fifth and sixth inductor elements each include a fifth group and a sixth group of junction lines, respectively, and the fourth capacitor is implemented in the first integrated passive device. In yet another embodiment, the second inductor element, the output-side harmonic termination circuit, and the intrinsic output capacitance of the transistor form a parallel inductor / capacitor (LC) circuit that resonates at or near the second harmonic frequency to effectively create a high impedance to signal energy at the second harmonic frequency. In yet another embodiment, the parallel inductor network resonates at a frequency lower than the amplifier's operating fundamental frequency. In yet another embodiment, the parallel inductor network resonates at an odd multiple of the desired signal bandwidth. In yet another embodiment, the transistor is a gallium nitride transistor. In yet another embodiment, the transistor has a drain-source capacitance of less than 0.2 picofarads per watt.

[0036] In another embodiment, the amplifier further includes a video bandwidth circuit coupled to a connection node between a fourth inductor and a third capacitor, wherein the video bandwidth circuit includes multiple components, and the multiple components include an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the connection node and a ground reference node. In another embodiment, the video bandwidth circuit further includes one or more bypass capacitors coupled in parallel across one or more of the multiple components of the video bandwidth circuit. In yet another embodiment, the bypass capacitor is coupled in parallel across the envelope inductor, and wherein the envelope inductor and the bypass capacitor form a parallel resonant circuit near the center operating frequency of the amplifier.

[0037] In another embodiment, the transistor, input circuitry, and output circuitry form a portion of a first amplification path, and the amplifier further includes a second amplification path, a power divider, and a combining node. The power divider has an input configured to receive a radio frequency (RF) signal, a first output coupled to the input of the first amplification path, and a second output coupled to the input of the second amplification path. The power divider is configured to divide the RF signal into a first RF signal provided to the first amplification path via the first output and a second RF signal provided to the second amplification path via the second output. The combining node is configured to receive and combine the amplified RF signals generated by the first and second amplification paths. In yet another embodiment, the amplifier is a Dougherty power amplifier.

[0038] An embodiment of a packaged RF amplifier device includes a device substrate, an input lead coupled to the device substrate, an output lead coupled to the device substrate, a transistor die coupled to the device substrate, an input circuit, and an output circuit. The transistor die includes a transistor, a transistor input coupled to the input lead, and a transistor output coupled to the output lead. The input circuit is coupled between the input lead and the transistor input, and includes an input-side harmonic termination circuit with a first capacitor coupled to the device substrate, and a first set of junction lines coupled between the transistor input and the first capacitor. The input-side harmonic termination circuit resonates at a harmonic frequency of the RF amplifier's operating fundamental frequency. The output circuit is coupled to the transistor output and the output lead. The output circuit includes a second set of junction lines coupled between the transistor output and the first output lead, an output-side harmonic termination circuit, and a parallel inductor network. The output-side harmonic termination circuit includes a second capacitor coupled to the device substrate and a third set of junction lines coupled between the output lead and the second capacitor. The output-side harmonic termination circuit resonates at the harmonic frequency. The parallel inductor network includes a third capacitor coupled to the device substrate and a fourth set of junction lines coupled between the output leads and the third capacitor.

[0039] In another embodiment, the packaged RF amplifier device further includes first and second integrated passive devices coupled to a device substrate. A first capacitor forms part of the first integrated passive device, and second and third capacitors form parts of the second integrated passive device. In yet another embodiment, the packaged RF amplifier device further includes a video bandwidth circuit coupled to a connection node between a fourth set of bonding wires and a third capacitor, wherein the video bandwidth circuit includes multiple components, and the multiple components include an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the connection node and a ground reference node. In yet another embodiment, the packaged RF amplifier device further includes an input impedance matching circuit, the input impedance matching circuit including a fifth set of bonding wires coupled between an input lead and a first node, a sixth set of bonding wires coupled between the first node and a transistor input terminal, and a fourth capacitor coupled to the device substrate.

[0040] An embodiment of a method for manufacturing an RF amplifier device includes: coupling input leads, output leads, and first, second, third, and fourth capacitors to a device substrate; and coupling a transistor die to the device substrate between the input and output leads. The transistor die includes a transistor, a transistor input terminal, and a transistor output terminal. The method further includes forming an input-side harmonic termination circuit by connecting a first set of bonding wires between the transistor input terminal and the first capacitor, wherein the input-side harmonic termination circuit resonates at a harmonic frequency of the operating fundamental frequency of the RF amplifier device. The method further includes forming an input-side impedance matching circuit by connecting a second set of bonding wires between the transistor input terminal and a second capacitor, and connecting a third set of bonding wires between the input lead and the second capacitor. The method further includes: connecting a third set of bonding wires between the transistor output terminal and the output lead; forming an output-side harmonic termination circuit by connecting a fourth set of bonding wires between the output lead and the third capacitor; and forming a parallel inductor network by connecting a fifth set of bonding wires between the output lead and the fourth capacitor. The output-side harmonic termination circuit resonates at the harmonic frequency.

[0041] Inverse Class-F filter circuits have been used in some types of amplifier topologies to improve amplifier efficiency at both peak and backoff levels. However, conventional inverse Class-F circuits add a significant phase delay at the transistor output. This phase delay may not have a negative impact on some amplifier topologies. However, using a conventional inverse Class-F structure in a Dougherty amplifier topology can make the amplifier's modulation impedance and phase characteristics suboptimal, thus limiting the overall efficiency and RF bandwidth of the Dougherty amplifier.

[0042] This is especially true because the impedance transformation of the phase shift and the specific trajectory of accumulation (e.g., from the eigenplane of the current source to the summing node of the Dougherty combiner) along the main amplifier path of the Dougherty amplifier have a significant impact on the performance of the Dougherty amplifier. The conventional inverse Class-F circuit section can reduce impedance at the fundamental frequency f0 and increase the accumulated phase shift at the second harmonic (2f0) cold spot of the output circuit, particularly under impedance modulation operation (“Zmod”).

[0043] Various embodiments of inverse Class-F amplifiers that address these challenges are described herein. More specifically, the inverse Class-F circuits disclosed herein include input and output harmonic termination circuits and an output parallel inductor network. More specifically, the inverse Class-F amplifier embodiments include power transistors (e.g., transistor 140, Figure 1 ), output inductor (e.g., inductor 132, Figure 1 And two output-side series inductor / capacitor (LC) circuits coupled in parallel between the amplifier output and ground (e.g., circuits 170, 180, ...). Figure 1 The first in a series LC circuit (e.g., circuit 170). Figure 1It acts as a second harmonic terminating circuit, resonating at or near the second harmonic (2f0) of the amplifier's operating fundamental frequency (f0), and is connected in series with the second (e.g., circuit 180) in an LC circuit. Figure 1 It resonates at a selected frequency below the fundamental frequency.

[0044] At the input side of the transistor, an additional series LC circuit (e.g., circuit 130) is connected near the transistor's input (e.g., gate) to act as a second harmonic termination circuit resonating at or near the second harmonic frequency (2f0). Figure 1 This allows the transistor input to present low impedance to signal energy at the second harmonic frequency. The aforementioned input and output circuitry helps the amplifier function as an efficient, high-impedance, inverting Dougherty-friendly, and superlinear inverse Class-F amplifier.

[0045] In some embodiments, the power transistor (e.g., transistor 140, Figure 1 This is implemented using gallium nitride (GaN) transistors. Generally, GaN transistors (and amplifiers using such transistors) exhibit relatively high efficiency and power density compared to conventional silicon-based devices, such as laterally diffused metal-oxide-semiconductor (LDMOS) power transistor devices. However, achieving broadband power amplification (e.g., fractional bandwidth exceeding 20%) using GaN technology presents challenges.

[0046] For example, the nonlinear input capacitance of RF power devices including GaN transistors is known to generate harmonics and intermodulation distortion that can impair efficiency and linearity. Furthermore, compared to silicon-based LDMOS transistors, the drain-source capacitance Cds of GaN-based transistors is relatively low per RF output peak power. For instance, while LDMOS transistors can have a drain-source capacitance exceeding approximately 0.4 pF / W, GaN-based transistors can have a drain-source capacitance less than approximately 0.2 pF / W. If GaN-based transistors are used in conventional devices, a relatively high inductance is required between the parallel capacitors in the transistor output and output impedance matching circuitry to provide adequate output impedance matching.

[0047] Second harmonic termination also plays a crucial role in the overall performance of power amplifier designs using harmonic-sensitive transistors, such as GaN-based transistors, low-power LDMOS transistors, or other transistors. Without information about the second harmonic impedance at the current source plane, it is extremely difficult to tune a power amplifier to achieve relatively high fractional bandwidth and good performance. Furthermore, second harmonic termination can vary significantly over a large bandwidth in broadband applications, further complicating circuit tuning.

[0048] The embodiments disclosed herein can use a simple input T-type matching network (e.g., input impedance matching circuit 110, Figure 1 This achieves broadband input impedance matching at the fundamental frequency. Additionally, as discussed above, this is achieved through an input-side harmonic termination circuit (e.g., circuit 130). Figure 1 This includes processing harmonic termination at the transistor input. Additionally, an output-side harmonic termination circuit (e.g., circuit 170) is implemented at the amplifier's output. Figure 1 ).

[0049] Figure 1 This is a schematic diagram of an RF power amplifier circuit 100 with an inverse Class F topology (i.e., an inverse Class F amplifier). In an embodiment, circuit 100 includes an input 102 (e.g., a first conductive package lead), an input impedance matching circuit 110 (which includes a harmonic termination circuit 130), a transistor 140, an output impedance matching circuit 150 (which includes a harmonic termination circuit 170), a video bandwidth circuit 162, and an output lead 104 (e.g., a second conductive package lead). Each of the input 102 and the output 104 may be more generally referred to as an "RF input / output (I / O)".

[0050] The input impedance matching circuit 110 (including harmonic termination circuit 130) can be referred to as the "input circuit". Similarly, the output impedance matching circuit 150 (including harmonic termination circuit 170) and the video bandwidth circuit 162 can be collectively referred to as the "output circuit". Although the individual elements of transistor 140 and the input impedance matching circuits 110 and 150, the video bandwidth circuit 162, and the harmonic termination circuits 130 and 170 are shown as single components, this depiction is for ease of explanation only. Based on the description herein, those skilled in the art will understand that certain elements of transistor 140 and / or the input impedance matching circuit 110 (including harmonic termination circuit 130), the output impedance matching circuit 150 (including harmonic termination circuit 170), and the video bandwidth circuit 162 can be implemented as multiple components (e.g., connected in parallel or series with each other). Furthermore, embodiments may include single-path devices (e.g., including a single input lead, output lead, transistor, etc.), dual-path devices (e.g., including two input leads, output leads, transistors, etc.), and / or multi-path devices (e.g., including two or more input leads, output leads, transistors, etc.). Additionally, the number of input / output leads may not be the same as the number of transistors (e.g., for a given set of input / output leads, multiple transistors may operate simultaneously). Therefore, the following description of the transistor 140 and various elements of the input impedance matching circuit 110 (including harmonic termination circuit 130), output impedance matching circuit 150 (including harmonic termination circuit 170), and video bandwidth circuit 162 is not intended to limit the scope of the invention to the embodiments shown.

[0051] Input 102 and output 104 may each include a conductor configured to electrically couple circuit 100 to an external circuitry (not shown). More specifically, input 102 and output 104 are physically positioned across the exterior and interior of a device package. Input impedance matching circuitry 110 (including harmonic termination circuitry 130) is electrically coupled between input 102 and a first terminal 142 (e.g., gate) of transistor 140, which is also located within the device. Similarly, output impedance matching circuitry 150 (including harmonic termination circuitry 170) and video bandwidth circuitry 162 are electrically coupled between a second terminal 144 (e.g., drain) of transistor 140 and output 104.

[0052] According to an embodiment, transistor 140 is the primary active component of circuit 100. Transistor 140 includes a control terminal 142 and two conductive terminals 144 and 145, wherein the conductive terminals 144 and 145 are spatially and electrically spaced apart by variable conductivity channels. For example, transistor 140 may be a field-effect transistor (FET), which includes a gate (control terminal 142), a drain (first conductive terminal 144), and a source (second conductive terminal 145). According to an embodiment, and using in a non-limiting manner the nomenclature commonly applied to FETs, the gate 142 of transistor 140 is coupled to input impedance matching circuit 110 (including harmonic termination circuit 130), the drain 144 of transistor 140 is coupled to output impedance matching circuit 150 (including harmonic termination circuit 170) and video bandwidth circuit 162, and the source 145 of transistor 140 is coupled to ground (or another voltage reference). The current between the conductive terminals of transistor 140 can be modulated by varying the control signal supplied to the gate of transistor 140.

[0053] According to various embodiments, transistor 140 is a III-V field-effect transistor (e.g., a high electron mobility transistor (HEMT)) that has a relatively low drain-source capacitance Cds compared to silicon-based FETs (e.g., LDMOS FETs). Figure 1 In the transistor, the drain-source capacitance of transistor 140 is used for the drain of transistor 140 and transistor output terminal 144 (for example, corresponding to transistor output terminal 744). Figure 7 The capacitor 146 between the transistor 140 and the source is represented by the capacitor 146. More precisely, capacitor 146 is not a physical component, but rather the drain-source capacitance of transistor 140. According to embodiments, transistor 140 may have a drain-source capacitance of less than about 0.2 pF / W. Furthermore, in some embodiments, transistor 140 may be a GaN FET, but in other embodiments, transistor 140 may be another type of III-V transistor (e.g., gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), or indium antimonide (InSb)), or another type of transistor with a relatively low drain-source capacitance. In yet another embodiment, transistor 140 may be a silicon-based FET (e.g., an LDMOS FET).

[0054] Input impedance matching circuit 110 is coupled between input 102 and control terminal 142 (e.g., gate) of transistor 140. Input impedance matching circuit 110 is configured to raise the impedance of circuit 100 to a higher (e.g., intermediate or higher) impedance level (e.g., in the range of about 2 ohms to about 10 ohms or higher).

[0055] According to an embodiment, the input impedance matching circuit 110 has a T-type matching topology, comprising two inductor elements 112, 116 (e.g., two sets of junction lines) and a parallel capacitor 114. A first inductor element 112 (e.g., a first set of junction lines) is coupled between the input 102 and node 118, which in turn is coupled to a first end of the capacitor 114. A second inductor element 116 (e.g., a second set of junction lines) is coupled between node 118 (or the first end of the capacitor 114) and the control terminal 142 of the transistor 140. A second end of the capacitor 114 is coupled to ground (or another voltage reference). The combination of inductor elements 112, 116 and parallel capacitor 114 acts as a low-pass filter. According to an embodiment, the series combination of inductor elements 112, 116 may have an inductance value ranging from about 50 picohenries (pH) to about 3 nanohenries (nH), and the parallel capacitor 114 may have a capacitance value ranging from about 5 picofarads (pF) to about 120 pF. In some embodiments, the parallel capacitor 114 may have a relatively large capacitance (e.g., more than about 60 pF) to provide an acceptable low RF impedance point.

[0056] Additionally, the harmonic termination circuit 130 is coupled between the control terminal 142 (e.g., the gate) of the transistor 140 and ground (or another voltage reference). The harmonic termination circuit 130 includes an inductor 132 (e.g., a third set of junction lines) and a capacitor 134, both coupled in series between the control terminal 142 of the transistor 140 and ground (or another voltage reference). According to an embodiment, the values ​​of the inductor 132 and the first capacitor 134 are selected such that the harmonic termination circuit 130 resonates at or near the second harmonic frequency 2f0. If below 2f0, the harmonic termination circuit 130 exhibits a capacitive effect. Essentially, the series combination of elements 172 and 174 acts as a low-impedance ground path for signal energy at the second harmonic frequency 2f0.

[0057] According to an embodiment, inductor 132 may have an inductance value in the range of about 50 pH to about 20 nH, and capacitor 134 may have a capacitance value in the range of about 0.1 pF to about 100 pF; however, these components may also have values ​​outside these ranges. As will be explained later, the desired inductance and / or capacitance values ​​for achieving a low-impedance ground path for signal energy at the second harmonic frequency may be affected by the mutual coupling between the bonding wires used to implement inductors 116 and 132.

[0058] On the output side of circuit 100, output impedance matching circuit 150 is coupled between the first conductive terminal 144 (e.g., drain) of transistor 140 and output 104. Output impedance matching circuit 150 is configured to match the output impedance of circuit 100 with the input impedance of external circuitry or components (not shown) that may be coupled to output 104.

[0059] As previously discussed, the output impedance matching circuit 150 has an inverse Class-F topology, which includes an output inductor 152 and two output-side series inductor / capacitor (LC) circuits 170 and 180 coupled in parallel between the first conductive terminal 144 (e.g., drain) of transistor 140 and ground. The first series LC circuit 170 acts as a harmonic terminating circuit, resonating at or near the second harmonic (2f0) of the amplifier's operating fundamental frequency (f0), and the second series LC circuit 180 resonates at a selected frequency below the fundamental frequency.

[0060] According to an embodiment, the output impedance matching circuit 150 includes a first inductor element 152 (e.g., a fourth set of junction lines, also referred to herein as the "output inductor") coupled between a first conductive terminal 144 (e.g., drain) of transistor 140 and output 104, wherein a first node 160 is present between the first inductor element 152 and output 104. As will be explained more fully below, the first node 160 corresponds to an RF cold spot at the second harmonic frequency 2f0 (i.e., twice the operating fundamental frequency f0 of amplifier 100). Furthermore, the value of inductor element 152 is chosen such that it resonates at 2f0 and has the drain-source capacitance Cds 146 of transistor 140. Because the first node 160 corresponds to an RF cold spot at 2f0, inductor element 152 resonates at 2f0 and has the drain-source capacitance Cds 146 of transistor 140 to form a very high impedance at 2f0, as seen in transistor 140.

[0061] The output impedance matching circuit 150 also includes a harmonic termination circuit 170 in the form of a first series LC circuit coupled between the first node 160 and a voltage reference (e.g., ground), wherein the first series LC circuit includes a second inductor element 172 (e.g., a fifth set of bonding wires) and a first capacitor 174 coupled in series. According to an embodiment, the values ​​of the inductor element 172 and the first capacitor 174 are selected such that the first LC circuit 170 resonates at the second harmonic frequency 2f0, thereby causing the first node 160 to exhibit an RF cold spot at 2f0. Below 2f0, the harmonic termination circuit 170 exhibits a capacitive effect. Essentially, the series combination of elements 172 and 174 acts as a low-impedance ground path for signal energy at the second harmonic frequency 2f0. As will be explained later, the desired inductance and / or capacitance values ​​for achieving a low-impedance ground path for signal energy at the second harmonic frequency may be affected by the mutual coupling between the bonding wires used to implement the inductors 152, 154, and 172.

[0062] The output inductor 152, harmonic terminating circuit 170, and intrinsic output capacitance 146 of transistor 140 form a parallel LC circuit resonating at or near the second harmonic frequency to effectively create a high impedance to signal energy at the second harmonic frequency. More specifically, during operation of amplifier 100, harmonic terminating circuit 170 is substantially equivalent to a capacitor at the fundamental operating frequency (f0) of amplifier 100, with a capacitance value approximately equivalent to the effective capacitance of the series-coupled inductor 172 and capacitor 174 of harmonic terminating circuit 170. Because this equivalent parallel capacitance from the combination of series-coupled inductor 172 and capacitor 174 is coupled in parallel with the intrinsic output capacitance 146 of power transistor 140, the equivalent parallel capacitance in harmonic terminating circuit 170 effectively increases the intrinsic output capacitance 146 of transistor 140. In some embodiments, the equivalent parallel capacitor of the series-coupled combination of inductor 172 and capacitor 174 in harmonic termination circuit 170 has an intrinsic output capacitance that effectively increases the capacitance value of the transistor to which it is connected by at least 10% (e.g., between 10% and about 100% or more).

[0063] According to an embodiment, the output impedance matching circuit 150 further includes a parallel inductor network 180 in the form of a second parallel LC circuit coupled between the first node 160 and the voltage reference, wherein the parallel inductor network 180 includes a third inductor element 154 (e.g., a sixth set of junction lines) and a second capacitor 156 coupled in series. A second node 158 exists between the inductor element 154 and the capacitor element 156 and corresponds to an RF cold spot at the fundamental frequency f0. The values ​​of the third inductor element 154 and the second capacitor 156 are selected such that the parallel inductor network 180 resonates at a sub-fundamental frequency (i.e., a frequency below the fundamental frequency f0). Therefore, the parallel inductor network 180 exhibits a negative susceptance applied to node 160 at f0. In various embodiments, the resonant frequency of the parallel inductor network 180 is selected based on the desired signal bandwidth (SBW). For example, the parallel inductor network 180 can be configured to resonate at an odd multiple of the desired signal bandwidth, such as 3xSBW, 5xSBW, 7xSBW, or some other frequency, in order to suppress the corresponding intermodulation products.

[0064] The parallel inductor network 180 forms an output parallel inductor structure with an output inductance 152 and an intrinsic output capacitance 146 to increase the output impedance against signal energy at the fundamental frequency and improve performance when the amplifier 100 is included in an inverting Dougherty amplifier (e.g., improve inverting Dougherty “friendliness”). The parallel inductor network 180 can also suppress intermodulation products by self-series resonance at a selected frequency (i.e., a frequency less than the fundamental frequency (f0)).

[0065] According to an embodiment, inductor 152 may have an inductance value in the range of about 0.1 nH to about 40 nH, inductor 154 may have an inductance value in the range of about 0.1 nH to about 40 nH, capacitor 156 may have a capacitance value in the range of about 2 to about 300 pF, inductor 172 may have an inductance value in the range of about 50 pF to about 20 nH, and capacitor 174 may have a capacitance value in the range of about 0.1 pF to about 100 pF, but these components may also have values ​​outside these ranges.

[0066] As described above, transistor 140 has an output harmonic-terminated with an embodiment of an inverse Class F filter circuit (i.e., output impedance matching circuit 150), which includes a negative susceptance of f0 at the 2f0 cold spot of the circuit. This configuration of the output impedance matching circuit 150 can significantly increase the impedance at the package plane (e.g., at output 104) when compared to a conventional output impedance matching circuit, particularly under Zmod. Therefore, the amount of impedance transformation performed on the PCB can be significantly reduced. Consequently, amplifier efficiency can be increased, and the PCB can be made more compact. Additionally, according to the embodiment, by including the negative susceptance at the 2f0 cold spot, the total phase shift of the inverse Class F filter circuit can be significantly reduced, particularly under Zmod, making it possible to design short-phase main amplifier paths for the Dougherty amplifier.

[0067] As described above, the parallel inductor network 180 includes an inductor element 154 and a capacitor 156, and according to an embodiment, an RF low impedance point at the fundamental frequency (or RF "cold spot") exists at node 158 (referred to as the "RF cold spot node") between the parallel inductor element 154 and the parallel capacitor 156. According to an embodiment, a video bandwidth circuit 162 is coupled between the RF cold spot node 158 and the ground reference node. The video bandwidth circuit 162 can be used to improve the low-frequency resonance (LFR) of circuit 100 caused by the interaction between the output impedance matching circuit 150 and the bias feed (not shown) by presenting low impedance at the envelope frequency and / or high impedance at the RF frequency. The video bandwidth circuit 162 can also be considered "invisible" from an RF matching perspective. As will now be combined... Figures 2A to 2F As described, in various embodiments, the video bandwidth circuit 162 may have any of several different circuit configurations.

[0068] For example, Figures 2A to 2F The video bandwidth circuit is shown (e.g., video bandwidth circuit 162). Figure 1 Six example implementations of ). In Figures 2A to 2F In each of these, video bandwidth circuits 200, 201, 202, 203, 204, 205 are coupled to connection node 218 (e.g., node 158). Figure 1Between the connection node 218 and ground (or another voltage reference). Additionally, each video bandwidth circuit 200 to 205 includes an envelope inductor 262L series coupled between the connection node 218 and ground. env Envelope resistor 264R env Envelope capacitor 266C env .exist Figures 2A to 2E In each of these, a first end of the envelope inductor 262 is coupled to node 218, and a second end of the envelope inductor 262 is coupled to node 280. A first end of the envelope resistor 264 is coupled to node 280, and a second end of the envelope resistor 264 is coupled to node 282. A first end of the envelope capacitor 266 is coupled to node 282, and a second end of the envelope capacitor 266 is coupled to ground (or another voltage reference). Although in Figures 2A to 2E In this embodiment, the order of the series of components between node 218 and the ground reference node is envelope inductor 262, envelope resistor 264, and envelope capacitor 266; however, in other embodiments, the order of components in the series circuit may be different. For example, in Figure 2F In the diagram, envelope resistor 264 is coupled between nodes 218 and 284, envelope inductor 262 is coupled between nodes 284 and 286, and envelope capacitor 266 is coupled between node 286 and ground (or another voltage reference).

[0069] refer to Figures 2A to 2F Furthermore, according to the embodiments, the envelope inductor 262 can be implemented as an integrated inductor (e.g., inductor 762, Figure 7 , 8 This can be implemented as a discrete inductor and / or as a set of junction lines coupling connection node 218 to envelope resistor 264 (e.g., through node 280). For example, as will be described in detail later, envelope inductor 262 can be integrally formed as part of an integrated passive device (IPD), such as IPDs 482, 483. Figure 4 , 7 8. For example, the envelope inductor 262 may have an inductance value in the range of about 5 pH to about 2000 pH. Ideally, the envelope inductor 262 has an inductance value less than about 500 pH (e.g., as low as 50 pH or even lower in this embodiment). In other embodiments, the value of the envelope inductor 262 may be lower or higher than the range given above.

[0070] Envelope resistor 264 can be implemented as an integrated resistor (e.g., resistor 764) in one embodiment. Figure 7 , 8 Alternatively, it can be implemented as a discrete resistor in another embodiment. For example, the envelope resistor 264 can be integrally formed as part of the IPD, such as IPDs 482 and 483. Figure 4 ,7 8. In an embodiment, the envelope resistor 264 may have a resistance value in the range of about 0.1 ohms to about 5.0 ohms, but the envelope resistor 264 may also have a resistance value outside this range.

[0071] Envelope capacitor 266 can be implemented as an integrated capacitor (e.g., capacitor 766) in one embodiment. Figure 7 , 8 Alternatively, in another embodiment, it can be implemented as a discrete capacitor (e.g., a "chip capacitor"). For example, the envelope capacitor 266 can be integrally formed as part of an IPD, such as IPDs 482, 483. Figure 4 , 7 8. In an embodiment, the envelope capacitor 266 may have a capacitance value in the range of about 1 nanofarad (nF) to about 1 microfarad (μF), but the envelope capacitor 266 may also have a capacitance value outside this range.

[0072] Figure 2A The first embodiment of the video bandwidth circuit 200 shown includes a simple series combination of an envelope inductor 262, an envelope resistor 264, and an envelope capacitor 266. Conversely, in Figures 2B to 2F In some embodiments, the video bandwidth circuits 201 to 205 may include one or more “bypass” or “parallel” capacitors 268, 270, 272, 274, 276, 278C. para They are coupled in parallel with envelope inductor 262 and / or envelope resistor 264. Each of the bypass capacitors 268, 270, 272, 274, 276, and 278 may be implemented as a discrete capacitor in some embodiments (e.g., capacitor 778). Figure 7 , 8 Alternatively, in other embodiments, it may be implemented as an integrated capacitor. In each of these embodiments, the bypass capacitors 268, 270, 272, 274, 276, and 278 may have a capacitance value ranging from about 3.0 pF to about 1400 pF. In other embodiments, the value of any one of the bypass capacitors 268, 270, 272, 274, 276, and 278 may be lower or higher than the range given above.

[0073] exist Figure 2B In the video bandwidth circuit 201, the bypass capacitor 268C para It is coupled in parallel with the envelope inductor 262. More specifically, the first end of the envelope inductor 262 and the bypass capacitor 268 is coupled to node 218, and the second end of the envelope inductor 262 and the bypass capacitor 268 is coupled to node 280.

[0074] exist Figure 2CIn the video bandwidth circuit 202, the bypass capacitor 270C para It is coupled in parallel with the envelope resistor 364. More specifically, the first end of the envelope resistor 264 and the bypass capacitor 270 is coupled to node 280, and the second end of the envelope resistor 264 and the bypass capacitor 270 is coupled to node 282.

[0075] exist Figure 2D In the video bandwidth circuit 203, the bypass capacitor 272C para It is coupled in parallel with envelope inductor 262 and envelope resistor 264. More precisely, bypass capacitor 272 is coupled across nodes 218 and 282.

[0076] exist Figure 2E In the video bandwidth circuit 204, the first bypass capacitor 274C para1 Coupled in parallel with envelope inductor 262, and second bypass capacitor 276C para2 It is coupled in parallel with envelope resistor 264. More specifically, the first end of envelope inductor 262 and the first bypass capacitor 274 is coupled to node 218, and the second end of envelope inductor 262 and the first bypass capacitor 274 is coupled to node 280. In addition, the first end of envelope resistor 264 and the second bypass capacitor 276 is coupled to node 280, and the second end of envelope resistor 264 and the second bypass capacitor 276 is coupled to node 282.

[0077] refer to Figure 2B , 2E The video bandwidth circuits 201, 204, and 205 of 2F, along with the parallel-coupled inductor 262 and capacitors 268, 274, or 278, form a parallel resonant circuit at a frequency close to the center operating frequency of the device or circuit (e.g., circuit 100), within which circuits 201, 204, or 205 are incorporated. As used herein and according to embodiments, the term "close to the center operating frequency" means "within 20% of the center operating frequency." Thus, for example, when the device has a center operating frequency of 2.0 GHz, the frequency "close to the center operating frequency" corresponds to a frequency in the range of 1.8 GHz to 2.2 GHz. Although 2.0 GHz is given as an example center operating frequency, the device may also have a center operating frequency different from 2.0 GHz. In alternative embodiments, the term "close to the center operating frequency" may mean "within 10% of the center operating frequency" or "within 5% of the center operating frequency."

[0078] Because L env / / C para A parallel resonant circuit is formed at a frequency close to the center operating frequency of the device, therefore the parallel resonant circuit L env / / Cpara Essentially, this presents as an open circuit at such frequencies. Therefore, RF energy that may exist near the center operating frequency at node 218 coupled to circuits 201, 204, or 205 will be transmitted through the parallel resonant circuit L. env / / C para Deflection. This deflection is provided even when inductor 262 uses a relatively low inductance value. For these reasons, circuits 201, 204, and 205 can significantly improve the LFR of the device or circuit (e.g., circuit 100) into which they are incorporated by presenting low impedance at the envelope frequency and high impedance at the RF frequency.

[0079] exist Figure 2C , 2D In each embodiment of the video bandwidth circuits 202, 203, and 204 of 2E, bypass capacitors 270, 272, or 276 are coupled in parallel with envelope resistor 264. Because capacitors 270, 272, or 276 can be used to guide RF current around envelope resistor 264, circuits 202, 203, and 204 can reduce the RF current dissipated by envelope resistor 264. This feature of circuits 202, 203, and 204 can also be used to better protect envelope resistor 264 from potential damage caused by excessive current that would flow through envelope resistor 264 in the absence of bypass capacitors 270, 272, or 276.

[0080] Each of circuits 201 through 205 improves device efficiency compared to circuit 200 because they allow less RF current to flow through (and be dissipated by) envelope resistor 264. Furthermore, because circuits 201 through 205 present high impedance to RF frequencies close to the center operating frequency of the device in which video bandwidth circuitry is incorporated, it is advisable to connect circuits 201 through 205 to an RF low impedance point (e.g., RF low impedance point 158). Figure 1 The specific details are not important, but they can be connected to points with low RF impedance. In fact, the benefits of circuits 201 to 205 can be achieved even when they are coupled to nodes exhibiting high RF impedance. This includes other nodes in the input and output impedance matching circuits.

[0081] Refer again Figure 1 And as will be combined later Figures 4 to 8 In more detail, various embodiments of the RF amplifier device may include at least one input-side integrated passive device (IPD) assembly (e.g., IPD assemblies 480, 481, ...). Figures 4 to 6 ) and at least one output-side IPD assembly (e.g., IPD assemblies 482, 483, Figure 4 , 7(and 8). Input-side IPD assemblies (e.g., IPD assemblies 480, 481) include portions of input circuitry 110 (including harmonic termination circuitry 130). Similarly, output-side IPD assemblies (e.g., IPD assemblies 482, 483) include portions of output circuitry 150 (including harmonic termination circuitry 170) and video bandwidth circuitry 162. More specifically, each IPD assembly may include a semiconductor substrate having one or more integrated passive components. In a particular embodiment, each input-side IPD assembly may include parallel capacitors 114 and 132. In other particular embodiments, each output-side IPD assembly may include parallel capacitors 156 and 174 and components of video bandwidth circuitry 162 (e.g., components 262, 264, 266, 268, 270, 272, 274, 276, 278, ... Figures 2A to 2F ).

[0082] In other embodiments, portions of the input impedance matching circuit 110 and the output impedance matching circuit 150, as well as the video bandwidth circuit 162, may be implemented as different / discrete components or as portions of other types of assemblies (e.g., low-temperature co-fired ceramic (LTCC) devices, small PCB assemblies, etc.). In yet another embodiment, portions of the input impedance matching circuit 110 and / or the output impedance matching circuit 150 may be coupled to and / or integrated within a semiconductor die including the transistor 140. The following detailed description of embodiments including IPD assemblies should not be construed as limiting the subject matter of the invention, and the terms "passive device substrate" or "IPD substrate" refer to any type of structure including passive devices, including IPDs, LTCC devices, transistor dies, PCB assemblies, etc.

[0083] In various embodiments, amplifier circuit 100 may further include bias circuit systems 190, 191. Bias circuit 190 includes an inductor 192 and a capacitor 196 connected in series, and bias circuit 191 includes an inductor 194 and a capacitor 198 connected in series, with intermediate nodes 193, 195 between each inductor / capacitor pair. To provide a bias voltage to the gate terminal 142 and / or drain terminal 144 of transistor 140, external bias circuitry (not shown) may be connected to each of nodes 193, 195, and the bias voltage may be provided through this node. In other embodiments, one or both of the input-side bias circuitry 190 or the output-side bias circuitry 191 may be omitted. In such embodiments, the external bias circuitry may actually be connected to input 102 or output 104, and the bias voltage may be provided through input 102 and / or output 104.

[0084] Figure 1The RF amplifier circuit 100 can be used as a single-path amplifier, receiving an RF signal at input 102, amplifying the signal through transistor 140, and generating an amplified RF signal at output 104. Alternatively, multiple instances of the RF amplifier circuit 100 can be used to provide a multipath amplifier, such as a Dougherty power amplifier or another type of multipath amplifier circuit.

[0085] For example, Figure 3 This is a simplified schematic diagram of a Dougherty power amplifier 300, one embodiment of which can implement the RF power amplifier circuit 100. Amplifier 300 includes an input node 302, an output node 304, a power divider 306 (or splitter), a main amplifier path 320, a peaking amplifier path 321, and a combination node 380. A load 390 can be coupled to combination node 380 (e.g., via an impedance transformer, not shown) to receive amplified RF signals from amplifier 300.

[0086] Power divider 306 is configured to divide the power of the input RF signal received at input node 302 into a principal portion and a peaked portion of the input signal. The principal input signal is provided to main amplifier path 320 at power divider output 308, and the peaked input signal is provided to peaked amplifier path 321 at power divider output 309. During full-power mode operation, when both main amplifier 340 and peaked amplifier 341 supply current to load 390, power divider 306 divides the input signal power between amplifier paths 320, 321. For example, power divider 306 may divide the power equally, such that approximately half of the input signal power is provided to each path 320, 321 (e.g., for a symmetrical Dougherty amplifier configuration). Alternatively, power divider 306 may divide the power unequally (e.g., for an asymmetrical Dougherty amplifier configuration).

[0087] Essentially, the power divider 306 divides the input RF signal supplied at input node 302, and the divided signals are amplified along the main amplifier path 320 and the peaking amplifier path 321, respectively. Then, the amplified signals are combined in phase at the combination node 380. Importantly, maintaining phase coherence between the main amplifier path 320 and the peaking amplifier path 321 within the band of interest ensures that the amplified main signal and the peaked signal arrive at the combination node 380 in phase, and thus ensures proper Dougherty amplifier operation.

[0088] Each of the main amplifier 340 and the peaking amplifier 341 includes one or more single-stage or multi-stage power transistor integrated circuits (ICs) (or power transistor dies) for amplifying RF signals conducted through amplifiers 340, 341. According to various embodiments, all amplification stages or final amplification stages of the main amplifier 340 and / or the peaking amplifier 341 may be implemented, for example, using III-V field-effect transistors (e.g., HEMTs), such as GaN FETs (or another type of III-V transistor, including GaAsFETs, GaP FETs, InP FETs, or InSb FETs). In some embodiments, when only one of the main amplifiers 340 or the peaking amplifier 341 is implemented as a III-V FET, the other amplifier may be implemented as a silicon-based FET (e.g., an LDMOS FET).

[0089] While the primary and peaking power transistor ICs can be of equal size (e.g., in a symmetrical Dougherty configuration), they can also be of unequal size (e.g., in various asymmetrical Dougherty configurations). In asymmetrical Dougherty configurations, the peaking power transistor IC is typically a multiple of the primary power transistor. For example, the peaking power transistor IC can be twice the size of the primary power transistor IC, such that the current-carrying capacity of the peaking power transistor IC is twice that of the primary power transistor IC. Similarly, peaking to main amplifier IC size ratios other than a 2:1 ratio can be implemented.

[0090] During operation of the Dougherty amplifier 300, the main amplifier 340 is biased to operate in Class AB mode, and the peaking amplifier 341 is biased to operate in Class C mode. At low power levels, where the power of the input signal at node 302 is below the turn-on threshold level of the peaking amplifier 341, amplifier 300 operates in low-power (or back-off) mode, where the main amplifier 340 is the only amplifier supplying current to the load 390. When the power of the input signal exceeds the threshold level of the peaking amplifier 341, amplifier 300 operates in high-power mode, where both the main amplifier 340 and the peaking amplifier 341 supply current to the load 390. At this time, the peaking amplifier 341 provides active load modulation at the combined node 380, allowing the current of the main amplifier 340 to continue to increase linearly.

[0091] Input impedance matching network 310 and output impedance matching network 350 (input MNm, output MNm) can be implemented at the input and / or output of main amplifier 340. Similarly, input impedance matching network 311 and output impedance matching network 351 (input MNp, output MNp) can be implemented at the input and / or output of peaking amplifier 341. In each case, matching networks 310, 311, 350, and 351 can be used to gradually increase the circuit impedance towards the load impedance and source impedance. All or part of the input impedance matching networks 310, 311 and output impedance matching networks 350, 351 can be implemented inside a power transistor package including main amplifier 340 and / or peaking amplifier 341, or some portions of the input impedance matching networks 310, 311 and output impedance matching networks 350, 351 can be implemented on a PCB or another substrate on which the power transistor package is mounted.

[0092] In embodiments, at least the main path output impedance matching network 350 includes an embodiment of an inverse Class-F filter circuit. In various embodiments, the peaking path output impedance matching network 351 may also include an embodiment of an inverse Class-F filter circuit, or the peaking path output impedance matching network 351 may be implemented as a high-pass impedance matching circuit topology or a low-pass impedance matching circuit topology. In other words, in one embodiment, the peaking path output impedance matching network 351 may have a different topology than the main path output impedance matching network 350, but in other embodiments, they may have the same topology.

[0093] Additionally, embodiments of the subject matter of this invention include harmonic frequency termination circuits 330 and 331 coupled between the inputs of amplifiers 340 and 341 and a ground reference. Further embodiments of the subject matter of this invention include harmonic frequency termination circuits 370 and 371 coupled between the outputs of amplifiers 340 and 341 and a ground reference. The harmonic frequency termination circuits 330, 331, 370, and 371 are configured to control harmonic impedance over a relatively wide fractional bandwidth. For example, the harmonic frequency termination circuits 330, 331, 370, and 371 can provide a low-impedance ground path for signal energy at the second harmonic 2f0 of the center operating frequency of amplifier 300.

[0094] The Dougherty amplifier 300 has an "inverting" load network configuration. In the inverting configuration, the input circuitry is configured such that, at the center operating frequency f0 of the amplifier 300, the input signal supplied to the main amplifier 340 is delayed by 90 degrees relative to the input signal supplied to the peaking amplifier 341. To ensure that the primary and peaking input RF signals arrive at the main amplifier 340 and peaking amplifier 341 with a phase difference of approximately 90 degrees, which is the basis for proper Dougherty amplifier operation, a phase delay element 382 applies a phase delay of approximately 90 degrees to the primary input signal. For example, the phase delay element 382 may comprise a quarter-wavelength transmit line, or another suitable type of delay element having an electrical length of approximately 90 degrees.

[0095] A 90-degree phase delay difference at the inputs of amplifiers 340 and 341 is applied between the main amplifier path 320 and the peaking amplifier path 321 to compensate for a 90-degree phase delay in the signal applied to the output of the peaking amplifier 341 and the combination node 380. This is achieved using an additional delay element 384.

[0096] Amplifiers 340 and 341, along with portions of harmonic frequency termination circuits 330, 331, 370, 371 and matching networks 310, 311, 350, 351, can be implemented in discrete packaged power amplifier devices. In such devices, input and output leads are coupled to a substrate, and each amplifier 340, 341 may include single-stage or multi-stage power transistors also coupled to the substrate. Portions of harmonic frequency termination circuits 330, 331, 370, 371 and input matching networks 310, 311 and output matching networks 350, 351 can be implemented as additional components within the packaged device. Furthermore, as described in detail below, video bandwidth circuitry (e.g., Figure 1 An embodiment of the VBW circuit 162, in Figures 2A to 2F (As shown in the image) It can also be implemented as an additional component within a packaged device.

[0097] Those skilled in the art will understand that the amplifier embodiments described herein, and more specifically the inverse Class F filter circuit embodiments, can be used in amplifier topologies other than the Dougherty amplifier topology. Although such alternatives are not discussed in detail herein, embodiments including such modifications are intended to be within the scope of the subject matter of this invention.

[0098] Figure 4 This is a top view of an embodiment of a packaged RF amplifier device 400, which embodies... Figure 1 Two parallel instances of circuit 100 can be used to provide a Dougherty amplifier (e.g., Dougherty amplifier 300). Figure 3 Amplifiers in (e.g., amplifiers 340, 341) Figure 3) and parts of the matching network (e.g., parts of matching networks 310, 311, 350, and 351, Figure 3 Additionally, as will be described in more detail below, device 400 includes two input-side IPD assemblies 480, 481, each of which includes input impedance matching circuits 410, 411 (e.g., circuits 110, 310, 311). Figure 1 , 3 The portion of the circuit and harmonic termination circuits 430 and 431 (e.g., circuits 130, 330, and 331) and harmonic termination circuits 430 and 431. Figure 1 , 3 In addition, device 400 includes two output-side IPD assemblies 482 and 483, each output-side IPD assembly including output impedance matching circuits 450 and 451 (e.g., circuits 150, 350, and 351). Figure 1 , 3 The video bandwidth circuits 462 and 463 (e.g., circuit 162) are part of the video bandwidth circuit. Figure 1 ) and harmonic termination circuits 470, 471 (e.g., circuits 170, 370, 371, Figure 1 , 3 ).

[0099] In an embodiment, device 400 includes a flange 406 (or "device substrate") that comprises a rigid conductive substrate with sufficient thickness to provide structural support for the various electrical components and elements of device 400. Additionally, flange 406 can serve as a heat sink for transistor dies 440, 441 and other devices mounted on flange 406. Flange 406 has a top surface and a bottom surface (…). Figure 4 Only the central part of the top surface can be seen in the image, as well as the generally rectangular perimeter corresponding to the perimeter of the device 400.

[0100] Flange 406 is formed of a conductive material and can be used to provide a ground reference node for device 400. For example, individual components and elements may have ends electrically coupled to flange 406, and flange 406 may be electrically coupled to system ground when device 400 is incorporated into a larger electrical system. At least the top surface of flange 406 is formed of a layer of conductive material, and it is possible that the entire flange 406 is formed of a bulk conductive material.

[0101] In one embodiment, the isolation structure 408 is attached to the top surface of the flange 406. The isolation structure 408, formed of a rigid electrically insulating material, provides electrical isolation between conductive features of the device (e.g., between leads 402 to 405 and flange 406). In one embodiment, the isolation structure 408 has a frame shape, comprising a generally closed structure with four sides and a central opening. The isolation structure 408 may have a generally rectangular shape, such as… Figure 4As shown, the isolation structure 408 may have another shape (e.g., ring-shaped, oval, etc.).

[0102] The portion of the top surface of flange 406 exposed through the opening in isolation structure 408 is referred to herein as the “active region” of device 400. Transistor dies 440, 441, together with IPD assemblies 480, 481, 482, 483, are positioned within the active device region of device 400, which will be described in more detail later. For example, transistor dies 440, 441 and IPD assemblies 480 to 483 may be coupled to the top surface of flange 406 using conductive epoxy, solder, solder bumps, sintering, and / or eutectic bonding.

[0103] Device 400 accommodates two amplification paths (indicated by arrows 420, 421), where each amplification path 420, 421 represents circuit 100. Figure 1 The physical implementation scheme of ). When incorporated into a Dougherty amplifier (e.g., Dougherty amplifier 300, Figure 3 In this context, amplification path 420 can correspond to the main amplifier path (e.g., main amplifier path 320). Figure 3 And amplification path 421 can correspond to peaking amplifier path (e.g., peaking amplifier path 321, Figure 3 ).

[0104] Each path 420, 421 includes input leads 402, 403 (e.g., input 102, Figure 1 Output leads 404, 405 (e.g., output 104, Figure 1 ), one or more transistor dies 440, 441 (e.g., transistor 140, Figure 1 Or amplifiers 340 and 341, Figure 3 ), input impedance matching circuits 410, 411 (e.g., input impedance matching circuit 110, Figure 1 Or enter parts of matching networks 310 and 311. Figure 3 ), output impedance matching circuits 450, 451 (e.g., output impedance matching circuit 150, Figure 1 Alternatively, output a portion matching network 350 or 351. Figure 3 ), output-side video bandwidth circuits 462, 463 (e.g., video bandwidth circuit 162, Figure 1 Input-side harmonic termination circuits 430, 431 (e.g., harmonic termination circuits 130, 330, 331, Figure 1 , 3 ) and output-side harmonic termination circuits 470, 471 (e.g., harmonic termination circuits 170, 370, 371, Figure 1 , 3 ).

[0105] Input and output leads 402 to 405 are mounted on the top surface of the isolation structure 408 on opposite sides of the central opening, and thus the input and output leads 402 to 405 are higher than the top surface of the flange 406 and electrically isolated from the flange 406. Generally, the input and output leads 402 to 405 are oriented to allow connection wires to be attached between the input and output leads 402 to 405 and components and elements within the central opening of the isolation structure 408.

[0106] Each transistor die 440, 441 includes an integrated power FET, wherein each FET has a control terminal (e.g., a gate) and two conductive terminals (e.g., a drain and a source). The control terminal of the FET within each transistor die 440, 441 is coupled to input leads 402, 403 via input impedance matching circuits 410, 411. Additionally, one conductive terminal (e.g., a drain) of the FET within each transistor die 440, 441 is coupled to output leads 404, 405 via output impedance matching circuits 450, 451. In an embodiment, the other conductive terminal (e.g., a source) of the FET within each transistor die 440, 441 is electrically coupled to flange 406 (e.g., ground) via die 440, 441.

[0107] Embodiments of input impedance matching circuits 410 and 411 and harmonic termination circuits 430 and 431 will be described later in conjunction with Figure 5 and 6 To describe in more detail, Figure 5 and 6 The components of these circuits 410, 411, 430, and 431 are shown in more detail. (As will be combined...) Figure 5 and 6 To explain, some components of these circuits can be implemented within IPD assemblies 480, 481. Simply put, each input impedance matching circuit 410, 411 is coupled between the input leads 402, 403 and the control terminals of the FETs within transistor dies 440, 441. Each harmonic termination circuit 430, 431 is coupled between the control terminal (e.g., the gate) of the FET within transistor dies 440, 441 and a ground reference (e.g., flange 406).

[0108] Embodiments of the output impedance matching circuits 450, 451 (including harmonic termination circuits 470, 471 and parallel inductor networks 484, 485) and video bandwidth circuits 462, 463 will be combined with Figure 7 , 8 To describe in more detail, Figure 7 , 8 The components of these circuits 450, 451, 462, 463, 470, 471, 484, and 485 are shown in more detail. (As will be combined...) Figure 7 , 8 To explain, some components of these circuits can be implemented within IPD assemblies 482, 483. Simply put, each output impedance matching circuit 450, 451 is coupled between the conductive terminal (e.g., drain) of the FET within transistor dies 440, 441 and output leads 404, 405. Each video bandwidth circuit 462, 463 is coupled between nodes 458, 459 (e.g., RF low-impedance points in the form of conductive pads) and a ground reference (e.g., flange 406) within IPD assemblies 482, 483. Each harmonic termination circuit 470, 471 and the parallel inductor network 484, 485 are coupled between output leads 404, 405 and the ground reference (e.g., flange 406).

[0109] In addition to input and output leads 402 to 405, device 400 may also include a bias circuit system (e.g., corresponding to bias circuits 190, 191, Figure 1 Each bias circuit includes an inductive element (e.g., inductors 192, 194, ...). Figure 1 ) and capacitors 496, 497, 498, 499 (e.g., capacitors 196, 198, Figure 1 The inductor element of each bias circuit may include, for example, a series coupling arrangement of bias leads 492, 493, 494, 495 and bonding wires (e.g., bonding wires 590, 790) coupling each bias lead 492 to 495 to the control terminal (e.g., gate) or conductive terminal (e.g., drain) of the FET within each transistor die 440, 441. Figure 5 , 7 The distal ends of each bias lead 492 to 495 (near each capacitor 496 to 499, and in) Figure 1 The elements (represented as nodes 193, 195) can be electrically coupled to an external bias circuit (not shown) that provides a bias voltage to the control or conductive terminals of each FET via bias leads 492 to 495. In other embodiments, one or both of the input-side or output-side bias circuits may be omitted. In such embodiments, the external bias circuit may actually be connected to input leads 402, 403 or output leads 404, 405, and the bias voltage may be provided via input leads 402, 403 and / or output leads 404, 405.

[0110] exist Figure 4In this example, device 400 includes two transistor dies 440 and 441 that operate substantially in parallel; however, another semiconductor device may similarly include a single transistor die or more than two transistor dies. Additionally, device 400 includes two input-side IPD assemblies 480 and 481 and two output-side IPD assemblies 482 and 483 that also operate substantially in parallel. It should be understood that more or fewer IPD assemblies 480 to 483 may also be implemented.

[0111] According to an embodiment, device 400 is incorporated in an air-chamber package, wherein transistor dies 440, 441, IPD assemblies 480 to 483, and various other components are located within an enclosed air-chamber. Essentially, the air-chamber is bounded by a flange 406, an isolation structure 408, and a cap (not shown) that covers and contacts the isolation structure 408 and leads 402 to 405. Figure 4 In the diagram, the perimeter of the cover is indicated by a dashed box 409. In other embodiments, components of device 400 may be incorporated into an overmolded package (i.e., a package in which electrical components within the active device region are encapsulated with a non-conductive molding compound and portions of leads 402 to 405 are also surrounded by a molding compound). In an overmolded package, the isolation structure 408 may not be included.

[0112] Now for reference Figure 5 and 6 They include device 400 ( Figure 4 An enlarged view of a portion of the image, which includes an embodiment of the input impedance matching circuit 410 and the harmonic termination circuit 430. More precisely, Figure 5 This is a top view of the lower left input side portion 500 of the packaged RF power amplifier device 400 along amplifier path 420. (Please note that this is a partial view of the portion 500.) Figure 5 This includes a portion of a power transistor die 440, a portion of an input lead 402, and an input-side IPD assembly 480. For better understanding, Figure 6 Including according to the example embodiments Figure 5 A cross-sectional side view of portion 500 of the RF power amplifier device along line 6-6. More precisely, Figure 6 This is a cross-sectional view passing through the input lead 402, IPD assembly 480, a portion of flange 406, and transistor die 440. (See diagram below.) Figure 6 As indicated, the power transistor die 440 and IPD assembly 480 are coupled to conductive flange 406, and the input lead 402 is electrically isolated from conductive flange 406 (e.g., using isolation structure 408). It should be noted that the input-side portion of the device 400 along amplifier path 421 may be substantially parallel to... Figure 5 and 6 The part shown is the same as 500.

[0113] The power transistor die 440 includes a transistor input terminal 542 (e.g., a conductive bonding pad) that is electrically connected within the power transistor die 440 to a control terminal (e.g., a gate terminal) of a single-stage or final-stage FET 630 integrated within the die 440. As previously discussed, each FET 630 may include a III-V field-effect transistor (e.g., a HEMT), such as a GaN FET (or another type of III-V transistor, including GaAs FET, GaP FET, InP FET, or InSb FET), or another type of transistor (e.g., an LDMOS FET). More specifically, each FET 630 may be integrally formed within and on a base semiconductor substrate 632 (e.g., a GaN substrate, a GaN-on-silicon substrate, a GaN-on-silicon substrate, a silicon-based substrate, etc.). The conductive connection between the control terminal (e.g., the gate terminal) of FET 630 and the input terminal 542 of die 440 can be made by a stacked structure 634 having alternating dielectric and patterned conductive layers, wherein portions of the patterned conductive layers are electrically connected using conductive vias. A conductive layer 636 on the bottom surface of die 440 can provide a ground node (e.g., for the source end, it can be connected to the conductive layer 636 via a through-substrate via or through a doped deposited region (not shown) (and thus to the conductive flange 406).

[0114] IPD assembly 480 may also include a base semiconductor substrate 682 (e.g., a silicon substrate, silicon carbide substrate, GaN substrate, or another type of semiconductor substrate, which may be referred to herein as an "IPD substrate") and a stacked structure 684 having alternating dielectric and patterned conductive layers, wherein portions of the patterned conductive layers are electrically connected using conductive vias. As will be discussed in more detail below, various electrical components of the input impedance matching circuit 410 and harmonic termination circuit 430 are integrally formed within and / or connected to the IPD assembly 480. These electrical components may be electrically connected to conductive bonding pads (e.g., bonding pads 418, 533) at the top surface of the IPD assembly 480 and may be electrically connected to conductive flanges 406 (e.g., grounded) using through-substrate vias leading to conductive layers 686 on the bottom surface of the IPD assembly 480.

[0115] In some embodiments, the input-side IPD assembly 480 more specifically includes an input impedance matching circuit (e.g., circuit 110, Figure 1 Or circuits 410 and 411, Figure 4 The first parallel capacitor 514 (e.g., parallel capacitor 114,) Figure 1 Harmonic terminating circuits (e.g., circuit 130, Figure 1 Or circuits 430 and 431, Figure 4The second parallel capacitor 534 (e.g., parallel capacitor 134) Figure 1 ).

[0116] First, the connection between transistor die 440 and input lead 402 via input impedance matching circuit 410 will be described in more detail. More specifically, input lead 402 is electrically coupled to input terminal 542 of transistor die 440 via an example of input impedance matching circuit 410. Input terminal 542 is in turn electrically coupled to the control terminal (e.g., gate) of the FET within transistor die 440. For example, in an embodiment, input impedance matching circuit 410 may include two inductor elements 512, 516 (e.g., inductor elements 112, 116, ...). Figure 1 ) and parallel capacitor 514 (e.g., parallel capacitor 114, Figure 1 First inductor element 512 (e.g., inductor element 152, Figure 1 This can be implemented as a first set of bonding wires coupled between the conductive bonding pads 418 on the top surface of the input lead 402 and the IPD assembly 480. The second inductor element 516 (e.g., inductor element 116) Figure 1 This can be implemented as a second set of bonding wires coupled between the conductive bonding pad 418 and the input terminal 542 of the transistor die 440. To avoid... Figure 5 The mix includes only one connection line in this set of connection lines of inductor element 516 that is circled and numbered with reference numeral 516. It should be understood that inductor element 516 includes all connection lines coupled between connection pad 418 and input terminal 542. For example, in an embodiment, conductive connection pad 418 may correspond to (or be coupled to) an RF low-impedance point node (e.g., node 118). Figure 1 ).

[0117] In an embodiment, the first end of the bonding wire 590 may also be connected to the conductive bonding pad 418, wherein the second end of the bonding wire 590 is connected to a bias lead (e.g., bias lead 492). Figure 4 When an external bias circuit provides a bias voltage to the bias lead, the bias voltage can be transmitted to the gate of the FET within the transistor die 440 via bonding line 590, conductive landing pad 418, bonding line 516, and conductive landing pad 542.

[0118] According to an embodiment, the parallel capacitor 514 of each input impedance matching circuit 410 can be implemented as a capacitor (or a set of parallel-coupled capacitors) integrally formed with the IPD substrate of the IPD assembly 480. For example, the parallel capacitor 514 can be implemented as an integrated metal-insulator-metal (MIM) capacitor, which includes first and second conductive electrodes (formed by patterned portions of the conductive layer of the stacked structure 684) aligned with each other and electrically spaced apart by the dielectric material of the stacked structure 684. In an embodiment, the first electrode (or end) of the parallel capacitor 514 is electrically coupled to a conductive bonding pad 418 (and thus electrically coupled to bonding lines 512, 516), and the second electrode (or end) of the parallel capacitor 514 is electrically coupled to a conductive flange (e.g., using a conductive through-substrate via extending through the semiconductor substrate 682). In a more specific embodiment, the first electrode of the parallel capacitor 514 is “directly connected” to the bonding pad 418, where “directly connected” means that an electrical connection may be made using one or more conductive traces and / or conductive vias, but without intermediate circuit elements (i.e., circuit elements having a trace inductance greater than the trace inductance, where the “trace inductance” is an inductance less than about 100 pH). In this embodiment, because the parallel capacitor 514 and the bonding pad 418 are “directly connected” and the bonding pad 418 also has only trace inductance, the bonding lines 512, 516 and the parallel capacitor 514 can also be considered “directly connected.” In an alternative embodiment, the parallel capacitor 514 may be implemented using a discrete capacitor coupled to the top surface of the IPD assembly 480 or using another type of capacitor.

[0119] According to embodiments, the series combination of inductor elements 512, 516 may have an inductance value in the range of about 50 pH to about 3 nH, and the parallel capacitor 514 may have a capacitance value in the range of about 5 pF to about 120 pF, but these components may also have values ​​outside these ranges. In some embodiments, the parallel capacitor 514 may have a relatively large capacitance (e.g., more than about 60 pF) to provide an acceptable low RF impedance point.

[0120] As previously combined Figure 1 As discussed, the harmonic termination circuit 430 is also connected between the control terminal (e.g., the gate) of the FET within each transistor die 440 and a ground reference (e.g., connected to a conductive layer 686 on the bottom surface of the IPD assembly 480). Figure 5 and 6 In the embodiments, the harmonic termination circuit 430 includes a parallel inductor 532 (e.g., a parallel inductor element 132, Figure 1 ) and parallel capacitor 534 (e.g., parallel capacitor 134, Figure 1The series combination of the inductors 532 and 542 can be implemented as a set of bonding wires, wherein the first end of the bonding wire is connected to the input terminal 542 of the die 440 (and thus to the control terminal of the FET), and the second end of the bonding wire is connected to the conductive bonding pad 533 exposed at the top surface of the IPD assembly 480. To avoid... Figure 5 The mixed set of bonding lines, including inductor element 532, includes only one bonding line with a circle and numbered with reference numeral 532. It should be understood that inductor element 532 includes all bonding lines coupled between bonding pad 533 and input terminal 542. Within IPD assembly 480, bonding pad 533 is electrically connected to a first end of parallel capacitor 534, and a second end of parallel capacitor 534 is electrically connected (e.g., using a through-substrate via) to a ground reference (e.g., electrically connected to a conductive layer 686 on the bottom surface of IPD assembly 480).

[0121] According to an embodiment, the parallel capacitor 534 of the harmonic termination circuit 430 can be implemented as a capacitor integrally formed with the IPD substrate of the IPD assembly 480. For example, the parallel capacitor 534 can be implemented as an integrated MIM capacitor, which includes first and second conductive electrodes (formed by patterned portions of the conductive layer of the stacked structure 684) aligned with each other and electrically spaced apart by the dielectric material of the stacked structure 684. In an embodiment, the first electrode (or end) of the parallel capacitor 534 is electrically coupled to a conductive bonding pad 533, and the second electrode (or end) of the parallel capacitor 534 is electrically coupled to a conductive flange (e.g., using a through-substrate via). In a more specific embodiment, the first electrode of the parallel capacitor 534 is “directly connected” (as previously defined) to the bonding pad 533. In an embodiment, because the parallel capacitor 534 and the bonding pad 533 are “directly connected” and the bonding pad 533 also has only trace inductance, the bonding line 532 and the parallel capacitor 534 can also be considered as “directly connected”. In alternative embodiments, the parallel capacitor 534 can be implemented using a discrete capacitor coupled to the top surface of the IPD assembly 480 or using another type of capacitor. Based on the description herein, those skilled in the art will understand that, although in Figure 6 The diagram shows specific double-plate capacitor structures for capacitors 514 and 534, but various other capacitor structures can be used alternatively.

[0122] According to an embodiment, the harmonic termination circuit 430 acts as a low-impedance ground path for signal energy at harmonic frequencies (e.g., the second harmonic of the operating fundamental frequency of device 400). More specifically, the component values ​​of the parallel inductor 532 and the parallel capacitor 534 are selected such that the series combination of the parallel inductor 532 and the parallel capacitor 534 resonates at or near the second harmonic frequency. For example, the operating fundamental frequency of device 400 can be in the range of about 800 MHz to about 6.0 GHz, so the second harmonic frequency (and the resonant frequency of circuit 430) can be in the range of about 1.6 GHz to about 12.0 GHz. According to an embodiment, the inductor 532 can have an inductance value in the range of about 50 pF to about 20 nH, and the capacitor 534 can have a capacitance value in the range of about 0.1 pF to about 100 pF, but these components can also have values ​​outside these ranges. However, the designed inductance and / or capacitance values ​​may be affected by the mutual coupling between the bonding wires used to implement inductors 516 and 532.

[0123] More specifically, and according to an embodiment, the bonding wires corresponding to inductor elements 516 and 532 are physically configured and arranged relative to each other to exhibit predictable mutual coupling between adjacent bonding wire groups during operation. More specifically, the bonding wire profiles (e.g., the height and shape of each group of bonding wires) and their proximity to other bonding wires induce predictable mutual coupling during operation, which produces effective inductance values ​​for inductor elements 516 and 532 that differ from their self-inductance values ​​when each inductor is acquired independently (i.e., unaffected by mutual inductance from other inductors).

[0124] Now for reference Figure 7 and 8 , Figure 7 and 8 Includes device 400 ( Figure 4 An enlarged view of a portion of the image, including embodiments of output impedance matching circuits 450, 451, video bandwidth circuits 462, 463, harmonic termination circuits 470, 471, and parallel inductor networks 484, 485. More precisely, Figure 7 This is a top view of the upper right output-side portion 700 of a packaged RF power amplifier device 400 along amplifier path 421, which includes a portion of a power transistor die 441, a portion of an output lead 405, and an output-side IPD assembly 483. For enhanced understanding, Figure 8 Including according to the example embodiments Figure 7 A cross-sectional side view of portion 700 of the RF power amplifier device along line 8-8. More precisely, Figure 8This is a cross-sectional view passing through a portion of the conductive flange 406, the transistor die 441, the IPD assembly 483, and the output lead 405. (See also...) Figure 8 As clearly shown, power transistor dies 440, 441 and IPD assemblies 482, 483 are coupled to flange 406, and output leads 404, 405 are electrically isolated from conductive flange 406 (e.g., using isolation structure 408).

[0125] Each power transistor die 440, 441 includes a transistor output terminal 744 (e.g., a conductive bonding pad) that is electrically connected within each power transistor die 440, 441 to a first conductive terminal (e.g., a drain terminal) of a single-stage or final-stage FET 630 integrated within the die 440, 441. The conductive connection between the first conductive terminal (e.g., the drain terminal) of the FET 630 and the output terminal 744 of the die 440, 441 can be made by a stacked structure 634.

[0126] Similar to the input-side IPD assemblies 480 and 481, each output-side IPD assembly 482 and 483 may also include an IPD substrate 882 (e.g., a silicon substrate, a silicon carbide substrate, a GaN substrate, or another type of semiconductor substrate) and a stacked structure 884 having alternating dielectric and patterned conductive layers, wherein portions of the patterned conductive layers are electrically connected using conductive vias. As will be discussed in more detail below, various electrical components of the output impedance matching circuits 450 and 451, the video bandwidth circuits 462 and 463, the harmonic termination circuits 470 and 471, and the parallel inductor networks 484 and 485 are integrally formed within and / or connected to the IPD assemblies 482 and 483. These electrical components can be electrically connected to conductive bonding pads (e.g., bonding pads 458, 459, 473, 474) on the top surface of IPD assemblies 482, 483, and can be electrically connected to conductive flange 406 (e.g., grounded) via through-substrate vias leading to conductive layer 886 on the bottom surface of IPD assemblies 482, 483.

[0127] In some embodiments, each IPD assembly 482, 483 more specifically includes a parallel inductor network (e.g., circuit 180, Figure 1 Or circuits 484 and 485, Figure 4 The first parallel capacitor 756 (e.g., parallel capacitor 156,) Figure 1 ), harmonic termination circuit (e.g., circuit 170, Figure 1 Or circuits 470 and 471, Figure 4 The second parallel capacitor 774 (e.g., parallel capacitor 174) Figure 1 ), and video bandwidth circuitry (e.g., circuit 162, Figure 1One of circuits 200 to 205. Figures 2A to 2F , or components of circuits 462, 463). Figure 7 , 8 In some embodiments, components of the video bandwidth circuitry included in each IPD assembly 482, 483 more specifically include an envelope resistor 764 (e.g., resistor 264, Figures 2A to 2F ), envelope inductor 762 (e.g., inductor 262, Figures 2A to 2F ), envelope capacitor 766 (e.g., capacitor 266, Figures 2A to 2F ) and bypass capacitor 778 (e.g., bypass capacitor 278, Figure 2F Each of these components will be discussed in more detail later. In alternative embodiments, the video bandwidth circuitry 462, 463 may be implemented outside of the IPD assemblies 482, 483. For example, the envelope inductor 762 may be replaced by one or more bonding wires connected to additional package leads (which may provide another inductance), and the envelope resistor and / or envelope inductor may be implemented outside the packaged device.

[0128] The connection between transistor dies 440, 441 and output leads 404, 405 via output impedance matching circuits 450, 451 will be described in more detail. More specifically, through output terminal 744, the first conductive terminal (e.g., drain) of the FET within each transistor die 440, 441 is electrically coupled to output leads 404, 405 via instances of output impedance matching circuits 450, 451. For example, in an embodiment, each output impedance matching circuit 450, 451 may include three inductor elements 752, 754, 772 (e.g., inductor elements 152, 154, 172, ...). Figure 1 ) and two parallel capacitors 756 and 774 (e.g., parallel capacitors 156 and 174, Figure 1 First inductor element 752 (e.g., inductor element 152, Figure 1 This can be implemented as a first set of bonding wires coupled between the output terminal 744 of each die 440, 441 and the output leads 404, 405. The second inductor element 754 (e.g., inductor element 154, Figure 1 This can be implemented as a second set of bonding wires coupled between conductive bonding pads 458, 459 on the top surfaces of output leads 404, 405 and IPD assemblies 482, 483. A third inductor element 774 (e.g., inductor element 174) Figure 1 This can be implemented as a third set of bonding wires coupled between conductive bonding pads 473, 474 on the top surfaces of output leads 404, 405 and IPD assemblies 482, 483. To avoid... Figure 7The mixed-signal configuration includes only one or two of the bonding wires in this group of inductor elements 752, 754, and 774, which are circled and numbered with reference numerals 752, 754, and 774. It should be understood that inductor elements 752, 754, and 774 each include all bonding wires coupled between the same bonding pads and features. In embodiments, conductive bonding pads 458 and 459 may correspond to RF low-impedance point nodes (e.g., node 158, ...). Figure 1 And leads 404 and 405 can correspond to Figure 1 Node 160.

[0129] In an embodiment, the first end of the bonding wire 790 may also be connected to conductive bonding pads 458, 459, wherein the second end of the bonding wire 790 is connected to bias leads (e.g., bias leads 494, 495). Figure 4 When the external bias circuit provides a bias voltage to the bias lead, the bias voltage can be transmitted through the bonding wire 790, conductive landing pads 458, 459, bonding wire 754 and conductive landing pad 744 to the drain of the FET in the transistor die 440, 441.

[0130] According to an embodiment, the parallel capacitor 756 of each parallel inductor network 484, 485 can be implemented as a capacitor (or a set of parallel-coupled capacitors) integrally formed with the IPD substrate of the IPD assembly 482, 483. For example, the parallel capacitor 756 can be implemented as an integrated MIM capacitor, which includes first and second conductive electrodes (formed by patterned portions of the conductive layer of the stacked structure 884) aligned with each other and electrically spaced apart by the dielectric material of the stacked structure 884. In an embodiment, the first electrode (or end) of the parallel capacitor 756 is electrically coupled to a conductive bonding pad 459 (and thus electrically coupled to a bonding line 754), and the second electrode (or end) of the parallel capacitor 756 is electrically coupled to a conductive flange (e.g., using a conductive through-substrate via extending through the semiconductor substrate 882). In a more specific embodiment, the first electrode of the parallel capacitor 756 is "directly connected" (as previously defined) to the bonding pad 459. In this embodiment, because the parallel capacitor 756 and the bonding pad 459 are "directly connected" and the bonding pad 459 has only trace inductance, the bonding line 754 and the parallel capacitor 756 can also be considered "directly connected." In an alternative embodiment, the parallel capacitor 756 can be implemented using a discrete capacitor coupled to the top surface of the IPD assemblies 482, 483 or using another type of capacitor. As just explained, the parallel inductor 754 and the parallel capacitor 756 form a parallel inductance network 485, which is electrically coupled between the output lead 405 and the flange 406 (e.g., ground). According to the embodiment, the parallel inductor 754 may have an inductance value in the range of about 100 pH to about 40 nH, and the parallel capacitor 756 may have a capacitance value in the range of about 2 pF to about 300 pF, but these components may also have values ​​outside these ranges.

[0131] As mentioned above, in the embodiments, video bandwidth circuits 462, 463 are included in each IPD assembly 482, 483. In various embodiments, each video bandwidth circuit 462, 463 may have any of several configurations, such as, but not limited to, those described above. Figures 2A to 2F One of the configurations shown. In Figure 7 , 8 The corresponding shown Figure 2F In an embodiment of the video bandwidth circuit 205, each video bandwidth circuit 462, 463 includes electrical connections to nodes 458, 459 (e.g., nodes 158, 218). Figure 1 , 2F This can correspond to the envelope resistor 764 (e.g., resistor 264) between the RF low impedance point and the ground reference (e.g., flange 406). Figure 2F ), envelope inductor 762 (e.g., inductor 262, Figure 2F) and envelope capacitor 766 (e.g., capacitor 266, Figure 2F The series combination of the envelope inductor 762 and 463. Additionally, each video bandwidth circuit 462, 463 includes a bypass capacitor 778 (e.g., bypass capacitor 278) connected in parallel with the envelope inductor 762. Figure 2F ).exist Figure 7 , 8 In the embodiments, two instances of the parallel combination of the envelope inductor 762 and the bypass capacitor 778 are implemented on opposite sides of the IPD assemblies 482, 483. More specifically, in the illustrated embodiment, the parallel combination of the envelope inductor 762 and the capacitor 778 is connected in parallel between the envelope resistor 764 and the envelope capacitor 766. In alternative embodiments, the video bandwidth circuits 462, 463 may include only one instance of the combination of the envelope inductor 762 and the capacitor 778, or may include more than two instances of the combination of the envelope inductor 762 and the capacitor 778.

[0132] exist Figure 7 , 8 In some embodiments, the envelope resistor 764 is integrally formed as part of the IPD assemblies 482, 483. For example, each envelope resistor 764 may be a polysilicon resistor formed by a layer of polysilicon on or within the stacked structure 884, and electrically coupled between nodes 458, 459 and the parallel combination of the envelope inductor 762 and the bypass capacitor 778. In other alternative embodiments, the envelope resistor 764 may be formed of tungsten silicide or another material, may be a thick-film or thin-film resistor, or may be a discrete component coupled to the top surface of the IPD assemblies 482, 483.

[0133] The envelope inductor 762 can also be integrally formed as part of the IPD assemblies 482 and 483, such as Figure 7 , 8 As illustrated in the embodiments. For example, each envelope inductor 762 may be a patterned conductor formed from portions of one or more conductive layers of a stacked structure 884, wherein a first end of the conductor is electrically coupled to an envelope resistor 764, and a second end of the conductor is electrically coupled to a first end of an envelope capacitor 766. In alternative embodiments, each envelope inductor 762 may be implemented as a plurality of bonding wires, or as a spiral inductor (e.g., on or near the top surface of IPD assemblies 482, 483), or as a discrete inductor coupled to the top surface of IPD assemblies 482, 483.

[0134] In this embodiment, a bypass capacitor 778 is coupled in parallel with each envelope inductor 762. Each bypass capacitor 778 may be a discrete capacitor, for example, connected (e.g., using solder, conductive epoxy, or other means) to the top surface of the IPD assemblies 482, 483. More specifically, a first terminal of each bypass capacitor 778 may be electrically coupled to the first terminals of the envelope resistor 764 and the envelope inductor 762, and a second terminal of each bypass capacitor 778 may be connected to the second terminal of the envelope inductor 762 and the first terminal of the envelope capacitor 766.

[0135] For example, each bypass capacitor 778 may be a multilayer capacitor (e.g., a multilayer ceramic capacitor) having parallel, interleaved electrodes and enclosed terminals. Alternatively, each bypass capacitor 778 may be formed as part of a separate IPD (e.g., a MIM capacitor formed on a semiconductor substrate), or may be a capacitor integrally formed with the semiconductor substrate of the IPD assemblies 482, 483. Alternatively, each bypass capacitor 778 may be implemented as another type of capacitor capable of providing the required capacitance to the video bandwidth circuits 462, 463.

[0136] Envelope capacitor 766 is electrically coupled between a ground reference node (e.g., a conductive layer 886 at the bottom surface of each IPD assembly 482, 483) and a parallel combination of envelope inductor 762 and bypass capacitor 778. For example, capacitor 766 may be a MIM capacitor integrally formed with the IPD substrate of IPD assemblies 482, 483. In some embodiments, capacitor 766 may be formed entirely above semiconductor substrate 882 in a stacked structure 884, or capacitor 766 may have portions extending into or otherwise coupled to or contacting semiconductor substrate 882. According to embodiments, capacitor 766 may be formed of a first electrode, a second electrode, and a dielectric material between the first and second electrodes. The dielectric material of capacitor 766 may include one or more layers of polysilicon, various oxides, nitrides, or other suitable materials. In various embodiments, the first and second electrodes of capacitor 766 may comprise horizontal portions of a conductive layer (e.g., portions parallel to the top and bottom surfaces of IPD assemblies 482, 483) and / or vertical portions of a conductive layer (e.g., portions parallel to the sides of IPD assemblies 482, 483), said portions being interconnected. Furthermore, the first and second electrodes of capacitor 766 may be formed of a metal layer and / or a conductive semiconductor material (e.g., polysilicon). Alternatively, each envelope capacitor 766 may be, for example, a discrete capacitor connected (e.g., using solder, conductive epoxy, or other means) to the top surface of IPD assemblies 482, 483. Based on the description herein, those skilled in the art will understand that, although... Figure 8The diagram shows specific double-plate capacitor structures for capacitors 756, 774, and 766, but various other capacitor structures can be used alternatively.

[0137] As previously combined Figure 1 As discussed, harmonic termination circuits 470 and 471 are also connected between output leads 404 and 405 and the ground reference (e.g., connected to conductive layer 886 on the bottom surface of IPD assemblies 482 and 483). Figure 7 and 8 In the embodiments, the harmonic termination circuit 471 includes a parallel inductor 772 (e.g., a parallel inductor element 172, Figure 1 ) and parallel capacitor 774 (e.g., parallel capacitor 174, Figure 1 The series combination of the parallel inductors 772 and 774 is described. The parallel inductor 772 can be implemented as a set of bonding wires, wherein a first end of the bonding wire is connected to the output lead 405 (and thus to the first conductive terminal of the FET), and a second end of the bonding wire is connected to a conductive bonding pad 474 exposed at the top surface of the IPD assembly 483. Within the IPD assembly 483, the bonding pad 474 is electrically connected to a first terminal of the parallel capacitor 774, and a second terminal of the parallel capacitor 774 is electrically connected (e.g., using a through-substrate via) to a ground reference (e.g., electrically connected to a conductive layer 886 on the bottom surface of the IPD assembly 483).

[0138] According to an embodiment, the parallel capacitor 774 of the harmonic termination circuit 471 can be implemented as a capacitor integrally formed with the IPD substrate of the IPD assembly 483. For example, the parallel capacitor 774 can be implemented as an integrated MIM capacitor, which includes first and second conductive electrodes (formed by patterned portions of the conductive layer of the stacked structure 884) aligned with each other and electrically spaced apart by the dielectric material of the stacked structure 884. In an embodiment, the first electrode (or end) of the parallel capacitor 774 is electrically coupled to a conductive bonding pad 474, and the second electrode (or end) of the parallel capacitor 774 is electrically coupled to a conductive flange (e.g., using a through-substrate via). In a more specific embodiment, the first electrode of the parallel capacitor 774 is "directly connected" (as previously defined) to the bonding pad 474. In an embodiment, because the parallel capacitor 774 and the bonding pad 474 are "directly connected" and the bonding pad 474 also has only trace inductance, the bonding line 772 and the parallel capacitor 774 can also be considered as "directly connected". In an alternative embodiment, the parallel capacitor 774 can be implemented using a discrete capacitor coupled to the top surface of the IPD assembly 483 or using another type of capacitor.

[0139] According to an embodiment, each harmonic termination circuit 470, 471 acts as a low-impedance ground path for signal energy at the harmonic frequency (e.g., the second harmonic of the operating fundamental frequency of device 400). More specifically, the component values ​​of the parallel inductor 772 and the parallel capacitor 774 are selected such that the series combination of the parallel inductor 772 and the parallel capacitor 774 resonates at or near the second harmonic frequency. For example, the operating fundamental frequency of device 400 can be in the range of about 800 MHz to about 6.0 GHz, and therefore the second harmonic frequency (and the resonant frequency of circuits 470, 471) can be in the range of about 1.6 GHz to about 12.0 GHz. According to an embodiment, the inductor 772 can have an inductance value in the range of about 50 pF to about 20 nH, and the capacitor 774 can have a capacitance value in the range of about 0.1 pF to about 100 pF, but these components can also have values ​​outside these ranges. However, the designed inductance and / or capacitance values ​​may be affected by the mutual coupling between the bonding wires used to implement inductors 752, 754 and 772.

[0140] More specifically, and according to embodiments, the bonding wires corresponding to inductor elements 752, 754, and 772 are physically configured and arranged relative to each other to exhibit predictable mutual coupling between adjacent bonding wire groups during operation. More specifically, the bonding wire profiles (e.g., the height and shape of each group of bonding wires) and their proximity to other bonding wires induce predictable mutual coupling during operation, which produces effective inductance values ​​for inductor elements 752, 754, and 772 that differ from the self-inductance values ​​of inductor elements 752, 754, and 772 when each inductor is acquired independently (i.e., unaffected by mutual inductance from other inductors). For example, at a center operating frequency of 2.0 GHz, the mutual coupling between inductors 752 and 754 can be in the range of about -100 pH to about 150 pH (e.g., about 86 pH), the mutual coupling between inductors 752 and 772 can be in the range of about -50 pH to about 100 pH (e.g., about 30 pH), and the mutual coupling between inductors 754 and 772 can be in the range of about -100 pH to about 150 pH (e.g., about 69 pH).

[0141] As described above, transistors 440 and 441 each have an output harmonic-terminated to an embodiment of an inverse Class-F filter circuit (i.e., output impedance matching circuit 150), which includes a negative susceptance of f0 at a 2f0 cold spot in the circuit. This configuration of output impedance matching circuits 450 and 451 can significantly increase the impedance at the package plane (e.g., at leads 404 and 405), particularly under Zmod, compared to conventional output impedance matching circuits. Therefore, the amount of impedance transformation performed on the PCB can be significantly reduced. Consequently, amplifier efficiency can be increased, and the PCB can be made more compact. Furthermore, according to the embodiment, by including the negative susceptance at the 2f0 cold spot, the total phase shift of the inverse Class-F filter circuit can be significantly reduced, particularly under Zmod, making it possible to design a short-phase main path for the Dougherty amplifier.

[0142] Figures 4 to 8 Embodiments of an RF amplifier device are illustrated, comprising input and output leads (e.g., with intermediate electrical isolation) coupled to a substrate and a transistor die also coupled to the substrate between the input and output leads. Such RF amplifier devices are particularly suitable for high-power amplification. Based on the description herein, those skilled in the art will understand that various embodiments can also be implemented using different forms of packaging or construction. For example, one or more amplification paths including embodiments of the subject matter of this invention may be coupled to a substrate, such as a PCB, a leadless package (e.g., a quad flat no-lead (QFN) package), or another type of package. In such embodiments, the inputs and outputs of the amplification paths may be implemented using conductive land or other input / output (I / O) structures. Such implementations are particularly suitable for low-power amplification systems, such as relatively low-power Dougherty amplifiers, where the main amplification path and peaking amplification path (including exposed transistor dies, IPDs, bias circuitry, etc.), power dividers, delay and impedance inversion elements, combiners, and other components may be coupled to the substrate. It should be understood that embodiments of the subject matter of this invention are not limited to the embodiments shown.

[0143] Figure 9 This is according to various example embodiments for manufacturing packaged RF power amplifier devices (e.g., device 400, Figure 4 The flowchart illustrates a method comprising an input and output impedance matching circuit and an output-side parallel inductor network, an output-side video bandwidth circuit, and an input-side and output-side harmonic termination circuit. The method can begin by forming one or more IPD assemblies at blocks 902 to 904. More specifically, in block 902, one or more input and output IPDs (e.g., IPDs 480 to 483) can be formed. Figures 4 to 8According to an embodiment, each input IPD (e.g., IPD 480, 481) includes components of impedance matching circuitry and harmonic termination circuitry. For example, each input IPD may include one or more integrated parallel capacitors (e.g., capacitors 514, 534, ...). Figure 5 , 6 According to embodiments, each output IPD (e.g., IPD 482, 483) also includes components of a parallel inductor network, video bandwidth circuitry, and harmonic termination circuitry. For example, each output IPD may include one or more integrated parallel capacitors (e.g., capacitors 756, 766, 774). Figure 7 , 8 ), one or more envelope inductor elements (e.g., inductor element 762, Figure 7 , 8 ) and one or more envelope resistors (e.g., resistor 764, Figure 7 , 8 In addition to the passive components forming each IPD, forming each IPD also includes forming various conductive features (e.g., conductive layers and vias) that facilitate electrical connections between the various components of each circuit. For example, forming an IPD may also include forming various accessible connection nodes (e.g., nodes 418, 419, 458, 459, 473, 474, 533) on the surface of the substrate of each IPD. Figures 4 to 8 As previously discussed, connection nodes may include conductive bonding pads that can accept inductive elements (e.g., bonding wires 512, 516, 532, 752, 754, 772, etc.). Figures 5 to 8 The attachment of the circuit elements is also possible. Additionally, in block 904, discrete components corresponding to various circuit elements (e.g., bypass capacitor 778) can be attached. Figure 7 , 8 Coupled to conductors exposed at the surface of each IPD to form one or more IPD assemblies.

[0144] In block 906, for the air chamber embodiment, an isolation structure (e.g., isolation structure 408) is provided. Figure 4 The active device (e.g., flange 406) is coupled to a device substrate. Additionally, one or more active devices (e.g., transistors 440, 441) and IPD assemblies (e.g., IPD assemblies 480-483) are coupled to portions of the top surface of the substrate exposed through openings in the isolation structure. Leads (e.g., input and output leads 402-405 and bias leads 492-495 (if included)) are coupled to the top surface of the isolation structure. For overmolded (e.g., encapsulated) device embodiments, the isolation structure may not be included, and the substrate and leads may form a portion of a lead frame.

[0145] In block 908, the input leads, transistors, IPD assemblies, and output leads are electrically coupled together. For example, bonding wires can be used to make electrical connections between the various device components and elements, as previously discussed. For example, some bonding wires correspond to inductor components of the input or output matching circuit (e.g., bonding wires 512, 516, 752, 754, etc.). Figures 4 to 8 Inductor components of harmonic terminating circuits (e.g., junction lines 532, 772, Figures 4 to 8 Finally, in box 910, the device is capped (e.g., for an air chamber enclosure) or encapsulated (e.g., using a molding compound for overmolding). The device can then be incorporated into a larger electrical system (e.g., a Dougherty amplifier or other type of electrical system).

[0146] The preceding detailed description is illustrative in nature only and is not intended to limit the embodiments of the subject matter or the application and use of such embodiments. As used herein, the word "exemplary" means "serving as an example, instance, or illustration." Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments. Furthermore, one is not to be limited by any expressed or implied theories presented in the prior art, background art, or detailed description.

[0147] The connecting lines shown in the figures contained herein are intended to represent exemplary functional relationships and / or physical couplings between various elements. It should be noted that many alternative or additional functional relationships or physical connections may exist in embodiments of this subject matter. Furthermore, certain terms may be used herein for reference only, and therefore are not intended to be limiting, and unless the context clearly indicates otherwise, the terms “first,” “second,” and other such numerical terms referring to structures do not imply order or sequence.

[0148] As used herein, a “node” means any internal or external reference point, connection point, junction, signal line, conductive element, etc., where a given signal, logic level, voltage, data pattern, current, or quantity is present. Furthermore, two or more nodes can be implemented with a single physical element (and although received or output at a common node, two or more signals can still be multiplexed, modulated, or otherwise distinguished).

[0149] The above description refers to elements, nodes, or features being "connected" or "coupled" together. As used herein, unless otherwise explicitly stated, "connected" means that one element is directly engaged to (or directly communicates with) another element, and not necessarily mechanically. Similarly, unless otherwise explicitly stated, "coupled" means that one element is directly or indirectly engaged to (or directly or indirectly communicates with) another element electrically or otherwise, and not necessarily mechanically. Therefore, although the schematic diagrams shown depict an exemplary arrangement of elements, additional intermediate elements, devices, features, or components may be present in embodiments of the depicted subject matter.

[0150] While at least one exemplary embodiment has been presented in the detailed description above, it should be understood that numerous variations exist. It should also be understood that the exemplary embodiments described herein are not intended to limit the scope, applicability, or configuration of the claimed subject matter in any way. In fact, the foregoing detailed description will provide a convenient guide for those skilled in the art to implement one or more of the described embodiments. It should be understood that various changes can be made to the function and arrangement of the elements without departing from the scope defined by the claims, which includes known and foreseeable equivalents at the time of filing of this patent application.

Claims

1. An amplifier, characterized in that, include: Amplifier input; Amplifier output; A transistor has a transistor input terminal and a transistor output terminal; An input circuit coupled between the amplifier input and the transistor input, wherein the input circuit includes an input-side harmonic termination circuit having a first inductor and a first capacitor connected in series between the transistor input and a ground reference node, wherein the input-side harmonic termination circuit resonates at a harmonic frequency of the amplifier's operating fundamental frequency, and wherein the first capacitor is implemented in a first integrated passive device. An input impedance matching circuit includes a second inductor coupled between the amplifier input and a first node, a third inductor coupled between the first node and the transistor input, and a second capacitor coupled between the first node and the ground reference node; and An output circuit coupled to the output terminal of the transistor, wherein the output circuit includes A fourth inductor element is coupled between the transistor output and the amplifier output. An output-side harmonic termination circuit includes a fifth inductor and a third capacitor connected in series between the amplifier output and the ground reference node, wherein the output-side harmonic termination circuit resonates at the harmonic frequency, and wherein the third capacitor is implemented in a second integrated passive device; and A parallel inductor network comprising a sixth inductor and a fourth capacitor connected in series between the amplifier output and the ground reference node, wherein the fourth capacitor is implemented in the second integrated passive device.

2. The amplifier according to claim 1, characterized in that, The first inductor element includes a first set of bonding wires, the fourth inductor element includes a second set of bonding wires, the fifth inductor element includes a third set of bonding wires, and the sixth inductor element includes a fourth set of bonding wires.

3. The amplifier according to claim 1, characterized in that, The fourth inductor element, the output-side harmonic termination circuit, and the intrinsic output capacitance of the transistor form a parallel inductor / capacitor (LC) circuit, which resonates at or near the second harmonic frequency to effectively generate high impedance to signal energy at the second harmonic frequency.

4. The amplifier according to claim 1, characterized in that, The parallel inductor network resonates at a frequency lower than the operating fundamental frequency of the amplifier.

5. The amplifier according to claim 1, characterized in that, Also includes: A video bandwidth circuit coupled to a connection node between the fourth inductor and the third capacitor, wherein the video bandwidth circuit includes multiple components, wherein the multiple components include an envelope resistor, an envelope inductor, and an envelope capacitor coupled in series between the connection node and the ground reference node.

6. The amplifier according to claim 1, characterized in that, The transistor, the input circuit, and the output circuit form a portion of the first amplification path, and the amplifier further includes: Second amplification path; A power divider having an input configured to receive a radio frequency (RF) signal, a first output coupled to an input of a first amplification path, and a second output coupled to an input of a second amplification path, wherein the power divider is configured to divide the RF signal into a first RF signal provided to the first amplification path via the first output and a second RF signal provided to the second amplification path via the second output; and A combining node configured to receive and combine amplified RF signals generated by the first and second amplification paths.

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