A power amplifier bias timing control circuit

Abstract

The application provides a power amplifier bias voltage timing control circuit and belongs to the technical field of radio frequency power amplifiers.The circuit comprises a power amplifier, a gate voltage power supply module, a drain voltage power supply module, an inverter, a first reference voltage module, a second reference voltage module, a first comparator, a second comparator, a processor, a three-input logic AND gate, an NPN transistor, a PNP transistor, an energy storage capacitor and a radio frequency choke.The output voltage of the gate voltage power supply module is converted into a negative voltage by the inverter and is supplied to the gate of the power amplifier.When the TDD timing sequence voltage output by the first comparator, the second comparator and the processor is at a high level, the three-input logic AND gate outputs a high level, at this time, the drain voltage power supply module supplies power to the drain of the power amplifier through Q2, and when the three-input logic AND gate circuit outputs a low level, the power amplifier is turned off, and C1 and L1 are rapidly discharged through the transistor Q4.Under the premise of meeting the power amplifier bias voltage power-on and power-off timing sequence protection, the application realizes the rapid switching of the GaN power amplifier in the on and off states and the rapid switching of the charging and discharging of the power amplifier energy storage capacitor in the mobile communication TDD timing sequence.

Description

Technical Field

[0001] This invention relates to the field of radio frequency power amplifier technology, and in particular to a power amplifier bias timing control circuit. Background Technology

[0002] GaN power amplifiers are particularly suitable for high-frequency, high-power radio frequency power amplifiers due to their superior broadband semiconductor characteristics, high saturated electron mobility, and high breakdown field strength. GaN power amplifiers require two power supplies: gate voltage and drain voltage. The power-on timing requires the gate voltage to precede the drain voltage, and the power-down timing requires the drain voltage to precede the gate voltage.

[0003] In existing technologies, the gate voltage is generally adjusted through a bias circuit to achieve the optimal operating state of the power amplifier. For example, patent document CN209627325U describes the use of a digital-to-analog converter chip for gate voltage adjustment, while patent documents CN107528553A and CN205725694U use a resistor voltage divider method. Regardless of the adjustment method, abnormal situations can occur during operation, such as the gate voltage unexpectedly exceeding the rated range of the power amplifier's gate voltage. If the gate voltage accidentally exceeds the rated range of the power amplifier's gate voltage during adjustment while the drain is powered on, or if the gate voltage unexpectedly drops due to some uncontrollable factors, the power amplifier circuit will be damaged.

[0004] Furthermore, to save power, GaN power amplifiers typically operate in a pulsed state according to the TDD (Transmit / Receive) timing of mobile communications, and their current requirements are also pulsed. To meet the pulsed current requirements during transmission and improve transient response, an energy storage capacitor is usually added at the power amplifier's drain. The large amount of charge stored in the energy storage capacitor must be released after the power amplifier is powered off; otherwise, it may damage the power amplifier and other modules. While ensuring the bias power-on and power-off timing is met, the energy stored in the RF choke also needs to be released promptly after the power amplifier is powered off.

[0005] The existing bias voltage protection circuits for GaN power amplifiers include the following:

[0006] Patent document CN113965173A discloses a power supply timing control system and method for a GaN power amplifier, including a voltage module, a buck regulator, logic gates, a voltage monitor, a multi-channel grid voltage generator, a voltage divider module, and a GaN power amplifier, solving the problem of power amplifier bias power-on and power-off timing protection. When the grid voltage is lower than a set reference value, the power amplifier drain is powered on. However, this patent cannot determine whether the set grid voltage value exceeds the lower limit of the power amplifier's rated grid voltage, and therefore cannot achieve rapid charging and discharging switching of the energy storage module under TDD timing control under the premise of power amplifier bias power-on and power-off timing protection.

[0007] Patent document CN113992164A discloses a GaN power amplifier negative gate voltage bias protection circuit and its operating method, enabling rapid switching between the power amplifier tube's on and off states under 5G mobile communication TDD timing stage control. However, this patent cannot determine whether the set gate voltage value meets the upper and lower reference voltage ranges of the power amplifier's gate voltage, and therefore cannot achieve rapid switching of the energy storage module's charging and discharging under TDD timing control while maintaining power amplifier bias voltage power-on / off timing protection.

[0008] Chinese patent document CN110048677A discloses a power amplifier power supply control method and device. While meeting the power amplifier power-on and power-off timing requirements, it saves on soft-start circuitry, MOS on the Vd line, and large-capacity energy storage capacitors at the Vg output, thus improving circuit reliability and saving board area and cost. However, this patent cannot determine whether the set gate voltage value meets the upper and lower reference voltage ranges of the power amplifier gate voltage, and therefore cannot achieve rapid charging and discharging switching of the energy storage module under TDD timing control while protecting the power amplifier bias power-on and power-off timing.

[0009] Chinese patent document CN215580896U discloses an automatic discharge circuit for power amplifier energy storage capacitors, which quickly releases energy from the energy storage module in the event of a power outage, preventing damage to other components in the circuit. However, this patent cannot determine whether the set gate voltage value meets the upper and lower reference voltage ranges of the power amplifier's gate voltage, and therefore cannot achieve rapid switching between charging and discharging of the energy storage module under TDD timing control, provided that the power amplifier bias voltage power-up and power-down timing protection is in place.

[0010] Chinese patent document CN110098809A discloses a timing protection power supply device for a gallium nitride power amplifier, which performs dynamic temperature compensation on the gate voltage while meeting the power-on and power-off timing protection requirements of the power amplifier. This patent compares the gate voltage with preset upper and lower reference voltage values ​​to confirm that the gate voltage is within the required range for the power amplifier. However, this patent cannot achieve rapid switching between the power amplifier's on and off states under TDD timing stage control, nor can it enable rapid switching of the energy storage module's charging and discharging under TDD timing control. Summary of the Invention

[0011] In view of this, the present invention provides a power amplifier bias timing control circuit, which can realize the rapid switching between the on and off states of the GaN power amplifier under the TDD timing stage control of mobile communication, and the rapid switching of the charging and discharging of the power amplifier energy storage capacitor under the TDD timing stage control of mobile communication, while meeting the power amplifier bias power-on and power-off timing protection requirements.

[0012] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0013] A power amplifier bias timing control circuit includes a GaN power amplifier; it also includes a gate voltage power supply module, a drain voltage power supply module, a three-input AND gate, an inverter, a first reference voltage module, a second reference voltage module, a first comparator, a second comparator, an energy storage module, and a processor;

[0014] The output of the gate voltage power supply module is connected to the non-inverting input of the first comparator, the inverting input of the second comparator, and the input of the inverter; the first reference voltage module is connected to the inverting input of the first comparator, and the second reference voltage module is connected to the non-inverting input of the second comparator; the output of the inverter is connected to the gate of the GaN power amplifier.

[0015] When the output voltage of the gate voltage power supply module is less than the voltage of the first reference voltage module or greater than the voltage of the second reference voltage module, the first comparator or the second comparator outputs a low level; when the output voltage of the gate voltage power supply module is greater than the voltage of the first reference voltage module and less than the voltage of the second reference voltage module, both the first comparator and the second comparator output a high level.

[0016] The outputs of the first comparator, the second comparator, and the TDD timing level output port of the processor are sequentially connected to the three inputs of the three-input AND gate. When the TDD timing level output by the processor is high and both the first and second comparators output high, the three-input AND gate outputs a high level; otherwise, the three-input AND gate outputs a low level.

[0017] The output of the three-input AND gate is connected to a first path for controlling the power-on and power-off of the drain of the GaN power amplifier and a second path for controlling the charging and discharging of the energy storage module; the first path includes a first transistor and a second transistor, and the second path includes a third transistor and a fourth transistor.

[0018] When the three-input AND gate outputs a high level, the first and second transistors are turned on. At this time, the drain voltage supply module supplies power to the drain of the GaN power amplifier through the second transistor and charges the energy storage module. When the three-input AND gate outputs a high level, the third transistor is turned on and the fourth transistor is turned off. At this time, the energy storage module cannot discharge.

[0019] When the three-input AND gate outputs a low level, the first and second transistors are turned off, and the drain of the GaN power amplifier is de-energized. When the three-input AND gate outputs a low level, the third transistor is turned off and the fourth transistor is turned on, and the energy storage module discharges.

[0020] Furthermore, the first transistor, the third transistor, and the fourth transistor are NPN type transistors, and the second transistor is a PNP type transistor.

[0021] Furthermore, the energy storage module is located at the drain of the GaN power amplifier and includes an energy storage capacitor and an RF choke.

[0022] Furthermore, the base of the first transistor is connected to the output of the three-input AND gate, the emitter of the first transistor is grounded through a resistor, and the collector of the first transistor is connected to the base of the second transistor.

[0023] The base of the third transistor is connected to the output of the three-input AND gate, the emitter of the third transistor is grounded, the collector of the third transistor is pulled up to 5V external power supply through a resistor, the collector of the third transistor is also connected to the base of the fourth transistor, the emitter of the fourth transistor is grounded through a resistor, and the collector of the fourth transistor is connected to the drain of the GaN power amplifier.

[0024] The beneficial effects of this invention are as follows:

[0025] 1. This invention enables rapid switching between the on and off states of a GaN power amplifier under TDD timing control in mobile communication, as well as rapid switching between charging and discharging of the energy storage module of the power amplifier under TDD timing control in mobile communication.

[0026] 2. This invention employs two comparators and a three-input AND gate circuit to prevent the power amplifier from being damaged by accidentally exceeding the rated value range of the power amplifier's grid voltage during the grid voltage adjustment process (such as when the adjustment range of the sliding rheostat is too large or the digital-to-analog converter is malfunctioning). Attached Figure Description

[0027] Figure 1 This is a schematic diagram of the structure of a power amplifier bias timing control circuit in an embodiment of the present invention. Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer and easier to understand, the invention will be further described in detail below with reference to the accompanying drawings and embodiments.

[0029] like Figure 1 As shown, a power amplifier bias timing control circuit includes a GaN power amplifier, a gate voltage power supply module, a drain voltage power supply module, an inverter, a first reference voltage module, a second reference voltage module, a first comparator, a second comparator, a processor, a three-input logic AND gate circuit, as well as NPN transistors Q1, Q3, and Q4, a PNP transistor Q2, an energy storage capacitor C1, and an RF choke L1.

[0030] The output voltage of the gate voltage power supply module is converted to a negative voltage by an inverter and then supplied to the power amplifier gate. The output of the gate voltage power supply module is simultaneously connected to the non-inverting input of the first comparator and the inverting input of the second comparator. The first reference voltage module is connected to the inverting input of the first comparator, and the second reference voltage module is connected to the non-inverting input of the second comparator. The first reference voltage module is set with reference to the lower limit of the rated gate voltage of the power amplifier (e.g., if the lower limit of the gate voltage is -2.2V, then the first reference voltage is set to 2.2V), and the second reference voltage module is set with reference to the upper limit of the rated gate voltage of the power amplifier (e.g., if the upper limit of the gate voltage is -4V, then the second reference voltage is set to 4V). When the output voltage of the gate voltage power supply module is less than the voltage of the first reference voltage module or greater than the voltage of the second reference voltage module, the first comparator or the second comparator outputs a low level; when the output voltage of the gate voltage power supply module is greater than the voltage of the first reference voltage module and less than the voltage of the second reference voltage module, both the first comparator and the second comparator output a high level.

[0031] The outputs of the first comparator, the second comparator, and the processor's TDD timing level output port are sequentially connected to the three inputs of a three-input AND gate. When the processor's TDD timing level is high and both the first and second comparators output high levels, the AND gate outputs a high level; otherwise, the AND gate outputs a low level.

[0032] A three-input AND gate controls the power amplifier's drain power-on / power-off and the power amplifier's energy storage module charging / discharging switching circuit. Its operating logic is as follows:

[0033] 1) When the three-input AND gate outputs a high level, the base of transistor Q1 is high, and Q1 is turned on. After Q1 is turned on, the base of transistor Q2 is pulled low by resistor R1, and Q2 is turned on. The drain voltage supply module supplies power to the drain of the power amplifier through Q2, and simultaneously charges the energy storage capacitor C1 and the RF choke L1; at this time, transistor Q3 is turned on, the base of transistor Q4 is pulled low, Q4 is turned off, and the energy storage capacitor C1 and the RF choke L1 cannot discharge.

[0034] 2) When the output of the three-input AND gate is low, the base of transistor Q1 is pulled low, Q1 is turned off, which causes Q2 to also be turned off, and the power amplifier drain is de-energized; at this time, transistor Q3 is turned off, and the 5V voltage pulls the base of Q4 high through resistor R2, Q4 is turned on, and the energy storage capacitor C1 and the RF choke L1 discharge rapidly through resistor R3.

[0035] In this circuit, the output voltage of the gate voltage power supply module is converted to a negative voltage by an inverter to supply the power amplifier gate. When the TDD timing levels output by the first comparator, the second comparator, and the processor are all high, the three-input AND gate outputs a high level. At this time, the drain voltage power supply module supplies power to the power amplifier drain through Q2. When the three-input AND gate outputs a low level, the power amplifier is turned off, and C1 and L1 discharge rapidly through transistor Q4. This circuit, while satisfying the power amplifier bias power-on / off timing protection, achieves rapid switching between the on and off states of the GaN power amplifier under TDD timing control in mobile communication, and rapid switching between charging and discharging of the power amplifier's energy storage capacitor under TDD timing control in mobile communication.

[0036] The specific control process of this circuit is as follows:

[0037] Step 1: The grid voltage power supply module outputs a positive voltage, which is then converted to a negative voltage by an inverter to power the power amplifier grid;

[0038] Step 2: The first reference voltage module is set with reference to the lower limit of the rated grid voltage of the power amplifier (e.g., if the lower limit of the grid voltage is -2.2V, then the first reference voltage is set to 2.2V). The second reference voltage module is set with reference to the upper limit of the rated grid voltage of the power amplifier (e.g., if the upper limit of the grid voltage is -4V, then the second reference voltage module is set to 4V). When the output voltage value of the grid voltage power supply module is greater than the first reference voltage value and less than the second reference voltage value, both the first comparator and the second comparator output a high level.

[0039] Step 3: Combine the three-input logic AND gate with the first comparator, the second comparator, and the TDD timing level output by the processor to output the corresponding level;

[0040] Step 4: Transistors Q1 and Q2 control the opening and closing of the drain voltage according to the state of the output voltage of the three-input AND gate;

[0041] Step 5: Transistors Q3 and Q4 control the opening and closing of the energy storage module's discharge circuit based on the state of the output voltage of the three-input AND gate.

[0042] When using GaN power amplifiers, the first thing to consider is the power-on and power-off timing of the gate and drain. The second thing to consider is how to ensure that the gate voltage is within the rated range of the power amplifier before powering on the drain. The third thing to consider is how to quickly release the energy in the energy storage module when the power is off.

[0043] When the power amplifier is powered on: The output voltage of the gate voltage supply module is inverted and supplied to the power amplifier gate. It is determined whether the output voltage of the gate voltage supply module is within the voltage range defined by the first and second reference voltage modules. If the gate voltage meets the rated value of the power amplifier gate voltage, both the first and second comparators output a high level. At this time, if the TDD timing level is high, indicating that the transmit channel is open, the three-input AND gate outputs a high level, transistors Q1 and Q2 are turned on, and the drain voltage supply module supplies power to the power amplifier drain through transistor Q2.

[0044] When the power amplifier is powered on: When the TDD timing level is low, it indicates that the receive channel is open and the transmit channel must be closed. At this time, the three-input AND gate outputs a low level, turning off transistor Q1. This prevents an effective voltage drop between the emitter and base of transistor Q2, causing Q2 to turn off. Ultimately, the output voltage of the drain voltage supply module cannot be supplied to the drain of the power amplifier, the power amplifier is in a shutdown state, and the transmit channel is closed.

[0045] When the energy storage module is charging: When the TDD timing level is high and the three-input AND gate output is high, transistors Q1 and Q2 are turned on, and the drain voltage power supply module charges the energy storage capacitor C1 and the RF choke L1 through transistor Q2. At this time, transistor Q3 is turned on and Q4 is turned off, so the energy storage capacitor C1 and the RF choke L1 cannot discharge through resistor R3.

[0046] When the energy storage module discharges: When the TDD timing level is low, the three-input AND gate outputs a low level, the base of transistor Q3 is pulled low, and Q3 is turned off. The 5V voltage pulls the base of Q4 high through resistor R2, Q4 turns on, and the power amplifier energy storage capacitor C1 and the RF choke L1 discharge rapidly through resistor R3.

[0047] During use, you may encounter the following abnormalities:

[0048] 1. The grid voltage power supply module fails to power, causing the first comparator and the second comparator to output a low level. The three-input AND gate outputs a low level, Q1 and Q2 are turned off, the drain voltage of the GaN power amplifier is turned off, and the power amplifier is protected.

[0049] 2. If the gate voltage adjustment unexpectedly exceeds the rated range of the power amplifier, for example, if the rated range of the power amplifier gate voltage is -4V to -2.2V, and the gate voltage power supply module outputs 2.1V, that is, the voltage supplied to the gate is -2.1V, the first comparator outputs a low level, the three-input logic AND gate outputs a low level, Q1 and Q2 are turned off, the drain voltage of the GaN power amplifier is turned off, and the power amplifier is protected.

[0050] In summary, the power amplifier bias timing control circuit provided by this invention ensures that the gate is powered on first and the drain is powered off first, meeting the timing requirements for GaN power amplifiers. Furthermore, this invention enables rapid switching between the on and off states of the GaN power amplifier under TDD timing control in mobile communication, as well as rapid switching between charging and discharging of the power amplifier's energy storage module under TDD timing control in mobile communication.

[0051] Having shown and described the embodiments of the present invention above, it is understood that these embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make designations, modifications, substitutions, and variations to the above embodiments within the scope of the present invention without departing from its principles and spirit. In summary, the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A power amplifier bias timing control circuit, comprising a GaN power amplifier; characterized in that, It also includes a gate voltage power supply module, a drain voltage power supply module, a three-input AND gate, an inverter, a first reference voltage module, a second reference voltage module, a first comparator, a second comparator, an energy storage module, and a processor; The output of the gate voltage power supply module is connected to the non-inverting input of the first comparator, the inverting input of the second comparator, and the input of the inverter; the first reference voltage module is connected to the inverting input of the first comparator, and the second reference voltage module is connected to the non-inverting input of the second comparator; the output of the inverter is connected to the gate of the GaN power amplifier. When the output voltage of the gate voltage power supply module is less than the voltage of the first reference voltage module or greater than the voltage of the second reference voltage module, the first comparator or the second comparator outputs a low level; when the output voltage of the gate voltage power supply module is greater than the voltage of the first reference voltage module and less than the voltage of the second reference voltage module, both the first comparator and the second comparator output a high level. The outputs of the first comparator, the second comparator, and the TDD timing level output port of the processor are sequentially connected to the three inputs of the three-input AND gate. When the TDD timing level output by the processor is high and both the first and second comparators output high, the three-input AND gate outputs a high level; otherwise, the three-input AND gate outputs a low level. The output of the three-input AND gate is connected to a first path for controlling the power-on and power-off of the drain of the GaN power amplifier and a second path for controlling the charging and discharging of the energy storage module; the first path includes a first transistor and a second transistor, and the second path includes a third transistor and a fourth transistor. When the three-input AND gate outputs a high level, the first and second transistors are turned on. At this time, the drain voltage supply module supplies power to the drain of the GaN power amplifier through the second transistor and charges the energy storage module. When the three-input AND gate outputs a high level, the third transistor is turned on and the fourth transistor is turned off. At this time, the energy storage module cannot discharge. When the three-input AND gate outputs a low level, the first and second transistors are turned off, and the drain of the GaN power amplifier is de-energized. When the three-input AND gate outputs a low level, the third transistor is turned off and the fourth transistor is turned on, and the energy storage module discharges. The first transistor, the third transistor, and the fourth transistor are NPN type transistors, and the second transistor is a PNP type transistor; The base of the first transistor is connected to the output of a three-input AND gate, the emitter of the first transistor is grounded through a resistor, and the collector of the first transistor is connected to the base of the second transistor. The base of the third transistor is connected to the output of the three-input AND gate, the emitter of the third transistor is grounded, the collector of the third transistor is pulled up to 5V external power supply through a resistor, the collector of the third transistor is also connected to the base of the fourth transistor, the emitter of the fourth transistor is grounded through a resistor, and the collector of the fourth transistor is connected to the drain of the GaN power amplifier.

2. The power amplifier bias timing control circuit according to claim 1, characterized in that, The energy storage module is located at the drain of the GaN power amplifier and includes an energy storage capacitor and an RF choke.

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