High‑linearity, high‑power gaas HBT power amplifier having power detection function

Abstract

Disclosed in the present invention is a high‑linearity, high‑power GaAs HBT power amplifier having a power detection function, characterized in that: the GaAs HBT power amplifier comprises a radio frequency path, a bias module and a power detection circuit. The radio frequency path is used to perform power amplification on a radio frequency signal, a negative feedback network is used to improve the stability and expand the bandwidth, and second harmonic suppression improves the overall linearity. The bias circuit is used to provide, to a three-stage amplification circuit, a bias voltage that dynamically changes along with an input power, so as to solve the problems of linearity degradation and current instability caused by a self-heating effect in a GaAs HBT transistor under high-power input, thereby mitigating amplitude-amplitude distortion and amplitude-phase distortion of the power amplifier. The power detection circuit is used to output a direct current voltage that is positively correlated with an output power, so as to achieve accurate control of the output power of the power amplifier. By fully integrating negative feedback, dynamic biasing and harmonic suppression techniques, the present invention effectively improves the overall linearity of the amplifier.

Description

A GaAs HBT power amplifier with high linearity and high power sensing Technical Field

[0001] This invention belongs to the field of analog and radio frequency circuit technology, and specifically relates to a GaAs HBT power amplifier with high linearity and high power detection. Background Technology

[0002] With the continuous growth of wireless communication demands, wireless local area networks (WLANs) are being increasingly widely used in various high-speed wireless communication scenarios, including computers, mobile handheld devices, and the Internet of Things (IoT). Power amplifiers, or simply power amplifiers, are key components in wireless communication transceiver systems, amplifying radio frequency (RF) signals. The performance parameters of a power amplifier, such as gain, linearity, gain-added efficiency, and output power, have a significant impact on system performance. GaAs HBT technology, with its advantages of high cutoff frequency, high linearity, high efficiency, and high power density, is widely used in the fabrication of power amplifiers.

[0003] When the amplitude of the input signal is large, the nonlinearity of the power amplifier will have a significant impact on the amplification effect. In addition, with the continuous improvement of modulation technology, such as quadrature amplitude modulation (QAM) and orthogonal frequency division multiple access (OFDMA), the requirements for the linearity of the power amplifier are constantly increasing.

[0004] Linearization techniques for power amplifiers generally include: digital predistortion, negative feedback, power back-off, dynamic bias, and harmonic suppression. While digital predistortion can optimize the linearity of a power amplifier at high power output by compensating for peak signal distortion in the nonlinear region, it increases system complexity and cost. Negative feedback offers good stability but provides limited improvement in linearity. Power back-off has poor power-added efficiency (PAE). Dynamic bias and harmonic suppression improve power amplifier linearity while exhibiting good performance in PAE, bandwidth, stability, and other metrics. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention proposes a high-linearity, high-power GaAs HBT power amplifier design with power detection. It fully integrates negative feedback, dynamic bias, and harmonic suppression techniques to improve the overall linearity of the amplifier, and integrates a power detection circuit at the output port to achieve precise control of the amplifier's output power.

[0006] This invention discloses a GaAs HBT power amplifier with high linearity and high power detection, wherein the GaAs HBT power amplifier includes an RF path, a bias module and a power detection circuit;

[0007] The radio frequency (RF) path includes an input matching circuit, a first amplification unit, a first inter-stage matching circuit, a second amplification unit, a second inter-stage matching circuit, a third amplification unit, an output matching circuit, a first negative feedback network, a second negative feedback network, and an electrostatic discharge (ESD) protection circuit, all connected in sequence. The input matching circuit, first amplification unit, first inter-stage matching circuit, second amplification unit, second inter-stage matching circuit, third amplification unit, and output matching circuit are connected in sequence. The first negative feedback network is connected in parallel to the first amplification unit, and the second negative feedback network is connected in parallel to the second amplification unit. The RF path is used to amplify the power of the input RF signal. The ESD protection circuit is connected to the first inter-stage matching circuit, the second inter-stage matching circuit, and the output matching circuit to construct an ESD discharge path.

[0008] The bias module includes a first dynamic linearization bias circuit, a second dynamic linearization bias circuit, and a third dynamic linearization bias circuit. The two input terminals of the first, second, and third dynamic linearization bias circuits are respectively connected to DC voltage Vref and DC voltage Vbatt. The output terminals of the first, second, and third dynamic linearization bias circuits are respectively connected to the input terminals of the first, second, and third amplification units, providing the first, second, and third amplification units with bias voltages that dynamically change with the input power.

[0009] The power detection circuit is connected to the output terminal of the third amplification unit and is used to output a DC voltage that is positively correlated with the output power.

[0010] As a preferred embodiment, the first amplification unit, the second amplification unit, and the third amplification unit have the same structure, and each amplification unit includes n parallel transistors [Q1, Q2, ... Q1]. n The transistor is a GaAs HBT transistor; the size of each transistor and the number n of GaAs HBT transistors connected in parallel are selected according to the power requirements of each amplifier stage.

[0011] As a preferred embodiment, the first negative feedback network and the second negative feedback network have the same structure; each negative feedback network includes a first resistor R connected in sequence. F Feedback inductor L F and the first capacitor C F First resistor R F Keep away from feedback inductor L F One end of the capacitor is connected to the input terminal of the corresponding amplification unit, and the first capacitor C F Keep away from feedback inductor L F One end is connected to the output of the corresponding amplification unit.

[0012] As a preferred embodiment, the input matching circuit includes a first inductor L1, a second inductor L2, a second capacitor C2, and a third capacitor C3; wherein, the two ends of the second capacitor C2 are connected to the input terminal and the output terminal of the input matching circuit, respectively; the first end of the first inductor L1 is connected to the input terminal of the input matching circuit, and the second end is grounded; the first end of the third capacitor C3 is connected to the output terminal of the input matching circuit, and the second end is grounded through the second inductor L2.

[0013] In one preferred embodiment, the first interstage matching circuit includes a third inductor L3, a fourth inductor L4, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6; wherein the first end of the third inductor L3 and the first end of the fourth capacitor C4 are connected to the input terminal of the first interstage matching circuit; the second end of the third inductor L3 is connected to the first end of the fifth capacitor C5 and the power supply terminal of the first interstage matching circuit; the second end of the fifth capacitor C5 is grounded; the second end of the fourth capacitor C4 is connected to the first end of the fourth inductor L4 and the first end of the sixth capacitor C6; the second end of the fourth inductor L4 is grounded; and the second end of the sixth capacitor C6 is connected to the output terminal of the first interstage matching circuit.

[0014] As a preferred example, the second-stage inter-stage matching circuit includes a fifth inductor L5, a sixth inductor L6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9, and a tenth capacitor C10. 10 The first end of the fifth inductor L5 and the first end of the seventh capacitor C7 are connected to the input terminal of the second-stage matching circuit; the second end of the fifth inductor L5 is connected to the first end of the eighth capacitor C8 and the power supply terminal of the second-stage matching circuit; the second end of the eighth capacitor C8 is grounded; the second end of the seventh capacitor C7 is connected to the first end of the ninth capacitor C9, the first end of the sixth inductor L6, and the tenth capacitor C... 10 The first terminal is connected; the second terminal of the ninth capacitor C9 is grounded; the second terminal of the sixth inductor L6 is grounded; the tenth capacitor C 10 The second end is connected to the output of the second-stage inter-matching circuit.

[0015] As a preferred example, the output matching circuit includes a seventh inductor L7, an eighth inductor L8, a ninth inductor L9, and a tenth inductor L1. 10 Eleventh Inductor L 11 12th Inductor L 12 Eleventh capacitor C 11 The twelfth capacitor C 12 The thirteenth capacitor C 13 Fourteenth capacitor C 14 The fifteenth capacitor C 15 and the sixteenth capacitor C 16; where the eleventh capacitor C 11 The first end, the twelfth capacitor C 12 The first end of the ninth inductor L9, the first end of the twelfth inductor L 12 The first end is connected to the input terminal of the output matching circuit; the eleventh capacitor C 11 The second end is connected to the first end of the seventh inductor L7; the second end of the seventh inductor L7 is grounded; the twelfth capacitor C 12 The second end is connected to the first end of the eighth inductor L8; the second end of the eighth inductor L8 is grounded; the twelfth inductor L... 12 The second end and the sixteenth capacitor C 16 The first end is connected to the power supply terminal of the output matching circuit; the sixteenth capacitor C 16 The second end is grounded; the second end of the ninth inductor L9 is connected to the thirteenth capacitor C. 13 The first end, the fourteenth capacitor C 14 The first end is connected; the thirteenth capacitor C 13 The second end is grounded; the fourteenth capacitor C 14 The second end and the tenth inductor L 10 First end, eleventh inductor L 11 The first end, the fifteenth capacitor C 15 The first end is connected; the tenth inductor L 10 The second end is grounded; the eleventh inductor L 11 The second end, the fifteenth capacitor C 15 The second end is connected to the output terminal of the output matching circuit.

[0016] As a preferred embodiment, the electrostatic discharge protection circuit includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, and a sixth diode D6; wherein the first diode D1, the second diode D2, the third diode D3, the fourth diode D4, and the fifth diode D5 are forward-biased and connected in series, the positive terminal of the first diode D1 is connected to the electrostatic discharge terminal of the electrostatic discharge protection circuit, and the negative terminal of the fifth diode D5 is grounded; the sixth diode D6 is reverse-biased, the positive terminal of the sixth diode D6 is connected to the electrostatic discharge terminal of the electrostatic discharge protection circuit, and the negative terminal is grounded.

[0017] As a preferred example, the first dynamic linearization bias circuit, the second dynamic linearization bias circuit, and the third dynamic linearization bias circuit have the same structure.

[0018] Each dynamic linearization bias circuit includes a second resistor R2, a third resistor R3, a fourth resistor R4, and a sixteenth capacitor C. pThe transistors are: a first transistor T1, a second transistor T2, and a third transistor T3; wherein the base of the first transistor T1 is connected to the base and collector of the second transistor T2, the first end of the second resistor R2, and the sixteenth capacitor C. p The first end of the first transistor T1 is connected to the first end of the fourth resistor R4; the collector of the first transistor T1 is connected to the first end of the third resistor R3; the second end of the fourth resistor R4 is connected to the output of the dynamic linearization bias circuit; the sixteenth capacitor C p The second end of the resistor R2 is grounded to the emitter of the third transistor T3; the base and collector of the third transistor T3 are connected to the emitter of the second transistor T2; the second end of the second resistor R2 is connected to the first input terminal of the dynamic linearization bias circuit; the second end of the third resistor R3 is connected to the second input terminal of the dynamic linearization bias circuit; the first input terminal of the dynamic linearization bias circuit is connected to the power supply terminal V. ref The second input terminal of the dynamic linearization bias circuit is connected to the power supply terminal V. batt .

[0019] As a preferred example, the power detection circuit includes a seventeenth capacitor C. 17 The eighteenth capacitor C 18 7th diode D p The fifth resistor R5 and the sixth resistor R6; the seventeenth capacitor C 17 The first end is connected to the voltage detection input terminal of the power detection circuit; the seventeenth capacitor C 17 The second end and the seventh diode D p The positive terminal is connected; the seventh diode D p The negative terminal and the eighteenth capacitor C 18 The first end of the capacitor is connected to the first end of the fifth resistor R5; the eighteenth capacitor C 18 The second end of the fifth resistor R5 is grounded; the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 and the voltage detection output terminal of the power amplifier circuit respectively; the second end of the sixth resistor R6 is grounded.

[0020] The beneficial effects of this invention are as follows:

[0021] First, the high-linearity, high-power GaAs HBT power amplifier with power detection of the present invention utilizes a negative feedback network to improve stability and expand bandwidth, and second harmonic suppression to improve overall linearity. It also features an electrostatic discharge (ESD) protection circuit to protect the entire circuit from damage by ESD current. Furthermore, a bias circuit is used to provide a dynamically changing bias voltage to the three-stage amplifier circuit, addressing the linearity degradation and current instability issues caused by self-heating effects of GaAs HBT transistors under high-power input. This improves the overall linearity of the power amplifier and reduces amplitude-amplitude distortion and amplitude-phase distortion. Thus, it fully combines negative feedback, dynamic bias, and harmonic suppression techniques to enhance the overall linearity of the amplifier.

[0022] Secondly, the GaAs HBT power amplifier with high linearity and high power detection of the present invention proposes a power detection circuit for outputting a DC voltage that is positively correlated with the output power, so as to achieve precise control of the output power of the power amplifier. Attached Figure Description

[0023] Figure 1 is a block diagram of the GaAs HBT power amplifier with high linearity and high power detection according to the present invention.

[0024] Figure 2 is a schematic diagram of the amplification unit of the present invention;

[0025] Figure 3 is a schematic diagram of the negative feedback network of the present invention;

[0026] Figure 4 is a schematic diagram of the input matching circuit of the present invention;

[0027] Figure 5 is a schematic diagram of the first-stage inter-stage matching circuit of the present invention;

[0028] Figure 6 is a schematic diagram of the second-stage inter-stage matching circuit of the present invention;

[0029] Figure 7 is a schematic diagram of the output matching circuit of the present invention;

[0030] Figure 8 is a schematic diagram of the electrostatic protection circuit of the present invention;

[0031] Figure 9 is a schematic diagram of the dynamic linearization bias circuit of the present invention;

[0032] Figure 10 is a schematic diagram of the power detection circuit of the present invention;

[0033] Figure 10 is a schematic diagram of the power detection circuit of the present invention;

[0034] Figure 11 is a simulation diagram of the S-parameters of the GaAs HBT power amplifier with high linearity and high power detection of the present invention.

[0035] Figure 12 shows the amplitude-amplitude (AM-AM) and amplitude-phase (AM-PM) distortion diagrams of the simulation of the high-linearity, high-power GaAs HBT power amplifier with power detection of the present invention.

[0036] Figure 13 is a simulation diagram of the second harmonic power of the GaAs HBT power amplifier with high linearity and high power with power detection according to the present invention.

[0037] Figure 14 is a simulation diagram of the power detection voltage of the power detection circuit of the present invention changing with the output power;

[0038] Figure 15 is a simulation diagram of the input power (Pin) and output power (Pout) of the GaAs HBT power amplifier with high linearity and high power detection of the present invention.

[0039] Figure 16 is a simulation diagram of the output power (Pout) and power-added efficiency (PAE) of the high linearity and high power GaAs HBT power amplifier with power detection of the present invention.

[0040] Figure 17 is a simulation diagram of the 1dB compression point of the output power of the GaAs HBT power amplifier with high linearity and high power detection of the present invention. Detailed Implementation

[0041] The following embodiments are provided to enable those skilled in the art to more fully understand the present invention, but do not limit the invention in any way.

[0042] Figure 1 is a block diagram of the high linearity, high power GaAs HBT power amplifier with power detection according to the present invention. In this embodiment, the power amplifier includes 14 parts: a first amplification unit, a second amplification unit, a third amplification unit, an input matching circuit, a first negative feedback network, a second negative feedback network, an input matching circuit, a first interstage matching circuit, a second interstage matching circuit, an output matching circuit, an electrostatic protection circuit, a first dynamic linearization bias circuit, a second dynamic linearization bias circuit, a third dynamic linearization bias circuit, and a power detection circuit.

[0043] Referring to Figure 1, each amplification unit includes terminal 1 and terminal 2, each negative feedback network includes terminal 1 and terminal 2, the input matching circuit includes terminal 1 and terminal 2, each inter-stage matching network includes terminal 1, terminal 2, and terminal 3, the output matching circuit includes terminal 1, terminal 2, and terminal 3, the electrostatic protection circuit includes terminal 1, each dynamic linearization bias circuit includes terminal 1, terminal 2, and terminal 3, and the power detection circuit includes terminal 1 and terminal 2.

[0044] Specifically, terminal 1 (signal input) of the input matching circuit is connected to the input terminal of the overall circuit; terminal 2 (signal output) of the input matching circuit is connected to terminal 1 (signal input) of the first-stage amplification unit, terminal 1 (signal output) of the first-stage negative feedback network, and terminal 1 (signal input) of the first-stage dynamic linearization bias circuit; terminal 2 (signal output) of the first-stage amplification unit is connected to terminal 1 (signal input) of the first-stage inter-stage matching network and terminal 2 (signal input) of the first-stage negative feedback network; terminal 2 (signal output) of the first-stage inter-stage matching network is connected to terminal 1 (signal input) of the second-stage amplification unit, terminal 1 (signal output) of the second-stage negative feedback network, and terminal 1 (signal input) of the second-stage dynamic linearization bias circuit; terminal 3 (power supply) of the first-stage inter-stage matching circuit is connected to the DC voltage Vdd and terminal 1 (static discharge) of the electrostatic protection circuit; terminal 2 (signal output) of the second-stage amplification unit is connected to the second-stage inter-stage matching circuit. Terminal 1 (signal input) of the first stage is connected to terminal 2 (signal input) of the second-stage negative feedback network; terminal 2 (signal output) of the second-stage inter-stage matching circuit is connected to terminal 1 (signal input) of the third-stage amplification unit and terminal 1 (signal input) of the third-stage dynamic linearization bias circuit; terminal 3 (power supply) of the second-stage inter-stage matching circuit is connected to DC voltage Vdd and terminal 1 (static discharge) of the electrostatic protection circuit; terminal 2 (signal output) of the third-stage amplification unit is connected to terminal 1 (signal input) of the output matching circuit and terminal 1 (voltage detection input) of the power detection circuit; terminal 2 (signal output) of the output matching circuit is connected to the output terminal of the overall circuit; terminal 3 (power supply) of the output matching circuit is connected to DC voltage Vdd and terminal 1 (static discharge) of the electrostatic protection circuit; terminal 2 (voltage detection output) of the power detection circuit is connected to the power detection voltage; terminals 2 and 3 (power supply) of the third-stage dynamic linearization bias circuit are each connected to DC voltage Vdd. ref and V batt Connected.

[0045] The working principle of the GaAs HBT power amplifier of this invention is as follows: The radio frequency signal enters the power amplifier through the input terminal, and then is amplified by three stages of amplification to output an amplified signal. The radio frequency signal path, composed of the first amplification unit, the second amplification unit, the third amplification unit, the input matching circuit, the first inter-stage matching circuit, the second inter-stage matching circuit, the output matching circuit, the first negative feedback network, and the second negative feedback network, achieves wide-bandwidth signal amplification. The first dynamic linearization bias circuit, the second dynamic linearization bias circuit, and the third dynamic linearization bias circuit provide bias to the first amplification unit, the second amplification unit, and the third amplification unit, respectively, and improve the linearity of the power amplifier through the nonlinear compensation characteristics of the active bias, thereby improving the amplitude-amplitude distortion and amplitude-phase distortion of the power amplifier. The electrostatic discharge protection circuit provides an electrostatic discharge path for the power amplifier, thereby protecting the overall circuit. The power detection circuit is used to output a DC voltage that is positively correlated with the output power to achieve precise control of the power amplifier's output power.

[0046] Figure 2 is a schematic diagram of the amplification unit of the present invention; each amplification unit includes n parallel transistors [Q1, ... Q1]. n The transistor is a GaAs HBT transistor. The size of each GaAs HBT transistor and the number of transistors n connected in parallel are selected according to the power required for each stage. In this embodiment, the collector width of each GaAs HBT transistor in the first amplification unit is 2um, the length is 25um, the interpolation index is 2, and the number of transistors connected in parallel is 2. In the second amplification unit, the collector width of each GaAs HBT transistor is 2um, the length is 25um, the interpolation index is 2, and the number of transistors connected in parallel is 4. In the third amplification unit, the collector width of each GaAs HBT transistor is 3um, the length is 35um, the interpolation index is 3, and the number of transistors connected in parallel is 16.

[0047] Figure 3 is a schematic diagram of the negative feedback network of the present invention; each negative feedback network adopts the same RLC structure, including resistor R F Inductor L F and capacitor C F The resistance R F One end is connected to end 1 of the negative feedback network; resistor R F The other end is connected to inductor L F Connected; Inductance L F The other end is connected to the two ends of the negative feedback network; by adopting this negative feedback structure, the bandwidth of the power amplifier can be effectively widened, the gain flatness can be improved, and the stability of the circuit can be significantly improved; the negative feedback network not only enhances the performance of the circuit, but also ensures consistency and reliability at different frequencies.

[0048] Figure 4 is a schematic diagram of the input matching circuit of the present invention, including inductor L1, inductor L2, capacitor C2, and capacitor C3; wherein one end of inductor L1 and capacitor C2 is connected to terminal 1 of the input matching circuit; the other end of inductor L1 is grounded; the other end of capacitor C2 is connected to capacitor C3 and terminal 2 of the input matching circuit; the other end of capacitor C3 is connected to inductor L2; the other end of inductor L2 is grounded; by reasonably selecting the values ​​of each capacitor and inductor, the impedance from terminal 2 can be transformed to around 50 ohms, thereby achieving good input impedance matching; this matching can not only reduce the loss of input signal, but also improve the overall performance of the system, ensuring the efficiency and stability of signal transmission.

[0049] Figure 5 is a schematic diagram of the first-stage inter-stage matching circuit of the present invention, including inductor L3, inductor L4, capacitor C4, capacitor C5, and capacitor C6; wherein one end of inductor L3 and capacitor C4 is connected to terminal 1 of the first-stage inter-stage matching circuit; the other end of inductor L3 is connected to capacitor C5 and terminal 3 of the first-stage inter-stage matching circuit; the other end of capacitor C5 is grounded; the other end of capacitor C4 is connected to inductor L4 and capacitor C6; the other end of inductor L4 is grounded; the other end of capacitor C6 is connected to terminal 2 of the first-stage inter-stage matching circuit; by reasonably selecting the values ​​of each capacitor and inductor, the impedance from terminal 2 can be transformed to near the appropriate optimal impedance, forming good inter-stage impedance matching, reducing input signal loss, and improving the performance and efficiency of the entire system.

[0050] Figure 6 is a schematic diagram of the second-stage inter-matching circuit of the present invention, including inductor L5, inductor L6, capacitor C7, capacitor C8, capacitor C9 and capacitor C1. 10 The inductor L5 and capacitor C7 are connected at one end to terminal 1 of the second-stage matching circuit; the other end of inductor L5 is connected to capacitor C8 and terminal 3 of the second-stage matching circuit; the other end of capacitor C8 is grounded; and the other end of capacitor C7 is connected to capacitor C9, inductor L6, and capacitor C... 10 Connected; the other end of capacitor C9 is grounded; the other end of inductor L6 is grounded; capacitor C 10 The other end is connected to the two ends of the second-stage interstage matching circuit. By reasonably selecting the values ​​of each capacitor and inductor, the impedance from the two ends can be transformed to a suitable optimal impedance, forming a good interstage impedance match, reducing input signal loss, and improving the performance and efficiency of the entire system.

[0051] Figure 7 is a schematic diagram of the output matching circuit of the present invention, including inductors L7, L8, L9, and L1. 10 Inductor L 11 Inductor L 12 Capacitor C 11 Capacitor C 12 Capacitor C 13 Capacitor C 14 Capacitor C 15 Capacitor C16 ;where the capacitor C 11 Capacitor C 12 Inductor L9, Inductor L 12 Connected to terminal 1 of the output matching circuit; capacitor C 11 The other end is connected to inductor L7; the other end of inductor L7 is grounded; capacitor C 12 The other end is connected to inductor L8; the other end of inductor L8 is grounded; inductor L 12 The other end is connected to capacitor C 16 The three terminals of the output matching circuit are connected; capacitor C 16 The other end is grounded; the other end of inductor L9 is connected to capacitor C. 13 Capacitor C 14 Connected; Capacitor C 13 The other end is grounded; capacitor C 14 The other end is connected to inductor L 10 Inductor L 11 Capacitor C 15 Connected; Inductance L 10 The other end is grounded; inductor L 11 Capacitor C 15 The other end is connected to two terminals of the output matching circuit; where L9 and C 13 and C 14 L 10 A second-order L-type matching network is formed, and the values ​​of each inductor and capacitor are determined by load pulling to achieve good output impedance matching, thereby maximizing saturated output power and maximum power-added efficiency; C 11 L7 and C 12 L8 forms a series resonance, with the resonant frequencies all at the second harmonic, used to short-circuit the second harmonic; C 15 L 11 The parallel resonance is formed, with the resonant frequency at the second harmonic, which is used to open the second harmonic; the second harmonic suppression function of the output matching circuit improves the overall linearity of the power amplifier.

[0052] Figure 8 is a schematic diagram of the electrostatic discharge (ESD) protection circuit of the present invention, including diodes D1 to D6; wherein diodes D1 to D5 are forward-biased and connected in series, the positive terminal of diode D1 is connected to terminal 1 of the ESD protection circuit, and the negative terminal of diode D5 is grounded; diode D6 is reverse-biased, the positive terminal is connected to terminal 1 of the ESD protection circuit, and the negative terminal is grounded; when static electricity occurs and exceeds the turn-on voltage, the forward diodes D1 to D5 conduct, and at the same time, the reverse diode D6 undergoes avalanche breakdown and conducts, and the current flows to ground, protecting the internal circuit.

[0053] Figure 9 is a schematic diagram of the dynamic linearization bias circuit of the present invention; the bias circuit includes resistors R2, R3, R4, and capacitor C. pTransistor T1, transistor T2, and transistor T3; wherein the base of transistor T1 is connected to the base and collector of transistor T2, resistor R2, and capacitor C. p Connected; the emitter of transistor T1 is connected to resistor R4; the collector of transistor T1 is connected to resistor R3; the other end of resistor R4 is connected to terminal 1 of the dynamic linearization bias circuit; capacitor C p The other end of resistor R2 is grounded to the emitter of transistor T3; the base and collector of transistor T3 are connected to the emitter of transistor T2; the other end of resistor R2 is connected to terminal 2 of the dynamic linearization bias circuit; the other end of resistor R3 is connected to terminal 3 of the dynamic linearization bias circuit; as the RF power increases, a small portion of the RF power will leak into the bias circuit, and after passing through transistor T1, it will be absorbed by the linear capacitor C. p With the circuit bypassed to ground, the base potential Vb1 of transistor T1 remains unchanged. The leaked power increases the DC current of transistor T1, and the DC rectification of transistor T1 reduces the DC component Vbe1 of the base-emitter junction voltage. Since Vb1 remains constant, the emitter potential of T1, i.e., the potential at terminal 1 of the dynamic linearization bias circuit, Ve1, rises, thus compensating for the decrease in terminal 1 potential of the bias circuit caused by the increase in RF power. Simultaneously, resistor R4 suppresses the instability of the bias circuit caused by self-heating. The dynamic linearization bias circuit improves the overall linearity of the power amplifier and reduces amplitude-amplitude distortion and amplitude-phase distortion.

[0054] Figure 10 is a schematic diagram of the power detection circuit of the present invention, including capacitor C. 17 Capacitor C 18 Diode D p Resistors R5 and R6; capacitor C 17 Connected to terminal 1 of the power detection circuit; capacitor C 17 The other end is connected to diode D p Connected; Diode D p The other end is connected to capacitor C 18 Resistor R5 is connected; capacitor C 18 The other end is grounded; the other end of resistor R5 is connected to one end of resistor R6 and terminals 2 of the power amplifier circuit; the other end of resistor R6 is grounded. Capacitor C 17 The radio frequency signal is coupled into the power detection circuit; due to diode D p Due to the nonlinear resistance, the diode output current will exhibit the nth harmonic current of the radio frequency signal; through capacitor C 18 High-frequency components are filtered out, and resistors R5 and R6 are used as loads to output a DC voltage at the two ends of the power detection circuit that is positively correlated with the output power.

[0055] Figure 11 shows the S-parameter simulation diagram of the high linearity, high power GaAs HBT power amplifier with power detection of the present invention. In the operating frequency range of 5-6 GHz, the gain S21 parameter of the power amplifier is about 34 dB, and the gain variation is less than 0.5 dB, which reflects the large gain provided by the three-stage amplification unit and the good gain flatness of the power amplifier provided by the negative feedback network. The S11 and S22 parameters of the power amplifier are both less than -10 dB, which reflects the extremely low input and output reflection loss of the power amplifier.

[0056] Figure 12 shows the amplitude-amplitude (AM-AM) and amplitude-phase (AM-PM) distortion diagrams of the simulated high-linearity, high-power GaAs HBT power amplifier with power detection according to the present invention. Compared with the case without dynamic linearization bias circuit, the dynamic linearization bias circuit improves the linearity degradation and current instability caused by self-heating effect of GaAs HBT transistor under high power input by providing a bias voltage that changes dynamically with the input power, thereby improving the amplitude-amplitude distortion and amplitude-phase distortion of the power amplifier. Simulation results show that when the input power is -0.5dBm, the dynamic linearization bias circuit improves the amplitude distortion of the power amplifier from 0.57 to 0.64 and the phase distortion from 1.97dB to 1.20dB.

[0057] Figure 13 shows the simulation diagram of the second harmonic power of the high-linearity, high-power GaAs HBT power amplifier with power detection according to the present invention. Compared with the case without harmonic suppression, the output matching circuit with harmonic suppression short-circuit and open-circuit the second harmonic through series resonance and parallel resonance of inductor and capacitor, respectively, thereby greatly reducing the second harmonic power at the output end and improving the overall linearity of the power amplifier. The simulation results show that when the output power is 33dBm, harmonic suppression reduces the output second harmonic power of the power amplifier from -8.75dBm to -26.11dBm.

[0058] Figure 14 is a simulation diagram of the power detection voltage of the power detection circuit of the present invention changing with the output power; capacitor C17 couples the radio frequency signal into the power detection circuit. Due to the nonlinear resistance of diode Dp, the diode output current will have the nth harmonic current of the radio frequency signal. Introducing capacitor C18 forms a low-pass filter. After filtering out the high frequency components, the remaining DC voltage is proportional to the power of the radio frequency signal, so the power of the radio frequency signal can be detected.

[0059] Figure 15 shows the input power (Pin) - output power (Pout) simulation diagram of the high linearity and high power GaAs HBT power amplifier with power detection of the present invention. The simulation results at different frequencies show good consistency, reflecting the consistent performance of the power amplifier in the operating frequency band of 5-6GHz. The 1dB compression point of the output power is between 32-33dBm, reflecting the high linearity of the power amplifier.

[0060] Figure 16 shows the simulation results of the output power (Pout) and power-added efficiency (PAE) of the high linearity and high power GaAs HBT power amplifier with power detection of the present invention. The simulation results at different frequencies show good consistency, reflecting the consistent performance of the power amplifier in the operating frequency band of 5-6 GHz. The maximum power-added efficiency is about 37%, which reflects the high efficiency of the power amplifier.

[0061] Figure 17 is a simulation diagram of the 1dB compression point of the output power of the GaAs HBT power amplifier with high linearity and power detection of the present invention. Within the operating frequency band of 5-6GHz, the 1dB compression point of the output power remains above 32dBm, which demonstrates the harmonic suppression effect of the output matching circuit and the significant effect of the dynamic linearization bias circuit on improving the linearity of the power amplifier.

[0062] The above are merely preferred embodiments of the present invention. The scope of protection of the present invention is not limited to the above embodiments. All technical solutions falling within the scope of the present invention's concept are within the scope of protection of the present invention. It should be noted that for those skilled in the art, any improvements and modifications made without departing from the principles of the present invention should be considered within the scope of protection of the present invention.

Claims

1. A GaAs HBT power amplifier with high linearity and high power sensing, characterized in that, The GaAs HBT power amplifier includes an RF path, a bias module, and a power detection circuit. The radio frequency (RF) path includes an input matching circuit, a first amplification unit, a first inter-stage matching circuit, a second amplification unit, a second inter-stage matching circuit, a third amplification unit, an output matching circuit, a first negative feedback network, a second negative feedback network, and an electrostatic discharge (ESD) protection circuit, all connected in sequence. The input matching circuit, first amplification unit, first inter-stage matching circuit, second amplification unit, second inter-stage matching circuit, third amplification unit, and output matching circuit are connected in sequence. The first negative feedback network is connected in parallel to the first amplification unit, and the second negative feedback network is connected in parallel to the second amplification unit. The RF path is used to amplify the power of the input RF signal. The ESD protection circuit is connected to the first inter-stage matching circuit, the second inter-stage matching circuit, and the output matching circuit to construct an ESD discharge path. The bias module includes a first dynamic linearization bias circuit, a second dynamic linearization bias circuit, and a third dynamic linearization bias circuit. The two input terminals of the first, second, and third dynamic linearization bias circuits are respectively connected to DC voltage Vref and DC voltage Vbatt. The output terminals of the first, second, and third dynamic linearization bias circuits are respectively connected to the input terminals of the first, second, and third amplification units, providing the first, second, and third amplification units with bias voltages that dynamically change with the input power. The power detection circuit is connected to the output terminal of the third amplification unit and is used to output a DC voltage that is positively correlated with the output power.

2. The GaAs HBT power amplifier with high linearity and high power detection according to claim 1, characterized in that, The first amplification unit, the second amplification unit and the third amplification unit are of the same structure, each of the amplification units comprises n-stage parallel GaAs HBT transistors [Q1, Q2, …Qn]; n ];The transistor triode is a GaAs HBT transistor triode;The size of each transistor triode and the number n of parallel GaAs HBT transistors are selected according to the power size requirement set by each stage of the amplifier.

3. The GaAs HBT power amplifier with high linearity and high power detection according to claim 1, characterized in that, The first negative feedback network and the second negative feedback network are of the same structure; each negative feedback network comprises a first resistor R F , a feedback inductor L F , and a first capacitor C F connected in sequence; one end of the first resistor R F away from the feedback inductor L F is connected with an input end of a corresponding amplification unit, and one end of the first capacitor C F away from the feedback inductor L F is connected with an output end of the corresponding amplification unit.

4. The GaAs HBT power amplifier with high linearity and high power detection according to claim 1, characterized in that, The input matching circuit includes a first inductor L1, a second inductor L2, a second capacitor C2, and a third capacitor C3; wherein, the two ends of the second capacitor C2 are connected to the input terminal and the output terminal of the input matching circuit, respectively; the first end of the first inductor L1 is connected to the input terminal of the input matching circuit, and the second end is grounded; the first end of the third capacitor C3 is connected to the output terminal of the input matching circuit, and the second end is grounded through the second inductor L2.

5. The GaAs HBT power amplifier with high linearity and high power detection according to claim 1, characterized in that, The first interstage matching circuit includes a third inductor L3, a fourth inductor L4, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6; wherein the first end of the third inductor L3 and the first end of the fourth capacitor C4 are connected to the input terminal of the first interstage matching circuit; the second end of the third inductor L3 is connected to the first end of the fifth capacitor C5 and the power supply terminal of the first interstage matching circuit; the second end of the fifth capacitor C5 is grounded; the second end of the fourth capacitor C4 is connected to the first end of the fourth inductor L4 and the first end of the sixth capacitor C6; the second end of the fourth inductor L4 is grounded; and the second end of the sixth capacitor C6 is connected to the output terminal of the first interstage matching circuit.

6. The GaAs HBT power amplifier with high linearity and high power detection according to claim 1, characterized in that, The second inter-stage matching circuit comprises a fifth inductor L5, a sixth inductor L6, a seventh capacitor C7, an eighth capacitor C8, a ninth capacitor C9 and a tenth capacitor C 10 ; wherein a first end of the fifth inductor L5, a first end of the seventh capacitor C7 are connected to an input end of the second inter-stage matching circuit; a second end of the fifth inductor L5 is connected to a first end of the eighth capacitor C8 and a power supply end of the second inter-stage matching circuit; a second end of the eighth capacitor C8 is grounded; a second end of the seventh capacitor C7 is connected to a first end of the ninth capacitor C9, a first end of the sixth inductor L6 and a first end of the tenth capacitor C 10 ; a second end of the ninth capacitor C9 is grounded; a second end of the sixth inductor L6 is grounded; and a second end of the tenth capacitor C 10 is connected to an output end of the second inter-stage matching circuit.

7. The GaAs HBT power amplifier with high linearity and high power detection according to claim 1, characterized in that, The output matching circuit includes a seventh inductor L7, an eighth inductor L8, a ninth inductor L9, and a tenth inductor L1. 10 Eleventh Inductor L 11 12th Inductor L 12 Eleventh capacitor C 11 The twelfth capacitor C 12 The thirteenth capacitor C 13 Fourteenth capacitor C 14 The fifteenth capacitor C 15 and the sixteenth capacitor C 16 ; where the eleventh capacitor C 11 The first end, the twelfth capacitor C 12 The first end of the ninth inductor L9, the first end of the twelfth inductor L 12 The first end is connected to the input terminal of the output matching circuit; the eleventh capacitor C 11 The second end is connected to the first end of the seventh inductor L7; the second end of the seventh inductor L7 is grounded; the twelfth capacitor C 12 The second end is connected to the first end of the eighth inductor L8; the second end of the eighth inductor L8 is grounded; the twelfth inductor L... 12 The second end and the sixteenth capacitor C 16 The first end is connected to the power supply terminal of the output matching circuit; the sixteenth capacitor C 16 The second end is grounded; the second end of the ninth inductor L9 is connected to the thirteenth capacitor C. 13 The first end, the fourteenth capacitor C 14 The first end is connected; the thirteenth capacitor C 13 The second end is grounded; the fourteenth capacitor C 14 The second end and the tenth inductor L 10 First end, eleventh inductor L 11 The first end, the fifteenth capacitor C 15 The first end is connected; the tenth inductor L 10 The second end is grounded; the eleventh inductor L 11 The second end, the fifteenth capacitor C 15 The second end is connected to the output terminal of the output matching circuit.

8. The GaAs HBT power amplifier with high linearity and high power detection according to claim 1, characterized in that, The electrostatic discharge (ESD) protection circuit includes a first diode D1, a second diode D2, a third diode D3, a fourth diode D4, a fifth diode D5, and a sixth diode D6. Diodes D1, D2, D3, D4, and D5 are forward-biased and connected in series. The anode of the first diode D1 is connected to the ESD discharge terminal of the ESD protection circuit, and the cathode of the fifth diode D5 is grounded. The sixth diode D6 is reverse-biased, with its anode connected to the ESD discharge terminal of the ESD protection circuit and its cathode grounded.

9. The GaAs HBT power amplifier with high linearity and high power detection according to claim 1, characterized in that, The first dynamic linearization bias circuit, the second dynamic linearization bias circuit, and the third dynamic linearization bias circuit have the same structure. Each dynamic linearization bias circuit includes a second resistor R2, a third resistor R3, a fourth resistor R4, and a sixteenth capacitor C. p The transistors are: a first transistor T1, a second transistor T2, and a third transistor T3; wherein the base of the first transistor T1 is connected to the base and collector of the second transistor T2, the first end of the second resistor R2, and the sixteenth capacitor C. p The first end of the first transistor T1 is connected to the first end of the fourth resistor R4; the collector of the first transistor T1 is connected to the first end of the third resistor R3; the second end of the fourth resistor R4 is connected to the output of the dynamic linearization bias circuit; the sixteenth capacitor C p The second end of the resistor R2 is grounded to the emitter of the third transistor T3; the base and collector of the third transistor T3 are connected to the emitter of the second transistor T2; the second end of the second resistor R2 is connected to the first input terminal of the dynamic linearization bias circuit; the second end of the third resistor R3 is connected to the second input terminal of the dynamic linearization bias circuit; the first input terminal of the dynamic linearization bias circuit is connected to the power supply terminal V. ref The second input terminal of the dynamic linearization bias circuit is connected to the power supply terminal V. batt .

10. The GaAs HBT power amplifier with high linearity and high power detection according to claim 1, characterized in that, The power detection circuit includes a seventeenth capacitor C. 17 The eighteenth capacitor C 18 7th diode D p The fifth resistor R5 and the sixth resistor R6; the seventeenth capacitor C 17 The first end is connected to the voltage detection input terminal of the power detection circuit; the seventeenth capacitor C 17 The second end and the seventh diode D p The positive terminal is connected; the seventh diode D p The negative terminal and the eighteenth capacitor C 18 The first end of the capacitor is connected to the first end of the fifth resistor R5; the eighteenth capacitor C 18 The second end of the fifth resistor R5 is grounded; the second end of the fifth resistor R5 is connected to the first end of the sixth resistor R6 and the voltage detection output terminal of the power amplifier circuit respectively; the second end of the sixth resistor R6 is grounded.

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