Error correction method for computed SSDs that support high-speed file semantic search

Abstract

In this specification, a device and method for performing semantic search on an SSD are disclosed via a computational SSD system that distributes calculations across each NAND flash die of the SSD and, at the same time, the SSD controller processes result aggregation using a new die-on computational logic circuit to provide file semantic search on the device. The computational SSD system can read file feature vectors from multiple dies to the SSD controller, and these feature vectors may be buffered in DRAM if necessary, and the controller processes distance calculations. A local die-on AI / ML processing unit can, for example, perform computational and comparison operations and pass the processing scores and results to the SSD controller. The SSD controller aggregates the results from all dies and returns the results to the host. The feature vector store size, circuitry, and the number of die-on AI / ML processing units can be configured as needed to adapt to different tasks, system constraints, and / or feature vector sizes.

Description

[Technical Field]

[0001] (Cross-reference of related applications) This application claims priority to U.S. Provisional Application No. 63 / 476,666 filed on 22 December 2022, and asserts the interests of U.S. Non-Provisional Application No. 18 / 449,165, entitled “Error Correction Methods for Computational SSD Supporting Rapid File Semantic Search,” filed with the U.S. Patent and Trademark Office on 14 August 2023, the entire contents of which are incorporated herein by reference for all purposes.

[0002] This disclosure relates to a storage system. More specifically, this disclosure relates to the use of a storage system to run machine learning processes. [Background technology]

[0003] Storage devices are ubiquitous within computing systems. In recent years, solid-state storage devices (SSDs) have become increasingly common. These non-volatile storage devices can communicate with and utilize various protocols, including non-volatile memory express (NVMe) and peripheral component interconnect express (PCIe), to reduce processing overhead and increase efficiency.

[0004] As SSDs evolve, they become more power-efficient compared to traditional hard disk drives (HDDs), thus giving SSDs advantages in both consumer and commercial markets. Over the years, many users have accumulated thousands of files documenting their lives, experiences, travels, and interests. To find specific media files based on that content, users often spend a lot of time navigating, organizing, and searching through albums and folders for specific photos, videos, and other media. Generally, user media is stored across various storage and computing devices, limiting the methods users have for contextually searching photos, videos, and other media to find desired media files. In fact, users are limited to conventional search methods, such as vocabulary searches, for finding media on storage systems, which are limited to searching for recent files or files with specific filenames or attributes. Furthermore, the vast amount of stored media files and the lack of contextual search methods make it difficult for users to find specific media on their storage and computing devices.

[0005] With the advancement of artificial intelligence (AI) and machine learning (ML), accurate semantic searching has become possible, enabling users to find relevant content within their media files stored on their storage devices. However, traditional implementations of AI / ML semantic search on storage devices have several problems that make them inefficient and limited. One problem with traditional AI / ML implementations of semantic search is that data is repeatedly moved between the host processor, host memory, and storage device, leading to a substantial waste of bandwidth and energy from data movement. Another problem with traditional AI / ML implementations of semantic search is preparing the data for AI / ML processing for on-host computing, that is, reading data from multiple dies to the storage device controller, buffering the data in memory for the controller to process the AI / ML, and then executing the AI / ML processing. This causes a bottleneck for the storage device controller because the controller must handle both I / O and computation operations, and such computations require additional memory buffers to store the data for AI / ML processing. [Brief explanation of the drawing]

[0006] The above and other embodiments, features, and advantages of some of the embodiments of this disclosure will become more apparent from the following description, presented in conjunction with some of the drawings below. [Figure 1] This is a schematic block diagram of an exemplary host computing device having a storage system suitable for a compute SSD system supporting semantic search, according to one embodiment of the present disclosure. [Figure 2] This is a schematic block diagram of an exemplary storage device suitable for a compute SSD system supporting semantic search, according to one embodiment of the present disclosure. [Figure 3]This is a conceptual diagram of pages of memory cells, for example, organized in a NAND configuration, that are sensed or programmed in parallel, according to one embodiment of the present disclosure. [Figure 4] This is a schematic block diagram of an exemplary computing SSD system supporting semantic search according to one embodiment of the present disclosure. [Figure 5] This is a schematic block diagram of an exemplary machine learning processing unit of a compute SSD system supporting semantic search, according to one embodiment of the present disclosure. [Figure 6] This is a schematic block diagram of an exemplary machine learning processing unit of a compute SSD system supporting semantic search, according to one embodiment of the present disclosure. [Figure 7] This flowchart shows a process for utilizing an exemplary compute SSD system that supports semantic search, according to one embodiment of the present disclosure. [Figure 8] This flowchart shows a process for utilizing an exemplary compute SSD system that supports semantic search, according to one embodiment of the present disclosure. [Figure 9] This is a schematic block diagram of an exemplary machine learning process according to one embodiment of the present disclosure. [Figure 10A] This is a schematic block diagram of an exemplary error correction system according to one embodiment of the present disclosure. [Figure 10B] Figure 10A is a chart illustrating an example error correction system according to one embodiment of the present disclosure. [Figure 10C] Figure 10A shows an example of an error correction system table according to one embodiment of the present disclosure. [Figure 11A] This is a schematic block diagram of an exemplary error correction system according to one embodiment of the present disclosure. [Figure 11B] Figure 11A is a chart illustrating an example error correction system according to one embodiment of the present disclosure. [Figure 11C] Figure 11A shows an example table of an error correction system according to one embodiment of the present disclosure. [Figure 12]This is a schematic block diagram of an exemplary error correction mode and storage mode of a computational SSD system supporting semantic search using an error correction system, according to one embodiment of the present disclosure. [Figure 13] This is a schematic block diagram of another exemplary error correction mode and storage mode of a compute SSD system supporting semantic search using an error correction system, according to one embodiment of the present disclosure. [Figure 14] This flowchart shows a process for utilizing an exemplary error correction method in a computed SSD system supporting semantic search, according to one embodiment of the present disclosure. [Figure 15] This flowchart shows a process for utilizing an exemplary error correction method in a computed SSD system supporting semantic search, according to one embodiment of the present disclosure.

[0007] Corresponding reference letters indicate corresponding components across multiple figures in the drawings. Elements in multiple figures are shown for brevity and clarity and are not necessarily drawn to scale. For example, some dimensions of elements in the figures may be emphasized relative to others to facilitate understanding of the various embodiments of this disclosure. In addition, common but well-understood elements that are useful or necessary in commercially viable embodiments are often omitted to facilitate more unobstructed drawings of these various embodiments of this disclosure. [Modes for carrying out the invention]

[0008] In response to the aforementioned problems, this specification describes a device and method that enables semantic lookup on an SSD via a compute SSD system that distributes computation across each NAND flash die of the SSD, while simultaneously the SSD controller processes result aggregation using new die-based compute logic circuits to provide file semantic lookup on the device. Specifically, many embodiments utilize a compute SSD system that reads file feature vectors from multiple dies to the SSD controller. If there are millions of feature vectors to be compared, these feature vectors may be buffered in DRAM, and the controller processes the distance calculation. An AI / ML processing unit on a local die can, for example, perform computation and comparison operations and pass the processing score and results to the SSD controller. The SSD controller aggregates the results from all dies and returns the results to the host. In some embodiments, the feature vector store size of each die-based AI / ML processing unit may be configured as needed to suit different tasks and / or feature vector sizes. Based on this, the circuitry of the AI / ML processing units and several die-based AI / ML processing units may be configured and distributed as needed to provide increased computation speed or to satisfy specific die area constraints. Additional embodiments will be discussed in more detail below.

[0009] These solutions can help reduce the substantial waste of bandwidth and energy from data movement between the host processor, host memory, and storage devices. Furthermore, these solutions can help reduce the bottleneck in storage device controllers in AI / ML processing, as storage device controllers need to handle both I / O and computational operations in AI / ML operations that require reading feature vectors from multiple dies to the controller and buffering the feature vectors into memory to perform AI / ML computations and processing.

[0010] Aspects of the present disclosure may be embodied as an apparatus, system, method, or computer program product. Accordingly, aspects of the present disclosure may take the form of an entirely hardware embodiment, an entirely software embodiment (including firmware, resident software, microcode, etc.), or an embodiment combining software aspects and hardware aspects that are generally referred to herein as a "function", "module", "apparatus", or "system". Furthermore, aspects of the present disclosure may take the form of a computer program product embodied in one or more non-transitory computer-readable storage media storing computer-readable and / or executable program code. Many of the functional units described herein are labeled as functions in order to more specifically emphasize their implementation independence. For example, a function may be implemented as a hardware circuit comprising off-the-shelf semiconductors such as custom VLSI circuits or gate arrays, logic chips, transistors, or other discrete components. A function may also be implemented on a programmable hardware device via a field programmable gate array, programmable array logic, programmable logic device, or the like.

[0011] A function may also be implemented at least partially in software for execution by various types of processors. The identified executable code of a function may comprise, for example, one or more physical or logical blocks of computer instructions that may be organized as an object, procedure, or function. Nevertheless, the executable files of the identified function need not be physically located together and may include heterogeneous instructions stored at different locations, which, when logically combined together, constitute the function and achieve the defined purpose of the function.

[0012] In fact, the functionality of executable code can include a single instruction or many instructions and can even be distributed over multiple different code segments, between different programs, across multiple storage devices, etc. When a functionality or a part of a functionality is implemented in software, the software part can be stored on one or more computer-readable and / or executable storage media. Any combination of one or more computer-readable storage media can be utilized. A computer-readable storage media can include, for example, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing, but does not include propagated signals. In the context of this document, a computer-readable and / or computer-executable storage media may be a tangible and / or non-transitory media that can include or store a program used by or in relation to an instruction execution system, apparatus, processor, or device.

[0013] The computer program code for performing operations for aspects of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages such as Python, Java, Smalltalk, C++, C#, Objective C, conventional procedural programming languages such as the "C" programming language, scripting programming languages, and / or other similar programming languages. The program code may be executed, partially or entirely, on one or more users' computers and / or via a data network, etc., on a remote computer or server.

[0014] When used herein, a component constitutes a tangible, physical, and non-transient device. For example, a component may be implemented as a ready-made semiconductor and / or other mechanical or electrical device, such as a hardware logic circuit, logic chip, transistor, or other discrete device comprising a custom VLSI circuit, gate array, or other integrated circuit. A component may also be implemented as a programmable hardware device, such as a field-programmable gate array, programmable array logic, or programmable logic device. A component may comprise one or more silicon integrated circuit devices (e.g., chips, dies, die planes, packages) or other discrete electrical elements that communicate electrically with one or more other components via electrical wires on a printed circuit board (PCB), etc. Each of the functions and / or modules described herein may, in particular embodiments, be embodied by or implemented as a component.

[0015] A circuit, as used herein, includes a set of one or more electrical and / or electronic components that provide one or more paths for current. In certain embodiments, a circuit may include a return path for current so that the circuit is a closed loop. However, in other embodiments, a set of components that may not include a return path for current may be referred to as a circuit (e.g., an open loop). For example, an integrated circuit may be referred to as a circuit whether or not it is coupled to ground (as a return path for current). In various embodiments, a circuit may include a part of an integrated circuit, an integrated circuit, a set of integrated circuits, or a set of non-integrated electrical components and / or electrical components with or without integrated circuit devices. In one embodiment, a circuit may include a custom VLSI circuit, a gate array, a logic circuit, or other integrated circuits. It may be implemented as off-the-shelf semiconductors and / or other mechanical or electrical devices such as logic chips, transistors, or other discrete devices. A circuit may also be implemented as a synthesized circuit (e.g., as firmware, a netlist, etc.) within a programmable hardware device such as a field-programmable gate array, a programmable array logic, or a programmable logic device. The circuit may comprise one or more silicon integrated circuit devices (e.g., chips, dies, die planes, packages) or other discrete electrical elements that communicate electrically with one or more other components via electrical wires on a printed circuit board (PCB). Each of the functions and / or modules described herein may, in particular embodiments, be embodied by a circuit or implemented as a circuit.

[0016] Throughout this specification, references to “one embodiment,” “an embodiment,” or similar terms mean that certain features, structures, or characteristics described in relation to these embodiments are included in at least one embodiment of this disclosure. Therefore, throughout this specification, phrases such as “in one embodiment,” “in an embodiment,” and similar terms do not necessarily refer to the same embodiment, but may mean “one or more embodiments, but not all,” unless otherwise explicitly stated. The terms “including,” “comprising,” “having,” and variations thereof mean “including, but not limited to,” unless otherwise explicitly stated. Lists of items may not mean that any or all of the items are mutually exclusive and / or mutually exclusive, unless otherwise explicitly stated. “a,” “an,” and “the” also mean “one or more,” unless otherwise explicitly stated.

[0017] Furthermore, as used herein, references to reading, writing, storing, buffering, and / or transferring data may include all of the data, a portion of the data, a set of the data, and / or a subset of the data. Similarly, references to reading, writing, storing, buffering, and / or transferring non-hosted data may include all of the non-hosted data, a portion of the non-hosted data, a set of the non-hosted data, and / or a subset of the non-hosted data.

[0018] Finally, the terms “or” and “and / or” as used herein should be interpreted as inclusive or to mean any one or any combination thereof. Thus, “A, B or C” or “A, B and / or C” means any of “A, B, C, A and B, A and C, B and C, A, B and C.” An exception to this definition arises only if the combination of elements, functions, processes, or actions is in any way inherently mutually exclusive.

[0019] Aspects of the present disclosure are described below with reference to schematic flowcharts and / or schematic block diagrams of methods, apparatus, systems, and computer program products according to embodiments of the present disclosure. Each block in the schematic flowcharts and / or schematic block diagrams, and combinations of blocks in the schematic flowcharts and / or schematic block diagrams, are understood to be implementable by computer program instructions. These computer program instructions may be provided to a processor of a computer or other programmable data processing device to generate a machine such that instructions executed through the processor or other programmable data processing device create means for implementing the functions and / or operations specified in the blocks of the schematic flowcharts and / or schematic block diagrams.

[0020] Furthermore, it should be noted that in some alternative implementations, the functions shown within a block may occur in a different order than that shown in the diagram. For example, two consecutively shown blocks may be executed substantially in parallel, or they may be executed in reverse order depending on the functions they relate to. Other processes and methods may be conceived that are equivalent in terms of function, logic, or effect to one or more blocks or parts thereof shown in the diagram. Various types of arrows and lines may be employed in flowcharts and / or block diagrams, but they are understood not to limit the scope of the corresponding embodiments. For example, arrows may indicate waiting or monitoring periods of an unspecified duration between enumerated processes in the illustrated embodiment.

[0021] The following detailed description will refer to the accompanying drawings, which constitute part of it. The above-mentioned overview is illustrative only and is not intended to limit it in any way. In addition to the exemplary aspects, embodiments, and features described above, further aspects, embodiments, and features will be revealed by reference to the drawings and the following detailed description. The descriptions of elements in each figure may refer to elements in previous figures. The same number may refer to the same element in the figures, including alternative embodiments of the same element.

[0022] Referring to Figure 1, a schematic block diagram of an exemplary host computing device 110 having a storage system 102 suitable for a compute SSD system supporting semantic lookup according to one embodiment of the present disclosure is shown. The compute SSD system 100 comprises one or more storage devices 120 of the storage system 102 within the host computing device 110 communicating via a controller 126. The host computing device 110 may include a processor 111, volatile memory 112, and a communication interface 113. The processor 111 may include one or more central processing units, one or more general-purpose processors, one or more application-specific processors, one or more virtual processors (for example, the host computing device 110 may be a virtual machine running within the host), one or more processor cores, etc. The communication interface 113 may include one or more network interfaces configured to connect the controller 126 of the host computing device 110 and / or the storage device 120 to a communication network 115 such as an Internet Protocol (IP) network, a Storage Area Network (SAN), a wireless network, or a wired network.

[0023] The storage device 120 can be located in one or more different positions relative to the host computing device 110 in various embodiments. In one embodiment, the storage device 120 comprises one or more non-volatile memory devices 123, such as semiconductor chips or packages or other integrated circuit devices, disposed on one or more printed circuit boards, storage housings, and / or other mechanical and / or electrical support structures. For example, the storage device 120 may comprise one or more direct inline memory module (DIMM) cards, one or more expansion cards and / or daughter cards, solid-state drives (SSDs) or other hard drive devices, and / or have other memory and / or storage form factors. The storage device 120 may be integrated with and / or mounted on the motherboard of the host computing device 110, installed in ports and / or slots of the host computing device 110, installed on a dedicated storage appliance on a different host computing device 110 and / or network 115, communicate with the host computing device 110 via an external bus (e.g., an external hard drive), or the like.

[0024] In one embodiment, the storage device 120 can be located on the memory bus of the processor 111 (for example, on the same memory bus as the volatile memory 112, on a different memory bus from the volatile memory 112, or in place of the volatile memory 112). In a further embodiment, the storage device 120 can be located on a peripheral bus of the host computing device 110, such as an NVM Express (NVMe) interface, a serial Advanced Technology Attachment (SATA) bus, a parallel Advanced Technology Attachment (PATA) bus, a small computer system interface (SCSI) bus, a FireWire bus, a Fibre Channel connection, a Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, or a peripheral component interconnect express (PCI Express or PCIe) bus. In another embodiment, the storage device 120 may be located on a communication network 115 such as an Ethernet network, an InfiniBand network, SCSI RDMA on network 115, a storage area network (SAN), a local area network (LAN), a wide area network (WAN) such as the Internet, or another wired and / or wireless network 115.

[0025] The host computing device 110 may further comprise a computer-readable storage medium 114. The computer-readable storage medium 114 may comprise executable instructions configured to cause the host computing device 110 (e.g., a processor 111) to perform one or more steps of the methods disclosed herein. Additionally or alternatively, the buffering component 150 may be embodied as one or more computer-readable instructions stored on the computer-readable storage medium 114.

[0026] In certain embodiments, the device driver and / or controller 126 may present a logical address space 134 to the host client 116. As used herein, the logical address space 134 refers to a logical representation of a memory resource. The logical address space 134 may comprise a plurality of logical addresses (e.g., ranges). As used herein, a logical address refers to any identifier for referring to a memory resource (e.g., data), which may include, but is not limited to, a logical block address (LBA), cylinder / head / sector (CHS), file name, object identifier, universally unique identifier (UUID), globally unique identifier (GUID), hash code, signature, index entry, range, extent, etc.

[0027] The device driver for the storage device 120 may maintain metadata 135, such as a logical-to-physical address mapping structure, to map logical addresses in the logical address space 134 to media storage locations on the storage device 120. The device driver may be configured to provide storage services to one or more host clients 116. The host clients 116 may include local clients running on the host computing device 110, and / or remote clients 117 accessible via the network 115 and / or communication interface 113. The host clients 116 may include, but are not limited to, operating systems, file systems, database applications, server applications, kernel-level processes, user-level processes, applications, etc.

[0028] In many embodiments, the host computing device 110 may include a plurality of virtual machines that can be instantiated or otherwise created based on user requirements. As those skilled in the art will understand, the host computing device 110 may create a plurality of virtual machines configured as virtual hosts limited only to available computing resources and / or demand. A hypervisor may be available to create, run, and otherwise manage the plurality of virtual machines. Each virtual machine may include a plurality of virtual host clients, similar to the host client 116, which can store and access data using the storage system 102.

[0029] The device driver may be further communicatively coupled to one or more storage systems 102, which may include storage devices 120 of different types and configurations, including but not limited to solid-state storage devices, semiconductor storage devices, and SAN storage resources. Each of the one or more storage devices 120 may comprise one or more controllers 126 and non-volatile memory channels 122. The device driver may provide access to the one or more storage devices 120 via any compatible protocol or interface 133, such as but not limited to SATA and PCIe. Metadata 135 may be used to manage and / or track data operations performed via the protocol or interface 133. The logical address space 134 may contain multiple logical addresses, each corresponding to a media location of one or more storage devices 120. The device driver may maintain metadata 135 containing arbitrary-to-arbitrary mappings between logical addresses and media locations.

[0030] The device driver further includes and / or can communicate with a storage device interface 139 configured to transfer data, commands, and / or queries to one or more storage devices 120 via a bus 125 that may include, but is not limited to, the memory bus of the processor 111, a Peripheral Component Interconnect Express (PCI Express or PCIe) bus, a Serial Advanced Technology Attachment (ATA) bus, a Parallel ATA bus, a Small Computer System Interface (SCSI), FireWire, Fibre Channel, Universal Serial Bus (USB), a PCIe Advanced Switching (PCIe-AS) bus, a network 115, Infiniband, SCSI RDMA, etc. The storage device interface 139 can communicate with one or more storage devices 120 using input-output control (IO-CTL) commands, IO-CTL command extensions, remote direct memory access, etc.

[0031] The communication interface 113 may comprise one or more network interfaces configured to connect the host computing device 110 and / or the controller 126 to the network 115 and / or one or more remote clients 117 (which may function as other hosts). The controller 126 may be part of and / or communicate with one or more storage devices 120. Although Figure 1 shows a single storage device 120, the disclosure is not limited thereto and can be adapted to incorporate any number of storage devices 120.

[0032] The storage device 120 may include one or more non-volatile memory devices 123 in the non-volatile memory channel 122, the non-volatile memory devices 123 being, but not limited to, ReRAM, memristor memory, programmable metallization cell memory, phase-change memory (PCM, PCME, PRAM, PCRAM, ovonic unified memory, chalcogenide RAM, or C-RAM), NAND flash memory (e.g., 2D NAND flash memory, 3D NAND flash memory), NOR flash memory, nano random access memory (nano RAM or NRAM), nanocrystal wire-based memory, silicon oxide-based sub-10 nanometer process memory, graphene memory, silicon oxide nitride silicon oxide (SONOS), programmable metallization cell (PMC), conductive-bridging RAM (CBRAM), magnetoresistive RAM This may include RAM, MRAM, magnetic storage media (e.g., hard disks, tapes), optical storage media, etc. One or more non-volatile memory devices 123 of the non-volatile memory channel 122 may, in certain embodiments, include storage class memory (SCM) (e.g., write-in-place memory, etc.).

[0033] The non-volatile memory channel 122 may be referred to herein as a “memory medium,” but in various embodiments, the non-volatile memory channel 122 may comprise one or more non-volatile recording media capable of recording data, which may be more generally referred to as a non-volatile memory medium, a non-volatile memory device, etc. Furthermore, in various embodiments, the storage device 120 may include a non-volatile recording device, a non-volatile memory array 129, a plurality of interconnected storage devices within the array, etc.

[0034] The non-volatile memory channel 122 may include, but is not limited to, one or more non-volatile memory devices 123, such as chips, packages, planes, or dies. The controller 126 may be configured to manage data operations on the non-volatile memory channel 122 and may comprise one or more processors, programmable processors (e.g., FPGAs), ASICs, microcontrollers, etc. In some embodiments, the controller 126 may be configured to store data in the non-volatile memory channel 122 and / or read data from there, and transfer data to / from the storage device 120, etc.

[0035] The controller 126 may be communicatively coupled to the non-volatile memory channel 122 via a bus 127. The bus 127 may include an I / O bus for communicating data to and from the non-volatile memory device 123. The bus 127 may further include a control bus for communicating addressing and other command and control information to the non-volatile memory device 123. In some embodiments, the bus 127 may communicatively couple the non-volatile memory device 123 to the controller 126 in parallel. This parallel access may allow the non-volatile memory device 123 to be managed as a group and form a non-volatile memory array 129. The non-volatile memory device 123 may be divided into logical memory units (e.g., logical pages) and / or logical memory partitions (e.g., logical blocks). A logical memory unit may be formed by logically combining each physical memory unit of the non-volatile memory device 123.

[0036] In certain embodiments, the controller 126 may organize blocks of word lines in the non-volatile memory device 123 using the addresses of word lines so that the word lines can be logically organized into a monotonically increasing sequence (e.g., by decoding and / or converting the addresses of word lines into a monotonically increasing sequence). In further embodiments, the word lines of a block in the non-volatile memory device 123 may be physically arranged in a monotonically increasing sequence of word line addresses, and the contiguously addressed word lines are also physically adjacent (e.g., WL0, WL1, WL2, ..., WLN).

[0037] The controller 126 includes and / or can communicate with a device driver running on the host computing device 110. The device driver can provide storage services to the host client 116 via one or more interfaces 133. The device driver may further include a storage device interface 139 configured to transfer data, commands, and / or queries to the controller 126 via the bus 125, as described above.

[0038] Referring to Figure 2, a schematic block diagram of an exemplary storage device 120 suitable for a compute SSD system supporting semantic lookup according to one embodiment of the present disclosure is shown. The controller 126 may include a front-end module 208 that interfaces with a host via a plurality of high-priority and low-priority communication channels, a back-end module 210 that interfaces with a non-volatile memory device 123, and various other modules that perform various functions of the storage device 120. In some examples, each module may be merely a portion of memory with instructions that can be executed using a processor to implement the features of the corresponding module without the module including any other hardware. Each module may be interchangeably referred to as a hardware module because each module includes at least some hardware even when the included hardware includes software.

[0039] The controller 126 may include a buffer management / bus control module 214 that manages buffers in random access memory (RAM) 216 and controls internal bus arbitration for communication on the controller 126's internal communication bus 217. Read-only memory (ROM) 218 ​​can store and / or access system boot code. Although shown separately from the controller 126 in Figure 2, in other embodiments, one or both of the RAM 216 and ROM 218 may be located within the controller 126. In yet another embodiment, parts of the RAM 216 and ROM 218 may be located both within and outside the controller 126. Furthermore, in some implementations, the controller 126, RAM 216, and ROM 218 can be located on separate semiconductor dies. As described below, in one implementation, the submission queue and completion queue may be stored in a controller memory buffer that can be housed in the RAM 216.

[0040] Additionally, the front-end module 208 may include a host interface 220 and a physical layer interface 222 that provides an electrical interface with the host or a next-level storage controller. The choice of host interface 220 type may depend on the type of memory used. Exemplary types of host interface 220, but not limited to, include SATA, SATA Express, SAS, Fibre Channel, USB, PCIe, and NVMe. The host interface 220 can typically facilitate the transfer of data, control signals, and timing signals.

[0041] The backend module 210 may include an error correction engine 224 that encodes data bytes received from the host and decodes and error-corrects data bytes read from the non-volatile memory device 123 using an error-correction code (ECC). The backend module 210 may also include a command sequencer 226 that generates command sequences, such as program, read, and erase command sequences, to be sent to the non-volatile memory device 123. Additionally, the backend module 210 may include a Redundant Array of Independent Drive (RAID) module 228 that manages the generation of RAID parity and the recovery of failed data. RAID parity can be used as an additional level of integrity protection for data written to the storage device 120. In some cases, the RAID module 228 may be part of the error correction engine 224. The memory interface 230 provides command sequences to the non-volatile memory device 123 and receives status information from the non-volatile memory device 123. The command sequence and status information, along with the data programmed into the non-volatile memory device 123 and read from there, can be communicated via the memory interface 230. The flash control layer 232 can control the overall operation of the backend module 210.

[0042] The additional modules of the storage device 120 shown in Figure 2 may include a media management layer 238 that performs wear leveling of the memory cells of the non-volatile memory device 123. The storage device 120 may also include other discrete components 240, such as an external electrical interface, external RAM, registers, capacitors, or other components that can interface with the controller 126. In alternative embodiments, one or more of the RAID module 228, the media management layer 238, and the buffer management / bus control module 214 may be optional components that are not required in the controller 126.

[0043] Finally, the controller 126 may also comprise an intelligent memory array logic 234. In many embodiments, the intelligent memory array logic 234 may be configured to receive queries, extract contextual data from the received queries, and determine a machine learning model for processing the queries based on the extracted contextual data. The determination of a machine learning model for further processing the queries can be performed by the controller 126. In some embodiments, the controller 126 may determine one or more suitable machine learning models for further processing the queries. The intelligent memory array logic 234 may be provided by hardware, firmware, software, electrical circuits and / or components, or any combination thereof, to receive data (e.g., queries), perform machine learning processes, computations, comparisons, actions, or other operations to acquire and / or extract contextual data from the received queries to generate one or more query vectors, and then determine one or more suitable machine learning models for further processing the one or more query vectors. This may include accessing control data stored in storage device 120, scanning non-volatile memory device 123 for relevant pages, determining the relevant non-volatile memory device 123 associated with the generated query vector, and passing the query vector to one or more determined relevant non-volatile memory devices 123.

[0044] Each of the non-volatile memory devices 123 may contain feature data and feature vector stores associated with one or more machine learning models and processes. The feature data may be evenly distributed within each of the one or more non-volatile memory devices 123. In some embodiments, the non-volatile memory devices 123 may be grouped into multiple sets, each set of non-volatile memory devices 123 providing a specific machine learning model and executing a machine learning process based on that specific machine learning model. Furthermore, each set of non-volatile memory devices 123 may have the same or different feature data and feature vector stores. The controller 126 may then pass query vectors to one or more associated non-volatile memory devices 123.

[0045] Each of the non-volatile memory devices 123 in the memory array 129 may further include one or more machine learning processing units configured to process a query vector obtained from the controller 126 as a first input. Feature data within one or more non-volatile memory devices 123 may be used as a second input, and the query vector and feature data may be buffered in the memory device before processing by one or more machine learning processing units. For example, the first and second inputs may be processed to generate a comparison value. One or more non-volatile memory devices 123 may be grouped into one or more memory sets based on similarity in the machine learning processing units or similarity in the feature data. The controller 126 may obtain either a comparison value or output data as a result of processing the first and second inputs from one or more non-volatile memory devices 123. In some embodiments, one or more sets of non-volatile memory devices 123 may be grouped together based on a particular machine learning model or process, similarity in the machine learning processing units, or similarity in the feature data.

[0046] Referring to Figure 3, a conceptual diagram of pages of memory cells, organized, for example in a NAND configuration, that are sensed or programmed in parallel according to one embodiment of the present disclosure. Figure 3 conceptually shows a bank of NAND strings 350 in the non-volatile memory device 123 of Figure 1. A “page,” such as page 360, is a group of memory cells that can be sensed or programmed in parallel. This is achieved in the peripheral circuitry by the corresponding pages of a sense amplifier 310. The sensed results can be utilized in latches in the corresponding set of data latches 320. Each sense amplifier can be coupled to a NAND string, such as a NAND string 350, via a bit line 336. For example, page 360 ​​may be along a row and be sensed by a sense voltage applied to the control gate of the cell in the page, which is commonly connected to a word line WL3. Along each column, each memory cell, such as memory cell 311, may be accessible by a sense amplifier via the bit line 336. Data in the data latch 320 can be toggled in or out to the memory controller 126 via a data I / O bus 331.

[0047] The NAND string 350 may be a series of memory cells, such as memory cells 311, daisy-chained by their sources and drains, with each of its two ends forming a source terminal and a drain terminal, respectively. A pair of selection transistors S1, S2 can control the connection of the memory cell chain to an external source via the source and drain terminals of the NAND string, respectively. In the memory array, when the source selection transistor S1 is turned on, the source terminal is coupled to the source line 334. Similarly, when the drain selection transistor S2 is turned on, the drain terminal of the NAND string is coupled to the bit line 336 of the memory array. Each memory cell 311 in the chain acts to store charge. It has a charge storage element that stores a given amount of charge to represent an intended memory state. In many embodiments, a control gate in each memory cell can enable control over read and write operations. Often, the control gates of the corresponding memory cells in each row of a plurality of NAND strings may all be connected to the same word line (WL0, WL1, ... WLn342, etc.). Similarly, the control gates of the selection transistors S1 and S2 (accessed via selection lines 344SGS and SGD, respectively) provide control access to the NAND string via their source and drain terminals, respectively.

[0048] The exemplary memory device described above includes a physical page memory cell that stores single-bit data, but in most embodiments, each cell stores multi-bit data, and each physical page can have multiple data pages. Additionally, in further embodiments, a physical page can store one or more logical sectors of data. A host computing device 110 (see Figure 1), typically operating with a disk operating system, manages file storage by organizing file contents into units of logical sectors, which are typically one or more units of 512 bytes. In some embodiments, a physical page may have a 16kB memory cell sensed in parallel by a corresponding 16kB sense amplifier via a 16kB bit line. An exemplary logical sector allocated by the host has a data size of 2kB. Therefore, if each cell is configured to store 1 bit of data (SLC), a physical page can store eight sectors. In the case of MLC, TLC, and QLC, as well as other dense structures, each cell can store 2, 3, 4, or more bits of data, and each physical page can store 16, 32, 64, or more logical sectors, depending on the structure used. For feature vector size and allocation in a compute SSD system supporting semantic lookup, the machine learning processing unit of the non-volatile memory device 123 may be configured to adapt to different feature vector sizes. As an example, a media file (e.g., images, documents, videos, etc.) can be represented by any number of feature vectors. In some embodiments, the feature vector of a media file may have 128 to 1024 features, and the size of the feature vector may be 256B to 2KB. Then, in the case of a 16KB NAND flash page, reading the page yields 8 to 64 feature vectors.

[0049] One inherent difference between flash memory and other types of memory is that memory cells must be programmed from an erased state, which is associated with the absence of charge within the memory cell. This requires that the floating gate must first be emptied of charge before programming. Programming returns the desired amount of charge to the floating gate. It may not support removing some of the charge from the floating gate to transition from a more programmed state to a less programmed state. Therefore, new data cannot overwrite existing data and must be written to locations that have not been written to or have been erased previously. Furthermore, erasing all charge from the floating gate can often be quite time-consuming. Thus, erasing cell by cell, or even page by page, is cumbersome and inefficient. Therefore, in most embodiments, arrays of memory cells are often divided into numerous blocks. As is common in many flash-based memory systems, a block is a unit of erasure; that is, each block contains the minimum number of memory cells that can be erased in a single operation. This, coupled with the limited lifespan of memory cells in flash memory, increases the desire to limit the amount of erasure and programming that occurs within a storage device.

[0050] Referring to Figure 4, a schematic block diagram of an exemplary compute SSD system supporting semantic search according to one embodiment of the present disclosure is shown. As described above, the controller 426 includes an intelligent memory array logic 434 and a results aggregation unit 412. The controller 426 receives a semantic search query 401 and passes the query 401 to the intelligent memory array logic 434 for processing. In some embodiments, the controller 426 may receive data (e.g., a query) and perform machine learning processes, computations, comparisons, actions, or other processing to obtain and / or extract contextual data from the received query 401 and prepare the query 401 for the intelligent memory array logic 434. The content of the query 401 may include one or more texts, documents, images, audio, or other media. Upon receiving the query 401, the controller 426 processes the query 401 and extracts contextual data from the query 401. In addition to extracting context data from query 401, other relevant context information for constructing the context data may be obtained by comparing query 401 and / or the context data with one or more dictionaries, libraries, or databases, or a combination thereof. The relevant context information may be added to query 401 or the context data extracted from query 401 for further processing. Furthermore, the context information may be stored locally in controller 426, or it may be remotely accessible to controller 426 and intelligent memory array logic 434. Controller 426 passes the context data to intelligent memory array logic 434, which then determines a machine learning model for processing query 401 based on the context data provided by controller 426.

[0051] In some embodiments, the controller 426 may determine one or more suitable machine learning models or processes within the intelligent memory array logic 434 to further process the query 401. The intelligent memory array logic 434 can receive data (e.g., a query) and perform machine learning processes, computations, comparisons, actions, or other operations to obtain and / or extract contextual data from the received query 401.

[0052] The intelligent memory array logic 434 processes query 401 and / or context data from query 401 and generates a query vector 403 based on the received query 401, the context data from query 401, or a combination thereof. Furthermore, the query vector 403 may be generated partially or entirely based on a determined machine learning model. The intelligent memory array logic 434 can determine one or more associated non-volatile memory devices 423 or a set of non-volatile memory devices 423 for processing the generated query vector 403. The determination may be based on query 401, context data from query 401, relevant context information from query 401, or a determined machine learning model, or any combination thereof. The intelligent memory array logic 434 then passes the generated query vector 403 to one or more associated non-volatile memory devices 423.

[0053] As described above, each of the one or more non-volatile memory devices 423 comprises feature data and one or more machine learning processing units 421aa, 421ab, ... 421an, 421ba, 421bb, ... 421bn, 421na, 421nb, ... 421nn, etc. (hereinafter referred to as "machine learning processing units 421"), each machine learning processing unit 421 may include hardware, firmware, software, electrical circuits and / or components, or any combination thereof, for performing machine learning processes, calculations, comparisons, operations, or other operations to obtain results and / or values ​​based on inputs from the feature data stored in the non-volatile memory devices 423 and inputs provided by the intelligent memory array logic 434. Each of the one or more machine learning processing units 421 may be configured to process a passed query vector 403 as a first input and to utilize the stored feature data as a second input. One or more machine learning processing units 421 may then process the first and second inputs to generate results and / or values ​​(e.g., comparison values) as outputs 405 to the controller 426. The intelligent memory array logic 434 may add feature metadata to the output 405 for further processing by the controller 426.

[0054] In some embodiments, the query vector 403 and feature data may be buffered in a memory device before processing by one or more machine learning processing units 421. Furthermore, the feature data may be evenly distributed within one or more non-volatile memory devices 423. In some embodiments, each of the one or more non-volatile memory devices 423 may be grouped into one or more memory sets based on similarity in the machine learning processing units or similarity in the feature data.

[0055] The results aggregation unit 412 retrieves results and / or values ​​from all machine learning processing units 421 as output 405, performs machine learning processes, calculations, comparisons, operations, or other processing on output 405, and retrieves, collects, and presents the results from output 405 in a summarized, report-based or tabular format as results 470. Results 470 may be passed to host 110 for further processing.

[0056] Referring to Figure 5, a schematic block diagram of an exemplary machine learning processing unit of a compute SSD system supporting semantic search according to one embodiment of the present disclosure is shown. In some embodiments, the machine learning processing unit 421 may be configured to trade off area with speed, resulting in parallel processing with less hardware reuse or lower area efficiency when speed is limited. As an example, the machine learning processing unit 500 may be configured to be faster. The machine learning processing unit 500 may include hardware, firmware, software, electrical circuits and / or components, or any combination thereof, for performing machine learning processes, computations, comparisons, operations, or other operations. The machine learning processing unit 500 uses a query vector V q Module 571 determines the feature vector size, and two input vectors (e.g., V q , V f(i) One or more distance calculation units 573a...573n (hereinafter referred to as "distance calculation units 573") calculate the distance between (e.g., Euclidean / Hamming distance) and a query vector V by module 571 q The feature size extracted from is received, and for example, the number of distance comparisons is compared with the feature vector size, and all input feature vectors V f(i)... V f(i+n)By selecting the correct one as the final similarity score, it includes a control unit 574 that adapts to the variable feature vector size. Further, the machine learning processing unit 500 includes, for example, a module 575 having one or more machine learning operators, functions, or registers for executing machine learning processing that compares two distance inputs from the distance calculation unit 573 and outputs the smaller distance to a register. Then, the register of the module 575 can provide a result, score, or value to the non-volatile memory device 423 and / or the controller 426.

[0057] Referring to FIG. 6, a schematic block diagram of an exemplary machine learning processing unit of a computational SSD system that supports semantic search according to an embodiment of the present disclosure is shown. In some embodiments, the machine learning processing unit 421 may be configured to trade off speed for area, where the area is limited, resulting in hardware reuse or sequential processing at a lower speed. As an example, the machine learning processing unit 600 may be configured to be highly area-efficient. The machine learning processing unit 600 may include hardware, firmware, software, electrical circuits and / or components, or any combination thereof for performing machine learning processes, calculations, comparisons, operations, or other processing. The machine learning processing unit 600 includes a module 671 that determines the feature vector size of the query vector V q and a distance calculation unit 673 for calculating the distance (e.g., Euclidean / Hamming distance) between two input vectors (e.g., V q , V f ). The module 671 receives the feature size extracted from the query vector V q and, for example, compares the number of distance comparisons with the feature vector size and all input feature vectors V fThe control unit 674 adapts to a variable feature vector size by selecting the correct final similarity score. Furthermore, the machine learning processing unit 600 includes a module 675 having one or more machine learning operators, functions, or registers for performing machine learning processing, such as comparing two distance inputs from a distance calculation unit 673 and outputting the smaller distance to a register. The registers of module 675 can then provide results, scores, or values ​​to a non-volatile memory device 423 and / or controller 426.

[0058] Referring to Figure 7, a flowchart is shown illustrating a process 700 for utilizing an exemplary compute SSD system supporting semantic search according to one embodiment of the present disclosure. Process 700 can be initiated by receiving a query (block 710). In many embodiments, this occurs when a host or SSD controller receives a query for semantic search. In some embodiments, a user provides a semantic search request that is passed to the host or SSD controller. Accordingly, various embodiments of the controller may instruct multiple processes, such as a process within the controller 426 for a compute SSD system supporting semantic search (see Figure 4), to execute the semantic search process 700.

[0059] Process 700 can extract context data from the received query (block 715). In some embodiments, the context data may be obtained directly from the query. As described above, in some embodiments, context information related to the query may be obtained through other resources to help construct the context data for the query. Relevant context information for constructing the context data may be obtained by comparing the query and / or context data with one or more machine learning processes that have access to dictionaries, libraries, databases, or combinations thereof.

[0060] Process 700 can determine a machine learning model based on the extracted contextual data (block 720). As is known in the art, various machine learning models, such as convolutional neural networks (CNNs), computer vision, supervised learning, semi-supervised learning, unsupervised learning, reinforcement learning (RL), deep learning (DL), artificial neural networks (ANNs), computer vision, speech recognition, natural language processing, and machine translation, can be used, as desired, to extract and process features from queries.

[0061] Once a machine learning model is determined based on the extracted contextual data, process 700 can use the machine learning model to process the query (block 725). As an example, and not an exhaustive one, various features can be obtained from the machine learning model when processing the query, processed to create vectors, and prepared for machine learning processes such as similarity search.

[0062] Based on the received query and the features obtained from the determined machine learning model, process 700 can generate a query vector (block 730) and determine one or more associated non-volatile memory devices associated with the generated query vector (block 735). As described above, the non-volatile memory device 123 may be part of any suitable storage device 120 which may have various different types of memory devices. As an example, but not an limitation, the storage device may comprise multiple non-volatile NAND memory devices, including single-level cell NAND memory and quad-level cell NAND memory.

[0063] Process 700 can pass a query vector to one or more determined associated non-volatile memory devices (block 740). Process 700 can process the passed query vector as a first input (block 745) and utilize feature data on one or more associated non-volatile memory devices as a second input (block 750). As described above, one or more determined associated non-volatile memory devices have machine learning processing units for processing the query vector as a first input and feature data stored on one or more non-volatile memory devices as a second input.

[0064] Process 700 can process the first and second inputs to generate a comparison value (block 755). In certain embodiments, process 700 may utilize a hyperdimensional vector / vector symbol architecture to enable on-die computation without error correction codes (ECC). In this way, features can be stored as hyperdimensional vectors rather than dense feature vectors that may be noise-resistant.

[0065] Referring to Figure 8, a flowchart is shown illustrating a process 800 for utilizing an exemplary compute SSD system supporting semantic search according to one embodiment of the present disclosure. Process 800 can be initiated by processing a query using a machine learning model (block 810). In many embodiments, this occurs when a host or SSD controller receives a query for semantic search. In some embodiments, a user provides a semantic search request that can be passed to the host or SSD controller. Accordingly, various embodiments of the controller can instruct multiple processes, such as a process within the controller 426 for a compute SSD system supporting semantic search (see Figure 4), to execute the semantic search process 800.

[0066] Process 800 can generate a query vector (block 815). When generating the query vector, contextual data can be obtained directly from the query and the processing of the query by the machine learning model. For example, when processing a query, various features can be obtained from the machine learning model, processed to create a vector, and prepared for machine learning processes such as similarity search. As is known in the art, various machine learning models, such as convolutional neural networks (CNNs), computer vision, supervised learning, semi-supervised learning, unsupervised learning, reinforcement learning (RL), deep learning (DL), artificial neural networks (ANNs), computer vision, speech recognition, natural language processing, and machine translation, can be used to extract and process features from a query.

[0067] Process 800 can pass a query vector to one or more machine learning processing units as a first unit (block 820), which further utilize feature data stored on one or more associated non-volatile memory devices as a second input (block 825). Process 800 can use one or more machine learning processing units to process the first and second inputs and determine output data to be retrieved from one or more non-volatile memory devices (block 830). Process 800 can use intelligent memory array logic to assign feature metadata to the output data (block 835). In certain embodiments, process 800 may utilize a hyperdimensional vector / vector symbol architecture to enable on-die computation without error correction code (ECC). In this way, features can be stored as hyperdimensional vectors rather than dense feature vectors that may be noise-resistant.

[0068] Referring to Figures 7 and 8, hyperdimensional computation for calculating similarity between data can be achieved by, for example, three operations including addition, multiplication, and substitution. Hyperdimensional computing can be inherently robust because information is evenly distributed across all bits of a hypervector, providing fast learning capabilities, high energy efficiency, and acceptable accuracy in learning and classification tasks.

[0069] Referring to Figure 9, a schematic block diagram of an exemplary machine learning process according to one embodiment of the present disclosure is shown. As shown, the input for the machine learning system 900 may include a semantic search request by one or more queries 901. The queries 901 may include text, images, documents, audio, or other media. The queries 901 may be passed to an intelligent memory array logic 934 that performs machine learning processes, computations, comparisons, actions, or other operations to obtain and / or extract contextual data from the received queries 901. The intelligent memory array logic 934 determines the contextual data from the queries 901 and assigns features to the queries 901 to form a query vector 903 as a first input for the machine learning processing unit (MPLU) 921 of the machine learning system 900.

[0070] The second input to the machine learning system 900 includes data stored on an SSD device, such as one or more media files 902. The media files 902 may include text, images, documents, audio, or other media. The stored media files 902 may be assigned feature data 904 by the intelligent memory array logic 934, and each media file 902 may be stored on one or more non-volatile memory devices 123. The feature data 904 can be scanned from one or more non-volatile memory devices 123 by the MPLU 921 as a second input for comparison with a query vector 903.

[0071] The MPLU 921 obtains output data 905 by following an iterative process of retrieving, extracting, calculating, and comparing feature data 904 from the stored media file 902 with a query vector 903. The output data 905 can be provided as a result of one or more operations by the MPLU 921. In some embodiments, the output data 905 may be a similarity score of a comparison between the query vector 903 and one or more sets of feature data 904. The output data 905 can then be passed to the controller 126 for further processing.

[0072] In some embodiments, the controller 426 may determine one or more suitable machine learning models or processes within the intelligent memory array logic 934 to further process the query 401. The intelligent memory array logic 934 can receive data (e.g., a query) and perform machine learning processes, computations, comparisons, operations, or other operations to obtain and / or extract contextual data from the received query 901.

[0073] As described above, each machine learning processing unit 921 may include hardware, firmware, software, electrical circuits and / or components, or any combination thereof, for performing machine learning processes, calculations, comparisons, operations, or other operations to obtain results and / or values ​​based on inputs from feature data stored on the non-volatile memory device 123 and inputs provided by the intelligent memory array logic 934.

[0074] In some embodiments, the query vector 903 and feature data 904 may be buffered in a memory device before processing by one or more machine learning processing units 921. Furthermore, the feature data 904 may be evenly distributed within one or more non-volatile memory devices 123. In some embodiments, each of the one or more non-volatile memory devices 123 may be grouped into one or more memory sets based on similarity in the machine learning processing units or similarity in the feature data.

[0075] Referring to Figure 10A, a schematic block diagram of an exemplary error correction system according to one embodiment of the present disclosure is shown. An error correction system 1000 for integrating ECC functionality for encoding and decoding dense feature vectors is shown.

[0076] An exemplary error correction system 1000 may include a host 1010, an SSD controller 1026, a NAND flash memory array 1029, and volatile memory 1016 (e.g., DRAM). The error correction system 1000 may further include a host interface 1020, an embedded processor 1011, an ECC memory module 1024 having at least one encoding circuit 1024a and a decoding circuit 1024b and processing, and a flash interface 1032 that is partially or entirely included with, or otherwise communicates with, or is integrated into, the SSD controller 1026. The embedded processor 1011 can communicate with the volatile memory 1016. The volatile memory 1016 may be integrated within the SSD controller 1026 and / or communicate with the embedded processor 1011.

[0077] The NAND flash memory array 1029 may include a plurality of NAND dies 1023, each NAND die having memory circuitry and logic 1027, including an ECC memory module 1028 and a machine learning processing unit 1021. In some embodiments, the exemplary error correction system 1000 can operate in storage mode, in which the SSD controller 1026 receives file data and one or more instructions from the host 1010 and stores the data on the NAND die 1023. Furthermore, in storage mode, the SSD controller 1026 may receive one or more instructions from the host 1010 to access the same or different file data stored on the NAND die 1023. As shown, in a write operation, the ECC memory module 1024 can encode error correction codes within the file data to facilitate the storage, retrieval, and processing of error-free file data on the NAND die 1023. Furthermore, in order to retrieve error-free file data for transmission to the host 1010, during the read operation, the ECC memory module 1024 may process and / or remove file data errors received from the file data stored on the NAND die 1023 using an encoded error correction code for the file data. In some embodiments, file data errors in storage mode may be introduced, for example, in the flash interface 1032, or at any file data processing stage within the SSD controller 1026 from the reception of file data and / or instructions by the host 1010 to the storage of file data and / or instructions on the NAND flash memory array 1029.

[0078] In some embodiments, the exemplary error correction system 1000 can operate in a compute mode in which the NAND flash memory array 1029 utilizes memory circuitry and logic 1027 having an ECC memory module 1028 to encode, decode, and verify error-free feature data (e.g., dense feature vectors) and provide it to a machine learning processing unit 1021 for comparison with a query vector to obtain a score. Thus, each NAND die 1023 includes ECC functionality for encoding and decoding feature data error correction codes to provide error-free feature data or error-free dense feature vectors. Thus, the NAND die 1023 stores at least two types of data, namely, raw file data and feature data (e.g., feature vectors) corresponding to the file. The memory circuitry and logic 1027 can perform feature data management to maximize feature data processing efficiency, e.g., parallel processing of feature data and on the die. In some embodiments, the memory circuits and logic 1027, as well as the machine learning processing units 1021 located on each NAND die 1023, may also be distributed across the NAND flash memory array 1029 as a single unit for each NAND die 1023 to process the file data and feature data stored on the corresponding NAND die 1023. Furthermore, in some embodiments, the feature data may be evenly divided and distributed across each NAND die 1023 of the NAND flash memory array 1029. In addition, the feature vectors may be rearranged within the same NAND die 1023 during storage management operations, such as garbage collection.

[0079] Figure 10B is a chart of an exemplary error correction system of Figure 10A according to one embodiment of the present disclosure. To ensure data integrity, data scrubbing can be performed on feature vectors (e.g., using FV scrubbing) and file data (e.g., using conventional data scrubbing). As shown, the number of bit flips per unit time for FV data scrubbing on feature data may be higher than that for conventional data scrubbing on file data, or a fraction of the frequency of conventional data scrubbing, e.g., 1 / 6, 1 / 4, 1 / 3, 1 / 2, 2 / 3 of the conventional scrubbing time. Furthermore, FV scrubbing and conventional scrubbing may be triggered when a predetermined threshold for bit flipping is reached. For example, FV scrubbing may be performed when the FV threshold is reached, and conventional scrubbing may be performed when the conventional threshold is reached. In some embodiments, a combination of time / frequency and threshold may be used to perform at least one of FV scrubbing or conventional scrubbing. As shown, FV data scrubbing can be performed in two-thirds the time of traditional file data scrubbing.

[0080] Figure 10C is a table of the exemplary error correction system of Figure 10A according to one embodiment of the present disclosure. Error correction of file data and feature data is shown above. File data and feature data may also undergo data scrubbing to reduce the possibility that a single correctable error may accumulate into a large number of uncorrectable errors. As shown, an error correction engine may be used to verify file data, and conventional data scrubbing may be used for wear leveling to maintain data integrity of file data in storage mode. Conventional data scrubbing may include error correction techniques that use one or more background tasks to periodically check main memory or storage for errors, and then correct any errors found using redundant data in the form of different checksums or copies of data. File data is cleansed through a process of detecting and correcting corrupted or inaccurate records from a recordset, table, or database, identifying incomplete, incorrect, inaccurate, or irrelevant portions of data, and then replacing, correcting, or deleting the incorrect, corrupted, or coarse data.

[0081] As an example, if the exemplary error correction system 1000 is in computation mode for feature vector data (e.g., dense feature vectors), on-die ECC is required. In some embodiments, weaker ECCs, such as Bose Chaudhuri Hocquenghem (BCH), may be used to reduce the area and latency overhead of the on-die ECC. In some embodiments, other types of on-die ECCs, such as Low Density Parity Check (LDPC), may be used. Furthermore, on-die ECCs may also be used for file data error correction. In some embodiments, feature vector data (e.g., dense feature vectors) may be stored in their own separate memory block from the file data to facilitate easier data management. In some embodiments, feature vector data (e.g., dense feature vectors) may be stored together with the associated file data in the same memory block to facilitate faster computation time and data access. File data can be scrubbed using the conventional data scrubbing methods described above, while feature data can be cleaned up using a separate data scrubbing algorithm to remove, for example, incorrect, wrong, incomplete, empty, or duplicate feature vector data.

[0082] In some embodiments, when the SSD storage device 120 is operating in semantic search mode, requests from the host 1010 to service read / write requests may be ignored, delayed, and executed after some semantic search operations have been completed, or queued to be executed after all semantic search operations have been completed, or any combination thereof. Thus, volatile memory 1016 may be used to load feature data related to data management data structures rather than logical-to-physical (L2P) tables for file data access.

[0083] With regard to feature vector data management, the application needs to maintain at least one database within the SSD storage device 120 to perform high-speed semantic searches. For example, the database may include file names, hash values, and attributes of the feature vector data. Furthermore, at least one file may contain attribute file names and hash values ​​that are loaded into the application when the application is started. In some embodiments, the hash value and feature vector data information may be contained in one or more data structures (e.g., Table X) to index one or more feature vectors. In some embodiments, Table X may be stored in the SSD storage device 120 firmware, and Table X may include Addr, hash values, and attributes of the feature vector data. Furthermore, according to the hash value returned from the semantic search, the application can retrieve file names from the search results. In some embodiments, the size of Table X may be proportional to the number of files stored in the SSD storage device 120. Furthermore, in some embodiments, Addr may be in the form [Die,Plane,Block,Page,Segment], where the number of bits represents the Segment.

[0084]

number

[0085] In some embodiments, the hash value feature vector may be a concatenation of the hash value and its feature vector to simplify data management. Furthermore, when the SSD storage device 120 receives a search request (e.g., a query), the SSD controller 1026 needs to generate special search commands and send them to each NAND flash die 1023. The SSD controller 1026 can inform the NAND flash die 1023 which blocks contain feature vector data, and the NAND flash die 1023 should perform calculations accordingly. Furthermore, each NAND flash die 1023 can execute the function top_k hashvalue=Loop(search(query_vec,plane#,block#,last_page#,last segment#)).

[0086] Figure 11A is a schematic block diagram of an exemplary error correction system according to one embodiment of the present disclosure. As shown, the error correction system 1100 integrates ECC functionality for encoding and decoding hyper-dimensional vectors (HDV) or vector symbolic architectures (VSA), where on-die ECC may be optional. In the present disclosure, HDV and VSA may be used interchangeably, but HDV will be used below. In some embodiments, integrating ECC logic, circuitry, or processing within each NAND die 1123 may be too costly. For example, incorporating an ECC memory module 1128 into each NAND die 1123 may be prohibitively expensive or may occupy too much space on the NAND flash memory array 1129. Instead, the HDV / VSA may be stored for each file, such context / semantic representations may be robust to noise, maintain similarity, be read from the NAND flash die 1123, and computed without error correction.

[0087] An exemplary error correction system 1100 may include a host 1110, an SSD controller 1126, a NAND flash memory array 1129, and volatile memory 1116 (e.g., DRAM). The error correction system 1100 may further include a host interface 1120, an embedded processor 1111, an ECC memory module 1124 having at least one encoding circuit 1124a and a decoding circuit 1124b and processing, and a flash interface 1132 that is partially or entirely included with the SSD controller 1126, or otherwise communicates with or is integrated therein. The embedded processor 1111 can communicate with the volatile memory 1116. The volatile memory 1116 may be integrated within the SSD controller 1126 and / or communicate with the embedded processor 1111.

[0088] The NAND flash memory array 1129 may include a plurality of NAND dies 1123, each NAND die having memory circuitry and logic 1127, including a machine learning processing unit 1121. In some embodiments, the exemplary error correction system 1100 can operate in storage mode, where the SSD controller 1126 receives file data and one or more instructions from the host 1110 and stores the data on the NAND dies 1123. Furthermore, in storage mode, the SSD controller 1126 may receive one or more instructions from the host 1110 to access the same or different file data stored on the NAND dies 1123. As shown, in a write operation, the ECC memory module 1124 can encode error correction codes within the file data to facilitate the storage, retrieval, and processing of error-free file data on the NAND dies 1123. Furthermore, in order to retrieve error-free file data for transmission to the host 1110, during the read operation, the ECC memory module 1124 may process and / or remove file data errors received from the file data stored on the NAND die 1123 using an encoded error correction code for the file data. In some embodiments, file data errors in storage mode may be introduced, for example, in the flash interface 1132, or at any file data processing stage in the SSD controller 1126 from the reception of file data and / or instructions by the host 1110 to the storage of file data and / or instructions on the NAND flash memory array 1129.

[0089] In some embodiments, the exemplary error correction system 1100 can operate in a computation mode in which the NAND flash memory array 1129 utilizes the memory circuitry and logic 1127 of the SSD controller 1126 and the ECC memory module 1128 to encode, decode, and verify error-free feature data (e.g., HDV / VSA vectors) and provide it to the machine learning processing unit 1121 to obtain a score by comparing it with a query vector. Each NAND die 1123 encodes and decodes feature data error correction codes using two copies of the HDV vector, the ECC functionality from the ECC memory module 1128, and the exemplary error correction scheme described below to provide error-free feature data, e.g., error-free HDV vectors.

[0090] In an exemplary error correction system 1100, the NAND die 1123 stores at least two types of data: raw file data and HDV / VSA vectors. Feature data corresponding to the file data (e.g., HDV vectors) can be highly robust to noise, maintain similarity, be read from the NAND die 1123, and computed without error correction. In some embodiments, two copies of the HDV vectors can be stored in each NAND die 1123 corresponding to the file data. The first copy is an HDV without ECC coding, and the second copy is an HDV with SSD controller 1026 ECC coding. As shown, the first copy of the HDV vectors without ECC coding can be used by the machine learning processing unit 1121. However, because there is an upper limit to its resilience, the blocks storing the HDV vectors also need to be wear-leveled.

[0091] A second copy of the HDV vector with ECC coding may be used to correct errors in the first copy of the HDV vector. If the scrubbing algorithm finds that the bit error rate of the HDV copy with ECC coding exceeds a predetermined threshold, the corrected HDV without ECC coding may be stored on the memory circuit and logic 1127, and the HDV copy with ECC coding may be relocated on the memory circuit and logic 1127. In some embodiments, depending on the application, if the VSA vector is very long and ultra-robust, a separate scrubbing algorithm for the second copy of the HDV vector with ECC coding may not be required; otherwise, a separate scrubbing algorithm can be implemented for the HDV vector with ECC coding.

[0092] The memory circuitry and logic 1127 can perform feature data management to maximize feature data processing efficiency, such as parallel processing of feature data and on the die. In some embodiments, the memory circuitry and logic 1127 can also be distributed within the NAND flash memory array 1129 as a single unit for each NAND die 1123 to process file data and HDV vector data stored on the corresponding NAND die 1123. Furthermore, in some embodiments, the feature data may be evenly divided and distributed across each NAND die 1123 of the NAND flash memory array 1129. In addition, the feature vector data can be rearranged within the same NAND die 1123 during storage management operations, such as garbage collection.

[0093] Figure 11B is a chart of an exemplary error correction system of Figure 11A according to one embodiment of the present disclosure. To ensure data integrity, data scrubbing can be performed on HDV vectors (e.g., using HDV scrubbing) and file data (e.g., using conventional data scrubbing). As shown, the number of bit flips per unit time for HDV data scrubbing on feature data may be higher than that for conventional data scrubbing on file data, or a fraction of the frequency of conventional data scrubbing, e.g., 1 / 6, 1 / 4, 1 / 3, 1 / 2, 2 / 3 of the conventional scrubbing time. Furthermore, HDV scrubbing and conventional scrubbing may be triggered when a predetermined threshold for bit flipping is reached. For example, HDV scrubbing may be performed when the HDV threshold is reached, and conventional scrubbing may be performed when the conventional threshold is reached. In some embodiments, a combination of time / frequency and threshold may be used to perform at least one of HDV scrubbing or conventional scrubbing. As shown, HDV data scrubbing can be performed in two-thirds the time of traditional file data scrubbing.

[0094] Figure 11C is a table of the exemplary error correction system of Figure 11A according to one embodiment of the present disclosure. Error correction of file data and feature data is shown above. File data and feature data may also undergo data scrubbing to reduce the possibility that a single correctable error may accumulate into a large number of uncorrectable errors. As shown, the ECC of the SSD controller 1126 may be used to verify file data, and conventional data scrubbing, such as low-density parity checking (LDPC) for wear leveling to maintain data integrity of file data in storage mode, may be used. Conventional data scrubbing may include error correction techniques that use one or more background tasks to periodically check main memory or storage for errors, and then correct any errors found using redundant data in the form of different checksums or copies of data. File data may be purified through a process of detecting and correcting corrupted or inaccurate records from a recordset, table, or database, identifying incomplete, incorrect, inaccurate, or irrelevant portions of data, and then replacing, correcting, or deleting the incorrect, corrupted, or coarse data.

[0095] For example, when the exemplary error correction system 1100 is in computation mode, conventional data scrubbing may not be required for the first copy of the HDV vector (i.e., HDV, HDV vector without ECC coding). In some embodiments, conventional data scrubbing may be used as needed for the first copy of the HDV vector to maintain data integrity of the feature data of the first copy of the HDV vector without ECC coding. Furthermore, in computation mode, the ECC of the SSD controller 1126 may be used, for example, with low-density parity check (LDPC) to verify the feature data of the second copy of the HDV vector (i.e., HDV-COPY, HDV vector with ECC coding). In addition, at least one of conventional data scrubbing or HDV scrubbing using a feature data scrubbing algorithm may be used, for example, to clean up incorrect, incorrect, incomplete, empty, or duplicate feature vector data.

[0096] In some embodiments, when the SSD storage device 120 is operating in semantic search mode, requests from the host 1110 to service read / write requests may be ignored, delayed, and executed after some semantic search operations have been completed, or queued to be executed after all semantic search operations have been completed, or any combination thereof. Thus, volatile memory 1116 may be used to load feature data related to data management data structures rather than logical-to-physical (L2P) tables for file data access. Furthermore, HDV vector data management may be performed as described above.

[0097] In some embodiments, the hash value feature vector may be a concatenation of the hash value and its feature vector to simplify data management. Furthermore, when the SSD storage device 120 receives a search request (e.g., a query), the SSD controller 1126 needs to generate special search commands and send them to each NAND flash die 1123. The SSD controller 1126 can inform the NAND flash die 1123 which blocks contain feature vector data, and the NAND flash die 1123 should perform calculations accordingly. Furthermore, each NAND flash die 1123 can execute the function top_k hashvalue=Loop(search(query_vec,plane#,block#,last_page#,last segment#)).

[0098] Figure 12 is a schematic block diagram of exemplary error correction mode and storage mode of a compute SSD system 1200 supporting semantic lookup with an error correction system according to one embodiment of the present disclosure. As shown, the exemplary compute SSD system 1200 supports semantic lookup in compute mode and raw file data processing in storage mode, with host 1210 providing the respective instructions and file data or feature data to SSD storage device 1220. In some embodiments, if non-volatile memory 1316 is limited, SSD storage device 1320 can switch between compute mode and storage mode to achieve retrieval of the result file. Furthermore, requests from host 1310 to service read / write requests may be ignored, delayed and executed after some semantic lookup operations are completed, or queued to be executed after all semantic lookup operations are completed, or any combination thereof. Thus, volatile memory 1116 may be used to load feature data related to data management data structures rather than logical-to-physical (L2P) tables for file data access.

[0099] Step 1: In computation mode, non-volatile memory 1216 (e.g., DRAM) may be used by table X, query 1201 is sent to SSD storage device 1220 for processing (e.g., machine learning processing unit 1021 / 1121), and then the result or hash 1203 may be returned to host 1210 for semantic search request.

[0100] Step 2: In memory mode, non-volatile memory 1216 (e.g., DRAM) may be used for L2P table mapping, data requests 1205 are sent to SSD storage device 1220 (e.g., by SSD controller 1026 / 1126) and processed, and then file data 1207 may be returned to host 1210 for file search / read / write / access requests.

[0101] Figure 13 is a schematic block diagram of another exemplary error correction mode and storage mode of a compute SSD system 1300 supporting semantic search using an error correction system, according to one embodiment of the present disclosure. In some embodiments, if the non-volatile memory 1316 is sufficient for both the storage mode and the compute mode, the storage and compute operations can be performed simultaneously or in parallel without requiring separate modes.

[0102] For example, non-volatile memory 1316 (e.g., DRAM) may be used by table X, query 1301 may be sent to SSD storage device 1320 and processed (e.g., by machine learning processing unit 1021 / 1121), and then the result or hash 1303 may be returned to host 1310 for semantic search requests. Furthermore, in parallel, non-volatile memory 1316 (e.g., DRAM) may be used for L2P table mapping, data request 1305 may be sent to SSD storage device 1320 and processed (e.g., by SSD controller 1026 / 1126), and then file data 1307 may be returned to host 1310 for file search / read / write / access requests. Furthermore, in some embodiments, if a hyperscale or storage array is used, semantic search and file data may be performed in parallel, and file data may be retrieved from conventional SSDs using file replicas from SSD storage device 1320.

[0103] Referring to Figure 14, a flowchart is shown illustrating a process 1400 for utilizing an exemplary error correction method in a computed SSD system supporting semantic search according to one embodiment of the present disclosure. Process 1400 can be initiated by storing raw file data in one or more memory structures (block 1410). Process 1400 can store feature data corresponding to the raw file data in one or more corresponding memory structures (block 1415). Process 1400 can load feature data from at least one of the one or more memory structures, the feature data including at least one of dense feature vectors or hyperdimensional vectors (block 1420). Process 1400 can generate one or more databases from the feature data (block 1425). Process 1400 can load raw file data from at least one of the one or more memory structures (block 1430). Process 1400 can store feature data and utilize an error correction algorithm for accessing the feature data (block 1435).

[0104] Referring to Figure 15, a flowchart is shown illustrating a process 1500 for utilizing an exemplary error correction method in a computed SSD system supporting semantic search according to one embodiment of the present disclosure. Process 1500 can be initiated by processing a query to retrieve raw file data stored on one or more memory structures using a machine learning model (block 1510). Process 1500 can generate one or more databases from feature data stored in one or more memory structures, the feature data comprising at least one of dense feature vectors or hyperdimensional vectors (block 1515). Process 1500 can load one or more databases and raw file data from one or more memory structures (block 1525). Process 1500 can process the raw file data and one or more databases to obtain a response to a query (block 1525).

[0105] The information presented and described in detail herein can fully achieve the aforementioned objectives of this disclosure and the current preferred embodiments thereof, and thus represent the subject matter broadly contemplated by this disclosure. The scope of this disclosure fully encompasses other embodiments which may be apparent to those skilled in the art and should therefore not be limited by anything other than the appended claims. Any reference to an element made in the singular is intended to mean "one or more" rather than "one and only" unless expressly stated so. All structural and functional equivalents to the elements of the above preferred embodiments and additional embodiments which may be conceivable to those skilled in the art are expressly incorporated herein by reference and are intended to be encompassed by the claims.

[0106] Furthermore, there are no requirements that the system or method address every possible problem that needs to be resolved by this disclosure, and solutions to such problems are covered by the claims. Moreover, the elements, components, or process steps in this disclosure, whether or not they are expressly described in the claims, are not intended for the public. As may be apparent to those skilled in the art, various changes and modifications to the form, materials, workpieces, and details of the manufacturing materials can be made without departing from the spirit and scope of this disclosure as described in the appended claims, and these are also covered by this disclosure.

Claims

1. It is a device, Processor and A memory array comprising multiple memory devices, The memory array comprises a controller that is communicatively coupled to the memory array, The plurality of memory devices are configured to store raw file data and feature data corresponding to the raw file data. The aforementioned feature data includes dense feature vectors, Each of the plurality of memory devices provides error-free feature data by storing the feature data and using an error correction algorithm for accessing the feature data. Each of the aforementioned plurality of memory devices comprises one or more machine learning processing units, The controller generates a query vector from the received query using a machine learning model, The device comprises one or more machine learning processing units that perform distance comparisons with the query vectors for the provided feature data and determine feature data with smaller distances.

2. The device according to claim 1, wherein the dense feature vector is stored in a block separate from the raw file data.

3. A device, Processor and A memory array comprising multiple memory devices, The memory array comprises a controller that is communicatively coupled to the memory array, The plurality of memory devices are configured to store raw file data and feature data corresponding to the raw file data. The aforementioned feature data includes a hyperdimensional vector, Each of the plurality of memory devices stores at least two copies of the hyperdimensional vector, the first copy of the hyperdimensional vector being stored without the use of an error correction algorithm, and the second copy being stored using an error correction algorithm and used to correct errors in the first copy, thereby each of the plurality of memory devices providing error-free feature data with the errors in the first copy corrected. Each of the aforementioned plurality of memory devices comprises one or more machine learning processing units, The controller generates a query vector from the received query using a machine learning model, The device comprises one or more machine learning processing units that perform distance comparisons with the query vectors for the provided feature data and determine feature data with smaller distances.

4. The device according to any one of claims 1 to 3, wherein the feature data is evenly distributed within each of the plurality of memory devices.

5. The device according to any one of claims 1 to 3, wherein the error correction algorithm is implemented as an on-die error correction code (ECC), and each of the plurality of memory devices has an ECC.

6. A processor and A memory array comprising multiple memory devices, A method performed by a device comprising a controller communicatively coupled to the memory array, The plurality of memory devices store raw file data and feature data corresponding to the raw file data, Loading feature data containing dense feature vectors from at least one of the aforementioned plurality of memory devices, A method comprising providing error-free feature data by storing the aforementioned feature data and using an error correction algorithm for accessing the aforementioned feature data.

7. The method according to claim 6, wherein storing feature data includes storing the dense feature vectors in a block separate from the raw file data.

8. A processor, A memory array comprising multiple memory devices, A method performed by a device comprising a controller communicatively coupled to the memory array, The plurality of memory devices store raw file data and feature data corresponding to the raw file data, This includes loading feature data, including a hyperdimensional vector, from at least one of the aforementioned plurality of memory devices, A method comprising storing at least two copies of the hyperdimensional vector in each of the plurality of memory devices, wherein a first copy of the hyperdimensional vector is stored without the use of an error correction algorithm, and a second copy is stored using an error correction algorithm and is used to correct errors in the first copy, thereby providing error-free feature data with the errors in the first copy corrected.

9. The method according to any one of claims 6 to 8, further comprising distributing the feature data evenly within each of the plurality of memory devices.

10. The method according to any one of claims 6 to 8, wherein the error correction algorithm is implemented as an on-die error correction code (ECC), and each of the plurality of memory devices has an ECC.

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