Switch Assembly

Abstract

1. An integrated switch assembly having a stacked configuration, comprising: a first layer including a photonic integrated circuit, a PIC; and a second layer including a switch ASIC, the first layer being attached to a substrate and the second layer being attached on top of the first layer.

Description

Technical Field

[0001] One or more aspects of embodiments according to the present invention relate to a monolithic switch assembly having a stacked configuration, and more particularly to a monolithic switch assembly having a stacked configuration, the monolithic switch assembly comprising a photonic integrated circuit PIC and a switch ASIC mounted on top of the PIC.

Background Art

[0002] Monolithic photonic platforms are known and are often the key to mass production of photonic products. Typically, an integrated or co-packaged concept includes photonic inputs / outputs disposed around a digital ASIC. Photonic components such as modulators and photodiodes are also typically disposed around the ASIC, and drivers for any of these components are either disposed within the digital ASIC or integrated into a photonic integrated chip disposed around the ASIC. A problem with such an arrangement is that fairly long lengths of high-speed traces (on the order of mm or cm) are often required to connect components within the digital ASIC to the optical inputs / outputs. An object of some embodiments of the present invention is to reduce the need for high-speed traces to be long lengths in a monolithic platform.

Summary of the Invention

[0003] Therefore, some embodiments of the present invention aim to solve the above problems by providing a monolithic switch assembly having a stacked configuration, the monolithic switch assembly comprising a first layer, the first layer including a photonic integrated circuit PIC, a second layer, the second layer including a switch ASIC, wherein the first layer is mounted on a substrate and the second layer is mounted on top of the first layer.

[0004] The resulting stack assembly is a 3D assembly. Typically, the board can include one of the following: a circuit board, motherboard, organic board, or an assembly of the following heights. The material of the PIC may be silicon-on-insulator material, and it should be understood that the ASIC is any relevant application-specific integrated circuit.

[0005] When the second layer is attached to the first layer, the second layer is positioned directly above the first layer, allowing for precise alignment of specific components so that the electrical connection is a vertical connection between the two layers, while minimizing any electrical connections between the two components. Thus, the connected components are aligned in the x and y directions, displaced relative to each other only along the z axis, and one component (e.g., a modulator driver) is positioned directly above the other component (e.g., a modulator).

[0006] The following describes some features of the present invention, which can be applied individually or in any combination with any aspect of the present invention.

[0007] Optionally, the PIC includes one or more vias to provide electrical contact between components of the ASIC above the PIC and the substrate.

[0008] In some embodiments, the PIC is a silicon photonic PIC, for example, a silicon-on-insulator material, and therefore the vias are through-silicon vias (TSVs). TSVs are low-speed connections. Thus, the stacked configurations of some embodiments of the present invention are designed to minimize the path length of high-speed RF. This maximizes the speed performance of the entire assembly and improves scalability.

[0009] Optionally, the PIC has multiple vias, each via providing electrical contact between the ASIC components above the PIC and the circuit board.

[0010] Optionally, the first layer of the PIC includes one or more modulators. Each modulator converts an unmodulated optical signal and a modulated electrical signal into a modulated optical signal.

[0011] Because ASICs are typically high-density ASICs, they may be associated with compact photoelectric modulators such as MTP EAMs (Micro-Transfer Printed Electro-Absorption Modulators) or Ring Resonators (RRs).

[0012] Optionally, the ASIC comprises one or more modulator drivers, each of which is configured to drive one of each of the modulators, each modulator converting unmodulated optical signals and modulated electrical signals into modulated optical signals.

[0013] Optionally, the first layer of the PIC includes one or more photodiodes.

[0014] Optionally, the ASIC may include one or more transimpedance amplifiers (TIAs), each of which is configured to amplify the signals from each of the one or more photodiodes.

[0015] Optionally, the PIC includes an array of interconnected modulators and photodiodes.

[0016] Optionally, the ASIC includes an arrangement of interspersed modulator drivers and TIAs such that each modulator of the PIC is aligned with the modulator driver of the ASIC above it, and each photodiode is aligned with the TIA of the ASIC above it. In such a configuration, the interspersed arrangement of modulator drivers and TIAs above it typically reflects the corresponding interspersed arrangement of each modulator and photodiode of the PIC below it. In this way, the connections between each modulator and its corresponding modulator driver are minimized, as are the electrical connections between each photodiode and its corresponding TIA.

[0017] Optionally, the PIC includes at least one serializer / deserializer, SerDes.

[0018] Optionally, the PIC itself is arranged across two layers: a photonic component layer containing modulators and / or photodiodes, and a driver layer containing modulator drivers and / or TIAs for each modulator and / or photodiode.

[0019] Optionally, the driver layer is placed between the photonic component layer and the substrate.

[0020] Optionally, the driver layer is placed between the photonic component layer and the switch ASIC.

[0021] Optionally, the PIC includes one or more data input points to which optical fibers are connected to components of the PIC in order to bring optical signals to the PIC components.

[0022] Optionally, one or more data input points include an optical demultiplexer.

[0023] Optionally, the PIC includes one or more data output points to which optical fibers are connected to components of the PIC in order to extract optical signals from the PIC components.

[0024] Optionally, one or more data output points include an optical multiplexer.

[0025] Optionally, the PIC further includes one or more banks of lasers. Typically, the bank of lasers will be a bank of hybrid lasers. A power splitter may be present to split the laser input into multiple components.

[0026] Optionally, the electrical connection between the PIC and the substrate includes one or more of Cu pillars, solder bumps, controlled-fold chip connection C4, ball grid array BGA, and column grid array CGA.

[0027] These and other features and advantages of the present invention will be recognized and understood by reference to the specification, claims, and appended drawings.

Brief Description of the Drawings

[0028] [Figure 1] (a) Design of a first related art, (b) Design of a second related art, and (c) Schematic diagram showing an integrated solution according to an embodiment of the present invention. [Figure 2] Two examples of ASIC layouts for an integrated switch assembly in some embodiments of the present invention are shown. In FIG. 2A, the ASIC layer includes a single switch logic that also includes a driver for the modulator and a TIA for amplifying the signal from the photodiode. In FIG. 2B, the ASIC layer is composed of two separate switch logic regions. [Figure 3A] An example of a PIC layout by an integrated switch assembly in some embodiments of the present invention suitable for attachment above the ASIC layer in a 3D stacked configuration is shown. An example of a PIC layer compatible with the ASIC layer of FIG. 2 is disclosed. [Figure 3B] An example of a PIC layout by an integrated switch assembly in some embodiments of the present invention suitable for attachment above the ASIC layer in a 3D stacked configuration is shown. An example of a PIC layer compatible with the ASIC layer of FIG. 2B is disclosed. [Figure 4] Two examples of PIC layouts including on-chip hybrid lasers are shown. Figure 4A has a first configuration in which the laser bank is located at the edge of the chip, away from the data output. Figure 4B has a laser bank located adjacent to the driver and along the length of the PIC, extending laterally with respect to the side where the data output is located. [Figure 5] Examples of cross-sections of integrated switch assemblies according to several embodiments of the present invention are shown. Figure 5A shows an example of compatibility between the ASIC layer in Figure 2A and the PIC layer in Figure 3A, and Figure 5B shows an example of compatibility between the ASIC layer in Figure 2B and the PIC layer in Figure 3B. [Figure 6] Further examples of cross-sections of integrated switch assemblies according to several embodiments of the present invention are shown. In this case, a PIC is shown that itself is arranged across two layers, with one secondary layer of the two PIC layers containing a modulator driver and a TIA. Figure 6A shows an example of compatibility between the ASIC layer of Figure 2A and the PIC layer of Figure 3A, and Figure 6B shows an example of compatibility between the ASIC layer of Figure 2B and the PIC layer of Figure 3B. [Figure 7] An example of the ASIC layer of an integrated switch assembly according to an embodiment of the present invention is shown. The ASIC layer comprises a scattered arrangement of modulator drivers and TIAs. [Figure 8] This shows an example of the PIC layer of an integrated switch assembly according to an embodiment of the present invention, the PIC layer comprising a scattered arrangement of modulators and photodiodes, the scattered arrangement being configured to match the arrangement of the modulator driver and TIA of the ASIC shown in Figure 7. [Figure 9] Further examples of the PIC layer of an integrated switch assembly according to embodiments of the present invention are shown, the PIC layer comprising a scattered arrangement of modulators and photodiodes along an integrated hybrid laser, the scattered arrangement being configured to match the arrangement of modulators and TIAs of the ASIC shown in Figure 7. [Figure 10] Figure 7 shows a cross-section of an integrated switch assembly including the ASIC layer and the PIC layer shown in Figure 9 or Figure 10. [Figure 11]A cross-section of a further embodiment of an integrated switch assembly is shown, in which the connection between the PIC and the substrate includes a column grid array (CGA). [Figure 12] A cross-section of a further embodiment of an integrated switch assembly is shown, in which the connection between the PIC and the board includes a ball grid array (BGA). [Figure 13A] The cross-section of a further embodiment of an integrated switch array according to some embodiments of the present invention is shown, in which the connections between layers of the 3D switch assembly include a Controlled Collapsed Chip Connection (C4). In this embodiment, a secondary layer containing a driver is located between the PIC and the substrate. [Figure 13B] The cross-section of a further embodiment of an integrated switch array according to some embodiments of the present invention is shown, in which the connections between layers of the 3D switch assembly include a Controlled Collapsed Chip Connection (C4). In this embodiment, a secondary layer containing a driver is placed between the PIC layer and the ASIC. [Figure 14-1] Figures 11, 12, 13A, and 13B show plan views of the embodiments disclosed. [Figure 14-2] Figures 11, 12, 13A, and 13B show plan views of the embodiments disclosed. [Modes for carrying out the invention]

[0029] The detailed description below, in relation to the accompanying drawings, is intended to describe exemplary embodiments of the integrated switch assemblies provided in accordance with the present invention and is not intended to represent the only forms in which the invention may be constructed or utilized. This description describes the features of the invention in relation to the illustrated embodiments. However, it should be understood that the same or equivalent functions and structures may be achieved by different embodiments, which are also intended to be encompassed within the spirit and scope of the invention. As shown elsewhere in this specification, the numbering of similar elements is intended to indicate similar elements or features.

[0030] A set of first embodiments of an integrated switch assembly is described below with reference to Figures 2-6. The integrated switch assembly has a stacked configuration such that its components are arranged in 3D. The stacked array includes a first layer, which is a PIC layer containing a photonic integrated circuit (PIC), and a second layer, which is an ASIC layer containing a switch ASIC. The switch ASIC includes switch logic, multiple drivers, including multiple modulator drivers, and multiple phototransimpedance amplifiers (TIAs). In the embodiment shown in Figure 2A, these are located directly on the switch logic, with the array of modulator drivers located on one side of the switch logic and the array of TIAs located on the other side of the switch logic. In the embodiment shown in Figure 2B, the drivers are located adjacent to the switch logic, more specifically, there are two switch logic regions located on the ASIC layer, the array of TIAs is located between the two switch logic regions, and the array of modulator drivers is located on both sides, opposite the TIAs with respect to the switch logic region.

[0031] As shown in Figures 3A and 3B, the PIC layer includes modulators and photodiodes. The embodiment in Figure 3A is configured to be mounted on top of the ASIC layer in Figure 2 and consists of a first part including a laser input, an array of modulators, and an optical multiplexer (MUX). The laser input takes the form of multiple (e.g., a given integer f) laser inputs, which may be fiber inputs. The shown PIC layer further includes multiple power splitters (in this case, a power splitter from f*1 to P (i.e., a power splitter for f, each from 1 to P)) and an optical multiplexer (in this case, a MUX from N to 1 or k*L to 1). The second part of the PIC layer includes an array of photodiodes and an optical demultiplexer (DeMUX) (in this case, a DeMUX from 1 to N or k*1 to L). The embodiment in Figure 3B is configured to be mounted on top of the ASIC layer in Figure 2B and therefore differs from Figure 3A in that it includes two outer regions, each containing an array of modulators, power splitters, and multiplexers, and an inner region containing an array of photodiodes and a DeMUX. The modulators and photodiodes in the PIC layer are positioned such that, if the PIC layer is positioned directly above the ASIC layer, the modulators and photodiodes align with the respective modulator drivers and TIAs located in the ASIC layer. Figures 4A and 4B show regions of the PIC containing modulators and differ from those shown in Figures 3A and 3B in that they further include a bank of lasers, which is typically a hybrid laser positioned directly on the PIC. As can be seen from the cross-sectional views in Figures 5A and 5B, the PIC includes multiple slow-speed through-silicon vias (TSVs) for providing electrical connections between the substrate and the switch ASIC via the PIC. In the embodiments of Figures 6A and 6B, the PIC itself consists of two layers, with a first secondary layer containing photonic components and a second secondary layer containing drivers for those components. Therefore, in this embodiment, the ASIC layer no longer needs to include a driver / TIA in addition to the switch logic.

[0032] Cu pillars or solder bumps can form electrical connections between the PIC and any of the underlying substrates, and between the PIC layer and the ASIC layer.

[0033] A second set of embodiments is described below with reference to Figures 7-10. These embodiments relate to an integrated switch assembly having an ASIC layer (Figure 7) with a scattered arrangement of modulator drivers and TIAs, and a corresponding PIC layer (Figure 8) with a scattered arrangement of modulators and photodiodes, wherein the scattered arrangement of the PIC layer is configured to match the arrangement of modulator drivers and TIAs in the ASIC shown in Figure 7. Similar to the previous embodiments, the PIC layer also includes a power splitter, MUX, and DeMUX. However, in this embodiment, these are arranged around the periphery, and the modulators and photodiodes are located at the center of the scattered array of the PIC layer. The scattered array can take the form of alternating rows of modulators and rows of photodiodes. In some embodiments (Figure 9), the PIC layer also includes one or more banks of lasers, typically arranged around the PIC. Generally, the banks of lasers are located next to the power splitter, which takes the optical input from the banks of lasers into the optical components.

[0034] Further embodiments are described below with reference to Figures 11-13. In all cases, the ASIC layer, including the switch ASIC, is located directly above the PIC layer, and the PIC layer is located directly above the substrate (also known as the Next Higher Assembly). At least one driver layer, including a modulator driver and / or TIA, is located between the PIC and the substrate. The driver layer is smaller than the PIC and is located directly below the area of ​​the PIC where the modulator and / or photodiode is located. In the embodiment shown in Figure 11, two driver layers are shown, each located on the respective side of the PIC adjacent to the laser input fiber. This can be clearly seen in the plan view shown in Figure 14, from which it can be seen that the input and output of the fiber are on the two opposite sides of the PIC. The TSV is located throughout the PIC, including within the central region of the PIC. In the embodiment shown in Figure 11, the connection between the PIC and the substrate includes a column grid array (CGA).

[0035] The embodiment in Figure 12 differs from Figure 11 in that the connection between the PIC and the substrate includes a ball grid array (BGA). In the embodiments of Figures 13A and 13B, the connections between layers of the 3D switch assembly include a Controlled Collapsed Chip Connection (C4). In the embodiment of Figure 13A, a secondary layer containing the driver is located between the PIC and the substrate, while in the embodiment of Figure 13B, the driver sublayer is located between the PIC and the switch ASIC.

[0036] As used herein, “unbreakable chip connection” means a pin or an unbreakable bump.

[0037] While exemplary embodiments of integrated switch assemblies have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it should be understood that integrated switch assemblies configured according to the principles of the present invention may be embodied in ways other than those specifically described herein. The present invention is also defined by the following claims and their equivalents.

Claims

1. An integrated switch assembly having a stacked structure, A first layer comprising a photonic integrated circuit having an array in which modulators and photodiodes are scattered, It includes a second layer comprising a switch ASIC having an array in which modulator drivers and transimpedance amplifiers are interspersed, An integrated switch assembly comprising a first layer mounted on a substrate, a second layer mounted on top of the first layer, and the arrangement of the arrays being aligned such that the modulators in the array of the first layer are aligned with the modulator drivers in the array of the second layer, and the photodiodes in the array of the first layer are aligned with the transimpedance amplifiers in the array of the second layer.

2. The integrated switch assembly according to claim 1, wherein the photonic integrated circuit comprises one or more vias for providing electrical contact between the components of the switch ASIC above the photonic integrated circuit and the substrate.

3. The aforementioned photonic integrated circuit comprises multiple vias, The integrated switch assembly according to claim 2, wherein each via provides electrical contact between the components of the switch ASIC above the photonic integrated circuit and the substrate.

4. The integrated switch assembly according to claim 1, wherein each of the modulator drivers is configured to drive the modulator.

5. The integrated switch assembly according to claim 1, wherein each of the transimpedance amplifiers is configured to amplify the signal from the photodiode.

6. The integrated switch assembly according to claim 1, wherein the photonic integrated circuit comprises at least one serializer / deserializer.

7. The integrated switch assembly according to claim 1, wherein the photonic integrated circuit itself is arranged across two layers: a photonic component layer including the modulator and / or the photodiode, and a driver layer including the modulator driver and / or the transimpedance amplifier for each of the modulators and / or the photodiode.

8. The integrated switch assembly according to claim 7, wherein the driver layer is disposed between the photonic component layer and the substrate.

9. The integrated switch assembly according to claim 7, wherein the driver layer is disposed between the photonic component layer and the switch ASIC.

10. The integrated switch assembly according to claim 1, wherein the photonic integrated circuit includes one or more data input units to which optical fibers are connected in order to bring optical signals to the components of the photonic integrated circuit.

11. The integrated switch assembly according to claim 10, wherein the one or more data input units include an optical demultiplexer.

12. The integrated switch assembly according to claim 1, wherein the photonic integrated circuit includes one or more data output units to which optical fibers are connected in order to extract optical signals from the photonic integrated circuit components.

13. The integrated switch assembly according to claim 12, wherein the one or more data output units include an optical multiplexer.

14. The integrated switch assembly according to claim 1, wherein the photonic integrated circuit further comprises a bank of one or more lasers.

15. The integrated switch assembly according to claim 1, wherein the electrical connection between the photonic integrated circuit and the substrate is an array of conductors, the array of conductors is either a ball grid array or a column grid array, and each of the conductors in the array of conductors is selected from the group consisting of solder bumps, copper pillars, controlled folding chip connections and non-folding chip connections.

16. The integrated switch assembly according to claim 1, comprising a plurality of photonic integrated circuits, including the first layer of the photonic integrated circuit.

17. The integrated switch assembly according to claim 1, comprising a plurality of switch ASICs, including the switch ASIC of the second layer.

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