Power supply device

Abstract

To provide a power supply device capable of further reducing an output voltage without complicating control.SOLUTION: A power supply device comprises: a bridge circuit that includes an arm of at least one phase; a transformation circuit that includes at least one phase; and a control circuit that outputs first to fourth switching signals to first to fourth switching elements. In a first case where the switching signals have a predetermined frequency or less, the control circuit performs first control of changing a frequency while keeping a duty of the switching signals at a standard value. In a second case where the switching signals reach a predetermined frequency, the control circuit performs second control of setting the duty of the first switching signal to be lower than the standard value while keeping the frequency of the switching signals at the predetermined frequency.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a power supply device. [Background technology]

[0002] To lower the output voltage of a 3-phase 3-level LLC converter, one can increase the switching frequency of the switching elements. However, there is an upper limit to the switching frequency in order to maintain LLC resonance and soft switching. In other words, there is a lower limit to the output voltage of a 3-phase 3-level LLC converter.

[0003] Patent Document 1 describes expanding the output power range by switching between symmetrical modulation and unmodulated modulation. However, the technology described in Patent Document 1 requires other control operations when switching modulation methods. Therefore, the technology described in Patent Document 1 is complicated to control.

[0004] Non-patent document 1 describes that asymmetric duty cycle control can accommodate a wide range of input voltages.

[0005] Non-patent document 2 describes how to disperse the thermal stress of an element by alternately repeating an asymmetric duty cycle control pattern using PSM (Periodically Swapping Modulation) control. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2021-35328 [Non-patent literature]

[0007] [Non-Patent Document 1] A. Zhenwei Li, et al., "Research on Dual-Operation Mode of 3-Level LLC Resonant Converter," 9th International Conference on Power Electronics - ECCE Asia, January 1-5, 2015, pp. 2636-2643. [Non-Patent Document 2] Dong Liu and others, “Periodically Swapping Modulation (PSM) Strategy for Three-Level(TL) DC / DC Converters With Balanced Switch Currents”, IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, January 2018, p.412-423 [Overview of the project] [Problems that the invention aims to solve]

[0008] The present invention aims to provide a power supply device that can further reduce the output voltage without complicating the control process. [Means for solving the problem]

[0009] A power supply device according to one embodiment of the present invention is: A bridge circuit comprising a first switching element, a second switching element, a third switching element, and a fourth switching element connected in series, wherein a first DC voltage is input to one end of the high-potential side of the first switching element, a second DC voltage lower than the first DC voltage is input to the connection point between the second and third switching elements, and at least one phase arm of the fourth switching element is electrically connected to a reference potential, A transformer circuit comprising: a primary circuit of at least one phase to which the output voltage of the arm is input and resonates; and a secondary circuit of at least one phase that is electromagnetically coupled with the primary circuit and outputs an AC voltage; A rectifier circuit for rectifying the aforementioned AC voltage, A smoothing circuit that smooths the voltage output from the rectifier circuit, A control circuit that changes the second switching signal complementary to the first switching signal, changes the fourth switching signal complementary to the third switching signal, and outputs the first to fourth switching signals to the first to fourth switching elements such that the voltage of the smoothing circuit becomes the command value voltage or the current output from the rectifier circuit becomes the command value current, Equipped with, The aforementioned control circuit is In the first case where the frequencies from the first switching signal to the fourth switching signal are below a predetermined frequency, a first control is performed to maintain the duty cycle of the first switching signal to the fourth switching signal at a standard value and change the frequency. In the second case, when the frequencies from the first switching signal to the fourth switching signal reach the predetermined frequency, a second control is performed to maintain the frequencies from the first switching signal to the fourth switching signal at the predetermined frequency and to reduce the duty cycle of the first switching signal to a value lower than the standard value. It is characterized by the following:

[0010] In the aforementioned power supply device, The aforementioned control circuit is In the second case described above, the duty cycle of the fourth switching signal is made the same as the duty cycle of the first switching signal. It is characterized by the following:

[0011] In the aforementioned power supply device, The aforementioned control circuit is In the second case, the duty cycle of the third switching signal is made smaller than the standard value. It is characterized by the following:

[0012] In the aforementioned power supply device, The aforementioned control circuit is In the second case described above, the phase difference between the phase of the first switching signal and the phase of the third switching signal is set to 180°. It is characterized by the following:

[0013] In the aforementioned power supply device, The aforementioned control circuit is In the second case described above, the duty cycle of the third switching signal is made the same as the duty cycle of the first switching signal. It is characterized by the following:

[0014] In the aforementioned power supply device, The aforementioned control circuit is When the output current from the rectifier circuit exceeds the threshold current, the first switching signal to the fourth switching signal are set to a predetermined duty cycle or a duty cycle corresponding to the output current. It is characterized by the following:

[0015] In the aforementioned power supply device, The aforementioned control circuit is Hysteresis is provided when switching between the first control and the second control. It is characterized by the following:

[0016] In the aforementioned power supply device, The aforementioned control circuit is In the case of the second control described above, PSM (Periodically Swapping Modulation) control is performed. It is characterized by the following: [Effects of the Invention]

[0017] One embodiment of the present invention provides a power supply device that can further reduce the output voltage without complicating the control process. [Brief explanation of the drawing]

[0018] [Figure 1] Figure 1 shows the configuration of the power supply device according to the first embodiment. [Figure 2]Figure 2 shows an example of the output voltage-output current characteristics of the power supply device according to the first embodiment. [Figure 3] Figure 3 shows an example of the waveform of the switching signal of the first phase arm of the power supply device according to the first embodiment. [Figure 4] Figure 4 shows the simulation results of the output voltage-duty cycle characteristics of the power supply device according to the first embodiment. [Figure 5] Figure 5 shows the configuration of the control circuit of the power supply device according to the first embodiment. [Figure 6] Figure 6 shows an example of the configuration of the overcurrent protection control circuit of the power supply device according to the first embodiment. [Figure 7] Figure 7 shows another example of the configuration of the overcurrent protection control circuit of the power supply device according to the first embodiment. [Figure 8] Figure 8 shows the configuration of the switching control circuit of the power supply device according to the first embodiment. [Figure 9] Figure 9 shows an example of the waveform of the switching control circuit of the power supply device according to the first embodiment. [Figure 10] Figure 10 shows an example of the waveform of the switching signal of the first phase arm of the power supply device according to the second embodiment. [Figure 11] Figure 11 shows an example of the configuration of the overcurrent protection control circuit of the power supply device according to the second embodiment. [Figure 12] Figure 12 shows another example of the configuration of the overcurrent protection control circuit of the power supply unit according to the second embodiment. [Figure 13] Figure 13 shows the configuration of the switching control circuit of the power supply device according to the second embodiment. [Figure 14] Figure 14 shows an example of the waveform of the switching control circuit of the power supply device according to the second embodiment. [Figure 15] Figure 15 shows the circuit simulation results of the power supply device according to the second embodiment. [Figure 16] Figure 16 shows the circuit simulation results of the power supply device according to the second embodiment. [Figure 17] Figure 17 shows the circuit simulation results for the power supply device of the second embodiment. [Figure 18] Figure 18 shows the circuit simulation results of the power supply device according to the second embodiment. [Figure 19] Figure 19 shows the circuit simulation results of the power supply device according to the second embodiment. [Figure 20] Figure 20 shows the circuit simulation results of the power supply device according to the second embodiment. [Figure 21] Figure 21 shows the circuit simulation results of the power supply device according to the second embodiment. [Modes for carrying out the invention]

[0019] Embodiments of the power supply device of the present invention will be described in detail below with reference to the drawings. However, the present invention is not limited to these embodiments.

[0020] <First Embodiment> (Overall configuration of the power supply unit) Figure 1 shows the configuration of the power supply unit according to the first embodiment. Power supply unit 1 is a 3-phase 3-level LLC converter.

[0021] In the first embodiment, the number of phases was set to 3, but this disclosure is not limited to this. The number of phases may be 1, 2, or 4 or more.

[0022] Power supply 2 has a voltage of V in It outputs the voltage V. Resistors 3 and 4, which are connected in series, have a voltage of V in The voltage is divided. The resistance value of resistor 3 and the resistance value of resistor 4 are assumed to be the same. That is, the voltage across resistor 3 and resistor 4 is V in Let it be / 2. However, this disclosure is not limited thereto. Capacitors 5 and 6 connected in series have a voltage V in Stabilize / 2.

[0023] The power supply unit 1 includes a bridge circuit 11, a transformer circuit 12, a rectifier circuit 13, a capacitor 14, a voltage sensor 15, a current sensor 16, and a control circuit 20.

[0024] Capacitor 14 corresponds to an example of a “smoothing circuit” in this disclosure.

[0025] The bridge circuit 11 includes a first phase arm 31, a second phase arm 32, and a third phase arm 33.

[0026] The first phase arm 31 includes transistors Q1 through Q4.

[0027] The source of transistor Q1 is electrically connected to the drain of transistor Q2. The source of transistor Q2 is electrically connected to the drain of transistor Q3. The source of transistor Q3 is electrically connected to the drain of transistor Q4.

[0028] The second phase arm 32 includes transistors Q5 through Q8.

[0029] The source of transistor Q5 is electrically connected to the drain of transistor Q6. The source of transistor Q6 is electrically connected to the drain of transistor Q7. The source of transistor Q7 is electrically connected to the drain of transistor Q8.

[0030] The third phase arm 33 includes transistors Q9 through Q12.

[0031] The source of transistor Q9 is electrically connected to the drain of transistor Q10. The source of transistor Q10 is electrically connected to the drain of transistor Q11. The source of transistor Q11 is electrically connected to the drain of transistor Q12.

[0032] Each of transistors Q1, Q5, and Q9 corresponds to an example of the “first switching element” in this disclosure. Each of transistors Q2, Q6, and Q10 corresponds to an example of the “second switching element” in this disclosure. Each of transistors Q3, Q7, and Q11 corresponds to an example of the “third switching element” in this disclosure. Each of transistors Q4, Q8, and Q12 corresponds to an example of the “fourth switching element” in this disclosure.

[0033] In this disclosure, each transistor is assumed to be a MOSFET, but this is not limited to this. Each transistor may be a silicon power device, GaN power device, SiC power device, or the like.

[0034] Each transistor has a parasitic diode (body diode) that can actively conduct current, or a diode connected in antiparallel. A parasitic diode is the pn junction between the back gate and the source and drain of a MOSFET.

[0035] The drains of transistor Q1, transistor Q5, and transistor Q9 are electrically connected to the first input terminal 11a of the bridge circuit 11. The first input terminal 11a is electrically connected to the high-potential side of capacitor 5.

[0036] The source of transistor Q2, the drain of transistor Q3, the source of transistor Q6, the drain of transistor Q7, the source of transistor Q10, and the drain of transistor Q11 are electrically connected to the second input terminal 11b of the bridge circuit 11. The second input terminal 11b is electrically connected to the low-potential side of capacitor 5 and the high-potential side of capacitor 6.

[0037] The sources of transistors Q4, Q8, and Q12 are electrically connected to the third input terminal 11c of the bridge circuit 11. The third input terminal 11c is electrically connected to the low-potential side of capacitor 6.

[0038] Between the first input terminal 11a and the second input terminal 11b of the bridge circuit 11, the voltage V across capacitor 5 in / 2 is entered.

[0039] Between the second input terminal 11b and the third input terminal 11c of the bridge circuit 11, the voltage V across capacitor 6 in / 2 is entered.

[0040] Switching signals are input from the control circuit 20 to the gates of transistors Q1 through Q12.

[0041] The control circuit 20 is exemplified by controlling the phase difference between the first phase arm 31 and the second phase arm 32 to 120°. The control circuit 20 is exemplified by controlling the phase difference between the second phase arm 32 and the third phase arm 33 to 120°. However, the disclosure is not limited thereto.

[0042] The source of transistor Q1 and the drain of transistor Q2 are electrically connected to the first output terminal 11d of the bridge circuit 11. The source of transistor Q3 and the drain of transistor Q4 are electrically connected to the second output terminal 11e of the bridge circuit 11.

[0043] The source of transistor Q5 and the drain of transistor Q6 are electrically connected to the third output terminal 11f of the bridge circuit 11. The source of transistor Q7 and the drain of transistor Q8 are electrically connected to the fourth output terminal 11g of the bridge circuit 11.

[0044] The source of transistor Q9 and the drain of transistor Q10 are electrically connected to the fifth output terminal 11h of the bridge circuit 11. The source of transistor Q11 and the drain of transistor Q12 are electrically connected to the sixth output terminal 11i of the bridge circuit 11.

[0045] The transformer circuit 12 includes transformers 41 through 43.

[0046] The transformer 41 includes a primary winding 41a, a secondary winding 41b, and a core 41c. The primary winding 41a and the secondary winding 41b are wound around the core 41c.

[0047] The primary winding 41a includes an excitation inductance 51 and a leakage inductance 52. A capacitor 53 is provided in series with the excitation inductance 51 and the leakage inductance 52 on the primary winding 41a. One end of the primary winding 41a is electrically connected to the first output terminal 11d of the bridge circuit 11. The other end of the primary winding 41a is electrically connected to the second output terminal 11e of the bridge circuit 11.

[0048] The excitation inductance 51, leakage inductance 52, and capacitor 53 constitute an LLC resonant circuit.

[0049] The transformer 42 includes a primary winding 42a, a secondary winding 42b, and a core 42c. The primary winding 42a and the secondary winding 42b are wound around the core 42c.

[0050] The primary winding 42a includes an excitation inductance 54 and a leakage inductance 55. A capacitor 56 is provided in series with the excitation inductance 54 and the leakage inductance 55 on the primary winding 42a. One end of the primary winding 42a is electrically connected to the third output terminal 11f of the bridge circuit 11. The other end of the primary winding 42a is electrically connected to the fourth output terminal 11g of the bridge circuit 11.

[0051] The excitation inductance 54, leakage inductance 55, and capacitor 56 constitute an LLC resonant circuit.

[0052] The transformer 43 includes a primary winding 43a, a secondary winding 43b, and a core 43c. The primary winding 43a and the secondary winding 43b are wound around the core 43c.

[0053] The primary winding 43a includes an excitation inductance 57 and a leakage inductance 58. A capacitor 59 is provided in series with the excitation inductance 57 and the leakage inductance 58 on the primary winding 43a. One end of the primary winding 43a is electrically connected to the fifth output terminal 11h of the bridge circuit 11. The other end of the primary winding 43a is electrically connected to the sixth output terminal 11i of the bridge circuit 11.

[0054] The excitation inductance 57, leakage inductance 58, and capacitor 59 constitute an LLC resonant circuit.

[0055] One end of the secondary winding 41b of transformer 41, one end of the secondary winding 42b of transformer 42, and one end of the secondary winding 43b of transformer 43 are electrically connected.

[0056] The rectifier circuit 13 is a bridge diode. The rectifier circuit 13 includes diodes D1 to D6.

[0057] The anode of diode D1 is electrically connected to the cathode of diode D2. The anode of diode D3 is electrically connected to the cathode of diode D4. The anode of diode D5 is electrically connected to the cathode of diode D6.

[0058] The anode of diode D1 and the cathode of diode D2 are electrically connected to the other end of the secondary winding 41b of transformer 41. The anode of diode D3 and the cathode of diode D4 are electrically connected to the other end of the secondary winding 42b of transformer 42. The anode of diode D5 and the cathode of diode D6 are electrically connected to the other end of the secondary winding 43b of transformer 43.

[0059] The cathodes of diodes D1, D3, and D5 are electrically connected to the high-potential side of capacitor 14. The anodes of diodes D2, D4, and D6 are electrically connected to the low-potential side of capacitor 14.

[0060] The capacitor 14 smoothes the voltage output by the rectifier circuit 13. The voltage of the capacitor 14 is the output voltage V out .

[0061] The voltage sensor 15 detects the output voltage V out and outputs a detection signal to the control circuit 20.

[0062] The current sensor 16 detects the output current I out and outputs a detection signal to the control circuit 20.

[0063] (Overview of control) Generally, in an LLC converter, the duty of each transistor is set to 0.5 (hereinafter referred to as the "standard value"). The control circuit 20 synchronizes the transistor Q1 and the transistor Q4 (same phase and same duty), and synchronizes the transistor Q2 and the transistor Q3. Similarly, the control circuit 20 synchronizes the transistor Q5 and the transistor Q8, and synchronizes the transistor Q6 and the transistor Q7. Similarly, the control circuit 20 synchronizes the transistor Q9 and the transistor Q12, and synchronizes the transistor Q10 and the transistor Q11.

[0064] FIG. 2 is a diagram showing an example of the output voltage-output current characteristics of the power supply device according to the first embodiment. The vertical axis in FIG. 2 represents the output voltage V out , and the horizontal axis represents the output current I out .

[0065] The control circuit 20 can lower the output voltage V out by increasing the switching frequency of each transistor. Hereinafter, this control is referred to as "first control".

[0066] However, in order to maintain LLC resonance and soft switching, there is an upper limit to the switching frequency. That is, the output voltage V by the first control outThere is a lower limit (hereinafter referred to as the "first control lower limit voltage") indicated by boundary line 201 in Figure 2. Therefore, the range of output voltage-output current that the power supply unit 1 can output by the first control is the region 202 in Figure 2, which is above boundary line 201.

[0067] Therefore, when the switching frequency reaches its upper limit, the control circuit 20 maintains the switching frequency at its upper limit while lowering the duty cycle of transistor Q1 (Q5, Q9) to below the standard value. Hereafter, this control will be referred to as the "second control."

[0068] Furthermore, in the second control, it is preferable that the control circuit 20 sets the duty cycle of transistor Q4 (Q8, Q12) to be the same as the duty cycle of transistor Q1 (Q5, Q9). In addition, it is preferable that the control circuit 20 synchronizes transistor Q4 (Q8, Q12) and transistor Q1 (Q5, Q9) in the second control. This makes it easier for the control circuit 20 to generate switching signals, as will be described later.

[0069] Figure 3 shows an example of the waveform of the switching signal of the first phase arm of the power supply unit according to the first embodiment. Note that the dead time is omitted in Figure 3.

[0070] Waveform 211 shows the switching signal input to the gate of transistor Q1. Waveform 212 shows the switching signal input to the gate of transistor Q2. Waveform 213 shows the switching signal input to the gate of transistor Q3. Waveform 214 shows the switching signal input to the gate of transistor Q4.

[0071] The switching signal input to the gate of transistor Q1 (waveform 211) and the switching signal input to the gate of transistor Q2 (waveform 212) change complementaryly. The switching signal input to the gate of transistor Q3 (waveform 213) and the switching signal input to the gate of transistor Q4 (waveform 214) change complementaryly.

[0072] Up to timing t0, the control circuit 20, as a first control, increases the frequency while maintaining the duty cycle of each switching signal at its standard value.

[0073] Up to timing t0, the on-period 215 of the switching signal (waveform 211) input to the gate of transistor Q1 is half of one period 216.

[0074] As a result, power supply unit 1 outputs voltage V out This can be reduced to the first control lower limit voltage.

[0075] At timing t0, when the frequency of each switching signal reaches its upper limit, the control circuit 20, as a second control, maintains the frequency of each switching signal at its upper limit while reducing the duty cycle of the switching signal (waveform 211) input to the gate of transistor Q1 to below the standard value.

[0076] After timing t0, the on-period 217 of the switching signal (waveform 211) input to the gate of transistor Q1 is less than half of one period 218.

[0077] Furthermore, it is preferable that, after timing t0, the control circuit 20 sets the duty cycle of the switching signal (waveform 214) input to the gate of transistor Q4 to be the same as the duty cycle of the switching signal (waveform 211) input to the gate of transistor Q1. In addition, it is preferable that the control circuit 20 synchronizes transistor Q4 and transistor Q1 in the second control. As a result, the control circuit 20 can share one switching signal between transistor Q1 and transistor Q4, making it easier to generate the switching signal and thus easier to control.

[0078] Figure 4 shows the simulation results of the output voltage-duty cycle characteristics of the power supply device according to the first embodiment. The vertical axis in Figure 4 represents the output voltage V out The horizontal axis represents the time, and the horizontal axis represents the duty cycle.

[0079] As shown in waveform 221 of Figure 4, as the duty cycle of transistor Q1 is reduced from the standard value, the output voltage V of power supply unit 1 increases. out It can be lowered.

[0080] In this way, when the switching frequency reaches the upper limit, the power supply unit 1 performs a second control, thereby controlling the output voltage V out This can be lowered even further than the first control lower limit voltage.

[0081] Referring again to Figure 2, the power supply unit 1 has an output voltage V above the boundary line 201 (first control lower limit voltage). out This can be reduced. Therefore, the output voltage-output current range that power supply unit 1 can output is the region 204, which is the sum of region 202 and region 203, which is below boundary line 201 in Figure 2.

[0082] (Control circuit configuration) Figure 5 shows the configuration of the control circuit of the power supply device according to the first embodiment.

[0083] The control circuit 20 includes an overcurrent protection control circuit 61, a switching control circuit 62, a switching circuit 63, and a dead time generation circuit 65.

[0084] The overcurrent protection control circuit 61 controls the output current I out If an overcurrent is detected, signal S1 is output to the switching circuit 63.

[0085] When signal S1 is input, the switching circuit 63 switches multiple signals S2 output from the overcurrent protection control circuit 61 to multiple switching signals S SW The output is then sent from transistor Q1 to transistor Q12.

[0086] When no signal S1 is input, the switching circuit 63 switches the multiple signals S3 output from the switching control circuit 62 to multiple switching signals S SWThe signal is then output to the dead time generation circuit 65, which sets an arbitrary dead time between the signals of complementary transistors and outputs it to transistors Q1 through Q12.

[0087] Figure 6 shows an example of the configuration of the overcurrent protection control circuit of the power supply device according to the first embodiment.

[0088] The overcurrent protection control circuit 61 includes resistors 71 and 72, a constant voltage source 73, a hysteresis comparator 74, a triangular wave signal source 75, a comparator 76, and an inverting circuit 77.

[0089] At one end of resistor 71, the output current I out The voltage V obtained by converting to a voltage. Iout The following is input. The other end of resistor 71 is electrically connected to one end of resistor 72. The other end of resistor 72 is electrically connected to a reference potential. The reference potential is exemplified by, but is not limited to, the ground potential.

[0090] The other end of resistor 71 and one end of resistor 72 are electrically connected to the non-inverting input terminal (+ terminal) of hysteresis comparator 74. Resistors 71 and 72 are connected to the voltage V Iout The voltage V obtained by dividing the voltage 11 This is output to the non-inverting input terminal (+ terminal) of the hysteresis comparator 74.

[0091] The constant voltage source 73 outputs current I out Reference voltage V corresponding to the overcurrent threshold Iref This is output to the inverting input terminal (- terminal) of the hysteresis comparator 74.

[0092] The hysteresis comparator 74 controls the voltage V 11 The reference voltage V Iref If it is higher than a certain value, the high-level voltage V 12 This is output to the inverting input terminal (- terminal) of comparator 76.

[0093] The hysteresis comparator 74 controls the reference voltage V IrefVoltage V 11 If it is higher than a certain value, the low-level voltage V 12 This is output to the inverting input terminal (- terminal) of comparator 76.

[0094] The overcurrent protection control circuit 61 can suppress frequent switching between overcurrent protection control and normal switching control by having a hysteresis comparator 74 with hysteresis.

[0095] The voltage V output by the hysteresis comparator 74 12 This is output to the switching circuit 63 as signal S1.

[0096] The triangular wave signal source 75 outputs a triangular wave signal V of a predetermined frequency. 13 This is output to the non-inverting input terminal (+ terminal) of comparator 76.

[0097] Comparator 76 receives the triangular wave signal V 13 The voltage is voltage V 12 If it is higher than, the high-level voltage V 14 It outputs the following. Comparator 76 outputs the voltage V 12 is a triangular wave signal V 13 If the voltage is higher than the low-level voltage V 14 Outputs.

[0098] The voltage V output by comparator 76 14 This is input to the switching circuit 63 (see Figure 5) as signal S2, and the switching signal S SW This is output to the gates of transistors Q1 (Q5, Q9) and Q4 (Q8, Q12).

[0099] The inverting circuit 77 controls the voltage V 14 The voltage V obtained by logically inverting the above. 15 Outputs.

[0100] Voltage V output by the inverting circuit 77 15 This is input to the switching circuit 63 (see Figure 5) as signal S2, and the switching signal S SWThis is output to the gates of transistors Q2 (Q6, Q10) and Q3 (Q7, Q11).

[0101] As a result, the overcurrent protection control circuit 61 outputs current I out If the current is higher than the overcurrent threshold by a certain value, control can be performed with a predetermined duty cycle. For example, the overcurrent protection control circuit 61 may set the duty cycle of transistors Q1 (Q5, Q8) and Q4 (Q8, Q12) to 0.1, and the duty cycle of transistors Q2 (Q6, Q10) and Q3 (Q7, Q11) to 0.9. The overcurrent protection control circuit 61 can perform pulse-by-pulse control using the hysteresis comparator 74.

[0102] Figure 7 shows another example of the configuration of the overcurrent protection control circuit of the power supply device according to the first embodiment.

[0103] Compared to the overcurrent protection control circuit 61 (see Figure 6), the overcurrent protection control circuit 64 includes an error amplifier 78 instead of a hysteresis comparator 74.

[0104] The non-inverting input terminal (+ terminal) of the error amplifier 78 has a voltage V 11 The following is input. The inverting input terminal (- terminal) of the error amplifier 78 is connected to the reference voltage V Iref The following is entered.

[0105] Error amplifier 78 uses voltage V 11 and reference voltage V Iref Voltage V corresponding to the difference 21 This is output to the inverting input terminal (- terminal) of comparator 76.

[0106] The voltage V output by the error amplifier 78 21 This is output to the switching circuit 63 as signal S1.

[0107] As a result, the overcurrent protection control circuit 64 outputs current I out If the output current I exceeds the overcurrent threshold, outIn response to the increase in [value], control can be performed to reduce the duty cycle of transistors Q1 (Q5, Q9) and Q4 (Q8, Q12).

[0108] Figure 8 shows the configuration of the switching control circuit of the power supply device according to the first embodiment.

[0109] In the first embodiment, the switching control circuit 62 controls the output voltage V out The present disclosure will describe a case in which constant output voltage control is performed so that the output current I becomes the target voltage, but is not limited thereto. out Alternatively, constant output current control may be performed to ensure that the target current is reached.

[0110] The switching control circuit 62 includes resistors 91 and 92, a variable voltage source 93, an error amplifier 94, a voltage limiter 95, a voltage-controlled oscillator 96, a constant voltage source 97, an error amplifier 98, comparators 99, 100 and 101, and inverting circuits 105, 106 and 107.

[0111] One end of resistor 91 is connected to the output voltage V out The following is input. The other end of resistor 91 is electrically connected to one end of resistor 92. The other end of resistor 92 is electrically connected to the reference potential.

[0112] In the case of constant output current control, one end of resistor 91 is connected to the output current I out The voltage V obtained by converting to a voltage. Iout The following is entered.

[0113] The other end of resistor 91 and one end of resistor 92 are electrically connected to the non-inverting input terminal (+ terminal) of the error amplifier 94. Resistors 91 and 92 are connected to the output voltage V out The voltage V obtained by dividing the voltage 31 This is output to the non-inverting input terminal (+ terminal) of the error amplifier 94.

[0114] The variable voltage source 93 has an output voltage V out Command value voltage V corresponding to the target voltageo-ref This is output to the inverting input terminal (- terminal) of the error amplifier 94.

[0115] In the case of output current control, the variable voltage source 93 controls the output current I out A voltage corresponding to the target current is output to the inverting input terminal (- terminal) of the error amplifier 94.

[0116] Error amplifier 94 uses voltage V 31 and command value voltage V o-ref Voltage V corresponding to the difference E1 This is output to the voltage limiter 95 and the non-inverting input terminal (+ terminal) of the error amplifier 98.

[0117] Voltage limiter 95 controls voltage V E1 Lower limit voltage V fmin From the upper limit voltage V fmax Voltage V limited to the range up to 32 This is output to the voltage-controlled oscillator 96.

[0118] The voltage limiter 95 is used to keep the oscillation frequency of the voltage-controlled oscillator 96 within the range from the lower limit frequency to the upper limit frequency of the LLC resonant circuit. Lower limit voltage V fmin From the upper limit voltage V fmax The range up to is the voltage V E1 The range of change is assumed to be narrower than the range in which it changes.

[0119] The voltage-controlled oscillator 96 controls the voltage V 32 Triangular wave signal V of the corresponding frequency tri1 , V tri2 and V tri3 This is output to the non-inverting input terminal (+ terminal) of comparator 99, the non-inverting input terminal (+ terminal) of comparator 100, and the non-inverting input terminal (+ terminal) of comparator 101, respectively.

[0120] The voltage-controlled oscillator 96 controls the triangular wave signal V tri1 and triangular wave signal V tri2 The phase difference between the two is set to 120°. The voltage-controlled oscillator 96 controls the triangular wave signal V tri2 and triangular wave signal V tri3Set the phase difference between them to 120°.

[0121] The voltage-controlled oscillator 96 has a triangular wave signal V 32 such that the higher the voltage V tri1 , V tri2 and V tri3 has a higher frequency, and the lower the voltage V 32 is, the lower the frequency of the triangular wave signals V tri1 , V tri2 and V tri3 .

[0122] The frequencies of the triangular wave signals V tri1 , V tri2 and V tri3 are minimum when the voltage V 32 is the lower limit voltage V fmin . The frequencies of the triangular wave signals V tri1 , V tri2 and V tri3 are maximum when the voltage V 32 is the upper limit voltage V fmax .

[0123] The voltage-controlled oscillator 96 changes each of the triangular wave signals V tri1 , V tri2 and V tri3 around 0V in the positive and negative directions.

[0124] The constant voltage source 97 outputs the voltage V fmax-ref to the inverting input terminal (- terminal) of the error amplifier 98.

[0125] Note that the voltage V fmax-ref is the same as the upper limit voltage V fmax .

[0126] The error amplifier 98 outputs a voltage V E1 corresponding to the difference between the voltage V fmax-ref and the voltage V E2 to the inverting input terminal (- terminal) of the comparator 99, the inverting input terminal (- terminal) of the comparator 100, and the inverting input terminal (- terminal) of the comparator 101.

[0127] Comparator 99 receives a triangular wave signal V tri1 The voltage is voltage V E2 If it is higher than, the high-level voltage V 33 It outputs the following. Comparator 99 outputs the voltage V E2 is a triangular wave signal V tri1 If the voltage is higher than the low-level voltage V 33 Outputs.

[0128] The voltage V output by comparator 99 33 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gates of transistors Q1 and Q4.

[0129] Figure 9 shows an example of the waveform of the switching control circuit of the power supply device according to the first embodiment. Specifically, Figure 9 shows the voltage V output by the error amplifier 98. E2 Then, the voltage-controlled oscillator 96 outputs a triangular wave signal V tri1 This is a diagram showing the waveforms of [the two signals].

[0130] Waveform 231 shows voltage V E2 This shows the triangular wave signal V. Waveform 232 is shown. tri1 This shows the triangular wave signal V. tri1 The voltage changes in both the positive and negative directions, centered around 0V.

[0131] timing t 10 Up to this point, the voltage V output by the error amplifier 94 E1 Voltage V fmax-ref It shall be lower than . In this case, as shown in waveform 231, the voltage V output by the error amplifier 98 E2 This becomes 0V. Therefore, the voltage V output by comparator 99 is 33 The duty cycle will be the standard value (0.5).

[0132] timing t 10 In this case, the voltage V output by the error amplifier 94 E1 Voltage V fmax-ref When it becomes higher than this, the voltage V output by the error amplifier 98E2 is the voltage V E1 As the voltage increases, it rises from 0V. Therefore, the voltage V output by comparator 99 33 The duty cycle decreases from the standard value.

[0133] Refer to Figure 8 again. If the switching control circuit 62 synchronizes transistors Q1 and Q4, the voltage V output by the comparator 99 will be 33 This can be shared between transistor Q1 and transistor Q4. In other words, the switching control circuit 62 becomes easier to generate and control switching signals.

[0134] The inverting circuit 105 controls the voltage V 33 The voltage V obtained by logically inverting the above. 39 Outputs.

[0135] Voltage V output by the inverting circuit 105 39 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gates of transistors Q2 and Q3.

[0136] If the switching control circuit 62 synchronizes transistors Q2 and Q3, the voltage V output by the inverting circuit 105 will be 39 This can be shared between transistor Q2 and transistor Q3. In other words, the switching control circuit 62 becomes easier to generate and control switching signals.

[0137] Comparator 100 receives a triangular wave signal V tri2 The voltage is voltage V E2 If it is higher than, the high-level voltage V 34 It outputs the voltage V. Comparator 100 outputs the voltage V. E2 is a triangular wave signal V tri2 If the voltage is higher than the low-level voltage V 34 Outputs.

[0138] The voltage V output by comparator 100 34 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gates of transistors Q5 and Q8.

[0139] If the switching control circuit 62 synchronizes transistors Q5 and Q8, the voltage V output by the comparator 100 will be 34 This can be shared between transistors Q5 and Q8. In other words, the switching control circuit 62 becomes easier to generate and control switching signals.

[0140] The inverting circuit 106 controls the voltage V 34 The voltage V obtained by logically inverting the above. 40 Outputs.

[0141] Voltage V output by the inverting circuit 106 40 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gates of transistors Q6 and Q7.

[0142] If the switching control circuit 62 synchronizes transistors Q6 and Q7, the voltage V output by the inverting circuit 106 40 This can be shared between transistors Q6 and Q7. In other words, the switching control circuit 62 becomes easier to generate and control switching signals.

[0143] Comparator 101 receives a triangular wave signal V tri3 The voltage is voltage V E3 If it is higher than, the high-level voltage V 35 It outputs the voltage V. Comparator 101 outputs the voltage V. E3 is a triangular wave signal V tri3 If the voltage is higher than the low-level voltage V 35 Outputs.

[0144] The voltage V output by comparator 10135 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gates of transistors Q9 and Q12.

[0145] If the switching control circuit 62 synchronizes transistors Q9 and Q12, the voltage V output by comparator 101 will be 35 This can be shared between transistor Q9 and transistor Q12. In other words, the switching control circuit 62 becomes easier to generate and control switching signals.

[0146] The inverting circuit 107 controls the voltage V 35 The voltage V obtained by logically inverting the above. 41 Outputs.

[0147] Voltage V output by the inverting circuit 107 41 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gates of transistors Q10 and Q11.

[0148] If the switching control circuit 62 synchronizes transistors Q10 and Q11, the voltage V output by the inverting circuit 107 41 This can be shared between transistors Q10 and Q11. In other words, the switching control circuit 62 becomes easier to generate and control switching signals.

[0149] (summary) As explained above, the switching control circuit 62 outputs the output voltage V out When lowering the switching frequency, if the switching frequency of each transistor is below the upper limit, a first control is performed to increase the switching frequency. Then, if the switching frequency of each transistor reaches the upper limit, the switching control circuit 62 performs a second control to lower the duty cycle of transistor Q1 (Q5, Q9) below the standard value while maintaining the switching frequency.

[0150] As a result, the power supply device 1 can further lower the output voltage V without complicating the control. out below the first control lower limit voltage.

[0151] It is preferable that the switching control circuit 62 makes the duty of the transistor Q4 (Q8, Q12) the same as the duty of the transistor Q1 (Q5, Q9).

[0152] As a result, the switching control circuit 62 can share one switching signal (voltage V in FIG. 8) 33 between the transistor Q1 and the transistor Q4. That is, the switching control circuit 62 can easily generate a switching signal and can be easily controlled.

[0153] When the output current I out exceeds the threshold current, it is preferable that the transistors Q1 to Q12 are switched at a predetermined duty.

[0154] As a result, the overcurrent protection control circuit 61 can out suppress the output current I.

[0155] (Supplementary Note) The control circuit 20 may provide hysteresis when switching between the first control and the second control. For example, the error amplifier 94 (see FIG. 8) may be replaced with a hysteresis comparator.

[0156] As a result, the control circuit 20 can suppress frequent switching between the first control and the second control.

[0157] The control circuit 20 may perform PSM control (see Non-Patent Document 2) in the case of the second control.

[0158] <Second Embodiment> In the second embodiment, components identical to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0159] (Overall configuration of the power supply unit) The overall configuration of the power supply unit in the second embodiment is the same as that of the power supply unit 1 in the first embodiment (see Figure 1), so its illustration and description are omitted.

[0160] (Overview of the control system) In the first embodiment, the control circuit synchronizes transistors Q1 (Q5, Q9) and Q4 (Q8, Q12) (in phase and with the same duty cycle), and synchronizes transistors Q2 (Q6, Q10) and Q3 (Q7, Q11).

[0161] The current in the primary circuits of transformers 41, 42, and 43 changes significantly when transistor Q1 (Q5, Q9) changes from the off state to the on state and when transistor Q3 (Q7, Q11) changes from the off state to the on state.

[0162] In the waveforms 211 and 213 of the second control (timing t0 onwards) shown in Figure 3, the timing at which the current in the primary circuits of transformers 41, 42, and 43 changes significantly is biased towards the first half of the control period 218. Therefore, a large ripple current may flow through capacitor 14 (see Figure 1).

[0163] Therefore, in the second embodiment, the control circuit reduces the duty cycle of transistor Q1 (Q5, Q9) and also reduces the duty cycle of transistor Q3 (Q7, Q11) during the second control.

[0164] Furthermore, in the second control, it is preferable to set the duty cycle of transistor Q1 (Q5, Q9) and transistor Q3 (Q7, Q11) to be the same. This makes it easier for the control circuit to generate switching signals, as will be described later.

[0165] Figure 10 shows an example of the waveform of the switching signal of the first phase arm of the power supply unit according to the second embodiment. Note that the dead time is omitted in Figure 10.

[0166] Waveform 241 shows the switching signal input to the gate of transistor Q1. Waveform 242 shows the switching signal input to the gate of transistor Q2. Waveform 243 shows the switching signal input to the gate of transistor Q3. Waveform 244 shows the switching signal input to the gate of transistor Q4.

[0167] The switching signal input to the gate of transistor Q1 (waveform 241) and the switching signal input to the gate of transistor Q2 (waveform 242) change complementaryly. The switching signal input to the gate of transistor Q3 (waveform 243) and the switching signal input to the gate of transistor Q4 (waveform 244) change complementaryly.

[0168] timing t 20 Up to this point, the control circuit, as its first control, increases the frequency while maintaining the duty cycle of each switching signal at its standard value.

[0169] timing t 20 Up to this point, the on-period 245 of the switching signal (waveform 241) input to the gate of transistor Q1 is half of one period 246.

[0170] As a result, the power supply unit will have an output voltage V out This can be reduced to the first control lower limit voltage.

[0171] timing t 20When the frequency of each switching signal reaches the upper limit, as a second control, the control circuit reduces the duty of the switching signal (waveform 241) input to the gate of transistor Q1 below the standard value while maintaining the frequency of each switching signal at the upper limit. At the same time, the control circuit reduces the duty of the switching signal (waveform 243) input to the gate of transistor Q3 below the standard value.

[0172] Timing t 20 Thereafter, the on-period 247 of the switching signal (waveform 241) input to the gate of transistor Q1 is less than half of one cycle 248. The on-period 249 of the switching signal (waveform 243) input to the gate of transistor Q3 is less than half of one cycle 250.

[0173] Note that at timing t 20 Thereafter, it is preferable that the control circuit makes the duty of the switching signal (waveform 243) input to the gate of transistor Q3 the same as the duty of the switching signal (waveform 241) input to the gate of transistor Q1. Thereby, as will be described later, the control circuit makes it easier to generate the switching signal.

[0174] Thereby, the control circuit can make the rise of transistor Q1 and the rise of transistor Q3 alternate (at equal intervals in the case of a 180° phase difference), so that the timing at which the primary-side currents of transformers 41, 42, and 43 change greatly can be shifted. Therefore, the power supply device can suppress the ripple current flowing through capacitor 14.

[0175] Note that it is preferable that the control circuit makes the phase difference between the phase of transistor Q1 and the phase of transistor Q3 180°. Thereby, as will be described later, the control circuit makes it easier to generate the switching signal.

[0176] (Configuration of the control circuit) Since the overall configuration of the control circuit of the second embodiment is the same as that of the control circuit 20 (see FIG. 5) of the first embodiment, illustration and description thereof are omitted.

[0177] Figure 11 shows an example of the configuration of the overcurrent protection control circuit of the power supply device according to the second embodiment.

[0178] Compared to the overcurrent protection control circuit 61 of the first embodiment (see Figure 6), the overcurrent protection control circuit 121 further includes a triangular wave signal source 79, a comparator 80, and an inverting circuit 81.

[0179] The triangular wave signal source 79 outputs the triangular wave signal V 13 A triangular wave signal V of the same frequency but in opposite phase (phase difference -180°) 16 This is output to the non-inverting input terminal (+ terminal) of comparator 80.

[0180] The inverting input terminal (- terminal) of comparator 80 receives a voltage V 12 The following is entered.

[0181] Comparator 80 receives a triangular wave signal V 16 The voltage is voltage V 12 If it is higher than, the high-level voltage V 17 It outputs the following. Comparator 80 outputs the voltage V 12 is a triangular wave signal V 16 If the voltage is higher than the low-level voltage V 17 Outputs.

[0182] The voltage V output by comparator 80 17 This is input to the switching circuit 63 (see Figure 5) as signal S2, and the switching signal S SW This is output to the gate of transistor Q1 (Q5, Q9).

[0183] The inverting circuit 81 controls the voltage V 17 The voltage V obtained by logically inverting the above. 18 Outputs.

[0184] Voltage V output by the inverting circuit 81 18 This is input to the switching circuit 63 (see Figure 5) as signal S2, and the switching signal S SWThis is output to the gate of transistor Q2 (Q6, Q10).

[0185] The voltage V output by comparator 76 14 This is input to the switching circuit 63 (see Figure 5) as signal S2, and the switching signal S SW This is output to the gate of transistor Q3 (Q7, Q11).

[0186] Voltage V output by the inverting circuit 77 15 This is input to the switching circuit 63 (see Figure 5) as signal S2, and the switching signal S SW This is output to the gate of transistor Q4 (Q8, Q12).

[0187] As a result, the overcurrent protection control circuit 121 outputs current I out If the current is higher than the overcurrent threshold by a certain value, control can be performed with a predetermined duty cycle. In addition, the overcurrent protection control circuit 121 can shift the phases of transistors Q1 and Q2 and transistors Q3 and Q4 (for example, a phase difference of -180°).

[0188] Figure 12 shows another example of the configuration of the overcurrent protection control circuit of the power supply unit according to the second embodiment.

[0189] Compared to the overcurrent protection control circuit 121 (see Figure 11), the overcurrent protection control circuit 122 includes an error amplifier 78 instead of a hysteresis comparator 74.

[0190] The non-inverting input terminal (+ terminal) of the error amplifier 78 has a voltage V 11 The following is input. The inverting input terminal (- terminal) of the error amplifier 78 is connected to the reference voltage V Iref The following is entered.

[0191] Error amplifier 78 uses voltage V 11 and reference voltage V Iref Voltage V corresponding to the difference 21 This is output to the inverting input terminal (- terminal) of comparator 80.

[0192] Comparator 80 receives a triangular wave signal V 16 The voltage is voltage V 12 If it is higher than, the high-level voltage V 17 It outputs the following. Comparator 80 outputs the voltage V 12 is a triangular wave signal V 16 If the voltage is higher than the low-level voltage V 17 Outputs.

[0193] As a result, the overcurrent protection control circuit 64 outputs current I out If the output current I exceeds the overcurrent threshold, out In response to the increase in [value], control can be performed to reduce the duty cycle of transistors Q1 (Q5, Q9) and Q4 (Q8, Q12).

[0194] Figure 13 shows the configuration of the switching control circuit of the power supply device according to the second embodiment.

[0195] In the second embodiment, the switching control circuit 123 controls the output voltage V out The present invention describes a case in which constant output voltage control is performed so that the output current I becomes the target voltage, but is not limited thereto. out Alternatively, constant output current control may be performed to ensure that the target current is reached.

[0196] Compared to the switching control circuit 62 (see Figure 8), the switching control circuit 123 includes a voltage-controlled oscillator 131 instead of a voltage-controlled oscillator 96. Furthermore, compared to the switching control circuit 62, the switching control circuit 123 further includes comparators 102, 103, and 104, and inverting circuits 108, 109, and 110.

[0197] The voltage-controlled oscillator 131 controls the triangular wave signal V tri1 This is output to the non-inverting input terminal (+ terminal) of comparator 99.

[0198] The voltage-controlled oscillator 131 controls the triangular wave signal V tri1The inverted triangular wave signal V tri1-n This is output to the non-inverting input terminal (+ terminal) of comparator 100.

[0199] The voltage-controlled oscillator 131 controls the triangular wave signal V tri2 This is output to the non-inverting input terminal (+ terminal) of comparator 101.

[0200] The voltage-controlled oscillator 131 controls the triangular wave signal V tri2 The inverted triangular wave signal V tri2-n This is output to the non-inverting input terminal (+ terminal) of comparator 102.

[0201] The voltage-controlled oscillator 131 controls the triangular wave signal V tri3 This is output to the non-inverting input terminal (+ terminal) of comparator 103.

[0202] The voltage-controlled oscillator 131 controls the triangular wave signal V tri3 The inverted triangular wave signal V tri3-n This is output to the non-inverting input terminal (+ terminal) of comparator 104.

[0203] Error amplifier 98 uses voltage V E2 This is output to the inverting input terminals (- terminals) from comparator 99 to comparator 104.

[0204] Comparator 99 receives a triangular wave signal V tri1 The voltage is voltage V E2 If it is higher than, the high-level voltage V 33 It outputs the following. Comparator 99 outputs the voltage V E2 is a triangular wave signal V tri1 If the voltage is higher than the low-level voltage V 33 Outputs.

[0205] The voltage V output by comparator 99 33 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gate of transistor Q3.

[0206] The inverting circuit 105 controls the voltage V 33 The voltage V obtained by logically inverting the above. 39 Outputs.

[0207] Voltage V output by the inverting circuit 105 39 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gate of transistor Q4.

[0208] Comparator 100 receives a triangular wave signal V tri1-n The voltage is voltage V E2 If it is higher than, the high-level voltage V 34 It outputs the voltage V. Comparator 100 outputs the voltage V. E2 is a triangular wave signal V tri1-n If the voltage is higher than the low-level voltage V 34 Outputs.

[0209] The voltage V output by comparator 100 34 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gate of transistor Q1.

[0210] The inverting circuit 106 controls the voltage V 34 The voltage V obtained by logically inverting the above. 40 Outputs.

[0211] Voltage V output by the inverting circuit 106 40 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gate of transistor Q2.

[0212] Figure 14 shows an example of the waveform of the switching control circuit of the power supply device in the second embodiment. Specifically, Figure 14 shows the voltage V output by the error amplifier 98. E2 Then, the voltage-controlled oscillator 131 outputs a triangular wave signal V tri1 and V tri1-nThis diagram shows the waveforms of the switching signal input to the gate of transistor Q1 and the switching signal input to the gate of transistor Q3.

[0213] Waveform 261 shows the voltage V output by the error amplifier 98. E2 This shows the triangular wave signal V. Waveform 262 is shown. tri1-n This shows that waveform 263 is a triangular wave signal V tri1 This shows the triangular wave signal V. tri1-n and V tri1 The voltage changes in both the positive and negative directions, centered around 0V.

[0214] Waveform 264 shows the switching signal input to the gate of transistor Q1. Waveform 265 shows the switching signal input to the gate of transistor Q3.

[0215] timing t 30 Up to this point, the voltage V output by the error amplifier 94 E1 Voltage V fmax-ref It shall be lower than . In this case, as shown in waveform 261, the voltage V output by the error amplifier 98 E2 This becomes 0V. Therefore, as shown in waveform 264, the duty cycle of the switching signal input to the gate of transistor Q1 becomes the standard value (0.5). On the other hand, as shown in waveform 265, the duty cycle of the switching signal input to the gate of transistor Q3 becomes the standard value, but is 180° out of phase with waveform 264.

[0216] timing t 30 In this case, the voltage V output by the error amplifier 94 E1 Voltage V fmax-ref When it becomes higher than this, the voltage V output by the error amplifier 98 E2 is the voltage V E1As the voltage increases, it rises from 0V. Therefore, as shown in waveform 264, the duty cycle of the switching signal input to the gate of transistor Q1 is less than the standard value (0.5). On the other hand, as shown in waveform 265, the duty cycle of the switching signal input to the gate of transistor Q3 is less than the standard value, and is 180° out of phase with waveform 264.

[0217] Refer to Figure 13 again. Comparator 101 receives the triangular wave signal V tri2 The voltage is voltage V E2 If it is higher than, the high-level voltage V 35 It outputs the voltage V. Comparator 101 outputs the voltage V. E2 is a triangular wave signal V tri2 If the voltage is higher than the low-level voltage V 35 Outputs.

[0218] The voltage V output by comparator 101 35 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gate of transistor Q7.

[0219] The inverting circuit 107 controls the voltage V 35 The voltage V obtained by logically inverting the above. 41 Outputs.

[0220] Voltage V output by the inverting circuit 107 41 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gate of transistor Q8.

[0221] Comparator 102 receives the triangular wave signal V tri2-n The voltage is voltage V E2 If it is higher than, the high-level voltage V 36 It outputs the voltage V. Comparator 102 outputs the voltage V. E2 is a triangular wave signal V tri2-n If the voltage is higher than the low-level voltage V 36 Outputs.

[0222] The voltage V output by comparator 102 36 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gate of transistor Q5.

[0223] The inverting circuit 108 controls the voltage V 36 The voltage V obtained by logically inverting the above. 42 Outputs.

[0224] Voltage V output by the inverting circuit 108 42 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gate of transistor Q6.

[0225] Comparator 103 receives the triangular wave signal V tri3 The voltage is voltage V E2 If it is higher than, the high-level voltage V 37 It outputs the following. Comparator 103 outputs the voltage V E2 is a triangular wave signal V tri3 If the voltage is higher than the low-level voltage V 37 Outputs.

[0226] The voltage V output by comparator 103 37 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gate of transistor Q11.

[0227] The inverting circuit 109 controls the voltage V 37 The voltage V obtained by logically inverting the above. 43 Outputs.

[0228] Voltage V output by the inverting circuit 109 43 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gate of transistor Q12.

[0229] Comparator 104 receives the triangular wave signal V tri3-nThe voltage is voltage V E2 If it is higher than, the high-level voltage V 38 It outputs the voltage V. Comparator 104 outputs the voltage V. E2 is a triangular wave signal V tri3-n If the voltage is higher than the low-level voltage V 38 Outputs.

[0230] The voltage V output by comparator 104 38 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gate of transistor Q9.

[0231] The inverting circuit 110 controls the voltage V 38 The voltage V obtained by logically inverting the above. 44 Outputs.

[0232] Voltage V output by the inverting circuit 110 44 This is input to the switching circuit 63 (see Figure 5) as signal S3, and the switching signal S SW This is output to the gate of transistor Q10.

[0233] (Circuit simulation) The circuit simulation results for the second embodiment will now be described.

[0234] Figure 1 shows the case with three phases (from the first phase arm 31 to the third phase arm 33), but the circuit simulation was performed for the case with one phase (only the first phase arm 31).

[0235] Figure 15 shows the circuit simulation results of the power supply device according to the second embodiment.

[0236] Waveform 271-1 shows the switching signal input to the gate of transistor Q1 in the case of the first control. Waveform 271-2 shows the switching signal input to the gate of transistor Q1 in the case of the second control.

[0237] Waveform 272-1 shows the switching signal input to the gate of transistor Q2 in the case of the first control. Waveform 272-2 shows the switching signal input to the gate of transistor Q2 in the case of the second control.

[0238] Waveform 273-1 shows the switching signal input to the gate of transistor Q3 in the case of the first control. Waveform 273-2 shows the switching signal input to the gate of transistor Q3 in the case of the second control.

[0239] Waveform 274-1 shows the switching signal input to the gate of transistor Q4 in the case of the first control. Waveform 274-2 shows the switching signal input to the gate of transistor Q4 in the case of the second control.

[0240] Comparing waveform 271-1 and waveform 271-2, waveform 271-2 has a lower duty cycle.

[0241] Comparing waveform 272-1 and waveform 272-2, waveform 272-2 has a higher duty cycle.

[0242] Comparing waveform 273-1 and waveform 273-2, waveform 273-2 has a lower duty cycle.

[0243] Comparing waveform 274-1 and waveform 274-2, waveform 274-2 has a higher duty cycle.

[0244] Figure 16 shows the circuit simulation results of the power supply device according to the second embodiment.

[0245] Waveform 281 shows the drain current of transistor Q1 in the second control case. Waveform 282 shows the drain current of transistor Q2 in the second control case. Waveform 283 shows the drain current of transistor Q3 in the second control case. Waveform 284 shows the drain current of transistor Q4 in the second control case.

[0246] As shown in Figure 16, power supply unit 1 achieves soft switching in the second control case. As a result, power supply unit 1 can suppress a decrease in efficiency and maintain high efficiency.

[0247] Figure 17 shows the circuit simulation results for the power supply unit of the second embodiment. Figure 17 shows the circuit simulation results when the output voltage command value changes from 80V to 200V.

[0248] Waveform 291 shows the output voltage command value. Waveform 292 shows the output voltage V out This indicates.

[0249] As shown in waveform 291, the output voltage command value is at timing t 40 Up to that point, it was constant at 80V, and the timing t 40 from timing t 50 Up until then, it was rising at a constant rate, timing t 50 From this point onward, the voltage remains constant at 200V. As shown in waveform 292, the output voltage V out It follows the output voltage command value.

[0250] Figure 18 shows the circuit simulation results of the power supply unit of the second embodiment. Figure 18 shows the timing t in Figure 17. 40 The waveforms of the surrounding areas are shown.

[0251] timing t 40 In the vicinity, the output voltage command value and the output voltage V out Since the voltage is low at 80V, the second control is executed.

[0252] Waveform 301 shows the drain current of transistor Q1. Waveform 302 shows the drain current of transistor Q2.

[0253] Waveform 303 shows the drain-source voltage waveform of transistor Q1. Waveform 304 shows the drain-source voltage waveform of transistor Q2.

[0254] As shown in waveforms 301 to 304, soft switching is achieved. As a result, power supply unit 1 can suppress a decrease in efficiency and maintain high efficiency.

[0255] As shown in waveforms 303 and 304, the duty cycle of the switching signals input to the gates of transistors Q1 and Q2 is the timing t 40 Up to this point, the output voltage command value and output voltage V out Since it is constant at 80V, it is constant.

[0256] timing t 40 Up to this point, the output voltage command value and output voltage V out The duty cycle is very low. Therefore, as shown in waveform 303, the duty cycle of the drain-source voltage waveform of transistor Q1 is very small. On the other hand, as shown in waveform 304, the duty cycle of the drain-source voltage waveform of transistor Q2 is very large.

[0257] timing t 40 From here on, the output voltage command value and output voltage V out The voltage is rising. Therefore, as shown in waveform 303, the duty cycle of the drain-source voltage waveform of transistor Q1 is increasing. On the other hand, as shown in waveform 304, the duty cycle of the drain-source voltage waveform of transistor Q2 is decreasing.

[0258] Figure 19 shows the circuit simulation results of the power supply unit in the second embodiment. Figure 19 shows the timing t in Figure 17. 35 The waveforms of the surrounding areas are shown.

[0259] timing t 35 In the vicinity, the output voltage command value and the output voltage V out Since the voltage is low at 80V, the second control is executed.

[0260] Waveform 305 shows the switching signal input to the gate of transistor Q3. Waveform 306 shows the switching signal input to the gate of transistor Q4.

[0261] Since the second control is executed, the duty cycle of the switching signals input to the gates of transistors Q1 and Q3 is reduced, as shown in waveforms 303 and 305.

[0262] As shown in waveform 304, the switching signal input to the gate of transistor Q2 changes complementaryly to the switching signal input to the gate of transistor Q1 (waveform 303).

[0263] As shown in waveform 306, the switching signal input to the gate of transistor Q4 changes complementaryly to the switching signal input to the gate of transistor Q3 (waveform 305).

[0264] Figure 20 shows the circuit simulation results of the power supply unit of the second embodiment. Figure 20 shows the timing t in Figure 17. 50 The waveforms of the surrounding areas are shown.

[0265] timing t 50 In the vicinity, the output voltage command value and the output voltage V out Since the voltage is high at 200V, the first control is executed.

[0266] Waveform 311 shows the drain current of transistor Q1. Waveform 312 shows the drain current of transistor Q2.

[0267] Waveform 313 shows the drain-source voltage waveform of transistor Q1. Waveform 314 shows the drain-source voltage waveform of transistor Q2.

[0268] As shown in waveforms 311 to 314, soft switching is achieved. As a result, the power supply unit 1 can suppress a decrease in efficiency and maintain high efficiency.

[0269] Since the first control is performed, the duty cycle of the drain-source voltage waveforms of transistors Q1 and Q2 is constant at the standard value, as shown in waveforms 313 and 314.

[0270] As shown in waveforms 313 and 314, the frequencies of the drain-source voltage waveforms of transistors Q1 and Q2 are at timing t. 50 Up to this point, the output voltage command value and output voltage V out It is rising at a constant rate, so it is falling.

[0271] timing t 50 From here on, the output voltage command value and output voltage V out This is constant. Therefore, as shown in waveforms 313 and 314, the frequencies of the drain-source voltage waveforms of transistors Q1 and Q2 are constant.

[0272] Figure 21 shows the circuit simulation results of the power supply unit of the second embodiment. Figure 21 shows the timing t in Figure 17. 55 The waveforms of the surrounding areas are shown.

[0273] timing t 55 In the vicinity, the output voltage command value and the output voltage V out Since the voltage is high at 200V, the first control is executed.

[0274] Waveform 315 shows the switching signal input to the gate of transistor Q3. Waveform 316 shows the switching signal input to the gate of transistor Q4.

[0275] Since the first control is performed, the duty cycle of the switching signals input to the gates of transistors Q1 to Q4 is constant at the standard value, as shown in waveforms 313 to 316.

[0276] timing t 55 In the vicinity, the output voltage command value and the output voltage V out The voltage is constant at 200V. Therefore, as shown in waveforms 313 to 316, the frequency of the switching signal input to the gates of transistors Q1 to Q4 is constant.

[0277] (summary) The power supply device of the second embodiment provides the same effects as the power supply device 1 of the first embodiment, in addition to the following effects.

[0278] In the second embodiment, the switching control circuit 123 reduces the duty cycle of transistor Q1 (Q5, Q9) and also reduces the duty cycle of transistor Q3 (Q7, Q11) during the second control.

[0279] As a result, the switching control circuit 123 can alternate the rising times of transistor Q1 (Q5, Q9) and transistor Q3 (Q7, Q11) (at equal intervals when the phase difference is 180°), thereby shifting the timing of large changes in the primary currents of transformers 41, 42, and 43.

[0280] Therefore, the power supply unit can suppress the ripple current flowing through the capacitor 14.

[0281] It is preferable that the switching control circuit 123 sets the duty cycle of the switching signal input to the gate of transistor Q3 (Q7, Q11) to be the same as the duty cycle of the switching signal input to the gate of transistor Q1 (Q5, Q9).

[0282] This makes it easier for the switching control circuit 123 to generate switching signals and to control them.

[0283] The switching control circuit 123 preferably sets the phase difference between the phase of transistor Q1 (Q5, Q9) and the phase of transistor Q3 (Q7, Q11) to 180°.

[0284] This makes it easier for the switching control circuit 123 to generate switching signals and to control them.

[0285] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0286] 1 Power supply 2 power supply 3, 4 resistors 5, 6, 14 Capacitors 11 Bridge Circuit 12 Transformer Circuits 13 Rectifier circuit 15 Voltage Sensor 16 Current Sensor 20 Control circuits 31. First phase arm 32 Phase 2 Arm 33 Third-phase arm 41, 42, 43 Transformers 61, 64, 121, 122 Overcurrent protection control circuits 62, 123 Switching control circuit 63 Switching circuit 65 Dead Time Generation Circuit

Claims

1. A bridge circuit comprising a first switching element, a second switching element, a third switching element, and a fourth switching element connected in series, wherein a first DC voltage is input to one end of the high-potential side of the first switching element, a second DC voltage lower than the first DC voltage is input to the connection point between the second and third switching elements, and at least one phase arm of the fourth switching element is electrically connected to a reference potential, A transformer circuit comprising: a primary circuit of at least one phase to which the output voltage of the arm is input and resonates; and a secondary circuit of at least one phase that is electromagnetically coupled with the primary circuit and outputs an AC voltage; A rectifier circuit for rectifying the aforementioned AC voltage, A smoothing circuit that smooths the voltage output from the rectifier circuit, A control circuit that changes the second switching signal complementary to the first switching signal, changes the fourth switching signal complementary to the third switching signal, and outputs the first to fourth switching signals to the first to fourth switching elements such that the voltage of the smoothing circuit becomes the command value voltage or the current output from the rectifier circuit becomes the command value current, Equipped with, The aforementioned control circuit is In the first case where the frequencies from the first switching signal to the fourth switching signal are below a predetermined frequency, a first control is performed to maintain the duty cycle from the first switching signal to the fourth switching signal at a standard value and change the frequency. In the second case, when the frequencies from the first switching signal to the fourth switching signal reach the predetermined frequency, a second control is performed to maintain the frequencies from the first switching signal to the fourth switching signal at the predetermined frequency and to reduce the duty cycle of the first switching signal to a value smaller than the standard value. In the second case described above, the duty cycle of the third switching signal is made smaller than the standard value, In the second case described above, the duty cycle of the third switching signal is made the same as the duty cycle of the first switching signal. A power supply device characterized by the following features.

2. The aforementioned control circuit is In the second case, the duty cycle of the fourth switching signal is made the same as the duty cycle of the first switching signal. The power supply device according to claim 1, characterized in that

3. The aforementioned control circuit is In the second case described above, the phase difference between the phase of the first switching signal and the phase of the third switching signal is set to 180°. The power supply device according to claim 1, characterized in that

4. The aforementioned control circuit is When the output current from the rectifier circuit exceeds the threshold current, the first switching signal to the fourth switching signal are set to a predetermined duty cycle or a duty cycle corresponding to the output current. A power supply device according to any one of claims 1 to 3, characterized in that

5. The aforementioned control circuit is Hysteresis is provided when switching between the first control and the second control. A power supply device according to any one of claims 1 to 4, characterized in that

6. The aforementioned control circuit is In the case of the second control described above, PSM (Periodically Swapping Modulation) control is performed. A power supply device according to any one of claims 1 to 5, characterized in that

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