Semiconductor equipment

Abstract

To provide a semiconductor device capable of achieving an off state without causing an increase in power consumption.SOLUTION: The semiconductor device includes: a power element under an on state without a voltage applied to a gate; a switching field effect transistor for applying a first voltage to a gate of the power element; and a switching field effect transistor for applying a lower voltage than the first voltage to the gate of the power element. The switching field effect transistor has a low off current.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Or a method for driving a semiconductor device. Or an electronic device including a semiconductor device.

[0002] In addition, in this specification and the like, the semiconductor device generally refers to a device that can function by utilizing semiconductor characteristics. For example, a power device, a display device having the power device, and an integrated circuit are included in the semiconductor device.

Background Art

[0003] Among semiconductor devices used as power devices, power devices made of silicon-based materials are widely distributed. Since a power device using silicon has a small bandgap, there is a limit to its operating range at high temperatures. For this reason, in recent years, the development of power devices using SiC or GaN having a wide bandgap has been carried out (for example, refer to Patent Document 1).

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] There is a HFET (heterojunction field effect transistor) as a power device using GaN. The HFET has a structure in which an AlN layer, a GaN layer, and an AlGaN layer, which are buffer layers, are stacked on a SiC substrate, and source electrodes, gate electrodes, and drain electrodes are provided on the AlGaN layer. ​​​​​​​​​It has the following characteristics. Furthermore, due to the difference in the band gap between the GaN layer and the AlGaN layer, the GaN layer and A high-concentration two-dimensional electron gas layer is formed at the interface of the AlGaN layer. Because the conductive band has an energy level lower than the Fermi level, in HFETs there is a two-dimensional electron gas layer. This acts as a channel, and current flows even when no voltage is applied to the gate (normally oscillator). This situation, where the drive and protection circuits become complex, is causing problems. If you simply reduce the electron concentration to make it normally off, then the resistance of the device will increase. Therefore, achieving both normally-off operation and low resistance is extremely difficult. Also, the device structure Attempts have been made to achieve normally-off mode by devising ways to modify the device structure, but This presents problems such as increased complexity and higher manufacturing costs.

[0006] Therefore, one embodiment of the present invention is to achieve an off state without increasing power consumption. The objective is to provide a semiconductor device that can perform this function. [Means for solving the problem]

[0007] One embodiment of the present invention is a power element that is in the ON state when no voltage is applied to the gate, and , a field-effect transistor for switching to apply a first voltage to the gate of a power element A switch for applying a voltage lower than the first voltage to the gate of a power element. The field-effect transistor is an A-f It is a semiconductor device with a low current. Furthermore, the field-effect transistor used for switching is, Semiconductor devices in which the channel region is formed by an i-type or substantially i-type oxide semiconductor layer This is the configuration. A field-effect transistor for switching brings a high potential to the gate of the power element. Alternatively, a low potential is applied to obtain the ON and OFF states of the power element.

[0008] One embodiment of the present invention is an acid having a first gate and a second gate, and having an n-type channel region. A power MOSFET formed with a semiconductor layer, and the first gate and A switching field-effect transistor for applying a positive voltage to the second gate, and A switch for applying a negative voltage to the first and second gates of a MOSFET. It has a field-effect transistor for the gate, and the first gate and second gate of the power MOSFET The node of the terminal is connected to a field-effect transistor for switching, and the above switching Oxide semiconductor with i-type or substantially i-type channel region in field-effect transistor. It is a semiconductor device formed in layers. Power is generated by field-effect transistors for switching. - Applying a high or low potential to the first and second gates of the MOSFET, power - Obtain the ON and OFF states of the MOSFET.

[0009] Furthermore, one embodiment of the present invention includes a first field-effect transistor connected to a high-voltage source, and a first A second field-effect transistor connected to the first field-effect transistor, and the second field-effect transistor A third field-effect transistor connected to the generator and also connected to a low-voltage source, and a second A field-effect transistor and a capacitive element connected to a third field-effect transistor, and a first electric A power MOSFET connected to a field-effect transistor and a second field-effect transistor The power MOSFET has a first gate and a second gate, and a gate in contact with the first gate. A first insulating layer, a second insulating layer in contact with the second gate, and the first insulating layer and the second insulating layer An oxide semiconductor layer formed between, a first terminal and a second terminal that function as a source region and a drain region in contact with the oxide semiconductor layer, and the gates of the first gate and the second gate are connected to the first field effect transistor and the second field effect transistor. The channel formation regions of the first field effect transistor to the third field effect transistor are formed of an i-type oxide semiconductor layer, and the oxide semiconductor layer of the power MOSFET is an n-type semiconductor device. The carrier concentration of the oxide semiconductor layer of the power MOSFET is 1×10 or more and 1×1 0 or less, preferably 1×10 or more and 1×10

[0010] or less. 16 cm -3 20 cm -3 17 cm -3 20 cm -3

[0011] For the field effect transistor for switching, the carrier concentration of the oxide semiconductor layer of the first field effect transistor to the third field effect transistor is less than 5×10 14 cm -3

[0012] The first gate or the second gate of the power MOSFET may overlap with one of the first terminal and the second terminal and may not overlap with the other.

Advantages of the Invention

[0013] According to one embodiment of the present invention, it is possible to provide a power device that can achieve an off state without causing an increase in power consumption and a semiconductor device having the same.

Brief Description of the Drawings

[0014] ​​​​​​​​​​ [Figure 1] This is an equivalent circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 2] This is an equivalent circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 3] This is an equivalent circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 4] This is an equivalent circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 5] These are a cross-sectional view and a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 6] This is a cross-sectional view illustrating a semiconductor device according to one aspect of the present invention. [Figure 7] This is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 8] This is a cross-sectional view illustrating a semiconductor device according to one aspect of the present invention. [Figure 9] These are a cross-sectional view and a top view illustrating a semiconductor device according to one embodiment of the present invention. [Figure 10] This is a cross-sectional view illustrating a semiconductor device according to one aspect of the present invention. [Figure 11] This is a cross-sectional view illustrating the manufacturing process of a semiconductor device according to one embodiment of the present invention. [Figure 12] This is an equivalent circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 13] This is an equivalent circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 14] This is an equivalent circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 15] This is an equivalent circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 16] This is an equivalent circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 17] This is an equivalent circuit diagram illustrating a semiconductor device according to one embodiment of the present invention. [Figure 18] This is a diagram illustrating electronic devices. [Modes for carrying out the invention]

[0015] Embodiments of the present invention will be described below with reference to the drawings. However, the present invention is not limited to many. It is possible to carry out the invention in different forms, without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that its form and details can be changed in various ways. This embodiment is not to be interpreted as being limited to its description. In the composition of drawings, symbols indicating the same object should be consistent across different drawings.

[0016] Furthermore, the size, layer thickness, or area of ​​each component shown in the drawings of each embodiment is as follows: The figures may be exaggerated for clarity. Therefore, they are not necessarily limited to that scale. It is not determined.

[0017] Furthermore, the terms 1st, 2nd, 3rd, through Nth (where N is a natural number) used herein are defined as follows: This is added to avoid confusion regarding the constituent elements and does not mean that the number is limited. do.

[0018] Furthermore, voltage is the potential difference between a certain potential and a reference potential (for example, ground potential). It is often used to indicate these things. Therefore, voltage, potential, and potential difference are often rephrased as potential, voltage, and voltage difference, respectively. It is possible to do so.

[0019] Furthermore, if it is explicitly stated that A and B are connected, it means that A and B are electrically connected. When A and B are functionally connected, and when A and B are directly connected This includes cases where A and B are objects (e.g., devices, elements, circuits). (Wiring, electrodes, terminals, conductive layer, layer, etc.) are assumed to be. Therefore, a predetermined connection relationship, For example, not limited to the connection relationships shown in the diagram or text, This includes those who are not in charge of the department.

[0020] (Embodiment 1) In this embodiment, the circuit configuration and operation of a semiconductor device, which is a power device, are described below. explain.

[0021] The semiconductor device shown in Figure 1 includes a power element 110 and a control circuit 100. 0 is a field-effect transistor 102 (also called the first transistor), field-effect transistor Zistor 103 (also called the second transistor), field-effect transistor 104 (the third Also called a transistor.), Capacitive element 105, Overvoltage detection circuit 106, Refresh control It has a circuit 107, a high-voltage source 108, and a low-voltage source 109.

[0022] The control circuit 100 generates the voltage to be applied to the power element 110 using the high voltage source 108. Switch to the low voltage generated by the high-voltage or low-voltage source 109, and input terminal I The amount of current flowing through the power element 110 when an overvoltage is applied between N and the output terminal OUT. Control.

[0023] The field-effect transistor 102 has its gate connected to the overvoltage detection circuit 106, and the first terminal The first terminal is connected to the high-voltage source 108, and the second terminal is connected to the power element 110. Transistor 102 applies a high potential to the power element 110 connected to the second terminal. To control.

[0024] The field-effect transistor 103 has its gate connected to the overvoltage detection circuit 106, and the first terminal The capacitive element 105 and the second terminal of the field-effect transistor 104 are connected to the second terminal This is connected to the power element 110.

[0025] The field-effect transistor 103 receives low voltage from the low voltage source 109 to charge the capacitive element 105. This controls the application of potential to the power element 110 connected to the second terminal.

[0026] In this specification, the off-current refers to the current that occurs when the field-effect transistor is not conducting. This refers to the current flowing between the first terminal and the drain, that is, between the first terminal and the second terminal.

[0027] The field-effect transistor 104 has its gate connected to the refresh control circuit 107, and the first The first terminal is connected to the low voltage source 109, and the second terminal is connected to the capacitive element 105 and the field effect transistor. The first terminal of transistor 103 is connected to the second terminal of field-effect transistor 104. This controls the low-potential charging of the connected capacitive element 105.

[0028] The channel region of field-effect transistors 102 to 104 is i-shaped. Alternatively, it is formed of a substantially i-type oxide semiconductor layer. i-type or substantially i-type The oxide semiconductor layer has a carrier density of 5 × 10 14 cm -3 Less than 1 × 1 0 12 cm -3 Less than 1 × 10 11 cm -3 The following applies. Also, the donor and It is preferable that there are few hydrogen and oxygen vacancies contributing to this, and the hydrogen concentration is 1 × 10⁻⁶ 16 cm -3 The following is preferable. The carrier density is obtained by Hall effect measurement. The carrier density of a concentration is measured using CV (Capacitance-Voltage-M). This is obtained from the measurement results of the easement. Also, the hydrogen concentration in the oxide semiconductor layer The measurement is performed using secondary ion mass spectrometry (SIMS). Obtained by pectrometry.

[0029] Field-effect transistor using i-type or substantially i-type oxide semiconductor in the channel region ZISTA 102 has an off-current of 1 × 10⁻⁶ -16 A / μm or less, and even 1 × 10⁻⁶ -19 A / It can be made smaller than μm. I-type or substantially I-type oxide semiconductors Because the band gap is wide and a large amount of thermal energy is required to excite electrons, Contact recombination and indirect recombination are less likely to occur. Therefore, when a negative potential is applied to the gate electrode... In the off state, the number of minority carriers, or holes, is practically zero, so direct recombination occurs. Furthermore, indirect recombination is less likely to occur, and the current becomes infinitely small. As a result, field-effect transients In the non-conductive (also called off) state of the sta, the oxide semiconductor layer is considered an insulator. Circuit design can be performed accordingly. On the other hand, i-type or substantially i-type oxide semiconductors In the conductive state of the field-effect transistor, the conductive layer is formed of amorphous silicon. A higher current supply capability can be expected than that of a conductive layer. Therefore, a field-effect transistor... The field-effect transistors 102 through 104 are enhancement type and are polar in the off state. It exhibits excellent switching characteristics, as it enters a normally-off state with low leakage current.

[0030] Capacitive element 105 causes intermittent conduction (also called turning on) of the field-effect transistor 104. Capacitive element 1 is an element for maintaining a low potential applied to the power element 110. For 05, it can be formed by a structure in which the insulating layer is sandwiched between conductive materials.

[0031] The overvoltage detection circuit 106 detects the electric field effect in accordance with the voltage between the input terminal IN and the output terminal OUT. To control the conduction or non-conductivity of the field-effect transistor 102 and the field-effect transistor 103. This is a circuit where an overvoltage is applied between the input terminal IN and the output terminal OUT. At that time, the field-effect transistor 102 is made conductive and the field-effect transistor 103 is made non-conductive. The high voltage source 108 controls the application of a high potential to the power element 110. Also, the input terminal When no overvoltage is applied between the IN terminal and the OUT terminal, the field-effect transistor 1 By making 02 non-conductive and field-effect transistor 103 conductive, a low voltage is generated to power element 110. The application of a low potential charged to the capacitive element 105 from the power source 109 is controlled.

[0032] The refresh control circuit 107 charges the capacitive element 105 with a low potential from the low voltage source 109. In order to control the current, a circuit controls the conduction or non-conductivity of the field-effect transistor 104. Yes. Specifically, the low voltage is maintained by charging the capacitive element 105 from the low voltage source 109. Before the potential discharges to the power element 110, the field-effect transistor 104 is intermittently made to conduct. It is a circuit for low-potential charging.

[0033] The power element 110 uses a power element that turns on when no voltage is applied to its gate. The power element 110 uses Si, SiC, GaN, and oxide semiconductors, and is bipod. Field-effect transistor (FET) Insulated gate bipolar transistor (IGBTs) and the like can be used as appropriate. Also, in field-effect transistors, power MOSFET (Metal Oxide Semiconductor FET), Use HFETs, JFETs (junction junction field-effect transistors), etc., as appropriate. This is possible. The equivalent circuit of the 3-terminal power element 121 is shown in Figure 2(A). Power element 121 The gates are connected to field-effect transistors 102 and 103. Furthermore, one of the source terminals and drain terminals of the power element 121 is designated as the first terminal, and the source terminal If the other end of the child and drain terminals is designated as the second terminal, then the first terminal is connected to the input terminal IN. The second terminal is connected to the output terminal OUT.

[0034] In this embodiment, a representative example of the power element 110 will be shown in Figure 2(B). Next, we will explain using a 4-terminal power MOSFET 101.

[0035] The power MOSFET 101 has four terminals, typically the first gate terminal (first gate (referred to as the gate), the second gate terminal (referred to as the second gate), and the drain terminal (referred to as the drain and It has a (also called) and a source terminal (also called source). Power MOSFET 101 is A first gate and a second gate are positioned above and below the channel region, and the first gate and the second A signal controlling the switching of the power MOSFET 101 is supplied to its gate.

[0036] Power M has a first gate 201 and a second gate 206 positioned above and below the channel region. The circuit symbol for OSFET101 is shown in Figure 2(C). As shown in Figure 2(C), the power MO SFET101 has a first gate 201, a second gate 206, and a first terminal 204A. The power MOSFET 101 has a first gate 201 The output from the high voltage source 108 or the low voltage source 109 is also output to the second gate 206. A signal (signal G shown in Figure 2(C)) is input. High voltage source 108 or low voltage source From the signal output from 109, the first terminal 204A of power MOSFET 101 and The switching between conduction and non-conductivity between terminals 2 and 204B is controlled.

[0037] Even if the channel region of the power MOSFET 101 is formed with an n-type oxide semiconductor layer Good. An n-type oxide semiconductor layer has a carrier density of 1 × 10⁻⁶. 16 cm -3 The above 1 x 10 20 cm -3 The following is preferably 1 × 10 17 cm -3 The above 1 x 10 20 cm -3 Below Furthermore, in oxide semiconductors, hydrogen and oxygen vacancies contribute as donors, Concentration is 1 × 10 16 cm -3 The above 1 x 10 20 cm -3 It is preferable that this be the case.

[0038] Since the power MOSFET 101 has an n-type oxide semiconductor layer in the channel region, Compared to a power MOSFET having an i-type oxide semiconductor layer in the channel region, the on-resistance It is possible to reduce resistance and allow large currents to flow. However, in the n type Because it has an oxide semiconductor layer in the channel region, it is a depletion type, and electricity is supplied to the gate. This is a normally-on element, meaning that current flows even when no pressure is applied. The power MOSFET has a second gate 206 along with a first gate 201. It is possible to turn off the gates by applying a negative voltage to gate 201 and the second gate 206. Therefore, power MOSFETs have low on-resistance and can handle large currents. This can be turned off. On the other hand, positive voltage is applied to the first gate 201 and the second gate 206. It can be turned on by applying pressure. Also, the power MOSFET 101 is Since it has one gate 201 and a second gate 206, it is a single-gate power MOS. Compared to FETs, increasing the thickness of the channel region makes the threshold voltage more negative. It is possible to increase the on-current.

[0039] Next, the operation of the semiconductor device shown in Figure 2(B) will be explained using Figures 3 and 4. Figure 3 In the explanation in Figure 4, the dotted arrows indicate the power MOSFET 101 and each field-effect transistor. To make the signal flow due to the conduction or non-conductivity of the transistor easier to understand, it is visualized and shown. Furthermore, in the channel region of the power MOSFET 101 that constitutes the semiconductor device It uses an n-type oxide semiconductor layer and conducts due to the high potential from the high voltage source 108. Therefore, it becomes non-conductive due to the low potential from the low voltage source 109. (See Figure 2(A)) The operation of the semiconductor device shown is as follows in the equivalent circuit shown in Figures 3 and 4: Power MOSFET Replace 101 with power element 121.

[0040] Figure 3(A) illustrates the operation when power MOSFET 101 is conductive. The voltage detection circuit 106 controls the field-effect transistor 102 to conduct, By deconducting the zista 103 and controlling the refresh control circuit 107, the field-effect transient By making transistor 104 non-conductive, and field-effect transistor 102 conductive, A high potential is supplied from the high voltage source 108 to the first gate and second gate of the power MOSFET 101. When power is applied to the circuit, the power MOSFET 101 becomes conductive.

[0041] Figure 3(B) illustrates the operation when power MOSFET 101 is made non-conductive. The overvoltage detection circuit 106 controls the field-effect transistor 102 to deconduct, thus eliminating the field effect. By making transistor 103 conductive and controlling the refresh control circuit 107, the field effect The transistor 104 is made non-conductive. As shown in Figure 3(B), the field-effect transistor 1 By making 03 conductive, the low voltage generated by the low voltage source 109 charges the capacitive element 105. A potential is applied to the first and second gates of the power MOSFET 101, and power M OSFET101 becomes non-conductive.

[0042] Figure 3(C) illustrates the operation of charging the capacitive element 105 with a low potential, as described in Figure 3(B). It is explained that the overvoltage detection circuit 106 controls the field-effect transistor 102 to deconduct, and the power The field effect transistor 103 is made conductive, and the refresh control circuit 107 controls the electric field. The effect transistor 104 is made conductive, and a low potential is introduced from the low voltage source 109 to the capacitive element 105. Charge it.

[0043] Furthermore, the low-potential charging of the capacitive element 105 described in Figure 3(C) is performed by the refresh control circuit 1 Controlled by 07, this is performed at regular intervals. Specifically, charging from the low voltage source 109. This maintains a low potential that causes the power MOSFET 101 to become non-conductive through the capacitive element 105. During this time, the semiconductor device maintains the state shown in Figure 3(B). Then, intermittently, it switches to the state shown in Figure 3(C). Then, the field-effect transistor 104 is made conductive, and the capacitive element 105 is charged with a low potential. For example, the operation shown in Figure 3(C) should be performed once every minute, taking sufficient time for charging. .

[0044] As described above, in the configuration of this embodiment, the state in Figure 3(A) or the state in Figure 3(B) The state repeats between this state and the state shown in Figure 3(C), but the period during which the state shown in Figure 3(B) is maintained becomes longer.

[0045] Here, the effects of this embodiment will be described in detail using Figure 4(A). Figure 4(A) is the same as described above. In the state shown in Figure 3(B), the first gate and second gate of the power MOSFET 101 A node connected to the terminal, a field-effect transistor 103, and one end of a capacitive element 105 The child element is represented by a solid line, while other connections are shown by a dashed line.

[0046] As a result of field-effect transistors 102 and 104 becoming non-conductive The nodes connected to the first and second gates of the power MOSFET 101 are electric It enters a state of floating (floating) in terms of energy. As mentioned above, field-effect transistor 1 02 and the field-effect transistor 104 have an i-type or substantially i-type channel region. Because it is composed of a specially treated oxide semiconductor layer, the off-current is extremely low. Therefore, the power M The nodes connected to the first and second gates of OSFET101 are low voltage sources. The low potential charged from 109 to the capacitive element 105 can be maintained for a long period of time. Instead of applying a low potential to the capacitive element without applying it, it is sufficient to apply a low potential to the capacitive element intermittently. Also, power -When a low potential is applied to the first and second gates of MOSFET 101, power M OSFET101 is in the off state. Therefore, the semiconductor device of this embodiment consumes less power. This allows the power MOSFET 101 to be turned off without causing an increase in power consumption. .

[0047] Furthermore, in the semiconductor device shown in Figure 2(C), the first gate of the power MOSFET 101 And in order to improve the potential retention characteristics of the node connected to the second gate, as shown in Figure 4(B) To this end, capacitive elements 401 are separately provided at nodes connected to the first and second gates. This configuration may also be used. In the semiconductor device shown in Figures 2(A) and 2(B), A configuration in which a capacitive element 401 is provided at the gate of the power MOSFET 101 and power element 121. You may do so.

[0048] In this embodiment, the details described in each figure are the same as those described in other embodiments. In contrast, you can freely combine or substitute elements as needed.

[0049] (Embodiment 2) In this embodiment, the structure and manufacturing method of the power MOSFET 101 shown in Embodiment 1 are as follows: This will be explained using Figures 5 to 7.

[0050] Figure 5(A) shows one cross-sectional configuration of the power MOSFET 101 shown in Embodiment 1. Figure 5(B) shows a top view of the power MOSFET 101. Figure 5(B) shows a cross-sectional view of A and B. This corresponds to Figure 5(A).

[0051] The power MOSFET 101 shown in Figure 5(A) has a first gate made of a conductive layer on the substrate 200. A gate 201 is provided, and a gate insulating layer 202 is provided on the first gate 201, and the gate insulating layer An n-type oxide semiconductor layer 203 is provided on the edge layer 202, and on the oxide semiconductor layer 203 Partially covered and made of a conductive layer, a first terminal 204A and a second terminal 204B are provided, and an oxide The insulating layer 205 covers the semiconductor layer 203, the first terminal 204A, and the second terminal 204B. A first terminal 204A and a second terminal 204B are provided on the insulating layer 205. The structure is formed so that a second gate 206, which is made of a conductive layer superimposed on the part, is provided.

[0052] The substrate 200 must have at least enough heat resistance to withstand subsequent heat treatment. This is crucial. When using a glass substrate as substrate 200, use one with a strain point of 730°C or higher. It is preferable that it be present. For example, the glass substrate may be aluminosilicate glass, aluminoh Glass materials such as borosilicate glass and barium borosilicate glass are used. It is preferable to use a glass substrate that contains more BaO than O3.

[0053] In addition, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used instead of the glass substrates mentioned above. A substrate made of edge material can be used. Other materials such as crystallized glass can also be used. Furthermore, the surface of semiconductor substrates such as silicon wafers and the surface of conductive substrates made of metal materials. It is also possible to use a material with an insulating layer formed on its surface.

[0054] Although not shown in Figure 5(A), heat conduction occurs between the substrate 200 and the first gate 201. By forming a highly insulating layer, a power MOSFET 101 with high heat resistance can be fabricated. This can be done. Examples of insulating layers with high thermal conductivity include aluminum nitride and aluminum nitride oxide. These include layers, silicon nitride layers, etc.

[0055] The first gate 201 is made of aluminum, chromium, copper, tantalum, titanium, molybdenum, and Metal elements selected from ngsten, or alloys containing the above-mentioned metal elements, or as described above It can be formed using alloys that combine various metallic elements. Also, manganese, ma Metallic elements selected from one or more of the following: magnesium, zirconium, and beryllium. It is also possible to use the following. Furthermore, the first gate 201 may be a single-layer structure or a stacked structure of two or more layers. For example, a single-layer structure of an aluminum layer containing silicon, or a titanium layer on top of an aluminum layer. Two-layer structure with stacked titanium layers, two-layer structure with a titanium layer stacked on top of a titanium nitride layer, titanium nitride layer A two-layer structure with a tungsten layer on top, or a tungsten layer stacked on top of a tantalum nitride layer. It has a two-layer structure, with a titanium layer and an aluminum layer laminated on top of that titanium layer, and then another titanium layer on top of that. There are also three-layer structures that form a layer. In addition, aluminum is combined with titanium, tantalum, and tungsten. Layers of elements selected from stainless steel, molybdenum, chromium, neodymium, and scandium, or multiple layers of these elements. Multiple alloy layers or nitride layers may be used.

[0056] Furthermore, the first gate 201 contains indium tin oxide and tungsten oxide. Indium zinc oxide containing oxides, tungsten oxide, and indium acid containing titanium oxide Adds indium tin oxide containing titanium dioxide, indium zinc oxide, and silicon dioxide. It is also possible to apply transparent conductive materials such as indium tin oxide. Alternatively, a laminated structure of the above-mentioned light-transmitting conductive material and the above-mentioned metal element can be used.

[0057] The gate insulating layer 202 consists of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, and an acid nitride layer. A silicon oxide layer or an aluminum oxide layer can be formed as a single layer or in a laminated manner. The gate insulating layer 202 preferably contains oxygen in the portion that is in contact with the oxide semiconductor layer 203. Particularly preferably, it is formed by a silicon oxide layer. By using a silicon oxide layer, acid This allows oxygen to be supplied to the ionized semiconductor layer 203, thereby improving its properties.

[0058] Furthermore, the gate insulating layer 202 is made of hafnium silicate (HfSiO x ), nitrogen is added Hafnium silicate (HfSi x O y N z ), Nitrogen-added hafnium aluminum (HfAl x O y N z ), high-k materials such as hafnium oxide and yttrium oxide By using this material, the gate leakage current can be reduced. Furthermore, high-k material and oxidation Silicon layer, silicon nitride layer, silicon oxide nitride layer, silicon nitride oxide layer, or oxide It can be a laminated structure with one or more luminium layers. Gate insulating layer 202 The thickness can be between 100 nm and 300 nm.

[0059] The n-type oxide semiconductor layer 203 is a quaternary metal oxide In-Sn-Ga-Zn- O-based metal oxides, and ternary metal oxides such as In-Ga-Zn-O metal oxides, In- Sn-Zn-O metal oxide, In-Al-Zn-O metal oxide, Sn-Ga-Zn- O-based metal oxide, Al-Ga-Zn-O-based metal oxide, Sn-Al-Zn-O-based metal oxide These include materials and binary metal oxides such as In-Zn-O metal oxides and Sn-Zn-O metal oxides. materials, Al-Zn-O metal oxides, Zn-Mg-O metal oxides, Sn-Mg-O metals Oxides, In-Mg-O-based metal oxides, etc., can be used. Here, n-component metals The oxide is composed of n types of metal oxides. The oxide semiconductor layer contains impurities, Other elements besides the main metal oxide component may be present in an amount of 1%, preferably 0.1%.

[0060] Furthermore, the n-type oxide semiconductor layer 203 is a ternary metal oxide, and InM X Zn Y O Z A metal oxide expressed as (Y=0.5~5) may also be used. Here, M is gallium. One of the elements selected from Group 13 such as (Ga), aluminum (Al), and boron (B) The symbols represent multiple elements. Note that the content of In, M, Zn, and O is arbitrary, and the content of M is arbitrary. This includes the case where the quantity is zero (i.e., x=0). On the other hand, the content of In and Zn is not zero. In other words, the above notation includes In-Ga-Zn-O metal oxides and In-Zn-O metal oxides. This includes oxide semiconductors, etc.

[0061] Furthermore, the metal oxide that forms the n-type oxide semiconductor layer 203 has an energy gap. The voltage is 2 eV or higher, preferably 2.5 eV or higher, and more preferably 3 eV or higher.

[0062] The n-type oxide semiconductor layer 203 has an amorphous structure, a microcrystalline structure, a polycrystalline structure, or a single-layer structure. A crystalline oxide semiconductor can be used as appropriate. Furthermore, the c-axis is approximately perpendicular to the surface. Oxide semiconductors having parallel crystals can be used.

[0063] The n-type oxide semiconductor layer 203 has a carrier density of 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 20 cm -3 The following is preferably 1 × 10 17 cm -3 The above 1 x 10 20 cm -3 Below In oxide semiconductors, hydrogen and oxygen vacancies contribute as donors, so the hydrogen concentration 1 x 10 16 cm -3 The above 1 x 10 20 cm -3 It is preferable that this be the case.

[0064] Furthermore, the thickness of the n-type oxide semiconductor layer 203 is negative at the first gate and the second gate. When a voltage is applied, the depletion layer expands into the channel region, and the power MOSFET 101 The thickness should be such that it can be switched off. The carrier density is 1 × 10⁻⁶. 16 cm -3 The above 1× 10 20 cm -3 The following values ​​are assumed: dielectric constant of 15, band gap of 3.15, and effective state density of the conduction band. The degree is Nc = 2.8 × 10 19 cm -3 The effective density of states in the valence band is Nv = 1.04 × 10⁻⁶ 19 cm -3 Therefore, if the gate is on one side of the oxide semiconductor layer, the maximum depletion layer width is The wavelength is between 7nm and 677nm. The power MOSFET shown in Figure 5(A) has a first gate Because it has gates 201 and a second gate 206, the thickness of the n-type oxide semiconductor layer 203 is The wavelength can be between 14 nm and 1354 nm. Furthermore, the carrier density can be 1 × 10⁻⁶. 17 cm -3 The above 1 x 10 20 cm -3 In the following cases, the maximum depletion layer width is 7 nm or more and 218 nm or less. Below. In this case, the thickness of the n-type oxide semiconductor layer 203 is 14 nm or more and 436 nm. It can be less than or equal to m.

[0065] The first terminal 204A and the second terminal 204B are made of aluminum, chromium, copper, tantalum, A metallic element selected from titanium, molybdenum, and tungsten, or a metallic element composed of the above-mentioned elements. It can be formed using an alloy, or an alloy combining the aforementioned metallic elements. Also, one or more of manganese, magnesium, zirconium, or beryllium A selected metal element may also be used. Furthermore, the first terminal 204A and the second terminal 204 B may be a single-layer structure or a laminated structure of two or more layers. For example, aluminum containing silicon. Single-layer structure of a titanium layer, double-layer structure with a titanium layer stacked on top of an aluminum layer, titanium nitride layer A two-layer structure in which a titanium layer is laminated, a two-layer structure in which a tungsten layer is laminated on a titanium nitride layer, A two-layer structure consisting of a tungsten layer stacked on a tantalum nitride layer, a titanium layer, and on that titanium layer One example is a three-layer structure in which aluminum layers are stacked and then a titanium layer is formed on top of them. Aluminum, titanium, tantalum, tungsten, molybdenum, chromium, neodymium, A layer of elements selected from scandium, or an alloy layer of multiple elements, or a nitride layer. You may also use [this].

[0066] Furthermore, the first terminal 204A and the second terminal 204B are made of indium tin oxide, tung oxide. Indium oxide containing tungsten, indium zinc oxide containing tungsten oxide, and tungsten oxide. Indium oxide containing tungsten, indium tin oxide containing titanium oxide, indium zinc oxide Transparent conductive materials such as indium tin oxide with added silicon dioxide and silicon dioxide are applied. It is also possible to combine the above-mentioned light-transmitting conductive material with the above-mentioned metal element laminated structure. It is also possible.

[0067] The insulating layer 205 can be made from any material shown in the gate insulating layer 202.

[0068] The second gate 206 can use the material shown for the first gate 201 as appropriate.

[0069] The power MOSFET 101 shown in Figure 5 has an n-type oxide semiconductor layer in the channel region. Therefore, it is possible to reduce the on-resistance and allow a large current to flow. However However, because it has an n-type oxide semiconductor layer in the channel region, it is a depletion type Yes, it is in a normally-on state where current flows even when no voltage is applied to the gate. The power MOSFET shown in this embodiment has a first gate 201 and a second gate It has 206, and by applying a negative voltage to the first gate 201 and the second gate 206 It can be turned off. Therefore, it has low on-resistance and can handle large currents. This makes it possible to achieve the off state of the power MOSFET. On the other hand, the first gate 201 It is possible to turn it on by applying a positive voltage to the first and second gates 206. Since the power MOSFET 101 has a first gate 201 and a second gate 206 Compared to a single-gate power MOSFET, the channel region thickness is increased. This makes it possible to pass large currents.

[0070] Furthermore, as shown in Figure 5(B), by connecting the power MOSFET 101 in parallel, The channel width W of the transistor can be increased. Therefore, high current can be increased. It is possible to create a power device capable of carrying a certain amount of current.

[0071] Next, Figure 6 shows a cross-sectional configuration of a power MOSFET that is different from that shown in Figure 5. Figure 6(A) shows... Power MOSFET 101A has a second gate 206A connected to the first terminal 204A and the second terminal It is characterized by overlapping with one terminal 204B and not overlapping with the other terminal.

[0072] The power MOSFET 101A shown in Figure 6(A) is a first gate made of a conductive layer on the substrate 200. A gate 201 is provided, and a gate insulating layer 202 is provided on the first gate 201, gate An n-type oxide semiconductor layer 203 is provided on the insulating layer 202, and on the oxide semiconductor layer 203 Partially covering it, a first terminal 204A and a second terminal 204B made of a conductive layer are provided, and an oxide The insulating layer 205 covers the semiconductor layer 203, the first terminal 204A, and the second terminal 204B. It is formed so as to be provided. Also, on the insulating layer 205, the first terminal 204A and the second A second gate 206A, made of a conductive layer, is provided, superimposed on one terminal 204B and not on the other. It is formed so that it can be attached. That is, the oxide semiconductor layer 203 is attached to the second gate 206A, A region 208 is formed that does not overlap with the first terminal 204A and the second terminal 204B.

[0073] The second gate 206A uses the same materials and manufacturing method as the second gate 206 shown in Figure 5. It can be formed by doing so.

[0074] The power MOSFET 101B shown in Figure 6(B) is a first gate made of a conductive layer on the substrate 200. A gate 201A is provided, and a gate insulating layer 202 is provided on the first gate 201A, An n-type oxide semiconductor layer 203 is provided on the insulating layer 202, and the oxide semiconductor layer 20 3 A first terminal 204A and a second terminal 204B, which are made of a conductive layer and partially cover the upper part, are provided, An insulating layer 20 covers the ion semiconductor layer 203, the first terminal 204A, and the second terminal 204B. 5 is formed to be provided. Also, the first terminal 204A and A second gate 206A, which is made of a conductive layer, is superimposed on one of the terminals 204B but not on the other. It is formed so that a first gate 201A is provided. That is, the oxide semiconductor layer 203 is formed so that a first gate 201A The second gate 206A, the first terminal 204A, and the second terminal 204B do not overlap. An offset region 209 is formed.

[0075] The first gate 201A uses the same materials and manufacturing method as the first gate 201 shown in Figure 5. It can be formed by doing so.

[0076] The power MOSFETs 101A and 101B shown in Figure 6 are n-type. Because the oxide semiconductor layer 203 is present in the channel region, it is possible to reduce the on-resistance. Therefore, it is possible to pass a large current. However, the n-type oxide semiconductor layer is channeled Because it is located in the depletion region, it is a depletion type, and when no voltage is applied to the gate... It is also in a normally-on state where current flows. The power MOSFET shown in this embodiment is The first gate has a second gate 206A along with a first gate 201 or 201A, and the first gate Turn off by applying a negative voltage to gate 201 or 201A and the second gate 206A. It is possible to have a positive signal in the first gate 201 or 201A and the second gate 206A. It can be turned on by applying voltage. Therefore, it has low on-resistance and high current. This makes it possible to achieve the off state of a power MOSFET, which allows current to flow. Since it has a first gate 201 or 201A and a second gate 206A, single Compared to gate power MOSFETs, it is possible to increase the thickness of the channel region. Furthermore, it is possible to pass a large current. In addition, the power MOSFET 101 shown in Figure 6(B) In B, in an n-type oxide semiconductor, the first gate 201A and the second gate 2 Offset region 20 not covered by 06A, the first terminal 204A, and the second terminal 204B Because it has 9, compared to the power MOSFET 101 shown in Figure 5(A), the drain breakdown voltage It is possible to increase the voltage, and a high voltage can be applied to the first terminal 204A or the second terminal 204B. It can be applied.

[0077] Here, the method for fabricating the power MOSFET 101 shown in Figure 5 will be explained using Figure 7. ru.

[0078] As shown in Figure 7(A), the first gate 201 is formed on the substrate 200. Next, the first A gate insulating layer 202 is formed on the gate 201.

[0079] The first gate 201 is manufactured using printing, inkjet, etc., reducing the number of steps. It can be reduced. Alternatively, the conductive layer can be created using sputtering, CVD, vapor deposition, etc. After formation, the resist formed by the photolithography process is used as a mask to create the conductive layer. By matching, the first gate 201 can be formed. If the ends are tapered, the coverage of the insulating layer, semiconductor layer, and conductive layer that will be formed later will be This is preferable because it can increase the heat. Also, between the substrate 200 and the first gate 201, A highly conductive insulating layer is formed by sputtering, CVD, coating, printing, etc. It is preferable.

[0080] The gate insulating layer 202 is formed by sputtering, CVD, printing, coating, or the like. This is possible. Alternatively, high-density plasma using μ-waves (e.g., frequency 2.45 GHz) can be used. CVD allows for the formation of a high-quality gate insulating layer 202 that is dense and has a high dielectric strength. The close contact between the semiconductor layer and the high-quality gate insulating layer reduces interface states and improves interface characteristics. This can improve the gate insulating layer 2 obtained by high-density plasma CVD. Because 02 can be formed with a constant thickness, it has excellent step coverage. Also, high-density plasma The gate insulating layer 202 obtained by CVD can have its thickness precisely controlled.

[0081] Next, as shown in Figure 7(B), an n-type oxide semiconductor layer 20 is placed on the gate insulating layer 202. 3 is formed. The n-type oxide semiconductor layer 203 is formed using printing, inkjet, etc. By manufacturing in this way, the number of steps can be reduced. Alternatively, on the gate insulating layer 202, n-type oxides are produced by sputtering, CVD, coating, pulsed laser deposition, etc. After forming the semiconductor layer, the resist formed by the photolithography process is used as a mask. The above oxide semiconductor layer is etched to form island-shaped n-type oxide semiconductor layer 203. It is possible.

[0082] The carrier density of an oxide semiconductor layer depends on the hydrogen concentration of the source gas and target under the deposition conditions. It also depends on the oxygen concentration, the material to be deposited and its composition, etc. The hydrogen concentration of the oxide semiconductor layer By increasing the oxygen concentration, or by lowering the oxygen concentration in the oxide semiconductor layer and introducing oxygen vacancies, It is possible to incorporate hydrogen or oxygen vacancies that contribute as a result into the oxide semiconductor layer. Therefore, an n-type oxide semiconductor layer can be formed.

[0083] Furthermore, after forming the oxide semiconductor layer 203, heat treatment is performed to create a microcrystalline structure and a polycrystalline structure. Alternatively, it may be an oxide semiconductor layer with a single crystal structure. Also, the c axis is perpendicular to the surface. It may also be an oxide semiconductor layer with a crystalline structure having nearly parallel crystals.

[0084] Next, as shown in Figure 7(C), the first terminal functions as the source electrode and drain electrode. The first terminal 204A and the second terminal 204B are formed. 4B can be manufactured using printing methods, inkjet methods, etc., which reduces the number of processes. Yes, it is possible. Alternatively, sputtering can be applied to the gate insulating layer 202 and the oxide semiconductor layer 203. After forming a conductive layer by CVD, vapor deposition, etc., it is formed by a photolithography process. The conductive layer is etched using the resist as a mask, and the first terminal 204A and the second terminal Terminal 204B can be formed.

[0085] Next, as shown in Figure 7(D), the gate insulating layer 202, oxide semiconductor layer 203, and the first edge An insulating layer 205 is formed on the child 204A and the second terminal 204B. The insulating layer 205 is The second gate can be formed in the same manner as the insulating layer 202. Next, the second gate can be formed on the insulating layer 205. A second gate 206 is formed. The second gate 206 can be formed in the same way as the first gate. .

[0086] Through the above process, an n-type oxide semiconductor layer is obtained in the channel region, and a depletion type A power MOSFET 101 can be fabricated. By changing the layout of the second gate, the power MOSFET 1 shown in Figure 6(A) can be modified. The power MOSFET 101B shown in Figure 01A or Figure 6(B) can be manufactured.

[0087] (Embodiment 3) In this embodiment, the power MOSFET 101 shown in Embodiment 1 and Embodiment 2 is replaced The structure of a power MOSFET that can be used as a substitute will be explained using Figures 8 and 9. I will reveal it.

[0088] The power MOSFETs shown in Figures 8 and 9 are, compared to the power MOSFETs shown in Figure 6, The difference is that there is no gate between the substrate 200 and the oxide semiconductor layer 213.

[0089] The power MOSFET 111A shown in Figure 8 has an n-type oxide semiconductor layer 2 on the substrate 200. A first terminal 204A is provided, which is made of a conductive layer and partially covers the oxide semiconductor layer 213. A second terminal 204B is provided, along with an oxide semiconductor layer 213, a first terminal 204A, and A gate insulating layer 212 is provided covering terminal 204B, and on the gate insulating layer 212, Gate 2, which consists of a conductive layer superimposed on a portion of one of terminals 204A and 204B It is formed so that 11 is provided. That is, the oxide semiconductor layer 213 is formed with gate 211, A region 208 is formed that does not overlap with the first terminal 204A and the second terminal 204B.

[0090] Furthermore, similar to the power MOSFET 101 shown in Embodiment 2, the substrate 200 and oxide semiconductor By forming an insulating layer with high thermal conductivity between the conductive layers 213, a power MOS with high heat resistance is achieved. FET111A can be fabricated. Also, the first terminal 204A and the second terminal 2 04B may be provided between the substrate 200 and the oxide semiconductor layer 213. Also, Figure 5(A) Similarly, without region 208, the first terminal 204A and the second terminal 204B A gate 211 made of a conductive layer superimposed on a portion of it may be provided.

[0091] The power MOSFET 111B shown in Figure 9(A) has a first edge made of a conductive layer on the substrate 200. A sub-terminal 204A is provided, and the first terminal 204A, which is made of a conductive layer, is covered by an n-type oxide semiconductor A body layer 213 is provided, and a second terminal 2, which is made of a conductive layer, partially covers the oxide semiconductor layer 213. A gate insulating layer is provided, covering the oxide semiconductor layer 213 and the second terminal 204B. A gate insulating layer 212 is provided, and on the gate insulating layer 212, there is a gate 211 made of a conductive layer and a first terminal A wire 214 is provided to connect to 204A, and a wire 215 is provided to connect to the second terminal 204B. It is formed in such a way.

[0092] Figure 9(B) is a top view of the power MOSFET 111B shown in Figure 9(A). The cross-sectional view of AB corresponds to Figure 9(A). As shown in Figure 9(B), the second terminal 20 Gates 211 are positioned around the wiring 215 that connects to terminals 4B and the second terminal 204B. Furthermore, around gate 211, there is a first terminal 204A, and connected to the first terminal 204A Wiring 214 is positioned.

[0093] In other words, the first terminal 204A and the second terminal 204B do not overlap. Gate 211 is It is provided in a region that includes areas that do not overlap with the first terminal 204A and the second terminal 204B. Furthermore, a portion (end) of gate 211 is one of the first terminal 204A and the second terminal 204B. It may be superimposed with one or both.

[0094] Furthermore, similar to the power MOSFET 101 shown in Embodiment 2, the substrate 200 and the first terminal By forming an insulating layer with high thermal conductivity between the substrate 204A and the oxide semiconductor layer 213, This allows for the fabrication of a high-thermal-temperature power MOSFET 111B.

[0095] The oxide semiconductor layer 213 shown in Figures 8 and 9 is the oxide semiconductor layer 203 shown in Embodiment 2. It can be formed using the same material as shown in Figure 8. The power MOSFET 111B shown in 1A and Figure 9 has a gate 211 on an oxide semiconductor layer 21 It is formed on only one side of 3. Therefore, the thickness of the oxide semiconductor layer 213 is the gate When a negative voltage is applied to 211, the depletion layer extends into the channel region, and the power MOSFET The thickness is such that ET111B can be turned off, but in this embodiment, the number of gates Because this is half the power MOSFET 101 shown in Embodiment 2, the carrier density is 1 × 10⁻⁶ 16 cm -3 The above 1 x 10 20 cm -3 In the following cases, the maximum depletion layer width is 7 nm or more and 677 nm. It is less than or equal to m. Therefore, the thickness of the n-type oxide semiconductor layer 213 is set to 7 nm or more and 677 nm. It can be less than or equal to m. Also, the carrier density is 1 × 10⁻⁶. 17 cm -3 The above 1 x 10 2 0 cm -3 In the following cases, the maximum depletion layer width is between 7 nm and 218 nm. The thickness of the n-type oxide semiconductor layer 213 can be set to 7 nm or more and 218 nm or less. .

[0096] The method for fabricating the power MOSFETs shown in Figures 8 and 9 is based on the configuration shown in Figures 8 and 9. In addition, the power MOSFET fabrication method shown in Embodiment 2 can be used as appropriate. .

[0097] The power MOSFETs shown in Figures 8 and 9 have an n-type oxide semiconductor layer in the channel region. Therefore, it is possible to reduce on-resistance and allow large currents to flow. However, because it has an n-type oxide semiconductor layer in the channel region, it is a depletion type Therefore, even when no voltage is applied to the gate, current flows in a normally-on state. The power MOSFET shown in this embodiment applies a negative voltage to the gate 211. It can be turned off by applying a positive voltage to gate 211, and turned on by applying a positive voltage to gate 211. This is possible. Therefore, power motors with low on-resistance and capable of carrying large currents are available. This allows for the SFET to be in the OFF state.

[0098] (Embodiment 4) In this embodiment, the field-effect transistors 102 to the field-effect transistors shown in Embodiment 1 are shown. The structure and manufacturing method of ZISTA 104 will be explained using Figures 10 and 11. Since the field-effect transistors 102 through 104 can have the same structure, here This will be explained using field-effect transistor 102 as a representative example.

[0099] The field effect transistor 102 shown in FIG. 10 has a gate 251 made of a conductive layer on a substrate 250 provided, a gate insulating layer 252 is provided on the gate 251, and an i-type or substantially i-type oxide semiconductor layer 253 is provided on the gate insulating layer 252 , and a first terminal 254A and a second terminal 254B made of a conductive layer are provided so as to partially cover the oxide semiconductor layer 2 53, and an insulating layer 255 is formed so as to cover the oxide semiconductor layer 253, the first terminal 254A, and the second terminal 254B , and an insulating layer 255 is provided . It is formed so as to be provided.

[0100] As the substrate 250, the substrate 200 shown in Embodiment 2 can be appropriately used.

[0101] As the gate 251, the material shown in the first gate 201 shown in Embodiment 2 can be appropriately used .

[0102] As the gate insulating layer 252, the material shown in the gate insulating layer 202 shown in Embodiment 2 can be appropriately used . The thickness of the gate insulating layer 252 can be set to 50 nm or more and 500 nm or less . By increasing the thickness of the gate insulating layer 252, the gate leakage current can be reduced .

[0103] As the oxide semiconductor layer 253, the metal oxide shown in the oxide semiconductor layer 203 shown in Embodiment 2 can be used . Also, an oxide semiconductor having an amorphous structure, a polycrystalline structure, or a single crystal structure can be appropriately used . Also, an oxide semiconductor having a crystal structure having a c-axis substantially parallel in a direction perpendicular to the surface can be used . However, since the oxide semiconductor layer 253 is i-type or substantially i-type, the carrier density is 5×10 cm 14 cm -3 less than, preferably is 1×10 12 cm-3 Less than 1 × 10 11 cm -3 The following applies. Also, It is preferable that the donor molecules have few hydrogen and oxygen deficiencies, and that the hydrogen concentration is 1 × 10⁻⁶. 16 cm -3 The following are preferable.

[0104] By thoroughly removing hydrogen, the purity is increased, reducing oxygen deficiency and satisfying the stoichiometric ratio. This allows for the use of an i-type or substantially i-type oxide semiconductor layer in the channel region, thereby enabling field-effect Transistor 102 has an off-current of 1 × 10⁻⁶ -16 It can be less than or equal to A. In the non-conductive state of a field-effect transistor, the oxide semiconductor layer can be considered an insulator and the circuit Design can be performed. On the other hand, the oxide semiconductor layer 253 is a guide for the field-effect transistor. Under normal conditions, it is expected to have a higher current supply capability than a semiconductor layer formed from amorphous silicon. This is possible. For this reason, the field-effect transistor 102 is an enhancement type, In the off state, it enters a normally-off state with extremely low leakage current, resulting in excellent switching performance. It possesses certain characteristics.

[0105] The first terminal 254A and the second terminal 254B are the same as the first terminal 204A shown in Embodiment 2. The materials shown in the second terminal 204B can be used as appropriate.

[0106] The insulating layer 255 is preferably formed of an oxide insulating layer. Typical examples of oxide insulating layers include: The layer includes a silicon oxide layer, a silicon oxide nitride layer, or an aluminum oxide layer. 205 may be a laminated structure of an oxide insulating layer and a nitride insulating layer. A typical example of a nitride insulating layer is... This includes a silicon nitride layer, a silicon oxide nitride layer, or an aluminum nitride layer. Insulating layer 2 In 55, the region in contact with the oxide semiconductor layer 253 is formed with an oxide insulating layer, This reduces oxygen vacancies in the semiconductor layer and allows the stoichiometric ratio to be satisfied.

[0107] Furthermore, the field-effect transistor 102 can take various forms and is not limited to a specific configuration. No, it is not. For example, a multi-gate structure with two or more gates can be applied. This allows for a structure in which gate electrodes are positioned above and below the channel region. By arranging the gates above and below the channel region, two field-effect transients are created. It is also possible to configure the system so that the components are connected in parallel.

[0108] Here, the method for fabricating the field-effect transistor 102 shown in Figure 10 is described using Figure 11. explain.

[0109] As shown in Figure 11(A), a gate 251 is formed on the substrate 250. Next, gate 2 A gate insulating layer 252 is formed on 51.

[0110] Gate 251 can be manufactured using the method for manufacturing the first gate 201 shown in Embodiment 2 as appropriate. It is possible. Also, the gate insulating layer 252 is made using the method for manufacturing the gate insulating layer 202 shown in Embodiment 2. The law may be used as appropriate. Furthermore, the i-type or substantially i-type oxide semiconductor layer Because it is extremely sensitive to interface levels and interface charges, the gate insulating layer 252 is designed using μ-waves. By forming it with high-density plasma CVD, the interface states are reduced and the interface properties are improved. It is possible.

[0111] Furthermore, when forming the gate insulating layer 252, the substrate 200 is heated, Hydrogen, water, hydroxyl groups, hydrides, etc. contained in 252 can be reduced.

[0112] In addition, in order to reduce hydrogen, water, hydroxyl groups, hydrides, etc. contained in the gate insulating layer 252, when forming the gate insulating layer 252 by sputtering, it is preferable to form the gate insulating layer 252 while removing hydrogen, water, hydroxyl groups or hydrides, etc. remaining in the processing chamber. In order to remove hydrogen, water, hydroxyl groups, hydrides, etc. remaining in the processing chamber, it is preferable to use an adsorption type vacuum pump. Representative examples of the adsorption type vacuum pump are cryopumps, ion pumps, and titanium sublimation pumps. In addition, as an exhaust means, a turbo pump with a cold trap added can be used.

[0113] Also, by setting the purity of the sputtering gas used when forming the gate insulating layer 252 to 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less), hydrogen, water, hydroxyl groups, hydrides, etc. contained in the gate insulating layer 252 can be reduced.

[0114] Next, as shown in FIG. 11(B), an oxide semiconductor layer 253A is formed on the gate insulating layer 202. The oxide semiconductor layer 253A can be formed using a printing method, an inkjet method, etc. Or, an oxide semiconductor layer is formed on the gate insulating layer 252 by sputtering, CVD, coating, pulsed laser deposition, etc., and the formed resist is used as a mask by a photolithography process to etch the above oxide semiconductor layer, and an island-shaped oxide semiconductor layer 253A can be formed.

[0115] The carrier density of an oxide semiconductor layer depends on the hydrogen concentration of the source gas and target under the deposition conditions. It also depends on the oxygen concentration, the material to be deposited and its composition, and the heat treatment conditions. Oxide semiconductor Lowering the hydrogen concentration in the layer, or increasing the oxygen concentration in the oxide semiconductor layer to reduce oxygen vacancies. By doing so, the oxide semiconductor layer becomes type i or substantially type i. In this embodiment, acid Since the oxide semiconductor layer is later subjected to a process to make it i-type or substantially i-type, the oxide semiconductor layer 2 53A can be either type i or type n.

[0116] Furthermore, when forming an oxide semiconductor layer by sputtering, heating the substrate causes oxidation. It is possible to reduce impurities such as hydrogen, water, hydroxyl groups, and hydrides contained in the semiconductor layer. Furthermore, crystal growth can be promoted during the first heat treatment.

[0117] Furthermore, when forming an oxide semiconductor layer by sputtering, the gold in the metal oxide target The relative density of the group oxide is 80% or more, preferably 95% or more, and more preferably 99.9%. By doing so, the impurity concentration in the oxide semiconductor layer can be reduced, improving the electrical properties and Highly reliable transistors can be obtained.

[0118] Furthermore, by performing a preheating treatment before forming the oxide semiconductor layer, the sputtering apparatus Hydrogen, water, hydroxyl groups, and hydrides remaining on the inner wall, target surface, and within the target material Because it can remove impurities such as hydrogen, water, hydroxyl groups, and hydrides contained in the oxide semiconductor layer, It can reduce the amount of material.

[0119] Also, similar to the gate insulating layer 252, before or during the formation of the oxide semiconductor layer, After formation, hydrogen, water, hydroxyl groups, hydrides, etc. remaining in the sputtering apparatus are removed. To remove it, it is preferable to use an adsorption-type vacuum pump. As a result, hydrogen, water, and hydroxyl Hydrogen groups, hydrides, etc. are exhausted, so hydrogen, water, hydroxyl groups, and hydrogen contained in the oxide semiconductor layer are released. It can reduce the concentration of toxic substances and other contaminants.

[0120] Next, the first heat treatment is performed, and the hydrogen, water, hydroxyl groups, and water contained in the oxide semiconductor layer 253A are removed. Remove impurities such as nitrates. That is, perform at least one of dehydration and dehydrogenation. This can be achieved. In addition, oxygen vacancies are also formed in the oxide semiconductor layer 253A during the first heat treatment. The first heat treatment removes impurities such as hydrogen, water, hydroxyl groups, and hydrides from the acid. In Figure 11(C), the oxide semiconductor layer is shown as oxide semiconductor layer 253B.

[0121] The temperature of the first heat treatment is 400°C to 750°C, preferably 400°C or higher, to reduce substrate strain. The temperature shall be below 1 / 2. The heat treatment apparatus used for the first heat treatment is not particularly limited. The object to be processed is heated by heat conduction or thermal radiation from a heat source such as a resistance heating element. The device may include an electric furnace or a GRTA (Gas Rapid Turbine). thermal annealing) equipment, LRTA (Lamp Rapid Thermal An Using RTA (Rapid Thermal Anneal) devices such as neal devices. It is possible. The LRTA device can use halogen lamps, metal halide lamps, xenon lamps. Lamps such as clamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. A GRTA device heats an object to be processed by radiating light (electromagnetic waves) emitted from it. It is a device that performs heat treatment using high-temperature gas.

[0122] In the first heat treatment, nitrogen, or a noble gas such as helium, neon, or argon is used. It is preferable that it does not contain hydrogen, water, hydroxyl groups or hydrides, etc. Alternatively, heat treatment The purity of nitrogen, or noble gases such as helium, neon, and argon, introduced into the apparatus is set to 6N. (99.9999% or more, preferably 7N (99.99999% or more), (i.e., impurities) It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0123] Furthermore, in the first heat treatment, the inside of the furnace is filled with a nitrogen atmosphere during heating, and during cooling, the furnace is filled with a nitrogen atmosphere. The atmosphere can be switched to an oxygen atmosphere inside, and dehydration or dehydrogenation can be performed in a nitrogen atmosphere. After the procedure, the atmosphere is switched to an oxygen atmosphere to replenish oxygen within the oxide semiconductor layer. It can supply hydrogen, reduce the hydrogen concentration, and form an oxygen vacancy in the oxide semiconductor layer. It is possible to supply the element and form an i-type or substantially i-type oxide semiconductor layer. It is possible.

[0124] Furthermore, depending on the conditions of the first heat treatment, or the material of the oxide semiconductor layer, the oxide semiconductor layer 253A may crystallize, forming an oxide semiconductor layer with crystals. For example, crystallization rate In some cases, this can result in an oxide semiconductor layer having 90% or more crystals, or even 80% or more crystals.

[0125] Furthermore, depending on the first heating conditions or the material of the oxide semiconductor layer, amorphous oxide semiconductor A crystalline structure is formed in the surface layer of the layer, in which the c-axis is nearly parallel to the direction perpendicular to the surface. In some cases, it may form an oxide semiconductor layer.

[0126] The first heat treatment is performed after forming the first and second terminals on the oxide semiconductor layer. You may go.

[0127] Here, the substrate is introduced into an electric furnace and subjected to an inert gas atmosphere such as nitrogen or a rare gas at 450°C. Heat treatment at °C for 1 hour.

[0128] Next, as shown in Figure 11(C), the first end functions as the source electrode and drain electrode. This forms the child terminal 254A and the second terminal 254B.

[0129] The first terminal 254A and the second terminal 254B are the same as the first terminal 204A shown in Embodiment 2. The and the second terminal 204B can be formed similarly.

[0130] Next, as shown in Figure 11(D), the gate insulating layer 252, oxide semiconductor layer 253B, and the first An insulating layer 255 is formed on terminal 254A and the second terminal 254B. The insulating layer 255 is It can be formed by sputtering, CVD, printing, coating, etc. When a silicon oxide layer is formed as the edge layer 255 by the sputtering method, silicon oxide Oxygen is supplied to the oxygen vacancies in the oxide semiconductor layer 253A that were generated in the first heat treatment from the layer. It is possible to supply oxygen, reduce the oxygen deficiency contributed by the donor, and satisfy the stoichiometric ratio. This configuration is possible. As a result, an i-type or substantially i-type oxide semiconductor can be formed. A body layer 253 can be formed.

[0131] Next, a second heat treatment (preferably 200°C) is performed in an inert gas atmosphere or an oxygen gas atmosphere. The second heat treatment is performed at a temperature between 250°C and 400°C (for example, between 250°C and 350°C). The procedure may be carried out after forming a protective insulating layer or a planar insulating layer on the edge layer 255. Furthermore, the oxide semiconductor layer generated by the first heat treatment from the oxide insulating layer of the insulating layer 255 is contained within the oxide insulating layer. It is possible to supply oxygen to oxygen-deficient cells, and to reduce the oxygen deficiency that can be contributed by donors. This makes it possible to create a configuration that satisfies the stoichiometric ratio. As a result, it becomes more i-type or essentially An i-type oxide semiconductor layer 253 can be formed.

[0132] In this embodiment, a second heat treatment is performed at 250°C for 1 hour in a nitrogen atmosphere.

[0133] Furthermore, a heat treatment is performed in air at a temperature between 100°C and 200°C for between 1 hour and 30 hours. This may also be done. This heat treatment can improve the reliability of the field-effect transistor.

[0134] Through the above process, an i-type or substantially i-type oxide semiconductor layer is formed in the channel region. The field-effect transistor 102 has an extremely low off-current and is an enhancement type. It is possible to produce this.

[0135] (Embodiment 5) Figure 12 shows a semiconductor device using the power elements shown in Embodiments 1 to 3 as protective elements. This shows one form of the setup. The protection element is a power supply terminal that, when an overvoltage is input, activates the protection element. It functions by passing current through a power element to prevent overcurrent from flowing into the protected circuit. The circuit includes all low-voltage circuits that would be destroyed by the application of overvoltage. In this embodiment, the power As an example of an element, the 4-terminal power MOSFET shown in Embodiments 1 and 2. We will explain using this method.

[0136] Figure 12 shows the power MOSFET 501, control circuit 502, protected circuit 503, and input terminals. This is a semiconductor device having terminals 504 and output terminals 505. The control circuit 502 has input terminals 5 The power MOS detects the overvoltage applied to terminal 04 or output terminal 505 and acts as a protection element. This controls the operation of the FET501.

[0137] Figure 13 shows a detailed view of the control circuit 502. The control circuit 502 is used for overvoltage detection. Circuit 511, inverter 512, positive power supply 513, switch transistors 514, 515, 5 16. Capacitive element 517, negative voltage generation circuit 518, oscillation circuit 519, frequency divider circuit 520, delay It consists of circuit 521 and AND circuit 522. The positive power supply 513 is shown in Embodiment 1. This corresponds to the high voltage source 108. Switch transistors 514, 515, and 516 are for this purpose. These correspond to the field-effect transistors 102, 103, and 104 shown in Embodiment 1. The capacitance element 517 corresponds to the capacitance element 105 shown in Embodiment 1. Also, the negative voltage generation circuit... 518 corresponds to the low voltage source 109 shown in Embodiment 1. Oscillator circuit 519, frequency divider circuit 520, delay circuit 521, and AND circuit 522 are refresh circuits as shown in Embodiment 1. This corresponds to circuit 107. Note that the control circuit 502 is not limited to this configuration.

[0138] Next, we will explain the operation of the control circuit 502 and power MOSFET 501 shown in Figure 13. The overvoltage detection circuit 511 detects an overvoltage that significantly exceeds the normal power supply voltage at the input terminal 50. This is a circuit that operates when input to 4, and in this embodiment, when an overvoltage is input, It has the function of outputting a pulse of type I.

[0139] The output terminal of the overvoltage detection circuit 511 is connected to the gate terminal and input of the switch transistor 514. It is connected to the input terminal of the inverter 512. The output terminal of the inverter 512 is connected to the switch transistor. It is connected to the gate terminal of the ZISTA 515. This switches the device when an overvoltage is applied. When transistor 514 is turned on, the gate terminal of power MOSFET 501 is connected to the positive power supply 51 When connected to 3, power MOSFET 501 turns on. This allows input terminal 504 to receive Current flows through output terminal 505, preventing overcurrent from flowing through the protected circuit 503 shown in Figure 12. Stop.

[0140] When no overvoltage is applied, the output of the overvoltage detection circuit 511 is low, and the switch... Transistor 514 is off, and switch transistor 515 is on. Negative voltage generation cycle The circuit 518 consists of a charge pump circuit as shown in Figure 17, which generates a negative voltage.

[0141] Since protection circuits are not circuits that operate frequently, constantly supplying them with a large current is a waste of power. It is not suitable from a power standpoint. Therefore, with a small current capacity, charge is stored in the capacitive element 517. This is effective in reducing power consumption. Therefore, intermittently generating a negative voltage from the negative voltage generation circuit 518 Power consumption is reduced by charging the capacitive element 517 via the switch transistor 516. It is possible.

[0142] The oscillation signal obtained by the oscillation circuit 519 is divided by the frequency divider circuit 520, and the divided signal is This is supplied to the gate terminal of the switch transistor 516. That is, the output of the frequency divider circuit 520. One of the terminals is connected to the first input terminal of the AND circuit 522. Also, the frequency divider circuit 520 The other output terminal is connected to the second input terminal of the AND circuit 522 via the delay circuit 521. In this way, the pulse width is equal to the delay time of the delay circuit 521, and the period is equal to the frequency divider circuit 5 A pulse similar to the output of 20 can be obtained. By using this pulse, the The gate terminal of transistor 516 can be controlled.

[0143] The oscillator circuit 519 can use a general oscillator circuit, such as a ring oscillator. It can do so, but the type is not limited. Also, the frequency divider circuit 520 can use flip-flops. This is possible. The delay circuit 521 can be a circuit using an inverter, a circuit using a CR delay circuit, etc. While these methods can be used, they are not particularly limited. Furthermore, other methods can be used to form the pulse. It can also be done this way.

[0144] In this way, a negative voltage is maintained across the capacitive element 517, and when no overvoltage is applied... A negative voltage is applied to the power MOSFET 501 via the switch transistor 515. While a negative voltage is applied to the gate terminal of power MOSFET 501, the power MOSFET FET501 turns off and no current flows.

[0145] Figure 14 shows a semiconductor device in which a power MOSFET is connected in series with the circuit to be protected. Unlike in 2, when an overvoltage is applied to the input terminal, the power MOSFET 601 is This prevents overvoltage from being applied to the protected circuit 603.

[0146] The semiconductor device shown in Figure 14 includes a power MOSFET 601, a control circuit 602, and a protected circuit. It consists of 603, input terminal 604, and output terminal 605. The control circuit 602 is the input terminal The power MO detects the overvoltage applied to terminal 604 or output terminal 605 and acts as a protection element. This controls the SFET601.

[0147] Figure 15 shows the details of the control circuit 602. The control circuit 602 includes the overvoltage detection circuit 611 and inverter Transistor 612, positive power supply 613, switch transistors 614, 615, 616, capacitive element 6 17. Negative voltage generation circuit 618, oscillation circuit 619, frequency divider circuit 620, delay circuit 621, AN It consists of the D circuit 622. The positive power supply 613 is the high voltage source 1 shown in Embodiment 1. This corresponds to 08. Switch transistors 614, 615, and 616 are, respectively, in the embodiment. This corresponds to the field-effect transistors 103, 102, and 104 shown in 1. The capacitive element 617 is This corresponds to the capacitive element 105 shown in Embodiment 1. Also, the negative voltage generation circuit 618 is in the embodiment This corresponds to the low voltage source 109 shown in state 1. Oscillator circuit 619, frequency divider circuit 620, delay circuit 621 and AND circuit 622 are phases of the refresh control circuit 107 shown in Embodiment 1. This applies. However, the control circuit 602 is not limited to this configuration.

[0148] Next, we will explain the operation of the control circuit 602 and power MOSFET 601 shown in Figure 15. The overvoltage detection circuit 611 detects an overvoltage that significantly exceeds the normal power supply voltage at the input terminal 60 This is a circuit that operates when input to 4, and in this embodiment, when an overvoltage is input, It has the function of outputting a pulse of type I.

[0149] The output terminal of the overvoltage detection circuit 611 is connected to the gate terminal of the switch transistor 615. It is connected to inverter 612. The output terminal of inverter 612 is connected to switch transistor 614. It is connected to the gate terminal. As a result, when an overvoltage is input to input terminal 604, When switch transistor 615 turns on, the gate terminal of power MOSFET 601 becomes negative. It is connected to the pressure generating circuit 618 and turned off. This protects the input terminal 604 and the circuit to be protected. Circuit 603 is disconnected to prevent overcurrent from flowing to the protected circuit 603. Negative voltage generation circuit 618 consists of a charge pump circuit as shown in Figure 17, and generates a negative voltage.

[0150] When no overvoltage is applied, the output of the overvoltage detection circuit 611 is low, and the switch... The switch transistor 615 is turned off, and the switch transistor 614 is turned on, and the power MOS The gate terminal of FET601 is connected to the capacitive element 617. Capacitive element 617 is described later. Since a positive voltage is maintained from the positive power supply, the power MOSFET 601 turns on.

[0151] Since protection circuits are not circuits that operate frequently, constantly supplying them with a large current is a waste of power. This is not appropriate from a power standpoint. Therefore, the capacitive element 617 is charged with a small current capacity. This is effective in reducing power consumption. Therefore, intermittently switching from the positive power supply 613 By charging the capacitive element 617 via the transistor 616, power consumption can be reduced. can.

[0152] The oscillation signal obtained by the oscillation circuit 619 is divided by the frequency divider circuit 620, and the divided signal is, It is supplied to the gate terminal of the switch transistor 616, that is, to the output terminal of the frequency divider circuit 620. One end of the child is connected to the first input terminal of the AND circuit 622. Also, the output of the frequency divider circuit 620 The other end of the power terminal is connected to the second input terminal of the AND circuit 622 via the delay circuit 621. In this way, the pulse width is equal to the delay time of the delay circuit 621, and the period is equal to that of the frequency divider circuit 620. A pulse similar to the output can be obtained. By using this pulse, the switch The gate terminal of transistor 616 can be controlled.

[0153] The oscillator circuit 619 can be used as a general oscillator circuit, such as a ring oscillator. It can do so, but the type is not limited. Also, the frequency divider circuit 620 can use flip-flops. This is possible. The delay circuit 621 can be an inverter circuit, a CR delay circuit, etc. While these methods can be used, they are not particularly limited. Furthermore, pulse formation methods other than those mentioned above may also be used. That's fine too.

[0154] In this way, a positive voltage is maintained across the capacitive element 617, and when no overvoltage is applied... A positive voltage is applied to the power MOSFET 601 via the switch transistor 614. While a positive voltage is applied to the gate terminal of power MOSFET 601, the power MOSFET FET 601 turns on, and the input terminal 604 is connected to the protected circuit 603 shown in Figure 14. It can be done.

[0155] Figure 16 shows an example configuration of the overvoltage detection circuits 511 and 611. Figure 16 shows transistor 70 A diode chain with diodes 1-705 connected, transistor 707, and resistor 70 6. It consists of inverters 708. When the number of stages in the diode chain is n, If the threshold voltage of the transistor is Vth, then the normal operating voltage is <nVthとなるようにn This is set so that when an overvoltage is applied, transistors 701-705 turn on, and the diode Allow current to flow through the chain. When transistor 705 turns on, the transistor When the 707 is turned on, a high signal is output from the inverter 708.

[0156] In this embodiment, an oxide semiconductor layer with a large band gap is used in the channel region. - Using Marion's power MOSFETs as protection elements, a semiconductor device is protected against overvoltage application. This can prevent its destruction.

[0157] (Embodiment 6) This embodiment describes the applications of the power device described in the above embodiment. The semiconductor device, which is a power device described in the above embodiment, is, for example, a computer, etc. In addition to battery protection circuits for electronic devices such as displays that can show images, induction cooking Battery protection circuit installed in vehicles (bicycles, etc.) powered by a device or fixed power supply. It can be used as such.

[0158] Referring to Figure 18, the semiconductor device is a power device that also functions as a protection circuit. Let me explain one example of its application.

[0159] Figure 18(A) shows an example of an application with a semiconductor device that functions as a protection circuit, specifically an induction cooktop. It shows 1000. The induction cooker 1000 works by passing an electric current through the coil section 1001. It uses the electromagnetic induction that occurs to heat cooking appliances, etc. Also, induction cookers 1000 This includes a battery 1002 for supplying current to the coil section 1001, and a protection circuit. A functional semiconductor device 1003, and a solar cell 100 for charging a battery 1002. It has 4. Note that in Figure 18(A), thick is used as a means for charging the battery 1002. Although the solar cell 1004 is shown, a configuration in which it is charged by other means is also acceptable. A semiconductor that functions as a protection circuit. The conductor device 1003 can reduce the application of overvoltage to the battery 1002 and function as a protection circuit. This allows for reduced power consumption when the device is not in operation.

[0160] Figure 18(B) shows an example application of an electric bicycle equipped with a semiconductor device that functions as a protection circuit. It indicates 1010. The electric bicycle 1010 supplies current to the motor unit 1011. Therefore, it obtains power. Also, the electric bicycle 1010 has electricity supplied to the motor unit 1011. A battery 1012 for supplying current, and a semiconductor device 101 that functions as a protection circuit. It has 3. Note that in Figure 18(B), a special means for charging the battery 1012 is shown. Although not shown in the diagram, a configuration using a separate generator or the like for charging is also possible. It functions as a protection circuit. The semiconductor device 1013 can reduce the application of overvoltage to the battery 1012 during charging. This allows for lower power consumption when the protection circuit is not in operation. (See Figure 18) Although a pedal is shown in B), it is not necessary.

[0161] Figure 18(C) shows an example application of a semiconductor device that functions as a protection circuit in an electric vehicle. It indicates 1020. The electric vehicle 1020 will supply current to the motor unit 1021. Therefore, it obtains power. Also, the electric vehicle 1020 supplies electricity to the motor unit 1021. A battery 1022 for supplying current, and a semiconductor device 102 that functions as a protection circuit. It has 3. Note that in Figure 18(C), a special means for charging the battery 1022 is shown. Although not shown in the diagram, a configuration using a separate generator or the like for charging is also possible. It functions as a protection circuit. The semiconductor device 1023 can reduce the application of overvoltage to the battery 1022 during charging. This allows for reduced power consumption when the protection circuit is not in operation.

[0162] In this embodiment, the details described in each figure are the same as those described in other embodiments. In contrast, you can freely combine or substitute elements as needed.

Claims

1. It comprises an oxide semiconductor layer having a channel formation region for a transistor, and a first to fourth conductive layer, The first conductive layer is electrically connected to the oxide semiconductor layer and has a region located below the oxide semiconductor layer. The second conductive layer is electrically connected to the oxide semiconductor layer and has a region located above the oxide semiconductor layer. The third conductive layer is electrically connected to the first conductive layer and has a region located above the oxide semiconductor layer. The fourth conductive layer functions as the gate electrode of the transistor, has a region located above the oxide semiconductor layer, and has an opening. In a plan view, the region of the second conductive layer that is in contact with the oxide semiconductor layer has a region that overlaps with the opening of the fourth conductive layer. Semiconductor equipment.

2. It comprises an oxide semiconductor layer having a channel formation region for a transistor, and a first to fourth conductive layer, The first conductive layer is electrically connected to the oxide semiconductor layer and has a region located below the oxide semiconductor layer. The second conductive layer is electrically connected to the oxide semiconductor layer and has a region located above the oxide semiconductor layer. The third conductive layer is electrically connected to the first conductive layer and has a region located above the oxide semiconductor layer. The fourth conductive layer functions as the gate electrode of the transistor, has a region located above the oxide semiconductor layer, and has an opening. In a plan view, the second conductive layer overlaps with the fourth conductive layer. In a plan view, the region of the second conductive layer that is in contact with the oxide semiconductor layer has a region that overlaps with the opening of the fourth conductive layer. Semiconductor equipment.

3. It comprises an oxide semiconductor layer having a channel formation region for a transistor, and a first to fourth conductive layer, The first conductive layer is electrically connected to the oxide semiconductor layer and has a region located below the oxide semiconductor layer. The second conductive layer is electrically connected to the oxide semiconductor layer and has a region located above the oxide semiconductor layer. The third conductive layer is electrically connected to the first conductive layer and has a region located above the oxide semiconductor layer. The fourth conductive layer functions as the gate electrode of the transistor, has a region located above the oxide semiconductor layer, and has an opening. In a plan view, the third conductive layer does not overlap with the fourth conductive layer. In a plan view, the region of the second conductive layer that is in contact with the oxide semiconductor layer has a region that overlaps with the opening of the fourth conductive layer. Semiconductor equipment.

4. It comprises an oxide semiconductor layer having a channel formation region for a transistor, and a first to fourth conductive layer, The first conductive layer is electrically connected to the oxide semiconductor layer and has a region located below the oxide semiconductor layer. The second conductive layer is electrically connected to the oxide semiconductor layer and has a region located above the oxide semiconductor layer. The third conductive layer is electrically connected to the first conductive layer and has a region located above the oxide semiconductor layer. The fourth conductive layer functions as the gate electrode of the transistor, has a region located above the oxide semiconductor layer, and has an opening. In a plan view, the second conductive layer overlaps with the fourth conductive layer. In a plan view, the third conductive layer does not overlap with the fourth conductive layer. In a plan view, the region of the second conductive layer that is in contact with the oxide semiconductor layer has a region that overlaps with the opening of the fourth conductive layer. Semiconductor equipment.

5. It comprises an oxide semiconductor layer having a channel formation region for a transistor, and a first to fourth conductive layer, The first conductive layer is electrically connected to the oxide semiconductor layer and has a region located below the oxide semiconductor layer. The second conductive layer is electrically connected to the oxide semiconductor layer and has a region located above the oxide semiconductor layer. The third conductive layer is electrically connected to the first conductive layer and has a region located above the oxide semiconductor layer. The fourth conductive layer functions as the gate electrode of the transistor, has a region located above the oxide semiconductor layer, and has an opening. In a plan view, the second conductive layer overlaps with the fourth conductive layer. Of the oxide semiconductor layer, the entire lower surface of the region that overlaps with the second conductive layer in a plan view is in contact with an insulating surface. In a plan view, the region of the second conductive layer that is in contact with the oxide semiconductor layer has a region that overlaps with the opening of the fourth conductive layer. Semiconductor equipment.

6. It comprises an oxide semiconductor layer having a channel formation region for a transistor, and a first to fourth conductive layer, The first conductive layer is electrically connected to the oxide semiconductor layer and has a region located below the oxide semiconductor layer. The second conductive layer is electrically connected to the oxide semiconductor layer and has a region located above the oxide semiconductor layer. The third conductive layer is electrically connected to the first conductive layer and has a region located above the oxide semiconductor layer. The fourth conductive layer functions as the gate electrode of the transistor, has a region located above the oxide semiconductor layer, and has an opening. In a plan view, the third conductive layer does not overlap with the fourth conductive layer. Of the oxide semiconductor layer, the entire lower surface of the region that overlaps with the second conductive layer in a plan view is in contact with an insulating surface. In a plan view, the region of the second conductive layer that is in contact with the oxide semiconductor layer has a region that overlaps with the opening of the fourth conductive layer. Semiconductor equipment.

7. It comprises an oxide semiconductor layer having a channel formation region for a transistor, and a first to fourth conductive layer, The first conductive layer is electrically connected to the oxide semiconductor layer and has a region located below the oxide semiconductor layer. The second conductive layer is electrically connected to the oxide semiconductor layer and has a region located above the oxide semiconductor layer. The third conductive layer is electrically connected to the first conductive layer and has a region located above the oxide semiconductor layer. The fourth conductive layer functions as the gate electrode of the transistor, has a region located above the oxide semiconductor layer, and has an opening. In a plan view, the second conductive layer overlaps with the fourth conductive layer. In a plan view, the third conductive layer does not overlap with the fourth conductive layer. Of the oxide semiconductor layer, the entire lower surface of the region that overlaps with the second conductive layer in a plan view is in contact with an insulating surface. In a plan view, the region of the second conductive layer that is in contact with the oxide semiconductor layer has a region that overlaps with the opening of the fourth conductive layer. Semiconductor equipment.

8. In any one of claims 1 to 7, The oxide semiconductor layer comprises In, Ga, and Zn.

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