Storage controller, its operating method, and non-volatile memory

Abstract

To provide a storage device including a storage controller capable of detecting command and address communication errors.SOLUTION: A storage device according to the present invention includes a non-volatile memory and a storage controller configured to control the non-volatile memory. The storage controller includes a command and address generator that generates a first command, an address, and a second command, the second command including an error detection signal for detecting a communication error in the first command and the address, an error detection module configured to generate the error detection signal from the first command and the address, and an interface circuit configured to sequentially transmit the first command, the address, and the second command to the non-volatile memory. The first command indicates the type of a memory operation to be executed in the non-volatile memory, and the second command corresponds to a confirm command.SELECTED DRAWING: Figure 2B

Description

[Technical Field]

[0001] The present invention relates to a memory device, and more particularly to a storage controller having a command and address communication error detection function. and non-volatile memory Regarding. [Background technology]

[0002] The storage controller uses an ECC (Error Correction Code) engine to detect errors that occur during data transmission and correction.

[0003] However, conventional storage controllers do not have the necessary configuration to detect errors that occur during the transmission of commands and addresses. As a result, even if an error occurred during the transmission of commands and addresses from the storage controller to non-volatile memory, it was difficult to detect and correct the error. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2011-164714 [Overview of the project] [Problems that the invention aims to solve]

[0005] This invention has been made in view of the problems in the above-mentioned conventional storage controllers, and the object of this invention is to be able to detect communication errors of commands and addresses. Storage controller, its operating method, and non-volatile memory The objective is to provide. [Means for solving the problem]

[0006] The present invention has been made to achieve the above objective. Storage controller teeth, A storage controller configured to control non-volatile memory, the Command 1, address, and Command 2 A command and address generator configured to generate a command set, wherein the second command includes an error detection signal for detecting a communication error in the first command and the address, so that the non-volatile memory detects a communication error in the first command and the address.An error detection module configured to generate the error detection signal from the first command and the address, and the non-volatile memory is configured to As the command set transmit the first command, the address, and the second command sequentially. Yes The first command indicates the type of memory operation to be executed in the non-volatile memory, and the second command Related to memory operations corresponds to a confirm command.

[0007] According to the present invention made to achieve the above object Non-volatile memory is The storage controller has an interface circuit configured to sequentially receive a first command, an address, and a second command as a command set from the storage controller, wherein the second command includes an error detection signal for detecting communication errors in the first command and the address, a memory cell array including a plurality of memory cells, and a control logic circuit configured to detect communication errors in the first command and the address based on the error detection signal, wherein the first command indicates the type of memory operation to be performed in the non-volatile memory, and the second command corresponds to a confirm command related to the memory operation. .

[0009] The present invention has been made to achieve the above objective. The operation method of the storage controller is A method for operating a storage controller configured to control non-volatile memory, comprising the steps of: generating a first command and an address; generating an error detection signal from the first command and the address; thereby causing the non-volatile memory to detect a communication error in the first command and the address and generate a confirm command including the error detection signal; and sequentially transmitting the first command, the address, and the confirm command as a command set to the non-volatile memory, wherein the first command includes a read command or a write command, and the confirm command is related to a read operation corresponding to the read command or a write operation corresponding to the write command. .

Effect of the Invention

[0010] According to the present invention Storage controller, its operating method, and non-volatile memory , it is possible to predict a communication error of a command and an address, generate an error detection signal only when a communication error is predicted, and transmit the error detection signal to a non-volatile memory, so that the storage controller can reduce performance degradation due to the generation and transmission of the error detection signal.

Brief Description of the Drawings

[0011] [Figure 1] It is a block diagram showing a schematic configuration of a storage device according to an embodiment of the present invention. [Figure 2A] It is a timing diagram showing communication between a storage controller and a non-volatile memory during a read operation of the non-volatile memory according to an embodiment of the present invention. <00001l4> [Figure 2B] It is a timing diagram showing communication between a storage controller and a non-volatile memory during a read operation of the non-volatile memory according to an embodiment of the present invention. <000011"7>This is a flowchart illustrating the read operation method between a storage controller and non-volatile memory according to one embodiment of the present invention. [Figure 4A] This is a timing diagram showing the communication between the storage controller and the non-volatile memory during a write operation of the non-volatile memory according to one embodiment of the present invention. [Figure 4B] This is a timing diagram showing the communication between the storage controller and the non-volatile memory during a write operation of the non-volatile memory according to one embodiment of the present invention. [Figure 5] This is a flowchart illustrating the write operation method between a storage controller and non-volatile memory according to one embodiment of the present invention. [Figure 6] This block diagram specifically illustrates the configuration of a storage controller according to one embodiment of the present invention. [Figure 7] This is a block diagram specifically illustrating the configuration of a non-volatile memory according to one embodiment of the present invention. [Figure 8] A block diagram showing a storage device according to one embodiment of the present invention. [Figure 9A] This is a timing diagram showing the communication between the storage controller and the non-volatile memory during a read operation of the non-volatile memory according to one embodiment of the present invention. [Figure 9B] This is a timing diagram showing the communication between the storage controller and the non-volatile memory during a read operation of the non-volatile memory according to one embodiment of the present invention. [Figure 9C] This is a timing diagram showing the communication between the storage controller and the non-volatile memory during a read operation of the non-volatile memory according to one embodiment of the present invention. [Figure 10A] This is a timing diagram showing the communication between the storage controller and the non-volatile memory during a write operation of the non-volatile memory according to one embodiment of the present invention. [Figure 10B] This is a timing diagram showing the communication between the storage controller and the non-volatile memory during a write operation of the non-volatile memory according to one embodiment of the present invention. [Figure 10C]This is a timing diagram showing the communication between the storage controller and the non-volatile memory during a write operation of the non-volatile memory according to one embodiment of the present invention. [Figure 11] This block diagram specifically illustrates the configuration of a storage controller according to one embodiment of the present invention. [Figure 12] This is a flowchart illustrating how a storage controller operates according to one embodiment of the present invention. [Figure 13] This is a flowchart illustrating the operation method of the storage controller and non-volatile memory in the first section according to one embodiment of the present invention. [Figure 14] This is a flowchart illustrating the operation method of the storage controller and non-volatile memory in the second section according to one embodiment of the present invention. [Figure 15] This is a flowchart illustrating the operation method of the storage controller and non-volatile memory in the third section according to one embodiment of the present invention. [Figure 16A] This is a timing diagram showing communication between a storage controller and non-volatile memory according to one embodiment of the present invention. [Figure 16B] This is a timing diagram showing communication between a storage controller and non-volatile memory according to one embodiment of the present invention. [Figure 17] This is a flowchart illustrating how a storage controller operates according to one embodiment of the present invention. [Figure 18] This block diagram shows a schematic configuration of a storage device according to an embodiment of the present invention. [Figure 19] This block diagram shows a schematic configuration of a system to which a storage device according to one embodiment of the present invention is applied. [Modes for carrying out the invention]

[0012] Next, according to the present invention Storage controller, its operating method, and non-volatile memory Specific examples of the forms for implementing this will be explained with reference to the drawings.

[0013] Figure 1 is a block diagram showing a schematic configuration of a storage device 10 according to one embodiment of the present invention. Referring to Figure 1, the storage device 10 includes a storage controller 100 and a non-volatile memory 200. The storage device 10 includes a recording medium for storing data upon request from the host.

[0014] As an example, the storage device 10 includes at least one of the following: an SSD (Solid State Drive), embedded memory, and removable external memory. If the storage device 10 is an SSD, the storage device 10 may be a device conforming to the NVMe (non-volatile memory express) standard. If the storage device 10 is embedded memory or external memory, the storage device 10 may be a device conforming to the UFS (universal flash storage) or eMMC (embedded multi-media card) standards.

[0015] Depending on the embodiment, the storage controller 100 may also be referred to as a controller, device controller, or memory controller. In one embodiment, the non-volatile memory 200 includes flash memory, in which case the storage controller 100 is also referred to as a flash memory controller (FMC). In some embodiments, the non-volatile memory 200 can also be represented by a plurality of memory chips or a plurality of memory dies. For example, each of the multiple memory chips could be a DDP (Dual Die Package), a QDP (Quadruple Die Package), or an Octuple Die Package.

[0016] The storage controller 100 controls the non-volatile memory 200 to write data to it in response to a write request from the host, or controls the non-volatile memory 200 to read data stored in it in response to a read request from the host. According to this embodiment, the storage controller 100 includes a command and address generator 110, an error detection module 120, an interface (I / F) circuit 130, and pins 1 to 4 (P1a to P1d). Pins 1 through 4 (P1a through P1d) correspond to pins 1 through 4 (P2a through P2d) of the non-volatile memory 200, respectively.

[0017] The command and address generator 110 generates commands and addresses (CMD / ADDR) for controlling the non-volatile memory 200. In one embodiment, the command and address (CMD / ADDR) are generated as a command set, which includes a first command CMD1, an address ADDR, and a second command (for example, CMD2 in Figure 2A), which are sequentially transmitted to the non-volatile memory 200. The first command, CMD1, indicates the type of memory operation, and the second command, CMD2, instructs the memory operation related to the first command, CMD1. In this embodiment, the first command CMD1 is referred to as the "input command," and the second command CMD2 is referred to as the "confirm command" or the "done command."

[0018] The error detection module 120 generates an Error Detection Signal (ED) to detect communication errors in commands and addresses (CMD / ADDR). In this embodiment, the error detection module 120 is referred to as a "command error detection module," a "command and address error detection module," or a "command set error detection module." For example, the error detection signal ED is a 1-bit signal. However, the present invention is not limited thereto, and the error detection signal ED can also be a multi-bit signal. Specifically, the error detection module 120 generates an error detection signal ED from the first command CMD1 and address ADDR generated by the command and address generator 110, and provides the generated error detection signal ED to the command and address generator 110.

[0019] In one embodiment, the error detection module 120 generates a parity bit from the first command CMD1 and address ADDR, and outputs the generated parity bit as an error detection signal ED. In one embodiment, the error detection module 120 generates a CRC (Cyclic Redundancy Check) value from the first command CMD1 and address ADDR, and outputs the generated CRC value as an error detection signal ED. In one embodiment, the error detection module 120 can generate a checksum from the first command CMD1 and address ADDR, and output the generated checksum as an error detection signal ED. However, the present invention is not limited to these, and the error detection module 120 can generate an error detection signal ED from the first command CMD1 and address ADDR using a variety of error detection programs or error detection logic.

[0020] The interface circuit 130 transmits multiple data signals DQ to the non-volatile memory 200 via the first pin P1a, or receives multiple data signals DQ from the non-volatile memory 200. Command CMD, address ADDR, and data DATA are transmitted via multiple data signals DQ. For example, multiple data signals DQ are transmitted through multiple data signal lines. The following description will focus on an embodiment in which the number of first pins P1a is 8. However, the present invention is not limited thereto, and the number of first pins P1a can be varied in various ways depending on the embodiment.

[0021] The interface circuit 130 receives a ready / busy output signal (nR / B) indicating the status information of the non-volatile memory 200 from the non-volatile memory 200 via the second pin P1b. Furthermore, the interface circuit 130 provides the command latch enable signal CLE and the address latch enable signal ALE to the non-volatile memory 200 via the third pin P1c and the fourth pin P1d, respectively. The interface circuit 130 transmits a command latch enable signal CLE, which has an enabled state, to the non-volatile memory 200, thereby transmitting a data signal DQ including the command CMD, and transmits an address latch enable signal ALE, which has an enabled state, to the non-volatile memory 200, thereby transmitting a data signal DQ including the address ADDR.

[0022] The non-volatile memory 200 includes a memory cell array 210, a control logic circuit 220, and an interface circuit 230. The interface circuit 230 receives multiple data signals DQ from the storage controller 100 via the first pin P2a, or transmits multiple data signals DQ to the storage controller 100. Furthermore, the interface circuit 230 receives the command latch enable signal CLE and the address latch enable signal ALE from the storage controller 100 via the third pin P2c and the fourth pin P2d, respectively. The interface circuit 230 transmits a ready / busy output signal (nR / B) to the storage controller 100 via the second pin P2b. When the non-volatile memory 200 is busy (i.e., when the internal operation of the non-volatile memory 200 is being performed), the interface circuit 230 transmits a ready / busy output signal (nR / B) indicating the busy state to the storage controller 100.

[0023] When the non-volatile memory 200 is in a ready state (i.e., when the internal operation of the non-volatile memory 200 is not being performed or has been completed), the interface circuit 230 transmits a ready / busy output signal (nR / B) indicating the ready state to the storage controller 100. For example, while the non-volatile memory 200 reads data DATA from the memory cell array 210 in response to a read command, the interface circuit 230 transmits a ready / busy output signal (nR / B) indicating a busy state (e.g., low level) to the storage controller 100. For example, while the non-volatile memory 200 programs data DATA in the memory cell array 210 in response to a program command, the interface circuit 230 transmits a ready / busy output signal (nR / B) indicating a busy state to the storage controller 100.

[0024] The memory cell array 210 includes multiple memory cells. For example, multiple memory cells can be flash memory cells. However, the present invention is not limited thereto, and the memory cell may be an RRAM (Resistive Random Access Memory) cell, an FRAM (Ferroelectric Random Access Memory) cell, a PRAM (Phase Change Random Access Memory) cell, a TRAM (Thyristor Random Access Memory) cell, or an MRAM (Magnetic Random Access Memory) cell. The following describes embodiments of the present invention, focusing on those in which the memory cell is a NAND flash memory cell.

[0025] The control logic circuit 220 provides overall control over the various operations of the non-volatile memory 200. The control logic circuit 220 determines the data signal DQ received via the first pin P2a during the enable interval of the command latch enable signal CLE as the command CMD, and determines the data signal DQ received via the first pin P2a during the enable interval of the address latch enable signal ALE as the address ADDR. The control logic circuit 220 generates control signals to control other components of the non-volatile memory 200 by command and address (CMD / ADDR). For example, the control logic circuit 220 generates various control signals to program data DATA into the memory cell array 210 or to read data DATA from the memory cell array 210.

[0026] In one embodiment, the control logic circuit 220 determines whether or not a communication error has occurred in the command and address (CMD / ADDR) based on the error detection signal ED included in the command and address (CMD / ADDR). If, as a result of the assessment, a communication error occurs in the command and address (CMD / ADDR), the non-volatile memory 200 transmits an error message (for example, code E in Figure 2B) to the storage controller 100. For example, error message E is transmitted to the storage controller 100 via the first pin P2a.

[0027] On the other hand, if no communication errors occur with the command and address (CMD / ADDR), the non-volatile memory 200 executes memory operations using the command and address (CMD / ADDR). For example, if the command (CDM / ADDR) includes a read command, data DATA can be read from the memory cell array 210. This will be explained in more detail with reference to Figures 2A, 2B, and 3. For example, if the command (CDM / ADDR) includes a write command, data DATA can be written to the memory cell array 210. This will be explained in more detail with reference to Figures 4A, 4B, and 5.

[0028] Figures 2A and 2B are timing diagrams showing communication between the storage controller 100 and the non-volatile memory 200 during a read operation of the non-volatile memory 200 according to one embodiment of the present invention. Referring to both Figure 1 and Figure 2A, the storage controller 100 sequentially transmits the first command 211, address 212, and second command 213 to the non-volatile memory 200 via multiple data signal lines. The first command 211 includes an input command (e.g., 00h) indicating that the type of memory operation is a read operation, and address 212 includes the first and second column addresses (C1, C2) and the first to third row addresses (R1, R2, R3). The second command, 213, is also a confirmation command that specifies the page size to read. For example, if the size of the page to be read is 4KB, the second command 213 includes the 4KB read command 50h. For example, if the size of the page to be read is 8KB, the second command 213 includes the 8KB read command 20h. For example, if the size of the page to be read is 16KB, the second command 213 includes the 16KB read command 30h.

[0029] In one embodiment, the error detection module 120 generates an error detection signal ED from the first command 211 and address 212, and the command and address generator 110 generates the second command 213 such that the reserved bit of the second command 213 includes the error detection signal ED. For example, the error detection signal ED is included in the MSB (Most Significant Bit) of the second command 213, but the present invention is not limited thereto. The non-volatile memory 200 determines whether a communication error has occurred at the first command 211 and address 212 based on the error detection signal ED. If, as a result of the assessment, no communication errors occur in the first command 211 and address 212, the non-volatile memory 200 performs a read operation and transmits the read data (R-DATA) to the storage controller 100.

[0030] Specifically, from the time of transmission of the second command 213 to the first hour t WB Thereafter, the non-volatile memory 200 will have a read operation time t R During this time, the read operation is performed. Reading operation time t R From the end of the second hour RR Thereafter, the non-volatile memory 200 transmits the read data (R-DATA) to the storage controller 100 via multiple data signal lines. For example, the first time t WB This corresponds to the enable interval of the write enable signal, and the second time t RR This corresponds to the enable interval of the read enable signal.

[0031] Referring to Figures 1 and 2B, the non-volatile memory 200 determines whether a communication error occurred at the first command 211 and address 212 based on the error detection signal ED. If, as a result of the determination, a communication error occurs in the first command 211 and address 212, the non-volatile memory 200 generates an error message E and transmits the error message E to the storage controller 100 via multiple data signal lines. In response to the error message E, the storage controller 100 sequentially transmits the first command 214, address 215, and second command 216 to the non-volatile memory 200 via multiple data signal lines. For example, the first command 214, address 215, and second command 216 are substantially identical to the previously transmitted first command 211, address 212, and second command 213, but the present invention is not limited thereto.

[0032] Figure 3 is a flowchart illustrating a read operation method between a storage controller 100 and a non-volatile memory 200 according to one embodiment of the present invention. Referring to Figures 1 to 3, in step S100, the storage controller 100 generates a read command and an address. For example, the read command corresponds to the first command 211 in Figures 2A and 2B, and the address corresponds to address 212 in Figures 2A and 2B. In step S110, the storage controller 100 generates an error detection signal ED from the read command and address. In step S120, the storage controller 100 generates a confirm command which includes the error detection signal ED. For example, the confirm command corresponds to the second command 213 in Figures 2A and 2B.

[0033] In step S130, the storage controller 100 transmits commands and addresses (CMD / ADDR) to the non-volatile memory 200 via multiple data signal lines. For example, the command and address (CMD / ADDR) includes a read command, an address, and a confirm command, which are transmitted sequentially to the non-volatile memory 200 via multiple data signal lines. In step S140, the non-volatile memory 200 detects a command and address (CMD / ADDR) communication error based on the error detection signal ED. Here, a command and address (CMD / ADDR) error is a communication error that occurs during the transmission of a command and address (CMD / ADDR). For example, the control logic circuit 220 detects communication errors in commands and addresses (CMD / ADDR) through logic calculations on the error detection signal ED.

[0034] In step S150, the non-volatile memory 200 determines whether a communication error has occurred in the command and address (CMD / ADDR). If, as a result of the assessment, a communication error occurs in the command and address (CMD / ADDR), then in step S160, the non-volatile memory 200 transmits an error message E to the storage controller 100. For example, error message E is transmitted to the storage controller 100 via multiple data signal lines.

[0035] In step S170, the storage controller 100 transmits the command and address (CMD / ADDR) to the non-volatile memory 200 again via multiple data signal lines. For example, the command and address (CMD / ADDR) includes a read command, an address, and a confirm command, which are transmitted sequentially to the non-volatile memory 200 via multiple data signal lines. For example, the read command, address, and confirm command correspond to the first command 214, address 215, and second command 216 in Figure 2B, respectively.

[0036] In step S180, the non-volatile memory 200 performs a read operation based on the command and address (CMD / ADDR). Specifically, the control logic circuit 220 has a read operation time t R During this time, data stored in the memory cell array 210 is read using commands and addresses (CMD / ADDR). In step S190, the non-volatile memory 200 transmits the read data R-DATA to the storage controller 100 via multiple data signal lines.

[0037] Figures 4A and 4B are timing diagrams showing communication between the storage controller 100 and the non-volatile memory 200 during a write operation of the non-volatile memory 200 according to one embodiment of the present invention. Referring to both FIG. 1 and FIG. 4A, the storage controller 100 sequentially transmits a first command 411, an address 412, write data (W-DATA), and a second command 413 to the non-volatile memory 200 via a plurality of data signal lines. The first command 411 includes an input command (e.g., 80h) indicating that the type of memory operation is a write operation, and the address 412 includes first and second column addresses (C1, C2) and first to third row addresses (R1, R2, R3). The second command 413 is also a confirm command (e.g., 10h) for instructing a write operation.

[0038] In one embodiment, the error detection module 120 generates an error detection signal ED from the first command 411 and the address 412, and the command and address generator 110 generates the second command 413 such that the reserved bit of the second command 413 includes the error detection signal ED. For example, the error detection signal ED is included in the MSB of the second command 413, but the present invention is not limited thereto. The non-volatile memory 200 determines whether a communication error has occurred in the first command 411 and the address 412 based on the error detection signal ED. As a result of the determination, if no communication error has occurred in the first command 411 and the address 412, the non-volatile memory 200 executes a write operation. Specifically, from the time point of transmission of the second command 413 to the first time t WB thereafter, the non-volatile memory 200 executes a write operation during the program operation time t PROG . For example, the first time t WB corresponds to the enable section of the write enable signal. After the end point of the program operation time t PROG the non-volatile memory 200 transmits a response message indicating that the write operation has been completed to the storage controller 100 via a plurality of data signal lines.

[0039] Referring to Figures 1 and 4B, the non-volatile memory 200 determines whether a communication error has occurred at the first command 411 and address 412 based on the error detection signal ED. If, as a result of the determination, a communication error occurs at the first command 411 and address 412, the non-volatile memory 200 generates an error message E and transmits the error message E to the storage controller 100 via multiple data signal lines. In response to the error message E, the storage controller 100 sequentially transmits a first command 414, address 415, write data (W-DATA), and a second command 416 to the non-volatile memory 200 via multiple data signal lines. For example, the first command 414, address 415, write data (W-DATA), and second command 416 are substantially identical to the previously transmitted first command 411, address 412, write data (W-DATA), and second command 413, but the present invention is not limited thereto. In one embodiment, the storage controller 100, in response to the error message E, sequentially transmits a first command 414, an address 415, and a second command 416 to the non-volatile memory 200 via a plurality of data signal lines, and does not necessarily transmit the write data (W-DATA) at this time.

[0040] Figure 5 is a flowchart illustrating a write operation method between a storage controller 100 and a non-volatile memory 200 according to one embodiment of the present invention. Referring to Figures 1, 4A, 4B, and 5, in step S200, the storage controller 100 generates a write command and an address. For example, the write command corresponds to the first command 411 in Figures 4A and 4B, and the address corresponds to address 412 in Figures 4A and 4B. In step S210, the storage controller 100 generates an error detection signal ED from the write command and address.

[0041] In step S220, the storage controller 100 generates a confirmation command that includes an error detection signal ED. For example, the confirm command corresponds to the second command 413 in Figures 4A and 4B. In step S230, the storage controller 100 transmits commands and addresses (CMD / ADDR) and write data (W-DATA) to the non-volatile memory 200 via multiple data signal lines. For example, the command and address (CMD / ADDR) includes a write command, an address, and a confirm command, and the write command, address, write data (W-DATA), and confirm command are transmitted sequentially to the non-volatile memory 200 via multiple data signal lines.

[0042] In step S240, the non-volatile memory 200 detects command and address (CMD / ADDR) errors based on the error detection signal ED. For example, a command and address (CMD / ADDR) error is a communication error that occurs during the transmission of a command and address (CMD / ADDR). For example, the control logic circuit 220 detects communication errors in commands and addresses (CMD / ADDR) through logic calculations on the error detection signal ED. In step S250, the non-volatile memory 200 determines whether or not a communication error has occurred in the command and address (CMD / ADDR). If, as a result of the assessment, a communication error occurs in the command and address (CMD / ADDR), then in step S260, the non-volatile memory 200 transmits an error message E to the storage controller 100. For example, error message E is transmitted to the storage controller 100 via multiple data signal lines.

[0043] In step S270, the storage controller 100 transmits the command and address (CMD / ADDR) to the non-volatile memory 200 again via multiple data signal lines. For example, the command and address (CMD / ADDR) includes a write command, an address, and a confirm command, which are transmitted sequentially to the non-volatile memory 200 via multiple data signal lines. For example, the write command, address, and confirm command correspond to the first command 414, address 415, and second command 416 in Figure 4B, respectively. In step S280, the non-volatile memory 200 performs a write operation using a command and address (CMD / ADDR). Specifically, the control logic circuit 220 operates during the program execution time t. PROG During this time, data is written to the memory cell array 210 using commands and addresses (CMD / ADDR). In step S290, the non-volatile memory 200 transmits a response message to the storage controller 100 via multiple data signal lines indicating the completion of the write operation.

[0044] Figure 6 is a block diagram that specifically shows the configuration of the storage controller 100 according to one embodiment of the present invention. Referring to both Figure 1 and Figure 6, the storage controller 100 includes a command and address generator 110, an error detection module 120, a processor 140, an ECC (Error Correction Code) engine 150, a host interface 160, and a non-volatile memory interface 170, which communicate via a bus 180. The processor 140 includes a CPU (Central Processing Unit) and a microprocessor, and controls the overall operation of the storage controller 100. In one embodiment, the processor 140 is embodied as a multi-core processor, and may be embodied as, for example, a dual-core processor or a quad-core processor.

[0045] In one embodiment, the command and address generator 110 and the error detection module 120 may be implemented by software. For example, the non-volatile memory 200 stores program code for command and address generation, and when power is applied to the storage device 10, the program code stored in the non-volatile memory 200 is loaded into the operating memory of the storage controller 100. The processor 140 executes the program code loaded into the operating memory, generating an error detection signal ED, a command, and an address (CMD / ADDR), as shown in Figures 1 to 5. However, the present invention is not limited thereto, and in one embodiment, the command and address generator 110 and the error detection module 120 may be embodied in hardware. In one embodiment, the command and address generator 110 and the error detection module 120 may be implemented by a combination of software and hardware.

[0046] In Figure 6, the command and address generator 110 and the error detection module 120 are shown as separate functional blocks from the non-volatile memory interface 170, but the present invention is not limited thereto. In one embodiment, at least one of the command and address generator 110 and the error detection module 120 may be implemented so as to be included in the non-volatile memory interface 170.

[0047] The host interface 160 sends and receives packets to and from the host. Packets transmitted from the host to the host interface 160 include commands or data recorded in the non-volatile memory 200, while packets transmitted from the host interface 160 to the host include responses to commands or data read from the non-volatile memory 200. The non-volatile memory interface 170 transmits data to be recorded in the non-volatile memory 200, i.e., write data (for example, (W-DATA) in Figures 4A and 4B), to the non-volatile memory 200, or receives data read from the non-volatile memory 200, i.e., read data (for example, (R-DATA) in Figures 2A and 2B). Such a non-volatile memory interface 170 is implemented to adhere to standard specifications such as Toggle or ONFI (Open NAND Flash Interface).

[0048] The ECC engine 150 performs error detection and correction functions related to the read data read from the non-volatile memory 200. More specifically, the ECC engine 150 generates parity bits for the data to be written to the non-volatile memory 200, and these generated parity bits are stored in the non-volatile memory 200 along with the data to be written. When reading data from the non-volatile memory 200, the ECC engine 150 corrects errors in the read data using parity bits read from the non-volatile memory 200 along with the read data, and outputs the error-corrected read data. Thus, the ECC engine 150 performs error detection and correction functions related to data, and the error detection module 120 performs error detection functions related to commands and addresses. In one embodiment, the error detection module 120 can also perform error detection and correction functions related to commands and addresses.

[0049] Although not shown in the diagram, the storage controller 100 may further include a Flash Translation Layer (FTL), a packet manager, buffer memory, and an AES (advanced encryption standard) engine. The storage controller 100 further includes working memory on which a flash conversion layer is loaded, and the processor 140 can control data write and read operations to the non-volatile memory 200 by executing the flash conversion layer.

[0050] Figure 7 is a block diagram specifically showing the configuration of a non-volatile memory 200 according to one embodiment of the present invention. Referring to both Figure 1 and Figure 7, the non-volatile memory 200 includes a memory cell array 210, a control logic circuit 220, an interface circuit 230, a page buffer circuit 240, a voltage generator 250, and a row decoder 260. The interface circuit 230 receives multiple data signals DQ, command latch enable signal CLE, and address latch enable signal ALE from the storage controller 100, and transmits a ready / busy output signal (nR / B) to the storage controller 100. For example, the interface circuit 230 may include multiple drive drivers and multiple receivers.

[0051] The interface circuit 230 determines, based on the command latch enable signal CLE and the address latch enable signal ALE, that multiple data signals DQ include a command CMD, an address ADDR, or data DATA. If multiple data signals DQ include a command CMD or address ADDR, the interface circuit 230 provides the command CMD or address ADDR to the control logic circuit 220. If multiple data signals DQ include data DATA, the interface circuit 230 provides the data DATA to the page buffer circuit 240.

[0052] The control logic circuit 220 provides overall control over the various operations within the non-volatile memory 200. The control logic circuit 220 outputs various control signals in response to the command CMD and / or address ADDR from the interface circuit 230. For example, the control logic circuit 220 outputs a voltage control signal (CTRL_vol), a row address (X-ADDR), and a column address (Y-ADDR). The control logic circuit 220 includes an error detection module 221, which detects communication errors of the command CMD and address ADDR. Specifically, the error detection module 221 detects communication errors between the command CMD and address ADDR by performing logic calculations on the error detection signal ED included in the command CMD. The control logic circuit 220 generates an error message if a communication error is detected and provides the generated error message to the interface circuit 230.

[0053] The interface circuit 230 provides the storage controller 100 with multiple data signals DQ, including error messages. Meanwhile, the control logic circuit 220 controls the page buffer circuit 240, the voltage generator 250, and the row decoder 260 so that no communication errors are detected and memory operations are performed according to the command CMD and address ADDR. The memory cell array 210 is connected to the page buffer circuit 240 via the bit line BL, and to the row decoder 260 via the word line WL, the string selection line SSL, and the ground selection line GSL. In an exemplary embodiment, the memory cell array 210 includes a three-dimensional memory cell array, the three-dimensional memory cell array includes a plurality of NAND strings. Each NAND string contains memory cells connected to word lines stacked vertically on the substrate.

[0054] U.S. Patent No. 7,679,133, U.S. Patent No. 8,553,466, U.S. Patent No. 8,654,587, U.S. Patent No. 8,559,235, and U.S. Patent Application Publication No. 2011 / 0233648 are incorporated herein by reference.

[0055] In an exemplary embodiment, the memory cell array 210 includes a two-dimensional memory cell array, the two-dimensional memory cell array includes a plurality of NAND strings arranged along the row and column directions. The page buffer circuit 240 selects at least one bit line from among the bit lines BL in response to the column address (Y_ADDR). The page buffer circuit 240 operates as either a write driver or a sense amplifier depending on the operating mode. For example, during program operation, the page buffer circuit 240 applies a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, the page buffer circuit 240 senses the current or voltage of the selected bit line to detect the data stored in the memory cell.

[0056] The voltage generator 250 generates various types of voltages for performing program, read, and erase operations based on a voltage control signal (CTRL_vol). For example, the voltage generator 250 generates program voltage, read voltage, program verification voltage, erase voltage, etc., as word line voltage VWL. The row decoder 260 selects one of several word lines WL and one of several string selection lines SSL in response to the row address (X_ADDR). For example, during program operation, the row decoder 260 applies a program voltage and a program verification voltage to the selected word line, and during read operation, it applies a read voltage to the selected word line.

[0057] Figure 8 is a block diagram showing a schematic configuration of a storage device 10a according to one embodiment of the present invention. Referring to Figure 8, the storage device 10a includes a storage controller 100a and a non-volatile memory 200a. Storage device 10a corresponds to a modified example of storage device 10 in Figure 1, and the details described with reference to Figures 1 to 7 also apply to this embodiment, thus omitting redundant explanations.

[0058] The command and address generator 110a generates commands and addresses (CMD / ADDR) for controlling the non-volatile memory 200a. In one embodiment, the command and address (CMD / ADDR) are generated as a command set including a first command CMD1, an address ADDR, and a second command (for example, CMD2 in Figure 2A), which are sequentially transmitted to the non-volatile memory 200a. The CRC (cyclic redundancy check) module 125 generates a CRC value (CRC-x) by executing CRC on the first command CMD1 and address ADDR.

[0059] Specifically, when the CRC module 125 transmits commands and addresses (CMD / ADDR) via multiple data signal lines, it calculates a check value, i.e., a CRC value (CRC-x), to confirm whether or not there are errors in the transmitted commands and addresses (CMD / ADDR). The generated CRC value (CRC-x) is transmitted to the non-volatile memory 200a via the first pin P1a. Here, x is a positive integer determined by the size of the CRC value to be generated. For example, if the CRC module 125 performs the (CRC-16) logic, then x is 16, and the CRC value (CRC-16) is generated as a 16-bit signal. For example, if the CRC module 125 performs (CRC-8) logic, then x is 8, and the CRC value (CRC-8) is generated in an 8-bit signal.

[0060] The CRC module 125 calculates a CRC value (CRC-x) based on the command and address (CMD / ADDR) before transmitting the command and address (CMD / ADDR), and transmits the CRC value (CRC-x) along with the command and address (CMD / ADDR) to the non-volatile memory 200a. In one embodiment, the CRC module 125 calculates a CRC value (CRC-x) for the command and address (CMD / ADDR) received after the command and address (CMD / ADDR) transmission is completed. If the two CRC values ​​are different, it can be determined that an error was added during the command and address (CMD / ADDR) transmission process due to noise or other factors.

[0061] In one embodiment, when the CRC module 125 receives an error message E from the non-volatile memory 200a, it can determine that the error was added during the command and address (CMD / ADDR) transmission process due to noise or other factors. The machine learning module 190 predicts the occurrence of command and address (CMD / ADDR) communication errors based on reliability probability values. Specifically, the machine learning module 190 measures the actual error rate of commands and addresses (CMD / ADDR), i.e., the communication error rate E. S The judgment error rate M determined by machine learning E The sum of these is the reference value B C Based on the comparison results, a machine learning decision system is applied when transmitting commands and addresses (CMD / ADDR).

[0062] If a communication error in the command and address (CMD / ADDR) is predicted, the machine learning module 190 enables the CRC module 125, which calculates a CRC value (CRC-x) from the first command CMD1 and address ADDR. The storage controller 100a then transmits the command and address (CMD / ADDR) along with the CRC value (CRC-x) to the non-volatile memory 200a. On the other hand, if it is predicted that no command and address (CMD / ADDR) communication errors have occurred, the machine learning module 190 disables the CRC module 125, thereby causing the storage controller 100a to transmit only the command and address (CMD / ADDR) to the non-volatile memory 200a, and not the CRC value (CRC-x).

[0063] As described above, according to this embodiment, the storage controller 100a uses the machine learning module 190 to predict communication errors in commands and addresses, generates an error detection signal (e.g., a CRC value) only when a communication error is predicted, and transmits the error detection signal (CRC value) to the non-volatile memory 200a. This allows the storage controller 100a to reduce performance degradation caused by the generation and transmission of error detection signals.

[0064] Figures 9A to 9C are timing diagrams showing the communication between the storage controller 100a and the non-volatile memory 200a during a read operation of the non-volatile memory 200a according to one embodiment of the present invention. The communication between the storage controller 100a and the non-volatile memory 200a in this embodiment corresponds to a modified example of the communication between the storage controller 100 and the non-volatile memory 200 illustrated in Figures 2A and 2B, and the details described with reference to Figures 2A and 2B also apply to this embodiment.

[0065] Referring to Figures 8 and 9A, the machine learning module 190 predicts that no command and address (CMD / ADDR) communication errors will occur. In this case, the machine learning module 190 disables the CRC module 125, so that the CRC module 125 does not calculate the CRC value. The storage controller 100a sequentially transmits the first command 911, address 912, and second command 914 to the non-volatile memory 200a via multiple data signal lines. For example, the first command 911 and address 912 correspond to the first command 211 and address 212 in Figure 2A, respectively. For example, the second command 914 is also a confirmation command that specifies the page size to read and does not necessarily have to include an error detection signal. For example, the second command 914 includes 50h, 20h, or 30h. The non-volatile memory 200a performs a read operation and transmits the read data (R-DATA) to the storage controller 100a.

[0066] Referring to both Figure 8 and Figure 9B, the machine learning module 190 predicts that a command and address (CMD / ADDR) communication error will occur. At this point, the machine learning module 190 enables the CRC module 125, which then calculates the CRC value 913 from the first command 911 and address 912. The storage controller 100a then sequentially transmits the first command 911, address 912, CRC value 913, and second command 914 to the non-volatile memory 200a via multiple data signal lines.

[0067] The CRC value 913 corresponds to the CRC value (CRC-x) generated by the CRC module 125. For example, the CRC module 125 applies the (CRC-16) error detection logic to perform a CRC on the first command 911 and address 912, thereby calculating (CRC-16)(1) and (CRC-16)(2), which are each provided as 8 bits. The non-volatile memory 200a determines whether a communication error occurred at the first command 911 and address 912 based on the CRC value 913. If, as a result of the assessment, no communication errors occur at the first command 911 and address 912, the non-volatile memory 200a performs a read operation and transmits the read data (R-DATA) to the storage controller 100a.

[0068] Referring to Figures 8 and 9C, the non-volatile memory 200a determines whether a communication error occurred at the first command 911 and address 912 based on the CRC value 913. If, as a result of the determination, a communication error occurs with the first command 911 and address 912, an error message E is generated and transmitted to the storage controller 100a via multiple data signal lines. In response to the error message E, the storage controller 100a sequentially transmits the first command 915, address 916, CRC value 917, and second command 918 to the non-volatile memory 200a via multiple data signal lines. For example, the first command 915, address 916, CRC value 917, and second command 918 are substantially identical to the previously transmitted first command 911, address 912, CRC value 913, and second command 914, but the present invention is not limited thereto.

[0069] Figures 10A to 10C are timing diagrams showing the communication between the storage controller 100a and the non-volatile memory 200a during a write operation of the non-volatile memory 200a according to one embodiment of the present invention. The communication between the storage controller 100a and the non-volatile memory 200a in this embodiment corresponds to a modified example of the communication between the storage controller 100 and the non-volatile memory 200 illustrated in Figures 4A and 4B, and the details described with reference to Figures 4A and 4B also apply to this embodiment.

[0070] Referring to Figures 8 and 10A, the machine learning module 190 predicts that no command and address (CMD / ADDR) communication errors will occur. In this case, the machine learning module 190 disables the CRC module 125, so that the CRC module 125 does not calculate the CRC value. The storage controller 100a sequentially transmits the first command 1011, address 1012, write data (W-DATA), and second command 1014 to the non-volatile memory 200a via multiple data signal lines.

[0071] For example, the first command 1011 and address 1012 correspond to the first command 411 and address 412 in Figure 4A, respectively. For example, the second command 1014 is a confirmation command that instructs a write operation (e.g., code 10h in Figure 8), and does not necessarily include an error detection signal. The non-volatile memory 200a executes a write operation for the data to be written (W-DATA), and once the write operation is complete, it transmits a response message to the storage controller 100a via multiple data signal lines indicating that the write operation is complete.

[0072] Referring to both Figure 8 and Figure 10B, the machine learning module 190 predicts that a command and address (CMD / ADDR) communication error will occur. At this time, the machine learning module 190 enables the CRC module 125, which calculates the CRC value 1013 from the first command 1011 and address 1012. The storage controller 100a then sequentially transmits the first command 1011, address 1012, CRC value 1013, write data (W-DATA), and the second command 1014 to the non-volatile memory 200a via multiple data signal lines.

[0073] The CRC value 1013 corresponds to the CRC value (CRC-x) generated by the CRC module 125. For example, the CRC module 125 applies the CRC-16 error detection logic to perform a CRC on the first command 1011 and address 1012, calculating (CRC-16)(1) and (CRC-16)(2), which are then provided as 8 bits each. The non-volatile memory 200a determines whether a communication error occurred at the first command 1011 and address 1012 based on the CRC value 1013. If, as a result of the assessment, no communication errors occurred at the first command 1011 and address 1012, the non-volatile memory 200a will execute the write operation for the data to be written (W-DATA).

[0074] Referring to Figures 8 and 10C, the non-volatile memory 200a determines whether a communication error occurred at the first command 1011 and address 1012 based on the CRC value 1013. If, as a result of the determination, a communication error occurs with the first command 1011 and address 1012, an error message E is generated and transmitted to the storage controller 100a via multiple data signal lines. In response to the error message E, the storage controller 100a sequentially transmits the first command 1015, address 1016, CRC value 1017, and the second command 1018 to the non-volatile memory 200a via multiple data signal lines. For example, the first command 1015, address 1016, CRC value 1017, and second command 1018 are substantially identical to the first command 1011, address 1012, CRC value 1013, and second command 1014 previously transmitted, but the present invention is not limited thereto.

[0075] Figure 11 is a block diagram that specifically shows the configuration of the storage controller 100a according to one embodiment of the present invention. Referring to both Figures 8 and 11, the storage controller 100a includes a command and address generator 110, a CRC module 125, a processor 140, an ECC engine 150, a host interface 160, a non-volatile memory interface 170, and a machine learning module 190, which communicate via a bus 180. Storage controller 100a corresponds to a modified example of storage controller 100 in Figure 6, and the details described with reference to Figure 6 also apply to this embodiment.

[0076] In one embodiment, the CRC module 125 is implemented by software. For example, the non-volatile memory 200a stores program code for CRC execution, and when power is applied to the storage device 10a, the program code stored in the non-volatile memory 200a is loaded into the operating memory of the storage controller 100a. Processor 140a executes the program code loaded into the operating memory and generates a CRC value (CRC-x) by performing CRC on the command and address (CMD / ADDR). However, the present invention is not limited thereto, and in one embodiment, the CRC module 125 can also be embodied in hardware. In one embodiment, the CRC module 125 can also be realized by a combination of software and hardware.

[0077] In one embodiment, the machine learning module 190 is implemented by software. For example, the non-volatile memory 200a stores program code for machine learning execution, and when power is applied to the storage device 10a, the program code stored in the non-volatile memory 200 is loaded into the operating memory of the storage controller 100a. The processor 140a executes the program code loaded into the operating memory to predict communication errors that may occur during the transmission of commands and addresses (CMD / ADDR), and enables the CRC module 125 based on the prediction results. However, the present invention is not limited thereto, and in one embodiment, the machine learning module 190 can also be embodied in hardware. In one embodiment, the machine learning module 190 can also be realized by a combination of software and hardware.

[0078] Figure 12 is a flowchart illustrating the operation of the storage controller 100a according to one embodiment of the present invention. Referring to Figure 12, in step S310, the machine learning module 190 of the storage controller 100a performs learning. Stage S310 begins when the command and address generator 110 of the storage controller 100a issues commands and addresses. Specifically, the machine learning module 190 learns about the commands and addresses transmitted from the storage controller 100a to the non-volatile memory 200a, and whether or not communication errors occur for those commands and addresses.

[0079] In step S320, it is determined whether the number of times n commands and addresses are processed is greater than the first reference value N1. Based on the judgment, if the number of processing steps n is greater than the first criterion value N1, step S330 is executed; otherwise, the machine learning module 190 continues learning. For example, the first reference value N1 may be 1,000,000 times, but the present invention is not limited to that. The machine learning module 190 performs learning during the first interval, for example, from the time of transmission of the first command and address that is first transmitted until the time of transmission of the 1,000,000th command and address that is the 1,000,000th command and address that is transmitted. As a result, the machine learning module 190 calculates the communication error rate, i.e., a statistical value, for the first to 1,000,000 commands and addresses. A detailed explanation of stages S310 and S320 will be provided later with reference to Figure 13.

[0080] In step S330, the machine learning module 190 collects machine learning-based decision data by predicting whether or not communication errors occur in commands and addresses (CMD / ADDR). During this process, the machine learning module 190 continues to learn about the commands and addresses transmitted from the storage controller 100a to the non-volatile memory 200a, and whether or not communication errors occur with respect to those commands and addresses.

[0081] In step S340, it is determined whether the number of command and address processing times n is greater than the second reference value N2. Based on the judgment, if the number of processing steps n is greater than the second criterion value N2, step S350 is executed; otherwise, the machine learning module 190 continues learning. For example, the second reference value N2 could be 2,000,000 times, but the present invention is not limited to that. The machine learning module 190 collects machine learning-based decision data by predicting whether or not communication errors occur in each of the following during the second interval, for example, the 1,000,001st command and address transmitted as the 1,000,001st command and address, up to the 2,000,000th command and address transmitted as the 2,000,000th command and address. As a result, the machine learning module 190 can determine the machine learning-based judgment error rate or the judgment error rate M E Calculate. For example, the judgment error rate M E This could be 0.000007.

[0082] Furthermore, the machine learning module 190 continues to collect machine learning-based decision data by predicting whether or not communication errors occur for each command and address from the 1,000,001st command and address to the 2,000,000th command and address during the second interval. As a result, the machine learning module 190 has a communication error rate E between the first and second intervals, i.e., between the first command and address and the 2,000,000th command and address (CMD / ADDR). S Calculate. In this case, the communication error rate E S This corresponds to the statistical figures for when communication errors actually occurred. For example, communication error rate E S This could be 0.000007. A detailed explanation of stages S330 and S340 will be provided later with reference to Figure 14.

[0083] In stage S350, the communication error rate E S Judgment error rate M E The sum of these is the reference value B C Determine whether it is smaller than or equal to. Here, the reference value B C This is a reference value for applying the machine learning decision system, and could be, for example, 0.0015%, or 0.000015. Based on the assessment, the communication error rate is E. S Judgment error rate M E The sum of these is the reference value B C If it is smaller, perform step S370; otherwise, continue with step S330. In step S360, the storage controller 100a applies the judgment system of the machine learning module 190 to predict whether or not a command and address communication error has occurred.

[0084] For example, communication error rate E S This is 0.000007, and the judgment error rate M E This is 0.000007, and the reference value is B. C If it is 0.000015, the communication error rate E S Judgment error rate M E The sum of these, 0.1000014, is the reference value B. C It is smaller than 0.000015. As a result, the storage controller 100a can apply the judgment system of the machine learning module 190 to subsequent commands and addresses to predict the occurrence of communication errors.

[0085] In stage S370, the communication error rate ME determined by machine learning. S The reference value is B C Determine whether it is smaller than or equal to. Here, the communication error rate ME S This corresponds to the statistical value of an actual error that occurred when a machine learning decision system is applied to predict communication errors for commands and addresses, and the CRC value is transmitted along with the command and address only when a communication error is predicted. Based on the assessment, the communication error rate ME S The reference value is B C If it is smaller than that, proceed to step S360; otherwise, proceed to step S330.

[0086] For example, communication error rate ME SThe value is 0.000016, and if the baseline value BC is 0.000015, then the communication error rate ME S 0.000016 is the reference value B C It is greater than 0.000015. As a result, in step S330, the machine learning module 190 continues to perform the step of collecting decision data. On the other hand, the communication error rate ME S The reference value is B C If it is smaller than this, the decision system of machine learning module 190 is considered suitable. As a result, in stage S360, the storage controller 100a continues to apply the judgment system of the machine learning module 190 to predict whether or not a command and address communication error will occur. A detailed explanation of stages S360 and S370 will be provided later with reference to Figure 15.

[0087] Figure 13 is a flowchart illustrating the operation method of the storage controller 100a and the non-volatile memory 200a in the first section according to one embodiment of the present invention. Referring to both Figure 9 and Figure 13, the first interval corresponds to the interval from the time the storage controller 100a issues the command and address (CMD / ADDR) until the time the number of command and address (CMD / ADDR) processing counts n reaches the first reference value N1. For example, the first reference value N1 could be 1,000,000 times.

[0088] In stage S400, the storage controller 100a generates commands and addresses. In step S410, the storage controller 100a generates a CRC value from the generated command and address. For example, as illustrated in Figure 9C, the storage controller 100a generates a CRC value 913 from the first command 911 that instructs a read operation and address 912. For example, as illustrated in Figure 10C, the storage controller 100a generates a CRC value 1013 from the first command 1011 that instructs a write operation and address 1012.

[0089] In step S420, the storage controller 100a transmits commands and addresses (CMD / ADDR) and CRC values ​​(for example, symbols 911-914 in Figure 9C, or symbols 1011-1014 in Figure 10C) to the non-volatile memory 200a via multiple data signal lines. In step S440, the non-volatile memory 200a detects errors in the command and address (CMD / ADDR) based on the CRC value. In step S450, the non-volatile memory 200a determines whether or not an error has occurred. If an error occurs as a result of the judgment, in step S460, the non-volatile memory 200a transmits an error message E to the storage controller 100a via multiple data signal lines.

[0090] In step S470, the storage controller 100a again transmits the command and address (CMD / ADDR) and CRC value (for example, symbols 915-918 in Figure 9C, or symbols 1015-1018 in Figure 10C) to the non-volatile memory 200a via multiple data signal lines.

[0091] In stage S480, the storage controller 100a performs machine learning. Specifically, the machine learning module 190 performs learning for determining communication errors of commands and addresses (CMD / ADDR) based on how it receives error message E related to commands and addresses (CMD / ADDR) in the first interval. For example, the first section corresponds to the transmission section for commands and addresses from the 1st to the 1,000,000th. In this process, the machine learning module 190 calculates the communication error rate based on statistical data showing that actual errors occurred in the first to 1,000,000 commands and addresses during the first interval. In step S490, the non-volatile memory 200a performs memory operations according to the command and address.

[0092] Figure 14 is a flowchart illustrating the operation method of the storage controller 100a and the non-volatile memory 200a in the second section according to one embodiment of the present invention. Referring to both Figure 9 and Figure 14, the second interval corresponds to the period from when the number of command and address (CMD / ADDR) processing counts n in the storage controller 100a reaches the second reference value N2, after the first reference value N1. For example, the second reference value N2 could be 2,000,000 times. The steps S500 to S590 shown in Figure 14 can be performed after step S490 in Figure 13.

[0093] In stage S500, the storage controller 100a generates commands and addresses. In step S510, the storage controller 100a generates a CRC value from the generated command and address. In step S520, the machine learning module 190 predicts whether a communication error will occur based on the command and address. Specifically, the machine learning module 190 determines whether a communication error has occurred for each command and address issued in the second section, based on the results learned in the first section. In one embodiment, steps S510 and S520 may be performed substantially simultaneously. In one embodiment, step S520 may be performed prior to step S510.

[0094] In step S530, the storage controller 100a transmits commands and addresses (CMD / ADDR) and CRC values ​​(for example, symbols 911-914 in Figure 9C, or symbols 1011-1014 in Figure 10C) to the non-volatile memory 200a via multiple data signal lines. In step S540, the non-volatile memory 200a detects errors in the command and address (CMD / ADDR) based on the CRC value. In step S550, the non-volatile memory 200a determines whether or not an error has occurred. If an error occurs as a result of the judgment, in step S560, the non-volatile memory 200a transmits an error message E to the storage controller 100a via multiple data signal lines. In step S570, the storage controller 100a again transmits the command and address (CMD / ADDR) and CRC value (for example, symbols 915-918 in Figure 9C or symbols 1015-1018 in Figure 10C) to the non-volatile memory 200a via multiple data signal lines.

[0095] In step S580, the storage controller 100a collects predictive or decision data through machine learning. For example, the second section corresponds to the transmission section for commands and addresses from 1,000,001 to 2,000,000. Specifically, the machine learning module 190 determines the machine learning error rate M based on the error judgment results and actual error occurrence results associated with each of the 1,000,001 to 2,000,000 commands and addresses in the second interval. E Calculate.

[0096] Furthermore, the machine learning module 190 continues to perform learning for determining communication errors in commands and addresses (CMD / ADDR) based on how it receives error message E related to commands and addresses (CMD / ADDR) in the second section. In this process, the machine learning module 190 calculates the communication error rate E based on the statistical data of actual errors that occurred in the first to 2,000,000 commands and addresses in the first and second intervals. S Calculate. In step S590, the non-volatile memory 200a performs memory operations according to the command and address.

[0097] Figure 15 is a flowchart illustrating the operation method of the storage controller 100a and the non-volatile memory 200a in the third section according to one embodiment of the present invention. Referring to both Figure 9 and Figure 15, the third interval corresponds to the interval after the second reference value N2 in which the number of command and address (CMD / ADDR) processing counts n in the storage controller 100a occurs. For example, the second reference value N2 could be 2,000,000 times. The steps S600 to S690 shown in Figure 15 can be performed after step S590 in Figure 14.

[0098] In stage S600, the storage controller 100a generates commands and addresses. In step S610, the machine learning module 190 predicts whether a communication error will occur based on the command and address. In step S620, the machine learning module 190 determines whether or not a communication error was predicted to occur. If the assessment predicts that a communication error will occur, step S640 will be performed. On the other hand, if it is predicted that no communication errors will occur, in step S630, the storage controller 100a transmits commands and addresses (CMD / ADDR) to the non-volatile memory 200a via multiple data signal lines.

[0099] In step S640, the storage controller 100a generates a CRC value from the command and address (CMD / ADDR). In step S650, the storage controller 100a transmits commands and addresses (CMD / ADDR) and CRC values ​​(for example, symbols 911-914 in Figure 9C, or symbols 1011-1014 in Figure 10C) to the non-volatile memory 200a via multiple data signal lines. In step S660, the non-volatile memory 200a detects errors in the command and address (CMD / ADDR) based on the CRC value.

[0100] In step S670, the non-volatile memory 200a determines whether or not an error has occurred. If an error occurs as a result of the judgment, in step S675, the non-volatile memory 200a transmits an error message E to the storage controller 100a via multiple data signal lines. In step S680, the storage controller 100a again transmits the command and address (CMD / ADDR) and CRC value (e.g., symbols 915-918 in Figure 9C, or symbols 1015-1018 in Figure 10C) to the non-volatile memory 200a via multiple data signal lines. In step S690, the non-volatile memory 200a performs memory operations based on commands and addresses.

[0101] Figures 16A and 16B are timing diagrams showing communication between a storage controller 100a and a non-volatile memory 200a according to one embodiment of the present invention. Referring to Figures 8, 16A, and 16B, the CRC module 125 includes multiple error detection logics, including a first error detection logic and a second error detection logic, and a selected error detection logic among the multiple error detection logics generates an error detection signal, i.e., a CRC value, related to the command and address. Specifically, the CRC module 125 applies the first error detection logic to perform error detection operations associated with each of the multiple commands / addresses, and based on the comparison result between the communication error rate of the multiple commands / addresses and the error rate of the first error detection logic, it changes the selected error detection logic from the first error detection logic to the second error detection logic.

[0102] In one embodiment, the first error detection logic may be a (CRC-k) error detection logic, and the second error detection logic may be a (CRC-m) error detection logic. Here, k and m are positive integers, and k is greater than m. The CRC module 125 applies the (CRC-k) error detection logic to calculate a first CRC value from each first command / address. If the (CRC-k) error rate is greater than the communication error rate for the first command / address, it applies the (CRC-m) error detection logic to calculate a second CRC value from each second command / address.

[0103] In one embodiment, the plurality of error detection logics further include a third error detection logic, where the first error detection logic is a (CRC-k) error detection logic and the third error detection logic is a (CRC-l) error detection logic. Here, k and l are positive integers, and k is less than l. The CRC module 125 applies the (CRC-k) error detection logic to calculate a first CRC value from each first command / address. If the (CRC-k) error rate is not greater than the communication error rate for the first command / address, it applies the (CRC-l) error detection logic to calculate a second CRC value from each second command / address.

[0104] Specifically, the storage controller 100a applies (CRC-16) error detection logic during the first interval to calculate the CRC value, i.e., (CRC-16), from the command and address. For example, the first interval corresponds to the period from the time of issuance of the command and address until the number of times the command and address are processed or issued reaches a predetermined threshold value. The storage controller 100a sequentially transmits the first command 1611, address 1612, CRC value 1613, and second command 1614 to the non-volatile memory 200a via multiple data signal lines. For example, the first command 1611 includes an input command (e.g., 80h) indicating that the type of memory operation is a read operation, and address 1612 includes the first and second column addresses (C1, C2) and the first to third row addresses (R1, R2, R3). The second command 1614 may be a confirmation command specifying the page size to read (e.g., 50h, 20h, or 30h).

[0105] The CRC module 125 calculates the CRC value 1613 from the first command 1611 and address 1612. For example, the CRC module 125 applies the (CRC-16) error detection logic to perform a CRC on the first command 1611 and address 1612, thereby calculating (CRC-16)(1) and (CRC-16)(2), which are each provided as 8 bits. The non-volatile memory 200a determines whether a communication error occurred at the first command 1611 and address 1612 based on the CRC value 1613. If, as a result of the assessment, no communication errors occur in the first command 1611 and address 1612, the non-volatile memory 200a performs a read operation and transmits the read data 1615 to the storage controller 100a.

[0106] The storage controller 100a applies (CRC-8) error detection logic during the second interval following the first interval to calculate the CRC value, i.e., (CRC-8), from the command and address. For example, the second section corresponds to the period from the end of the first section until the number of times commands and addresses are processed or issued reaches a predetermined threshold value. The storage controller 100a sequentially transmits the first command 1616, address 1617, CRC value 1618, and second command 1619 to the non-volatile memory 200a via multiple data signal lines.

[0107] The CRC module 125 calculates the CRC value 1618 from the first command 1616 and address 1617. For example, the CRC module 125 calculates the (CRC-8) by applying the (CRC-8) error detection logic and performing a CRC on the first command 1616 and address 1617, and the (CRC-8) is provided in 8 bits. The non-volatile memory 200a determines whether a communication error occurred at the first command 1616 and address 1617 based on the CRC value 1618. If, as a result of the assessment, no communication errors occur with the first command 1616 and address 1617, the non-volatile memory 200a performs a read operation and transmits the read data 1620 to the storage controller 100a.

[0108] The storage controller 100a applies (CRC-4) error detection logic during the third period following the second period to calculate the CRC value, i.e., (CRC-4), from the command and address. For example, the third section corresponds to the period from the end of the second section until the number of times commands and addresses are processed or issued reaches a predetermined threshold value. The storage controller 100a sequentially transmits the first command 1621, address 1622, CRC value 1623, and second command 1624 to the non-volatile memory 200a via multiple data signal lines.

[0109] The CRC module 125 calculates the CRC value 1623 from the first command 1621 and address 1622. For example, the CRC module 125 calculates the (CRC-4) by applying the (CRC-4) error detection logic and performing a CRC on the first command 1621 and address 1622, and the (CRC-4) is provided as a 4-bit value. The non-volatile memory 200a determines whether a communication error occurred at the first command 1621 and address 1622 based on the CRC value 1623. If, as a result of the assessment, no communication errors occur with the first command 1621 and address 1622, the non-volatile memory 200a performs a read operation and transmits the read data 1625 to the storage controller 100a.

[0110] The storage controller 100a applies (CRC-1) error detection logic during the fourth period, from the third period onward, to calculate the CRC value, i.e., (CRC-1), from the command and address. For example, the fourth section corresponds to the period from the end of the third section until the number of times commands and addresses are processed or issued reaches a predetermined threshold value. The storage controller 100a sequentially transmits the first command 1626, address 1627, CRC value 1628, and the second command 1629 to the non-volatile memory 200a via multiple data signal lines.

[0111] The CRC module 125 calculates the CRC value 1628 from the first command 1626 and address 1627. For example, the CRC module 125 calculates (CRC-1) by applying (CRC-1) error detection logic and performing a CRC on the first command 1626 and address 1627, and (CRC-1) is provided as a single bit. The non-volatile memory 200a determines whether a communication error occurred at the first command 1626 and address 1627 based on the CRC value 1628. If, as a result of the assessment, no communication errors occur with the first command 1626 and address 1627, the non-volatile memory 200a performs a read operation and transmits the read data 1630 to the storage controller 100a. However, the present invention is not limited thereto, and (CRC-1) may be included in the spare bits of the second command 1629.

[0112] Figure 17 is a flowchart illustrating how the storage controller 100a operates according to one embodiment of the present invention. Referring to both Figure 8 and Figure 17, the storage controller 100a compares the actual error rate of commands and addresses with the reliability of the error detection logic, and dynamically changes the error detection logic based on the comparison results. The storage controller 100a repeatedly performs a comparison operation at predetermined reference intervals n.

[0113] Specifically, after applying the first error detection logic, if the number of command and address processing times n corresponds to a reference number N, the storage controller 100a performs a comparison operation to decide whether or not to change the error detection logic. Furthermore, if the error detection logic is changed from the first error detection logic to the second error detection logic, and after applying the second error detection logic, if the number of command and address processing times n corresponds to the reference number N, the storage controller 100a performs a comparison operation to decide whether or not to change the error detection logic. The following describes the operation of the storage controller 100a, using the case where the error detection logic is CRC error detection logic as an example, with reference to Figures 8, 16, and 17.

[0114] When a command is issued, in step S710, the CRC module 125 applies the (CRC-16) error detection logic to calculate a CRC value from the command and address. In step S720, it is determined whether the number of times n the command and address to which the (CRC-16) error detection logic is applied corresponds to the reference number N. For example, the reference number N could be 5,000,000 times, but the present invention is not limited thereto. If the result of the judgment is that the number of times n the command and address are processed is less than the reference number N, then in step S710, the CRC module 125 continues to apply the (CRC-16) error detection logic and calculates the CRC value from the command and address.

[0115] On the other hand, if the number of times n commands and addresses are processed corresponds to a reference number N, then in step S730, it is determined whether the error rate of (CRC-16) is greater than the actual error rate. For example, the error rate for (CRC-16) is 0.000015258789. If the error rate of (CRC-16) is greater than the actual error rate, perform step S740. On the other hand, if the error rate of (CRC-16) is not as high as the actual error rate, then it is judged that the actual error rate is very high. In that case, an error detection logic with a lower error rate than (CRC-16) is applied to generate an error detection signal from the command and address (step S735).

[0116] In step S740, the CRC module 125 calculates the CRC value from the command and address by applying an error detection logic (CRC-8) with a higher error rate than (CRC-16). In step S750, it is determined whether the number of times n the command and address to which the (CRC-8) error detection logic is applied corresponds to the reference number N. For example, the reference number N could be 5,000,000 times, but the present invention is not limited thereto. If the result of the judgment is that the number of times n the command and address are processed is less than the reference number N, then in step S740, the CRC module 125 continues to apply the (CRC-8) error detection logic and calculates the CRC value from the command and address.

[0117] On the other hand, if the number of times n commands and addresses are processed corresponds to a baseline number N, then in step S760, it is determined whether the error rate of (CRC-8) is greater than the actual error rate. If the error rate of (CRC-8) is greater than the actual error rate, execute step S770. On the other hand, if the error rate of (CRC-8) is not as high as the actual error rate, it is judged that the actual error rate is high. In that case, returning to step S710, the CRC module 125 applies the (CRC-16) error detection logic to calculate the CRC value from the command and address. For example, the error rate of (CRC-8) is 0.00390625, and the actual error rate E S However, if it is 0.0015, the error rate of (CRC-8) is the actual error rate E S Since it is larger, we will perform step S770.

[0118] In step S770, the CRC module 125 calculates the CRC value from the command and address by applying an error detection logic (CRC-4) which has a higher error rate than (CRC-8). In step S780, it is determined whether the number of times n the command and address to which the (CRC-4) error detection logic is applied corresponds to the reference number N. For example, the reference number N could be 5,000,000 times, but the present invention is not limited thereto. If the result of the judgment is that the number of times n the command and address are processed is less than the reference number n, then in step S770, the CRC module 125 continues to apply the (CRC-4) error detection logic and calculates the CRC value from the command and address.

[0119] On the other hand, if the number of times n commands and addresses are processed corresponds to a reference number N, then in step S790, it is determined whether the error rate of (CRC-4) is greater than the actual error rate. For example, the error rate of (CRC-4) is 0.0625. If the error rate of (CRC-4) is greater than the actual error rate, proceed to step S770. On the other hand, if the error rate of (CRC-4) is not as high as the actual error rate, it is judged that the actual error rate is high. In that case, returning to step S740, the CRC module 125 applies the (CRC-8) error detection logic to calculate the CRC value from the command and address.

[0120] According to the embodiment described above, the storage controller 100a selects one of several error detection logics based on the error rate of commands and addresses, thereby reducing the computational load on the storage controller 100a based on the actual communication error rate.

[0121] Figure 18 is a block diagram showing a schematic configuration of a storage device 20 according to an embodiment of the present invention. Referring to Figure 18, the storage device 20 includes a memory device 300 and a memory controller 400. The memory device 300 corresponds to the non-volatile memory 200 in Figure 1 or the non-volatile memory 200a in Figure 8. The memory controller 400 corresponds to the storage controller 100 in Figure 1 or the storage controller 100a in Figure 8.

[0122] The memory device 300 includes pins 1 to 8 (P11 to P18), a memory interface circuit 310, a control logic circuit 320, and a memory cell array 330. The memory interface circuit 310 receives the chip enable signal nCE from the memory controller 400 via the first pin P11. The memory interface circuit 310 transmits and receives signals to and from the memory controller 400 via the second to eighth pins (P12 to P18) using the chip enable signal nCE. For example, when the chip enable signal nCE is in the enabled state (e.g., low level), the memory interface circuit 310 sends and receives signals to and from the memory controller 400 via pins 2 to 8 (P12 to P18).

[0123] The memory interface circuit 310 receives the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE from the memory controller 400 via the second to fourth pins (P12 to P14). The memory interface circuit 310 receives the data signal DQ from the memory controller 400 via pin 7 P17, or transmits the data signal DQ to the memory controller 400. The command CMD, address ADDR, and data DATA are transmitted via the data signal DQ. For example, a data signal DQ can be transmitted through multiple data signal lines. In that case, pin 7 P17 includes multiple pins corresponding to multiple data signals DQ.

[0124] The memory interface circuit 310 obtains the command CMD from the data signal DQ, which is received during the enable interval (e.g., high-level state) of the command latch enable signal CLE, based on the toggle timing of the write enable signal nWE. The memory interface circuit 310 obtains the address ADDR from the data signal DQ, which is received during the enable interval (e.g., high-level state) of the address latch enable signal ALE, based on the toggle timing of the write enable signal nWE. In an exemplary embodiment, the write enable signal nWE holds a static state (e.g., high level or low level) and toggles between high and low levels. For example, the write enable signal nWE toggles during the transmission of the command CMD or address ADDR. As a result, the memory interface circuit 310 obtains the command CMD or address ADDR based on the toggle timing of the write enable signal nWE.

[0125] The memory interface circuit 310 receives a read enable signal nRE from the memory controller 400 via the fifth pin P15. The memory interface circuit 310 receives the data strobe signal DQS from the memory controller 400 via pin 6 P16, or transmits the data strobe signal DQS to the memory controller 400. In the data output operation of the memory device 300, the memory interface circuit 310 receives a toggle read enable signal nRE via the 5th pin P15 before outputting the data DATA. The memory interface circuit 310 generates a data strobe signal DQS that toggles based on the toggling of the read enable signal nRE. For example, the memory interface circuit 310 generates a data strobe signal DQS that starts to toggle after a pre-set delay (e.g., tDQSRE) based on the toggling start time of the read enable signal nRE. The memory interface circuit 310 transmits a data signal DQ containing data DATA based on the toggle timing of the data strobe signal DQS. As a result, the data DATA is aligned with the toggle timing of the data strobe signal DQS and transmitted to the memory controller 400.

[0126] During the data input operation of the memory device 300, when a data signal DQ containing data DATA is received from the memory controller 400, the memory interface circuit 310 receives a data strobe signal DQS that toggles along with the data DATA from the memory controller 400. The memory interface circuit 310 acquires data DATA from the data signal DQ based on the toggle timing of the data strobe signal DQS. For example, the memory interface circuit 310 acquires data DATA by sampling the data signal DQ at the rising and falling edges of the data strobe signal DQS.

[0127] The memory interface circuit 310 transmits a ready / busy output signal (nR / B) to the memory controller 400 via pin 8 P18. The memory interface circuit 310 transmits status information of the memory device 300 to the memory controller 400 via a ready / busy output signal (nR / B). When the memory device 300 is busy (i.e., when the internal operation of the memory device 300 is in progress), the memory interface circuit 310 transmits a ready / busy output signal (nR / B) indicating the busy state to the memory controller 400. When the memory device 300 is in a ready state (i.e., when internal operations of the memory device 300 are not being performed or have been completed), the memory interface circuit 310 transmits a ready / busy output signal (nR / B) indicating the ready state to the memory controller 400.

[0128] For example, while the memory device 300 reads data DATA from the memory cell array 330 in response to a page read command, the memory interface circuit 310 transmits a ready / busy output signal (nR / B) indicating a busy state (e.g., low level) to the memory controller 400. For example, while the memory device 300 is programming data DATA in the memory cell array 330 in response to a program instruction, the memory interface circuit 310 transmits a ready / busy output signal (nR / B~) indicating a busy state to the memory controller 400.

[0129] The control logic circuit 320 provides overall control over the various operations of the memory device 300. The control logic circuit 320 receives commands and addresses (CMD / ADDR) obtained from the memory interface circuit 310. The control logic circuit 320 generates control signals to control other components of the memory device 300 based on the received command and address (CMD / ADDR). For example, the control logic circuit 320 generates various control signals to program data DATA into the memory cell array 330 or to read data DATA from the memory cell array 330.

[0130] The memory cell array 330 stores data DATA acquired from the memory interface circuit 310 under the control of the control logic circuit 320. The memory cell array 330 outputs the stored data DATA to the memory interface circuit 310 under the control of the control logic circuit 320. The memory cell array 330 includes multiple memory cells.

[0131] For example, multiple memory cells can be flash memory cells. However, the present invention is not limited thereto, and the memory cell may be an RRAM (Resistive Random Access Memory) cell, an FRAM (Ferroelectric Random Access Memory) cell, a PRAM (Phase Change Random Access Memory) cell, a TRAM (Thyristor Random Access Memory) cell, or an MRAM (Magnetic Random Access Memory) cell. The embodiments of the present invention will be described below, focusing primarily on embodiments in which the memory cell is a NAND flash memory cell.

[0132] The memory controller 400 includes pins 1 to 8 (P21 to P28) and a controller interface circuit 410. Pins 1 through 8 (P21 through P28) correspond to pins 1 through 8 (P11 through P18) of the memory device 300. The controller interface circuit 410 transmits the chip enable signal nCE to the memory device 300 via the first pin P21. The controller interface circuit 410 transmits and receives signals to and from the selected memory device 300 via the chip enable signal nCE, through pins 2 to 8 (P22 to P28).

[0133] The controller interface circuit 410 transmits the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device 300 via the second to fourth pins (P22 to P24). The controller interface circuit 410 transmits the data signal DQ to the memory device 300 via pin 7 P27, or receives the data signal DQ from the memory device 300. The controller interface circuit 410 transmits a data signal DQ, which includes a command CMD or address ADDR, to the memory device 300 along with a toggleable write enable signal nWE.

[0134] The controller interface circuit 410 transmits a command latch enable signal CLE, which has an enabled state, to the memory device 300, thereby transmitting a data signal DQ including the command CMD, and transmits an address latch enable signal ALE, which has an enabled state, to the memory device 300, thereby transmitting a data signal DQ including the address ADDR. The controller interface circuit 410 transmits a read enable signal nRE to the memory device 300 via the fifth pin P25. The controller interface circuit 410 receives the data strobe signal DQS from the memory device 300 via pin 6 P26, or transmits the data strobe signal DQS to the memory device 300.

[0135] During the data output operation of the memory device 300, the controller interface circuit 410 generates a toggleable read enable signal nRE and transmits the read enable signal nRE to the memory device 300. For example, the controller interface circuit 410 generates a read enable signal nRE that is changed from a fixed state (e.g., high level or low level) to a toggle state before the data DATA is output. This generates a data strobe signal DQS that toggles in the memory device 300 based on the read enable signal nRE. The controller interface circuit 410 receives a data signal DQ containing data DATA along with a toggle data strobe signal DQS from the memory device 300. The controller interface circuit 410 acquires data DATA from the data signal DQ based on the toggle timing of the data strobe signal DQS.

[0136] During the data input operation of the memory device 300, the controller interface circuit 410 generates a toggle data strobe signal DQS. For example, the controller interface circuit 410 generates a data strobe signal DQS that is changed from a fixed state (e.g., high level or low level) to a toggle state before transmitting data DATA. The controller interface circuit 410 transmits the data signal DQ, which includes the data DATA, to the memory device 300 based on the toggle timing of the data strobe signal DQS. The controller interface circuit 410 receives a ready / busy output signal (nR / B) from the memory device 300 via pin 8 P28. The controller interface circuit 410 determines the status information of the memory device 300 based on the ready / busy output signal (nR / B).

[0137] Figure 19 is a block diagram showing a schematic configuration of system 1000 to which a storage device according to one embodiment of the present invention is applied. System 1000 in Figure 19 can basically be a mobile system such as a mobile phone, smartphone, tablet PC, wearable device, healthcare device, or IoT (Internet of Things) device. However, the system 1000 of FIG. 19 is not necessarily limited to a mobile system, and can also be a personal computer, a laptop computer, a server, a media player, or an automotive device such as navigation.

[0138] Referring to FIG. 19, the system 1000 includes a main processor 1100, memories (1200a, 1200b), and storage devices (1300a, 1300b), and further includes one or more of an image capturing device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supplying device 1470, and a connecting interface 1480.

[0139] The main processor 1100 controls the overall operation of the system 1000, and more specifically, the operations of other components constituting the system 1000. Such a main processor 1100 can be implemented by a general-purpose processor, a dedicated processor, an application processor, or the like. The main processor 1100 includes one or more CPU cores 1110, and further includes a controller 1120 for controlling the memories (1200a, 1200b) and / or the storage devices (1300a, 1300b).

[0140] According to one embodiment, the main processor 1100 further includes an accelerator 1130, which is a dedicated circuit for high-speed data operations such as AI (artificial intelligence) data operations. Such an accelerator 1130 may include a GPU (Graphics Processing Unit), an NPU (Neural Processing Unit), and / or a DPU (Data Processing Unit), and may also be embodied by a separate chip that is physically independent of the other components of the main processor 1100.

[0141] The memory (1200a, 1200b) is used as the main memory of system 1000 and includes volatile memory such as SRAM and / or DRAM, but may also include non-volatile memory such as flash memory, PRAM and / or RRAM. The memory (1200a, 1200b) can be implemented in the same package as the main processor 1100.

[0142] The storage devices (1300a, 1300b) function as non-volatile storage devices that save data regardless of the power supply, and have a relatively larger storage capacity compared to the memory (1200a, 1200b). The storage devices (1300a, 1300b) include a storage controller (1310a, 1310b) and non-volatile memory (NVM) (1320a, 1320b) that stores data under the control of the storage controller (1310a, 1310b). Non-volatile memory (1320a, 1320b) includes flash memory with a 2D (2-dimensional) structure or a 3D (3-dimensional) V-NAND (Vertical NAND) structure, but may also include other types of non-volatile memory such as PRAM and / or RRAM. Referring to Figure 19, the storage devices (1300a, 1300b) correspond to the storage devices (10, 10a, or 20) illustrated in Figures 1, 8, or 15.

[0143] The storage devices (1300a, 1300b) are included in the system 1000, physically separated from the main processor 1100, and can be implemented within the same package as the main processor 1100. Furthermore, the storage devices (1300a, 1300b) can take the form of an SSD (solid state device) or a memory card, and can be detachably coupled to other components of the system 1000 through an interface such as the connection interface 1480 described later. Such storage devices (1300a, 1300b) are devices to which standard specifications such as UFS (universal flash storage), eMMC (embedded multi-media card), or NVMe (non-volatile memory express) apply, but this is not necessarily the case.

[0144] The imaging device 1410 captures still images or videos and may be a camera, camcorder, and / or webcam. The user input device 1420 receives various types of data input from the user of the system 1000 and may be a touch pad, keypad, keyboard, mouse, and / or microphone. Sensor 1430 senses various types of physical quantities acquired from outside the system 1000 and converts the sensed physical quantities into electrical signals. Such sensors 1430 may be temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors, and / or gyroscope sensors.

[0145] The communication device 1440 performs signal transmission and reception with other devices outside the system 1000 using various communication protocols. Such a communication device 1440 may be embodied in the form of an antenna, a transceiver and / or a modem. The display 1450 and speaker 1460 function as output devices that output visual and auditory information, respectively, to the user of the system 1000. The power supply device 1470 appropriately converts power supplied from a battery (not shown) built into the system 1000 and / or an external power source and supplies it to each component of the system 1000. The connection interface 1480 provides a connection between the system 1000 and an external device that is connected to the system 1000 and can send and receive data with the system 1000.

[0146] The 1480 connection interface can also be implemented through a variety of interface methods, such as ATA (Advanced Technology Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe, IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC, UFS, eUFS (embedded Universal Flash Storage), and CF (compact flash) card interfaces.

[0147] Furthermore, the present invention is not limited to the embodiments described above. It can be modified and implemented in various ways without departing from the technical scope of the present invention. [Explanation of symbols]

[0148] 10, 10a, 100a storage devices 100, 100a Storage Controllers 110, 110a Command and address generator 120 Error Detection Module 125 CRC module 130, 230 I / F circuit 140 processors 150 ECC engine 160 Host I / F 170 Non-volatile memory interface 190 Machine Learning Modules 200, 200a Non-volatile memory 200a Non-volatile memory 210 memory cell array 220 Control Logic Circuits 221 Error Detection Module 240-page buffer circuit 250 Voltage Generator 260 Low Decoder 270 CRC modules

Claims

1. A storage controller configured to control non-volatile memory, A command and address generator configured to generate a command set consisting of a first command, an address, and a second command, Here, the second command includes an error detection signal for detecting a communication error between the first command and the address, An error detection module is configured to generate the error detection signal from the first command and the address so that the non-volatile memory can detect a communication error in the first command and the address, The non-volatile memory includes an interface circuit configured to sequentially transmit the first command, the address, and the second command as the command set, The first command indicates the type of memory operation to be performed in the non-volatile memory, The storage controller is characterized in that the second command corresponds to a confirm command related to memory operations.

2. The storage controller according to claim 1, characterized in that the error detection signal is a 1-bit signal.

3. The error detection module is further configured to generate a parity bit from the first command and the address, The storage controller according to claim 1, characterized in that the parity bit is the error detection signal.

4. The error detection module is further configured to generate a CRC (Cyclic Redundancy Check) value from the first command and the address, The storage controller according to claim 1, characterized in that the CRC value is the error detection signal.

5. The error detection module is further configured to generate a checksum from the first command and the address, The storage controller according to claim 1, characterized in that the checksum is the error detection signal.

6. The interface circuit further transmits a command latch enable signal having an enable level to the non-volatile memory during the transmission intervals of the first command and the second command. The storage controller according to claim 1, characterized in that it is configured to transmit an address latch enable signal having an enable level to the non-volatile memory during the address transmission section.

7. The storage controller according to claim 1, wherein the interface circuit is further configured to receive an error message from the non-volatile memory when a communication error is detected.

8. The storage controller according to claim 7, characterized in that the interface circuit sequentially transmits the first command, the address, and the second command to the non-volatile memory again based on the error message.

9. A non-volatile memory, An interface circuit configured to sequentially receive a first command, an address, and a second command as a command set from a storage controller, Here, the second command includes an error detection signal for detecting a communication error between the first command and the address, A memory cell array containing multiple memory cells, The system includes a control logic circuit configured to detect communication errors in the first command and the address based on the error detection signal, The first command indicates the type of memory operation to be performed in the non-volatile memory, The non-volatile memory is characterized in that the second command corresponds to a confirm command related to memory operations.

10. The non-volatile memory according to claim 9, characterized in that the error detection signal is a 1-bit signal.

11. The non-volatile memory according to claim 9, characterized in that the error detection signal includes a parity bit generated from the first command and the address.

12. The non-volatile memory according to claim 9, characterized in that the error detection signal includes a CRC (Cyclic Redundancy Check) value generated from the first command and the address.

13. The non-volatile memory according to claim 9, characterized in that the error detection signal includes a checksum generated from the first command and the address.

14. The non-volatile memory according to claim 9, wherein the interface circuit is further configured to transmit an error message to the storage controller when a communication error is detected.

15. A method for operating a storage controller configured to control non-volatile memory, The first step involves generating the command and address, A step of generating an error detection signal from the first command and the address, As a result, the non-volatile memory detects a communication error in the first command and the address. The steps include generating a confirm command that includes the aforementioned error detection signal, The process includes the step of sequentially transmitting the first command, the address, and the confirm command as a command set to the non-volatile memory, The first command includes a read command or a write command, A method for operating a storage controller, characterized in that the confirmation command is related to a read operation corresponding to the read command or a write operation corresponding to the write command.

16. The method of operating a storage controller according to claim 15, characterized in that the step of generating the error detection signal includes the step of generating the error detection signal which includes a 1-bit signal.

17. The method of operating a storage controller according to claim 15, characterized in that the step of generating the error detection signal includes the step of generating the error detection signal including a parity bit from the first command and the address.

18. The method of operating a storage controller according to claim 15, characterized in that the step of generating the error detection signal includes the step of generating the error detection signal including a CRC (Cyclic Redundancy Check) value from the first command and the address.

19. The method of operating a storage controller according to claim 15, characterized in that the step of generating the error detection signal includes the step of generating the error detection signal including a checksum from the first command and the address.

20. The method of operating a storage controller according to claim 15, further comprising the step of receiving an error message from the non-volatile memory when the communication error is detected.

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