Asynchronous data networking over a network bus

Abstract

The present disclosure provides a system for data networking. The system includes a plurality of asynchronous data devices, including a router device and a set of base station devices. The system further includes a master-slave communication protocol interface. Each of the plurality of asynchronous data devices is coupled to the master-slave communication protocol interface. Data is transmitted over a two-wire bus between the router device and the set of base station devices via the master-slave communication protocol interface.

Description

Technical Field

[0001] Cross - reference to related applications This application is a non - provisional application claiming the benefit of Indian Provisional Patent Application No. 2022 / 41023709, filed on April 22, 2022, entitled "Method for Asynchronous Data Networking Over A2B", the content of which is incorporated herein by reference in its entirety.

[0002] The present disclosure relates to a method for networking, and more particularly, to a method for asynchronous data networking via a network bus.

Background Art

[0003] As electronic components are miniaturized and the expectations for performance increase, more components are included in devices that previously had few or no components. In some settings, the communication infrastructure used to exchange signals between such components (e.g., within a vehicle) has required thick and heavy cable bundles.

[0004] Therefore, there is a need to provide a communication infrastructure with efficient and uncomplicated connections.

Summary of the Invention

Means for Solving the Problems

[0005] The present disclosure provides a system for data networking. The system includes a plurality of asynchronous data devices, including a router device and a set of base station devices. The system further includes a master - slave communication protocol interface. Each of the plurality of asynchronous data devices is coupled to the master - slave communication protocol interface. Data is transmitted via a two - wire bus between the router device and the set of base station devices through the master - slave communication protocol interface.

[0006] In one embodiment, a method is provided. This method includes coupling a plurality of asynchronous data devices, including a set of router devices and base station devices. This method further includes coupling each of the plurality of asynchronous data devices to a master-slave communication protocol interface. Data is transmitted via the master-slave communication protocol interface over a two-wire bus between the router devices and the base station devices. [Brief explanation of the drawing]

[0007] The present invention will now be described in more detail with reference to the accompanying drawings, which are not intended to be limiting.

[0008] [Figure 1] This is a block diagram illustrating various examples of two-wire communication systems. [Figure 2] This is a block diagram of node transceivers that may be included in the nodes of the system in Figure 1, in various configurations. [Figure 3] This is a diagram showing a portion of a synchronous control frame used for communication within the system shown in Figure 1, in various configurations. [Figure 4] This is a diagram of superframes used for communication within the system shown in Figure 1, in various configurations. [Figure 5] The following illustrates exemplary formats for synchronous control frames in different operating modes of the system shown in Figure 1, depending on various configurations. [Figure 6] The following illustrates exemplary formats for synchronous response frames in different operating modes of the system shown in Figure 1, depending on various configurations. [Figure 7] This is a block diagram of various components of the bus protocol circuit shown in Figure 2, in various configurations. [Figure 8] Examples of information exchange along a two-wire bus according to various embodiments of the bus protocol described herein are illustrated. [Figure 9] Examples of information exchange along a two-wire bus according to various embodiments of the bus protocol described herein are illustrated. [Figure 10]Examples of information exchange along a two-wire bus according to various embodiments of the bus protocol described herein are illustrated. [Figure 11] Examples of information exchange along a two-wire bus according to various embodiments of the bus protocol described herein are illustrated. [Figure 12] Various ring topologies for two-wire buses and one-way communication schemes on the bus are illustrated. [Figure 13] This is a block diagram of devices that can function as nodes or hosts in the system shown in Figure 1, in various configurations. [Figure 14] This is a flowchart illustrating asynchronous device networking via a 2-wire bus in various configurations. [Figure 15] This diagram illustrates systems and methods for asynchronous device networking over a two-wire bus in various configurations. [Figure 16] This diagram illustrates systems and methods for asynchronous device networking over a two-wire bus in various configurations. [Figure 17] This diagram illustrates systems and methods for asynchronous device networking over a two-wire bus in various configurations. [Figure 18] This diagram illustrates systems and methods for asynchronous device networking over a two-wire bus in various configurations. [Figure 19] This diagram illustrates systems and methods for asynchronous device networking over a two-wire bus in various configurations. [Figure 20] This is a flowchart of the method in various forms. [Figure 21] This is a flowchart of the method in various forms. [Figure 22] This is a flowchart of the method in various forms. [Figure 23] This is a flowchart of the method in various forms. [Modes for carrying out the invention]

[0009] This specification discloses systems and techniques for an efficient mechanism to network data devices via a network bus. The data devices can be asynchronous data devices. The network bus can be a two-wire bus. The network bus can be a Serial Peripheral Interface (SPI). In some examples, the method provides a virtual peer-to-peer communication mechanism on a shared bus with a single owner. Additionally, the method can provide a mechanism for instantaneous bandwidth allocation. Further, the method can provide mechanisms for latency management and flow control. The method can also include a caching mechanism for rapid startup. In some examples, the system and method include the Musical Instrument Digital Interface (MIDI) protocol, which operates via an SPI interface or other types of master-slave communication protocol interfaces.

[0010] Generally, sharing bandwidth cooperatively while meeting latency requirements is a problem in networking technology. Ethernet includes a mechanism for reserving bandwidth using the Audio Video Bridging (AVB) protocol. Network bus protocols can offer synchronous bandwidth and lower cost. Within network bus protocols, synchronous slots can be used for bulk data transfer by implementing protocols such as High-Level Data Link Control (HDLC). However, these are MIPS-intensive and do not use bandwidth efficiently.

[0011] The network bus can provide SPI functionality over long distances. However, the network bus does not include hardware support for cooperatively sharing bandwidth. Additionally, each node in a typical network bus cannot initiate transactions independently. This specification provides systems and techniques to enable nodes in a network bus to initiate transactions independently.

[0012] In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and like numerals designate like parts throughout. By way of illustration, embodiments that may be implemented are shown. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present disclosure. Accordingly, the following detailed description is not to be taken in a limiting sense.

[0013] Various operations may be described in turn, as a plurality of distinct actions or operations, in a manner that is most helpful in understanding the claimed subject matter. However, the order of description is not to be construed as implying that these operations necessarily depend on order. In particular, these operations may not be performed in the order of presentation. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed and / or the described operations may be omitted in additional embodiments.

[0014] For the purposes of the present disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of the present disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0015] In this specification, various components may be referred to or illustrated in the singular (e.g., "processor", "peripheral device", etc.), but this is merely for ease of discussion, and any element referred to in the singular may include a plurality of such elements according to the teachings of this specification.

[0016] In this description, the phrases “in an aspect” or “in aspects” may refer to one or more of the same or different aspects, respectively. Furthermore, as used in reference to aspects of this disclosure, terms such as “comprising,” “including,” and “having” are synonymous. As used herein, the term “circuit” may mean, be part of, or include, application-specific integrated circuits (ASICs), electronic circuits, and optical circuits, (shared, dedicated, or group) processors and / or (shared, dedicated, or group) memory running one or more software or firmware programs, combinational logic circuits providing the described functions, and / or other suitable hardware.

[0017] Regarding naming conventions, in the case of A2B, there are primary and secondary nodes. In the case of SPI, there are controller nodes and responder nodes. In the case of MIDI protocols, there are routers and base stations or base station devices.

[0018] Figure 1 is a block diagram of an exemplary half-duplex two-wire communication system (hereinafter referred to as the System) 100 in various configurations. The System 100 includes a host 110, a main node 102-1, and at least one subnode 102-2. Three subnodes (0, 1, and 2) are illustrated in Figure 1. The depiction of the three subnodes 102-2 in Figure 1 is purely illustrative, and the System 100 may include one, two, or more subnodes 102-2 as desired.

[0019] Main node 102-1 can communicate with subnode 102-2 via a two-wire bus 106. Bus 106 may include different two-wire bus links between adjacent nodes along bus 106 to connect nodes along bus 106 in a daisy-chain configuration. For example, as shown in Figure 1, bus 106 may include a link connecting main node 102-1 to subnode 0, a link connecting subnode 0 to subnode 1, and a link connecting subnode 1 to subnode 2. In some embodiments, each link of bus 106 may be formed from a single stranded pair (e.g., an unshielded twisted pair). In some embodiments, each link of bus 106 may be formed from a coaxial cable (e.g., having a core providing a "positive" line and a shield providing a "negative" line, or vice versa). The two-wire bus links also provide a complete electrical path (e.g., a forward current path and a return current path) so as not to require the use of additional grounding or voltage source lines.

[0020] The host 110 may include a processor that programs the main node 102-1 and acts as both the sender and receiver of various payloads transmitted along the bus 106. In some embodiments, the host 110 may be, or include, a microcontroller. Specifically, the host 110 may be the master of inter-integrated sound (I2S) communications occurring along the bus 106. The host 110 may communicate with the main node 102-1 via the I2S / Time Division Multiplexing (TDM) protocol, the Serial Peripheral Interface (SPI) protocol, and / or the Inter-Integrated Circuit (I2C) protocol. In some embodiments, the main node 102-1 may be a transceiver (e.g., a node transceiver 120, discussed below with reference to Figure 2) located within the same housing as the host 110. The main node 102-1 may be programmable by the host 110 via the I2C bus for configuration and readability and may be configured to generate the clock, synchronization, and framing for all subnodes 102-2. In some embodiments, an extension of the I2C control bus between host 110 and main node 102-1 may be embedded in a data stream transmitted via bus 106, allowing host 110 to directly access registers and status information for one or more subnodes 102-2, and enabling long-range I2C-to-I2C communication to allow host 110 to control peripheral devices 108. In some embodiments, an extension of the SPI control bus between host 110 and main node 102-1 may be embedded in a data stream transmitted via bus 106, allowing host 110 to directly access registers and status information for one or more subnodes 102-2, and enabling long-range SPI-to-SPI or SPI-to-I2C communication to allow host 110 to control peripheral devices 108. In embodiments where system 100 is included in a vehicle, host 110 and / or main node 102-1 may be included in the vehicle's headend.

[0021] Main node 102-1 may generate “downstream” signals (e.g., data signals, power signals, etc., transmitted away from main node 102-1 along bus 106) and may receive “upstream” signals (e.g., transmitted towards main node 102-1 along bus 106). Main node 102-1 may provide a clock signal for synchronous data transmission via bus 106. As used herein, “synchronous data” may include data (e.g., audio signals) that is streamed continuously at regular time intervals between two consecutive transmissions to / from the same node along bus 106. In some embodiments, the clock signal provided by main node 102-1 may be derived from an I2S input provided to main node 102-1 by host 110. Subnode 102-2 may be an addressable network connection point representing a possible destination for data frames transmitted downstream or upstream on bus 106. Subnode 102-2 may also represent a possible source of a downstream or upstream data frame. System 100 may enable control information and other data to be transmitted bidirectionally from one node to the next via bus 106. One or more of the subnodes 102-2 may also be powered by signals transmitted via bus 106.

[0022] Specifically, each of the main node 102-1 and subnode 102-2 may include a positive upstream terminal (indicated as "AP"), a negative upstream terminal (indicated as "AN"), a positive downstream terminal (indicated as "BP"), and a negative downstream terminal (indicated as "BN"). The positive and negative downstream terminals of a node may be coupled to the positive and negative upstream terminals of adjacent downstream nodes, respectively. As shown in Figure 1, the main node 102-1 may include a positive and negative upstream terminal, but these terminals may not be used, and in other embodiments, the main node 102-1 may not include a positive or negative upstream terminal. The last subnode 102-2 along the bus 106 (subnode 2 in Figure 1) may include a positive and negative downstream terminal, but these terminals may not be used, and in other embodiments, the last subnode 102-2 along the bus may not include a positive or negative downstream terminal.

[0023] As will be discussed in detail below, the main node 102-1 may optionally periodically send synchronous control frames downstream along with data destined for one or more of the subnodes 102-2. For example, the main node 102-1 may send synchronous control frames at a frequency of 48 kHz for every 1024 bits (representing a superframe), resulting in an effective bitrate of 49.152 Mbps on bus 106. Other rates may be supported, including, for example, 44.1 kHz. The synchronous control frames may enable the subnodes 102-2 to identify the beginning of each superframe, and, in combination with physical layer coding / signaling, may enable each subnode 102-2 to derive its internal operating clock from bus 106. The synchronous control frame may include a preamble for signaling the start of synchronization, as well as control fields enabling various addressing modes (e.g., normal, broadcast, discovery), configuration information (e.g., writing to registers on subnode 102-2), transmission of I2C information, transmission of SPI information, remote control of specific general-purpose input / output (GPIO) pins on subnode 102-2, and other services. Parts of the synchronous control frame following the preamble and payload data may be scrambled to reduce the likelihood of information within the synchronous control frame being mistaken for a new preamble and to flatten the spectrum of associated electromagnetic radiation.

[0024] The synchronous control frame may pass through subnodes 102-2 (along with other data that may optionally come from the main node 102-1, but additionally or alternatively from one or more upstream subnodes 102-2, or from subnode 102-2 itself) until it reaches the last subnode 102-2 (i.e., subnode 2 in Figure 1), which is configured by the main node 102-1 as the last subnode 102-2, or which has self-identified itself as the last subnode 102-2. Upon receiving the synchronous control frame, the last subnode 102-2 may transmit a synchronous response frame, followed by any data that it is permitted to transmit (e.g., a 24-bit audio sample within a specified time slot). The synchronous response frame may be passed upstream between subnodes 102-2 (optionally, along with data from downstream subnodes 102-2), and based on the synchronous response frame, each subnode 102-2 may be able to identify the time slot, if any, that subnode 102-2 is permitted to transmit.

[0025] In some embodiments, one or more of the subnodes 102-2 within the system 100 may be coupled to and communicate with a peripheral device 108. For example, a subnode 102-2 may be configured to read data from and / or write data to an associated peripheral device 108 using the I2S protocol, pulse density modulation (PDM) protocol, TDM protocol, SPI protocol, and / or I2C protocol and / or interface, as discussed below. In this specification, “peripheral device 108” may be referred to in the singular form, but this is simply for the sake of clarity, and a single subnode 102-2 may be coupled to zero, one, or more peripheral devices. Examples of peripheral devices that may be included in peripheral device 108 include digital signal processors (DSPs), field-programmable gate arrays (FPGAs), ASICs, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), codecs, microphones, microphone arrays, speakers, audio amplifiers, protocol analyzers, accelerometers or other motion sensors, environmental condition sensors (e.g., temperature sensors, humidity sensors, and / or gas sensors), wired or wireless communication transceivers, display devices (e.g., touchscreen displays), user interface components (e.g., buttons, dials, or other control keys), cameras (e.g., video cameras), memory devices, or any other suitable devices for transmitting and / or receiving data. Several examples of different peripheral device configurations will be discussed in detail herein.

[0026] In some embodiments, peripheral device 108 may include any device configured for I2S communication, and peripheral device 108 may communicate with associated subnode 102-2 via the I2S protocol. In some embodiments, peripheral device 108 may include any device configured for I2C communication, and peripheral device 108 may communicate with associated subnode 102-2 via the I2C protocol. In some embodiments, peripheral device 108 may include any device configured for SPI communication, and peripheral device 108 may communicate with associated subnode 102-2 via the SPI protocol. In some embodiments, subnode 102-2 may not be coupled to any peripheral device 108.

[0027] Subnodes 102-2 and their associated peripheral devices 108 may be housed in separate housings, coupled via wired or wireless communication connections, or housed in a common housing. For example, a speaker connected as a peripheral device 108 may be packaged together with the hardware for the associated subnode 102-2 (e.g., a node transceiver 120, discussed below with reference to Figure 2) so that the hardware for the associated subnode 102-2 is housed in a housing that also contains other speaker components. The same may apply to any type of peripheral device 108.

[0028] As discussed above, host 110 can communicate with and control main node 102-1 using multi-channel I2S communication protocols, SPI communication protocols, and / or I2C communication protocols. For example, host 110 can send data via I2S to a frame buffer (not shown) in main node 102-1, and main node 102-1 can read data from the frame buffer and send the data along bus 106. Similarly, main node 102-1 can store data received via bus 106 in a frame buffer and then send the data to host 110 via I2S.

[0029] Each subnode 102-2 may have internal control registers, which may be configured by communication from the main node 102-1. Some such registers will be discussed in detail below. Each subnode 102-2 may receive downstream data and retransmit data further downstream. Each subnode 102-2 may receive and / or generate upstream data, and / or retransmit data upstream, and / or add data to upstream transactions.

[0030] Communication along bus 106 may occur in periodic superframes. Each superframe may begin with a downstream synchronous control frame, be divided into a downstream transmission period (also called the “downstream portion”), an upstream transmission period (also called the “upstream portion”), and a no-transmission period (when bus 106 is not driven), and may end immediately before the transmission of another downstream synchronous control frame. Main node 102-1 may be programmed (by host 110) with some downstream portions for transmitting to one or more of the subnodes 102-2, and some upstream portions for receiving from one or more of the subnodes 102-2. Each subnode 102-2 may be programmed (by main node 102-1) with some downstream portions for retransmitting down bus 106, some downstream portions for consumption, some upstream portions for retransmitting up bus 106, and some upstream portions from which the subnode 102-2 may transmit data received from the subnode 102-2 from its associated peripheral device 108. Communication along bus 106 will be discussed in more detail below with reference to Figures 2 to 12.

[0031] The embodiments of the communication system 100 disclosed herein are unique among conventional communication systems in that all subnodes 102-2 can receive output data via bus 106 within the same superframe (for example, all subnodes 102-2 can receive the same voice sample without sample delay between nodes 102). In conventional communication systems, data is buffered and processed within each node before being passed to the next node downstream in the next frame. As a result, in these conventional communication systems, the data transmission latency depends on the number of nodes (each node adds a delay of one voice sample). In the communication system 100 disclosed herein, bus 106 can add only one cycle of latency, regardless of whether the data is received by the first subnode or the last subnode 102-2. The same applies to upstream communication, where data may be available to the upstream node 102 in the next superframe, regardless of which subnode 102-2 provided the data.

[0032] Furthermore, in embodiments of the communication system 100 disclosed herein, downstream data (e.g., downstream voice data) may be carried on bus 106 by the main node 102-1 or by any of the subnodes 102-2 upstream of the receiving subnode 102-2, and similarly, upstream data (e.g., upstream voice data) may be carried on bus 106 by any of the subnodes 102-2 downstream of the receiving node 102 (i.e., the main node 102-1 or subnode 102-2). Such capability enables a subnode 102-2 to provide both upstream and downstream data at a specific time (e.g., a specific voice sample time). In the case of voice data, this data can be received at the next voice sample of any downstream node 102 or upstream node 102 without further delay (other than a slight delay to enter the superframe boundary). As will be further discussed herein, a control message (e.g., in a synchronous control frame (SCF)) may be moved to the last node 102 (addressing a specific node 102 or broadcast), and an upstream response (e.g., in a synchronous response frame (SRF)) may be created by the last downstream node 102 within the same superframe. Node 102 addressed by the SCF modifies the contents of the upstream SRF in its response. As a result, control and response can be fully performed across multiple nodes 102 within the same voice sample. This also contrasts with conventional communication systems where sample latency occurs between nodes (for relaying messages from one node to another).

[0033] Each of the main node 102-1 and subnode 102-2 may include a transceiver for managing communication between components of system 100. Figure 2 is a block diagram of a node transceiver 120 that may be included in a node of system 100 in Figure 1 (e.g., main node 102-1 or subnode 102-2) in various embodiments. In some embodiments, the node transceiver 120 may be included in each of the nodes of system 100, and control signals may be provided to the node transceiver 120 via the main pin to indicate whether the node transceiver 120 is functioning as a main node (e.g., when the main pin is high) or as a subnode (e.g., when the main pin is low).

[0034] The node transceiver 120 may include an upstream differential signaling (DS) transceiver 122 and a downstream DS transceiver 124. The upstream DS transceiver 122 may be coupled to the positive upstream terminal and the negative upstream terminal discussed above with reference to Figure 1, and the downstream DS transceiver 124 may be coupled to the positive downstream terminal and the negative downstream terminal discussed above with reference to Figure 1. In some embodiments, the upstream DS transceiver 122 may be a low-voltage DS (LVDS) transceiver, and the downstream DS transceiver 124 may be an LVDS transceiver. Each node of system 100 may be AC ​​coupled to bus 106, and data signals may be transmitted along bus 106 (e.g., via upstream DS transceiver 122 and / or downstream DS transceiver 124) using a predetermined form of DS (e.g., LVDS or multipoint LVDS (MLVDS) or similar signal transmission) with appropriate encoding (e.g., differential Manchester coding, two-phase mark coding, Manchester coding, non-zero return, non-zero return inversion with run length limiting (NRZI) coding, or any other suitable coding) to provide timing information via bus 106.

[0035] The upstream DS transceiver 122 and the downstream DS transceiver 124 can communicate with the bus protocol circuit 126, which in turn can communicate with the phase-locked loop (PLL) 128 and the voltage regulator circuit 130, among other components. When the node transceiver 120 is powered on, the voltage regulator circuit 130 can raise a "good power" signal, which is used by the PLL 128 as a power-on reset.

[0036] As described above, one or more of the subnodes 102-2 of system 100 may receive power transmitted via bus 106 simultaneously with data. (Some of the subnodes 102-2 may be configured to have local power supplies provided exclusively for them, so this is optional.) For power distribution, main node 102-1 may DC bias the bus link between main node 102-1 and subnode 0 by (for example, by connecting one of its downstream terminals to a voltage source provided by a voltage regulator through a low-pass filter and grounding the other downstream terminal.) The DC bias may be a predetermined voltage, such as 5 volts, 8 volts, the voltage of a car battery, or a higher voltage. Each consecutive subnode 102-2 may selectively tap its upstream bus link to recover power (for example, using a voltage regulator circuit 130). This power can be used to power subnode 102-2 itself (and optionally, one or more peripheral devices 108 coupled to subnode 102-2). Subnode 102-2 may also selectively bias the downstream bus links for the next subnode 102-2 in the following order with power recovered from either the upstream bus link or the local power supply. For example, subnode 0 may use a DC bias on the upstream link of bus 106 to recover power for subnode 0 itself and / or one or more associated peripheral devices 108, and / or subnode 0 may recover power from the upstream link of bus 106 in order to bias the downstream links of bus 106.

[0037] Therefore, in some embodiments, each node of system 100 may supply power to the next downstream node via a downstream bus link. Powering of nodes may be performed sequentially. For example, after discovering and configuring subnode 0 via bus 106, main node 102-1 may instruct subnode 0 to supply power to its downstream link on bus 106 in order to power subnode 1, and after subnode 1 is discovered and configured, main node 102-1 may instruct subnode 1 to supply power to its downstream link on bus 106 in order to power subnode 2 (and so on for any additional subnodes 102-2 coupled to bus 106). In some embodiments, one or more subnodes 102-2 may be powered locally instead of, or in addition to, being powered from their upstream bus link. In some such embodiments, a local power source for a given subnode 102-2 may be used to power one or more downstream subnodes.

[0038] In some embodiments, the upstream bus interface circuit 132 may be located between the upstream DS transceiver 122 and the voltage regulator circuit 130, and the downstream bus interface circuit 131 may be located between the downstream DS transceiver 124 and the voltage regulator circuit 130. Since each link of the bus 106 can carry AC (signal) and DC (power) components, the upstream bus interface circuit 132 and the downstream bus interface circuit 131 can separate the AC and DC components, providing the AC components to the upstream DS transceiver 122 and the downstream DS transceiver 124, and the DC components to the voltage regulator circuit 130. The line-side AC coupling of the upstream DS transceiver 122 and the downstream DS transceiver 124 substantially isolates them from the DC components on the line in order to enable high-speed bidirectional communication. As discussed above, the DC component may be tapped for power supply, and the upstream bus interface circuit 132 and the downstream bus interface circuit 131 may include, for example, ferrite, common-mode choke, or inductor to reduce the AC component supplied to the voltage regulator circuit 130. In some embodiments, the upstream bus interface circuit 132 may be included in the upstream DS transceiver 122 and / or the downstream bus interface circuit 131 may be included in the downstream DS transceiver 124, and in other embodiments, the filtering circuit may be outside the upstream DS transceiver 122 and the downstream DS transceiver 124.

[0039] The node transceiver 120 may include transceivers 127 for I2S, TDM, and PDM communication between the node transceiver 120 and the external device 155. While “external device 155” may be referred to in the singular form in this specification, this is merely for illustrative purposes, and multiple external devices may communicate with the node transceiver 120 via the I2S / TDM / PDM transceiver 127. As is well known in the art, the I2S protocol is for carrying pulse code modulation (PCM) information (e.g., between audio chips on a printed circuit board (PCB)). As used herein, “I2S / TDM” may refer to the extension of I2S stereo (2-channel) content to multiple channels using TDM. As is well known in the art, PDM may be used in sigma-delta converters, specifically, the PDM format may represent an oversampled 1-bit sigma-delta ADC signal before decimation. The PDM format is often used as the output format for digital microphones. The I2S / TDM / PDM transceiver 127 can communicate with the bus protocol circuit 126 and pins for communication with an external device 155. Six pins (BCLK, SYNC, DTX[1:0], and DRX[1:0]) are shown in Figure 2, where the BCLK pin may be used for the I2S bit clock, the SYNC pin may be used for the I2S frame synchronization signal, and the DTX[1:0] and DRX[1:0] pins are used for the transmit data channel and the receive data channel, respectively. Two transmit pins (DTX[1:0]) and two receive pins (DRX[1:0]) are shown in Figure 2, but any desired number of receive and / or transmit pins may be used.

[0040] If node transceiver 120 is included in main node 102-1, external device 155 may include host 110, and I2S / TDM / PDM transceiver 127 may provide an I2S slave (for BCLK and SYNC) that can receive data from host 110 and send data to host 110 in synchronization with host 110's I2S interface clock. Specifically, the I2S frame synchronization signal may be received on the SYNC pin as input from host 110, and PLL 128 may use that signal to generate a clock. If node transceiver 120 is included in subnode 102-2, external device 155 may include one or more peripheral devices 108, and I2S / TDM / PDM transceiver 127 may provide an I2S clock master (for BCLK and SYNC) that can control I2S communication with peripheral devices 108. Specifically, the I2S / TDM / PDM transceiver 127 may provide an I2S frame synchronization signal as an output on the SYNC pin. The registers of the node transceiver 120 may determine which I2S / TDM channels and how many I2S / TDM channels are being transmitted as data slots via the bus 106. The TDM mode (TDMMODE) register of the node transceiver 120 may store a value for the number of TDM channels that matches between consecutive SYNC pulses on the TDM transmit pin or TDM receive pin. With knowledge of the channel size, the node transceiver 120 may automatically set the BCLK rate to match the number of bits within the sampling time (e.g., 48 kHz).

[0041] The node transceiver 120 may include a transceiver 129 for I2C communication between the node transceiver 120 and an external device 157. While “external device 157” may be referred to in the singular form in this specification, this is merely for illustrative purposes, and multiple external devices may communicate with the node transceiver 120 via the I2C transceiver 129. As is well known in the art, the I2C protocol provides data transfer using clock (SCL) lines and data (SDA) lines. The I2C transceiver 129 may communicate with the bus protocol circuit 126 and pins for communication with the external device 157. Four pins (ADR1, ADR2, SDA, and SCL) are shown in Figure 2. ADR1 and ADR2 may be used to modify the I2C address used by the node transceiver 120 when the node transceiver 120 functions as an I2C slave (for example, when it is included in the main node 102-1), and SDA and SCL are used for the I2C serial data and serial clock signals, respectively. If the node transceiver 120 is included in the main node 102-1, the external device 157 may include the host 110, and the I2C transceiver 129 may provide an I2C slave that can receive programming instructions from the host 110. Specifically, the I2C serial clock signal may be received on the SCL pin as input from the host 110 for register access. If node transceiver 120 is included in subnode 102-2, external device 157 may include peripheral device 108, and I2C transceiver 129 may provide an I2C master to enable the I2C transceiver to program one or more peripheral devices in accordance with instructions provided by host 110 and transmitted to node transceiver 120 via bus 106. Specifically, I2C transceiver 129 may provide an I2C serial clock signal as an output on the SCL pin.

[0042] The node transceiver 120 may include a transceiver 136 for SPI communication between the node transceiver 120 and the external device 138. While “external device 138” is sometimes referred to in the singular form in this specification, this is merely for illustrative purposes, and multiple external devices may communicate with the node transceiver 120 via the SPI transceiver 136. As is well known in the art, the SPI protocol uses a slave selection (SS) data line, a clock (BCLK) data line, a master-out-slave-in (MOSI) data line, and a master-in-slave-out (MISO) data line to provide data transfer, with the pins corresponding to these four lines shown in Figure 2. The SPI transceiver 136 may communicate with the bus protocol circuit 126 and the pins for communication with the external device 138. If node transceiver 120 is included in main node 102-1, external device 138 may include host 110 or another external device, and SPI transceiver 136 may provide an SPI slave capable of receiving and responding to commands from host 110 or other external devices. If node transceiver 120 is included in subnode 102-2, external device 138 may include peripheral device 108, and SPI transceiver 136 may provide an SPI host to enable SPI transceiver 136 to send commands to one or more peripheral devices 108. SPI transceiver 136 may include a read data first-in, first-out (FIFO) buffer and a write data FIFO buffer. The read data FIFO buffer may be used to collect data read from other nodes 102 and can be read by external device 138 when external device 138 sends an appropriate read command. The write data FIFO buffer may be used to collect write data from external device 138 before the write data is sent to another device.

[0043] The node transceiver 120 may include an interrupt request (IRQ) pin that communicates with the bus protocol circuit 126. If the node transceiver 120 is included in the main node 102-1, the bus protocol circuit 126 may provide event-driven interrupt requests to the host 110 via the IRQ pin. If the node transceiver 120 is included in the subnode 102-2 (for example, if the MSTR pin is low), the IRQ pin may function as a GPIO pin with interrupt request capability. The node transceiver 120 may include other pins in addition to those shown in Figure 2 (for example, as discussed below).

[0044] System 100 can operate in one of several different operating modes. Each node on bus 106 may have a register indicating which operating mode is currently enabled. Examples of the various operating modes that can be implemented are described below. In standby operating mode, bus activity is suppressed to enable comprehensive power saving, and the only traffic required is minimal downstream preamble to maintain synchronization of each node's PLL (e.g., PLL128). Reads and writes across bus 106 are not supported in standby operating mode. In discovery operating mode, main node 102-1 may send predetermined signals along bus 106 to await a suitable response to draw the topology of subnodes 102-2 distributed along bus 106. In normal operating mode, full register access to and from subnodes 102-2 may be available, as well as access to peripheral devices 108 via bus 106 and access from peripheral devices 108. The normal mode can be comprehensively configured by host 110, regardless of the presence or absence of synchronous upstream data and synchronous downstream data.

[0045] Figure 3 shows a portion of a synchronous control frame 180 used for communication within system 100 in various configurations. Specifically, the synchronous control frame 180 may be used for data clock repair and PLL synchronization, as discussed below. As mentioned above, communication via bus 106 can occur in both directions, so the communication may be time-division into a downstream and an upstream portion. In the downstream portion, the synchronous control frame and downstream data may be transmitted from the main node 102-1, while in the upstream portion, the synchronous response frame and upstream data may be transmitted from each of the subnodes 102-2 to the main node 102-1. The synchronous control frame 180 may include a preamble 182 and control data 184. Each subnode 102-2 may be configured to use the preamble 182 of the received synchronous control frame 180 as a time base for input to the PLL 128. To facilitate this, the preamble 182 does not follow the “rules” of valid control data 184, and therefore can be easily distinguished from the control data 184.

[0046] For example, in some embodiments, communication along bus 106 may be encoded using a differential Manchester coding scheme with a clock, zero transition at the beginning. According to such a coding scheme, each bit time begins with a clock transition. If the data value is zero, the coded signal transitions again in the middle of the bit time. If the data value is 1, the coded signal does not transition again. The preamble 182 shown in Figure 5 may violate the coding protocol (by having clock transitions that do not occur, for example, at the beginning of bit times 5, 7, and 8), meaning that the preamble 182 does not have to match any valid (e.g., correctly coded) pattern for the control data 184. In addition, the preamble 182 cannot take a valid pattern for the control data 184 and cannot be duplicated by forcing bus 106 high or low for a period of a single bit time or a period of multiple bit times. The preamble 182 shown in Figure 5 is simply illustrative, and the synchronous control frame 180 may include a different preamble 182 that may violate the encoding used by the control data 184 in any preferred manner.

[0047] The bus protocol circuit 126 may include a differential Manchester decoder circuit that operates on a clock recovered from bus 106 and detects the synchronous control frame 180 and sends a frame synchronous indicator to the PLL 128. In this way, the synchronous control frame 180 can be detected without using the system clock or a faster oversampling clock. As a result, subnode 102-2 can receive the PLL synchronous signal from bus 106 without requiring a crystal clock source in subnode 102-2.

[0048] As described above, communication along bus 106 may occur in periodic superframes. Figure 4 shows superframes 190 in various configurations. As shown in Figure 6, superframes may begin with a synchronous control frame 180. When the synchronous control frame 180 is used as a timing source for the PLL 128, the frequency at which superframes are communicated ("superframe frequency") may be the same as the synchronous signal frequency. In some configurations where voice data is transmitted along bus 106, the superframe frequency may be the same as the voice sampling frequency used in system 100 (e.g., either 48 kHz or 44.1 kHz), but any preferred superframe frequency may be used. Each superframe 190 may be divided into a downstream transmission period 192, an upstream transmission period 194, and a no-transmission period 196 (e.g., when bus 106 is not driven).

[0049] In Figure 4, the superframe 190 is shown in an initial downstream transmission period 192 and a later upstream transmission period 194. The downstream transmission period 192 may include a synchronous control frame 180 and X downstream data slots 198, where X may be zero. Substantially all signals on bus 106 may be line-coded, and synchronous signals may be transmitted downstream from the main node 102-1 to the last subnode 102-2 (e.g., subnode 102-2C) in the form of a synchronous preamble 182 within the synchronous control frame 180, as discussed above. Downstream data, TDM data, and synchronous data may be contained in X downstream data slots 198 after the synchronous control frame 180. The downstream data slots 198 may have equal widths. As discussed above, the PLL 128 may provide a clock that nodes use to time communications over bus 106. In some embodiments where bus 106 is used to transmit audio data, the PLL 128 may operate at a multiple of the audio sampling frequency (e.g., 1024 times the audio sampling frequency, resulting in 1024 bit clocks for each superframe).

[0050] The upstream transmission period 194 may include a synchronous response frame 197 and Y upstream data slots 199, where Y may be zero. In some embodiments, each subnode 102-2 may consume a portion of the downstream data slots 198. The last subnode (e.g., subnode 2 in Figure 1) may respond with a synchronous response frame 197 (after a predetermined response time stored in the last subnode's register). Upstream data, TDM data, and synchronous data may be added by each subnode 102-2 to the upstream data slots 199 immediately after the synchronous response frame 197. The upstream data slots 199 may have equal widths. Subnodes 102-2 that are not the last subnode (for example, subnodes 0 and 1 in Figure 1) may replace their own upstream response with the received synchronous response frame 197 if a read of one of their registers is requested in the synchronous control frame 180 of the superframe 190, or if a remote I2C read is requested in the synchronous control frame 180 of the superframe 190.

[0051] As discussed above, the synchronous control frame 180 may initiate each downstream transmission. In some embodiments, the synchronous control frame 180 may be 64 bits long, but any other suitable length may be used. The synchronous control frame 180 may begin with a preamble 182, as described above. In some embodiments, when the synchronous control frame 180 is retransmitted by subnode 102-2 to a downstream subnode 102-2, the preamble 182 may be generated by the transmitting subnode 102-2 rather than being retransmitted.

[0052] The control data 184 of the synchronous control frame 180 may include fields containing data used to control the transaction via the bus 106. Examples of these fields are discussed below, and several embodiments are shown in Figure 5. Specifically, Figure 5 shows exemplary formats for the synchronous control frame 180 in normal mode, I2C mode, and discovery mode in various embodiments. In some embodiments, different preambles 182 or synchronous control frames 180 may all be used in standby mode so that subnodes 102-2 do not need to receive all of the synchronous control frames 180 until a transition to normal mode is sent.

[0053] In some embodiments, the synchronous control frame 180 may include a count (CNT) field. The CNT field may have any preferred length (e.g., 2 bits) and may be increased from the value used in the previous superframe (modulo the field length). Subnode 102-2 that receives an unexpected CNT value may be programmed to return an interrupt.

[0054] In some embodiments, the synchronization control frame 180 may include a node addressing (NAM) field. The NAM field may have any preferred length (e.g., 2 bits) and may be used to control access to the registers of subnodes 102-2 via bus 106. In normal mode, the registers of subnodes 102-2 may be read and / or written based on the ID of subnode 102-2 and the address of the register. A broadcast transaction is a write that all subnodes 102-2 should undertake. In some embodiments, the NAM field may provide four node addressing modes, including “None” (e.g., data not addressed to any particular subnode 102-2), “Normal” (e.g., a data unicast to a specific subnode 102-2 identified in the address field discussed below), “Broadcast” (e.g., addressed to all subnodes 102-2), and “Discovery.”

[0055] In some embodiments, the synchronous control frame 180 may include an I2C field. The I2C field may have any preferred length (e.g., 1 bit) and may be used to indicate that the period 192 of the downstream transmission includes an I2C transaction. The I2C field may indicate that the host 110 has provided an instruction to the associated subnode 102-2 to remotely access a peripheral device 108 that acts as an I2C slave.

[0056] In some embodiments, the synchronization control frame 180 may include a node field. The node field may have any suitable length (e.g., 4 bits) and may be used to indicate which subnodes are addressed for normal access and I2C access. In discovery mode, this field may be used to program the identifier of the newly discovered subnode 102-2 in the node ID register of subnode 102-2. Each subnode 102-2 of system 100 may be assigned a unique ID when it is discovered by the main node 102-1, as discussed below. In some embodiments, the main node 102-1 may not have a node ID, while in other embodiments, the main node 102-1 may have a node ID. In some embodiments, a subnode 102-2 attached to the main node 102-1 on the bus 106 (e.g., subnode 0 in Figure 1) is subnode 0, and each subsequent subnode 102-2 has a number one higher than the previous subnode. However, this is merely illustrative, and any suitable subnode identification system can be used.

[0057] In some embodiments, the synchronization control frame 180 may include a read / write (RW) field. The RW field may have any preferred length (e.g., 1 bit) and may be used to control whether the normal access is a read (e.g., RW==1) or a write (e.g., RW==0).

[0058] In some embodiments, the synchronization control frame 180 may include an address field. The address field may have any preferred length (e.g., 8 bits) and may be used to address a specific register of subnode 102-2 via the bus 106. For I2C transactions, the address field may be replaced with I2C control values ​​such as start / stop, wait, RW, and data VLD. For discovery transactions, the address field may have a predetermined value (e.g., as shown in Figure 5).

[0059] In some embodiments, the synchronous control frame 180 may include a data field. The data field may have any preferred length (e.g., 8 bits) and may be used for normal writes, I2C writes, and broadcast writes. The RESPCYCS value (multiplied by 4) may be used to determine the number of elapsed cycles that a newly discovered node should allow between the start of the received synchronous control frame 180 and the start of the transmitted synchronous response frame 197. If the NAM field indicates discovery mode, the node address field and data field discussed below may be encoded as a RESPCYCS value that, when multiplied by a preferred optional multiplier (e.g., 4), represents the time in bits from the end of the synchronous control frame 180 to the start of the synchronous response frame 197. This allows a newly discovered subnode 102-2 to determine an appropriate time slot for upstream transmission.

[0060] In some embodiments, the synchronous control frame 180 may include a cyclic redundancy check (CRC) field. The CRC field may have any preferred length (e.g., 16 bits) and may be used to transmit the CRC value of the control data 184 of the synchronous control frame 180, following the preamble 182. In some embodiments, the CRC may be calculated according to a CCITT-CRC error detection scheme.

[0061] In some embodiments, at least a portion of the synchronous control frame 180 between the preamble 182 and the CRC field may be scrambled to reduce the likelihood that the sequence of bits in this interval periodically coincides with the preamble 182 (and thus could be misinterpreted by subnodes 102-2 at the start of a new superframe 190), and to reduce electromagnetic radiation as described above. In some such embodiments, the CNT field of the synchronous control frame 180 may be used by scrambling logic to ensure that the scrambled field is scrambled differently from one superframe to the next. Various embodiments of the system 100 described herein may omit scrambling.

[0062] As discussed above, in addition to, or instead of, techniques such as scrambling and / or error coding, other techniques can be used to ensure that the preamble 182 can be uniquely identified by subnode 102-2, or to reduce the likelihood that the preamble 182 appears elsewhere in the synchronization control frame 180. For example, a longer synchronization sequence may be used so that a particular encoding of the rest of the synchronization control frame 180 reduces the likelihood of it matching. Additionally or alternatively, the rest of the synchronization control frame may be structured in such a way that no synchronization sequence can occur, for example, by setting a fixed value of "0" or "1" to the appropriate bits.

[0063] The main node 102-1 can send read and write requests to subnodes 102-2, including both requests specific to communication on bus 106 and I2C requests. For example, the main node 102-1 can send read and write requests (indicated using the RW field) to one or more designated subnodes 102-2 (using the NAM field and the node field), indicating whether the request is a request to subnode 102-2 specific to bus 106, an I2C request to subnode 102-2, or an I2C request to be passed to an I2C-enabled peripheral device 108 coupled to subnode 102-2 via one or more I2C ports on subnode 102-2.

[0064] For upstream communication, a synchronous response frame 197 may initiate each upstream transmission. In some embodiments, the synchronous response frame 197 may be 64 bits long, but any other suitable length may be used. The synchronous response frame 197 may also include a preamble and a subsequent data portion, as discussed above with respect to the preamble 182 of the synchronous control frame 180. At the end of downstream transmission, the last subnode 102-2 on bus 106 may wait until the RESPCYCS counter expires, and then begin sending a synchronous response frame 197 upstream. If the upstream subnode 102-2 is targeted by a normal read or write transaction, the subnode 102-2 may generate its own synchronous response frame 197, replacing the one received from downstream. If any subnode 102-2 does not find a synchronous response frame 197 from a downstream subnode 102-2 at the expected time, subnode 102-2 generates its own synchronous response frame 197 and begins sending it upstream.

[0065] The data portion of the synchronous response frame 197 may include fields containing data used to send response information back to the main node 102-1. Examples of these fields are discussed below, and several embodiments are shown in Figure 6. Specifically, Figure 6 shows exemplary formats for the synchronous response frame 197 in various embodiments in normal mode, I2C mode, and discovery mode.

[0066] In some embodiments, the synchronous response frame 197 may include a count (CNT) field. The CNT field may have any preferred length (e.g., 2 bits) and may be used to transmit the value of the CNT field of the previously received synchronous control frame 180.

[0067] In some embodiments, the synchronous response frame 197 may include an acknowledgment (ACK) field. The ACK field may have any preferred length (e.g., 2 bits) and may be inserted by subnode 102-2 when it generates the synchronous response frame 197 to acknowledge the command received in the previous synchronous control frame 180. Exemplary indicators that may be communicated in the ACK field include wait, acknowledgment, negation (NACK), and retry. In some embodiments, the ACK field may be sized to indicate that a broadcast message has been received and processed, so that subnode 102-2 sends an acknowledgment (e.g., by sending a broadcast acknowledgment to main node 102-1). In some such embodiments, subnode 102-2 may also indicate whether it has data to send (which can be used for request-based upstream transmissions, such as non-TDM input from a keypad or touchscreen, or for preferred upstream transmissions, such as when subnode 102-2 wants to report an error or emergency condition).

[0068] In some embodiments, the synchronous response frame 197 may include an I2C field. The I2C field may have any preferred length (e.g., 1 bit) and may be used to transmit the value of the I2C field of the previously received synchronous control frame 180.

[0069] In some embodiments, the synchronous response frame 197 may include a node field. The node field may have any preferred length (e.g., 4 bits) and may be used to transmit the ID of the subnode 102-2 that generates the synchronous response frame 197.

[0070] In some embodiments, the synchronous response frame 197 may include a data field. The data field may have any preferred length (e.g., 8 bits), and its value may depend on the type of transaction and the ACK response of the subnode 102-2 that generates the synchronous response frame 197. In the case of a discovery transaction, the data field may include the value of the RESPCYCS field of the previously received synchronous control frame 180. When the ACK field indicates a NACK, or when the synchronous response frame 197 is responding to a broadcast transaction, the data field may include a broadcast acknowledgment (BA) indicator (which may indicate whether the last subnode 102-2 received the broadcast write without error), a discovery error (DER) indicator (which indicates whether the newly discovered subnode 102-2 in the discovery transaction matches an existing subnode 102-2), and a CRC error (CER) indicator (which indicates whether the NACK was caused by a CRC error).

[0071] In some embodiments, the synchronous response frame 197 may include a CRC field. The CRC field may have any preferred length (e.g., 16 bits) and may be used to transmit the CRC value of the portion of the synchronous response frame 197 between the preamble and the CRC field.

[0072] In some embodiments, the synchronous response frame 197 may include an interrupt request (IRQ) field. The IRQ field may have any preferred length (e.g., 1 bit) and may be used to indicate that an interrupt was signaled from subnode 102-2.

[0073] In some embodiments, the synchronous response frame 197 may include an IRQ node (IRQNODE) ​​field. The IRQNODE field may have any preferred length (e.g., 4 bits) and may be used to transmit the ID of the subnode 102-2 that signaled the interrupt indicated by the IRQ field. In some embodiments, the subnode 102-2 for generating the IRQ field inserts its own ID into the IRQNODE field.

[0074] In some embodiments, the synchronous response frame 197 may include a second CRC (CRC-4) field. The CRC-4 field may have any preferred length (e.g., 4 bits) and may be used to transmit the CRC values ​​of the IRQ field and the IRQNODE field.

[0075] In some embodiments, the synchronous response frame 197 may include the IRQ field, the IRQNODE field, and the CRC-4 field as the last bits (e.g., the last 10 bits) of the synchronous response frame 197. As discussed above, these interrupt-related fields may have their own CRC protection in the form of CRC-4 (and therefore not protected by the preceding CRC field). Any subnode 102-2 that needs to signal an interrupt to the main node 102-1 inserts its interrupt information into these fields. In some embodiments, a subnode 102-2 with an interrupt wait may have a higher priority than any further downstream subnode 102-2 that also has an interrupt wait. The last subnode 102-2 along the bus 106 (e.g., subnode 2 in Figure 1) may always populate these interrupt fields. If the last subnode 102-2 has no interrupt waiting, it may set the IRQ bit to 0, set the IRQNODE field to its node ID, and provide the correct CRC-4 value. For convenience, the synchronous response frame 197 that propagates the interrupt may be referred to herein as the “interrupt frame”.

[0076] In some embodiments, at least a portion of the synchronous response frame 197 between the preamble 182 and the CRC field may be scrambled to reduce radiation. In some such embodiments, the CNT field of the synchronous response frame 197 may be used by scrambling logic to ensure that the scrambled field is scrambled differently from one superframe to the next. Various embodiments of the system 100 described herein may omit scrambling.

[0077] As discussed above, in addition to, or instead of, techniques such as scrambling and / or error coding, other techniques can be used to ensure that the preamble 182 can be uniquely identified by subnode 102-2, or to reduce the likelihood that the preamble 182 appears elsewhere in the synchronous response frame 197. For example, a longer synchronization sequence may be used so that a particular encoding of the rest of the synchronous response frame 197 reduces the likelihood of it matching. Additionally or alternatively, the rest of the synchronous response frame may be structured in such a way that no synchronization sequence can occur, for example, by setting a fixed value of "0" or "1" to the appropriate bits.

[0078] Figure 7 is a block diagram of the bus protocol circuit 126 of Figure 2 in various configurations. The bus protocol circuit 126 may include a control circuit 154 for controlling the operation of the node transceiver 120 in accordance with the bus 106 protocol described herein. Specifically, the control circuit 154 may control the generation of a synchronous frame for transmission (e.g., a synchronous control frame or synchronous response frame, as discussed above), the processing of a received synchronous frame, and the execution of a control operation specified in the received synchronous control frame. The control circuit 154 may include programmable registers, as discussed below. The control circuit 154 may create and receive synchronous control frames, respond appropriately to received messages (e.g., associated with a synchronous control frame when the bus protocol circuit 126 is included in subnode 102-2, or from an I2C device when the bus protocol circuit 126 is included in mainnode 102-1), and adjust framing for different operating modes (e.g., normal, discovery, standby, etc.).

[0079] When node transceiver 120 is preparing data for transmission along bus 106, preamble circuit 156 may be configured to generate a preamble for a synchronous frame for transmission and to receive a preamble from a received synchronous frame. In some embodiments, the preamble for downstream synchronous control frames may be sent out by main node 102-1 every 1024 bits. As discussed above, one or more subnodes 102-2 may synchronize with the preamble for downstream synchronous control frames and generate a local, phase-aligned main clock from the preamble.

[0080] The CRC insertion circuit 158 ​​may be configured to generate one or more CRCs for the transmission synchronization frame. The frame / compression circuit 160 may take input data from the I2S / TDM / PDM transceiver 127 (e.g., the frame buffer associated with transceiver 127), the I2C transceiver 129, and / or the SPI transceiver 136, and optionally compress the data, and optionally generate parity check bits or error correction codes (ECCs) for the data. The multiplexer (MUX) 162 may multiplex the preamble from the preamble circuit 156, the synchronization frame, and the data into a transmission stream. In some embodiments, the transmission stream may be scrambled before transmission by the scrambling circuit 164.

[0081] For example, in some embodiments, the frame / compression circuit 160 may apply a floating-point compression scheme. In such embodiments, the control circuit 154 may transmit 3 bits indicating the number of repeating sign bits, followed by a sign bit and N-4 bits of data, where N is the size of the data transmitted over bus 106. The use of data compression may be configured by the main node 102-1 if desired.

[0082] In some embodiments, the received stream entering the node transceiver 120 may be descrambled by the descramble circuit 166. The demultiplexer (DEMUX) 168 may demultiplex the preamble, sync frame, and data from the received stream. The receiving CRC check circuit 159 may check the received sync frame for a correct CRC. If the CRC check circuit 159 identifies a CRC fault in the incoming sync control frame 180, the control circuit 154 may be notified of the fault and will not execute any control commands in the control data 184 of the sync control frame 180. If the CRC check circuit 159 identifies a CRC fault in the incoming sync response frame 197, the control circuit 154 may be notified of the fault and may generate an interrupt in the interrupt frame for transmission to the host 110. The frame de-frame / restore circuit 170 can accept received data, optionally check its parity, optionally perform error detection and correction (e.g., single error correction, double error detection (SECDED)), optionally restore the data, and write the received data to the I2S / TDM / PDM transceiver 127 (e.g., the frame buffer associated with transceiver 127), the I2C transceiver 129, and / or the SPI transceiver 136.

[0083] As discussed above, upstream and downstream data can be transmitted along bus 106 in TDM data slots within the superframe 190. The control circuit 154 may include registers dedicated to managing these data slots on bus 106, some examples of which are discussed below. When the control circuit 154 is included in the main node 102-1, the values ​​of these registers can be programmed into the control circuit 154 by the host 110. When the control circuit 154 is included in the subnode 102-2, the values ​​of these registers can be programmed into the control circuit 154 by the main node 102-1.

[0084] In some embodiments, the control circuit 154 may include a downstream slots (DNSLOTS) register. When the node transceiver 120 is included in the main node 102-1, this register may hold a value for the total number of downstream data slots. This register may also define the number of data slots used for combined I2S / TDM / PDM reception by the I2S / TDM / PDM transceiver 127 of the main node 102-1. In subnode 102-2, as will be discussed in more detail below with respect to LDNSLOTS, this register may define the number of data slots passed downstream to the next subnode 102-2 before or after the addition of locally generated downstream slots.

[0085] In some embodiments, the control circuit 154 may include a local downstream slots (LDNSLOTS) register. This register may be unused on the main node 102-1. On the subnode 102-2, this register may define the number of data slots that the subnode 102-2 will use and will not retransmit. Alternatively, this register may define the number of slots that the subnode 102-2 may contribute to the downstream links of the bus 106.

[0086] In some embodiments, the control circuit 154 may include an Upstream Slots (UPSLOTS) register. In the main node 102-1, this register may hold the value of the total number of upstream data slots. This register may also define the number of slots used for I2S / TDM transmission by the I2S / TDM / PDM transceiver 127 of the main node 102-1. In the subnode 102-2, this register may define the number of data slots that are passed upstream before the subnode 102-2 begins to add its own data.

[0087] In some embodiments, the control circuit 154 may include a local upstream slots (LUPSLOTS) register. This register may be unused in the main node 102-1. In the subnode 102-2, this register may define the number of data slots that the subnode 102-2 adds to data before it is sent upstream after receiving data from downstream. This register may also define the number of data slots used for combined I2S / TDM / PDM reception by the I2S / TDM / PDM transceiver 127 of the subnode 102-2.

[0088] In some embodiments, the control circuit 154 may include a broadcast downstream slots (BCDNSLOTS) register. This register may be unused on the main node 102-1. On subnode 102-2, this register may define the number of broadcast data slots. In some embodiments, broadcast data slots may always occur at the beginning of a data field. The data in a broadcast data slot may be used by multiple subnodes 102-2 and may be passed downstream by all subnodes 102-2, whether they are used or not.

[0089] In some embodiments, the control circuit 154 may include a slot format (SLOTFMT) register. This register may define the format of data for upstream or downstream transmission. The data size of the I2S / TDM / PDM transceiver 127 may also be determined by this register. In some embodiments, valid data sizes include 8 bits, 12 bits, 16 bits, 20 bits, 24 bits, 28 bits, and 32 bits. This register may also include a bit to enable floating-point compression for downstream or upstream traffic. When floating-point compression is enabled, the I2S / TDM data size may be 4 bits larger than the data size via bus 106. All nodes in system 100 may have the same value for SLOTFMT when a data slot is enabled, and these nodes may be programmed by broadcast writes so that all nodes are updated with the same value.

[0090] Figures 8-11 illustrate examples of information exchange along bus 106 according to various embodiments of the bus protocol described herein. Specifically, Figures 8-11 illustrate embodiments in which each subnode 102-2 is coupled to one or more speakers and / or one or more microphones as peripheral devices 108. This is merely illustrative, as any desired arrangement of the peripheral devices 108 can be coupled to any particular subnode 102-2 according to the techniques described herein.

[0091] First, Figure 8 illustrates the consideration of signal transmission and timing for bidirectional communication on bus 106 in various configurations. The subnodes 102-2 shown in Figure 8 have varying numbers of sensor / actuator elements, and therefore, different amounts of data can be sent to or received from various subnodes 102-2. Specifically, subnode 1 has 2 elements, subnode 4 has 4 elements, and subnode 5 has 3 elements. Therefore, the data transmitted by the main node 102-1 includes 2 time slots for subnode 1, 4 time slots for subnode 4, and 3 time slots for subnode 5. Similarly, subnode 0 has 3 elements, subnode 2 has 3 elements, subnode 3 has 3 elements, subnode 6 has 1 element, and subnode 7 has 4 elements. Therefore, the data transmitted upstream by these subnodes 102-2 includes the corresponding number of time slots. Note that a one-to-one correlation between elements and time slots is not required. For example, a microphone array having three microphones included in peripheral device 108 may include a DSP that combines signals from the three microphones (and possibly information received from main node 102-1 or other subnodes 102-2) to produce a single data sample that may correspond to a single time slot or multiple time slots, depending on the type of processing.

[0092] In Figure 8, the main node 102-1 transmits the SCF, followed by data for a speaker coupled to a specific subnode 102-2 (SD). Each successive subnode 102-2 forwards the SCF and also forwards at least one of the data destined for a downstream subnode 102-2. A specific subnode 102-2 may forward all the data or may omit any data destined for that subnode 102-2. When the last subnode 102-2 receives the SCF, it transmits an SRF, and optionally follows it with any data that subnode 102-2 is permitted to transmit. Each successive subnode 102-2 forwards the SRF along with any data from downstream subnodes 102-2 and optionally inserts data from one or more microphones coupled to a specific subnode 102-2 (MD). In the example in Figure 8, the main node 102-1 sends data to subnodes 1, 4, and 5 (shown as active speakers in Figure 8) and receives data from subnodes 7, 6, 3, 2, and 0 (shown as a microphone array in Figure 8).

[0093] Figure 9 schematically illustrates the dynamic deletion of data from downstream transmissions and the insertion of data into upstream transmissions from the perspective of the downstream DS transceiver 124, under various conditions. In Figure 9, as in Figure 8, the main node 102-1 transmits the SCF and then the data for subnodes 1, 4, and 5 (SD) in reverse order (for example, the data for subnode 5 is followed by the data for subnode 4, and then the data for subnode 1) (see the row labeled Main). When subnode 1 receives this transmission, subnode 1 deletes its own data and forwards only the SCF and the subsequent data for subnodes 5 and 4 to subnode 2. Subnodes 2 and 3 forward the data without modification so that the data forwarded by subnode 1 is received by subnode 4 (see the row labeled Sub 3) (see the row labeled Sub 2). Subnode 4 deletes its own data and transfers only the SCF and the subsequent data for subnode 5 to subnode 5. Similarly, subnode 5 deletes its own data and transfers only the SCF to subnode 6. Subnode 6 transfers the SCF to subnode 7 (see the line labeled Subnode 6).

[0094] At this point, subnode 7 sends the SRF, followed by its own data, to subnode 6 (see the line labeled "Sub 6"). Subnode 6 forwards the SRF, along with the data from subnode 7 and its own data, to subnode 5, which then forwards the SRF, along with the data from subnodes 7 and 6, to subnode 4. Subnode 4 has no additional data to add, and therefore simply forwards the data to subnode 3 (see the line labeled "Sub 3"). Subnode 3 forwards the data, along with its own data, to subnode 2 (see the line labeled "Sub 2"). Subnode 2 then forwards the data, along with its own data, to subnode 1. Subnode 1 has no additional data to add, and therefore forwards the data to subnode 0, which forwards the data, along with its own data. As a result, main node 102-1 receives the SRF, followed by data from subnodes 7, 6, 3, 2, and 0 (see the line labeled "Main").

[0095] Figure 10, similar to Figure 9, illustrates another example of dynamic deletion of data from downstream transmissions and insertion of data into upstream transmissions from the perspective of the downstream DS transceiver 124, but in Figure 10, subnodes 102-2 are coupled to both sensors and actuators as peripheral devices 108 so that the main node 102-1 sends data to all of the downstream subnodes 102-2 and receives data back from all of the subnodes 102-2. Also in Figure 10, the data is ordered based on the node address to which it is sent or the node address to which it is sent. Data slots labeled "Y" may be used for data integrity checks or data corrections.

[0096] Figure 11, similar to Figure 9, illustrates another example of dynamic deletion of data from downstream transmissions and insertion of data into upstream transmissions from the perspective of the downstream DS transceiver 124, except that in Figure 11, the data is transmitted sequentially downstream and upstream, rather than in reverse order. Buffering at each subnode 102-2 allows for the selective addition, deletion, and / or transfer of data.

[0097] As discussed above, each subnode 102-2 can delete data from a downstream or upstream transmission, and / or add data to a downstream or upstream transmission. Therefore, for example, the main node 102-1 can send a separate data sample to each of several subnodes 102-2, and each such subnode 102-2 can delete its own data sample and forward only the data destined for the downstream subnode 102-2. On the other hand, a subnode 102-2 can receive data from a downstream subnode 102-2 and forward that data along with additional data. One advantage of transmitting only as much information as necessary is to reduce the amount of power consumed by the system 100 as a whole.

[0098] System 100 may also support broadcast transmissions (and multicast transmissions) from main node 102-1 to subnode 102-2, specifically through a configuration using the downstream slots of subnode 102-2. Each subnode 102-2 may process a broadcast transmission and pass it on to the next subnode 102-2, but a particular subnode 102-2 may "consume" a broadcast message (i.e., not pass the broadcast transmission on to the next subnode 102-2).

[0099] System 100 may also support upstream transmissions (for example, from a particular subnode 102-2 to one or more other subnodes 102-2). Such upstream transmissions may include unicast upstream transmissions, multicast upstream transmissions, and / or broadcast upstream transmissions. As discussed above with respect to downstream transmissions, upstream addressing allows subnode 102-2 to determine, based on its configuration of upstream slot usage, whether to remove data from the upstream transmission and / or to pass the upstream transmission to the next upstream subnode 102-2. Thus, for example, data may be passed by a particular subnode 102-2 to one or more other subnodes 102-2 in addition to, or instead of, passing the data to the main node 102-1. Such sub-sub relationships may be established, for example, via the main node 102-1.

[0100] Therefore, in various embodiments, subnodes 102-2 can operate as active / intelligent relay nodes with the ability to selectively transfer, delete, and add information. Since each subnode 102-2 knows the relevant time slots for receiving / transmitting data internally, subnodes 102-2 can generally perform such functions without necessarily decoding / examining all of the data, and thus can delete data from a time slot or add data to a time slot. Even though subnodes 102-2 do not need to decode / examine all of the data, they can typically reclock the data they transmit / transmit. This can increase the robustness of system 100.

[0101] In some embodiments, bus 106 may be configured for one-way communication in a ring topology. For example, Figure 12 illustrates an arrangement 1200 of a main node 102-1 and four subnodes 102-2 in a ring topology and illustrates considerations of signal transmission and timing for one-way communication in arrangement 1200 in various embodiments. In such embodiments, the node transceiver 120 within a node may include a receive-only transceiver (main input) and a transmit-only transceiver (main output), rather than two bidirectional transceivers for upstream and downstream communication. In the link layer synchronization scheme shown in Figure 12, the main node 102-1 transmits the SCF 180 and, optionally thereafter, "downstream" data 1202 for three speakers coupled to various subnodes 102-2 (as discussed above with reference to Figures 8-11, the data for different speakers may be arranged in any preferred order), and each successive subnode 102-2 transmits the synchronization control frame 180 along with any "upstream" data from the previous subnode 102-2 and its own "upstream" data to provide "upstream" data 1204 (for example, as discussed above with reference to Figures 8-11, the data from eight different microphones may be arranged in any preferred order).

[0102] As described herein, data can be communicated between elements of system 100 in any of several ways. In some embodiments, data can be sent upstream by subnode 102-2 (e.g., using data slot 199) or downstream by subnode 102-2 or main node 102-1 (e.g., using data slot 198) as part of a set of synchronous data slots. The amount of such data can be adjusted by changing the number of bits in the data slot or by including additional data slots. In system 100, data can also be communicated by including it in a synchronous control frame 180 or a synchronous response frame 197. The data communicated in this manner may include I2C control data from host 110 (with responses from peripheral device 108 associated with subnode 102-2), access to registers in subnode 102-2 (e.g., for slot and interface discovery and configuration), write access from host 110 / main node 102-1 to subnode 102-2, and read access from subnode 102-2 to host 110 / main node 102-1, and event signal transmission via interrupts from peripheral device 108 to host 110. In some embodiments, GPIO pins may be used to transmit information from subnode 102-2 to main node 102-1 (e.g., by having main node 102-1 poll the GPIO pins via I2C, or by having the node transceiver 120 of subnode 102-2 generate an interrupt on the interrupt request pin). For example, in some such embodiments, host 110 may send information to main node 102-1 via I2C, and main node 102-1 may then send that information to subnode 102-2 via GPIO pins. Any of the types of data discussed herein as being transmitted via bus 106 may be transmitted using any one or more of these communication paths. Other types of data and data communication techniques within system 100 may be disclosed herein.

[0103] Aspects of this disclosure can be implemented in a system using any suitable hardware and / or software to be configured as desired. Figure 13 schematically illustrates a device 1300 that can function as a host or node (e.g., host 110, main node 102-1, or subnode 102-2) in a system 100 in various embodiments. Several components are shown in Figure 13 as being included in device 1300, but any one or more of these components can be omitted or duplicated to suit the application.

[0104] Additionally, in various embodiments, device 1300 may not include one or more of the components shown in Figure 13, but may include interface circuits for coupling with one or more of those components. For example, device 1300 may not include the display device 1306, but may include a display device interface circuit (e.g., a connector and driver circuit) to which the display device 1306 can be coupled. In another set of examples, device 1300 may not include the audio input device 1324 or the audio output device 1308, but may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device 1324 or the audio output device 1308 can be coupled.

[0105] In any of the embodiments disclosed herein, device 1300 may include a node transceiver 120 for managing communication along bus 106 when device 1300 is coupled to bus 106. Device 1300 may include a processing device 1302 (e.g., one or more processing devices) which may be included in or separate from the node transceiver 120. As used herein, the term “processing device” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts that electronic data into other electronic data which can be stored in registers and / or memory. The processing device 1302 may include one or more DSPs, ASICs, central processing units (CPUs), graphics processing units (GPUs), cryptographic processors, or any other suitable processing devices. Device 1300 may include memory 1304, which itself may include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid memory, and / or a hard disk drive.

[0106] In some embodiments, memory 1304 may be used to store working and permanent copies of programming instructions that cause device 1300 to execute any preferred technique among those disclosed herein. In some embodiments, machine-accessible media, methods, systems, and devices (including non-temporary computer-readable storage media) for executing the above techniques are examples of the embodiments disclosed herein for communication over a two-wire bus. For example, a computer-readable medium (e.g., memory 1304) may have stored instructions that, when executed by one or more processing devices included in processing device 1302, cause device 1300 to execute any of the techniques disclosed herein.

[0107] In some embodiments, device 1300 may include another communication chip 1312 (e.g., one or more other communication chips). For example, communication chip 1312 may be configured to manage wireless communication for data transfer to and from device 1300. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data using modulated electromagnetic radiation through a non-solid medium. The term does not mean that the associated device does not include any wiring, although in some embodiments it may not.

[0108] The communication chip 1312 may implement any of several wireless standards or protocols, including, but not limited to, the Long-Term Evolution (LTE) project, with any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP® 2"), etc.), including Wi-Fi (IEEE 802.11 family), the IEEE 802.16 standard (e.g., IEEE 802.16-2005 amendment), the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP® 2"), etc. IEEE 802.16-compatible broadband radio access (BWA) networks are commonly referred to as WiMAX networks, which are certified by Worldwide Interoperability for Microwave, a certification mark for products that pass conformance and interoperability testing of the IEEE 802.16 standard. It is an acronym for Access. One or more communication chips 1312 may operate according to Global System for Mobile Communications (GSM), General Purpose Packet Radio Service (GPRS), Universal Mobile Communications System (UMTS), High-Speed ​​Packet Access (HSPA), Advanced HSPA (E-HSPA), or LTE network. One or more communication chips 1312 may support Enhanced Data for GSM Innovation (EDGE), GSM The device may operate in accordance with the Edge Radio Access Network (GERAN), Universal Terrestrial Radio Connectivity Network (UTRAN), or Advanced UTRAN (E-UTRAN). One or more communication chips 1312 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Radio Telecommunications (DECT), Advanced Data Optimization (EV-DO), and their derivatives, as well as any other radio protocols designated as 3G, 4G, 5G, and later. In other embodiments, the communication chips 1312 may operate in accordance with other radio protocols. The device 1300 may include an antenna 1322 for facilitating wireless communication and / or receiving other wireless communication (such as AM or FM radio transmission).

[0109] In some embodiments, the communication chip 1312 may manage wired communications using protocols other than those described herein for bus 106. Wired communications may include telecommunications protocols, optical communications protocols, or any other suitable communications protocols. Examples of wired communications protocols that can be enabled by the communication chip 1312 include Ethernet, Controller Area Network (CAN), I2C, Media-Oriented Systems Transport (MOST), or any other suitable communications protocols.

[0110] As described above, the communication chip 1312 may include multiple communication chips. For example, the first communication chip 1312 may be dedicated to short-range wireless communication such as Wi-Fi or Bluetooth®, and the second communication chip 1312 may be dedicated to Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or other long-range wireless communication. In some embodiments, the first communication chip 1312 may be dedicated to wireless communication, and the second communication chip 1312 may be dedicated to wired communication.

[0111] Device 1300 may include a battery / power circuit 1314. The battery / power circuit 1314 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuits for coupling components of device 1300 to an energy source separate from device 1300 (e.g., an AC line power supply, a voltage provided by a car battery, etc.). For example, the battery / power circuit 1314 may include the upstream bus interface circuit 132 and the downstream bus interface circuit 131 discussed above with reference to Figure 2, and may be charged by a bias on bus 106.

[0112] Device 1300 may include a display device 1306 (or a corresponding interface circuit as discussed above). The display device 1306 may include any visual indicator, such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0113] Device 1300 may include an audio output device 1308 (or a corresponding interface circuit as discussed above). The audio output device 1308 may include any device that generates an audible indicator, such as a speaker, headphones, or earphones.

[0114] Device 1300 may include an audio input device 1324 (or a corresponding interface circuit as discussed above). The audio input device 1324 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a MIDI output).

[0115] Device 1300 may include a GPS device 1318 (or a corresponding interface circuit as discussed above). The GPS device 1318 may communicate with satellite-based systems, as is well known in the art, and may receive the location of device 1300.

[0116] Device 1300 may include another output device 1310 (or a corresponding interface circuit as discussed above). Examples of the other output device 1310 include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device. Additionally, any preferred peripheral device 108 discussed herein may be included in the other output device 1310.

[0117] Device 1300 may include another input device 1320 (or a corresponding interface circuit as discussed above). Examples of the other input device 1320 include an accelerometer, a gyroscope, an image acquisition device, a keyboard, a cursor control device (such as a mouse, stylus, or touchpad), a barcode reader, a quick response (QR) code reader, or a radio frequency identification (RFID) reader. Additionally, any preferred sensor or peripheral device 108 discussed herein may be included in the other input device 1320.

[0118] Any suitable display device, input device, output device, communication device, or memory device described above with respect to device 1300 may function as a peripheral device 108 of system 100. Alternatively or additionally, any suitable display device, input device, output device, communication device, or memory device described above with respect to device 1300 may be included in a host (e.g., host 110) or node (e.g., main node 102-1 or subnode 102-2).

[0119] The elements of system 100 are selected and configured to provide voice control and / or light control via bus 106. In some embodiments, system 100 may be configured to function as a light control system in a vehicle or other environment, comprising a lighting device (e.g., stripline light-emitting diodes (LEDs) or other LED arrangement) that functions as a peripheral device 108 communicating with a node 102 along bus 106, and data may be communicated via bus 106 to control the color, intensity, duty cycle, and / or other parameters of the lighting device. In some embodiments, system 100 may be configured to function as a voice control system in a vehicle or other environment, comprising a microphone or other device including an accelerometer that can function as a peripheral device 108 communicating with a node 102 along bus 106, and data from the accelerometer may be communicated via bus 106 to control other peripheral devices 108 along bus 106. For example, large spikes in acceleration data or other predetermined acceleration data patterns may be used to trigger the generation of sound effects such as cowbells or drum hits by a processing device coupled to node 102, and the sound effects may be output by a speaker coupled to the processing device and / or a speaker coupled to another node 102 along bus 106. Some embodiments of system 100 may combine any of the lighting control techniques and / or sound control techniques disclosed herein.

[0120] The various embodiments discussed above describe the system 100 in a vehicle setting, but this is merely illustrative, and the system 100 can be implemented in any desired setting. For example, in some embodiments, a “portable” implementation of the system 100 may include a portable housing containing the desired components of the system 100, and such an implementation may be particularly suitable for portable applications such as portable karaoke or entertainment systems.

[0121] As described above, asynchronous data devices can be networked via a network bus (for example, in a system 100 where one or more of the peripheral devices 108 include base station devices such as musical instruments, microphones, or speakers). The network bus may be a two-wire bus. The network bus may be a Serial Peripheral Interface (SPI). In some examples, the method provides a virtual peer-to-peer communication mechanism on a shared bus with a single owner. Additionally, the method may provide a mechanism for instantaneous bandwidth allocation. Furthermore, the method may provide a mechanism for latency management and flow control. The method may also include a caching mechanism for rapid startup. In some examples, the system and method include the MIDI protocol, which operates via the SPI interface.

[0122] Figures 14-18 illustrate exemplary systems and techniques for networking asynchronous devices.

[0123] Figure 14 is a flowchart 1400 illustrating a method for enabling nodes on a network bus to independently initiate transactions. In step 1402, one of the network bus nodes is assigned the label "Router" and / or "Owner," while the remaining network bus nodes are assigned the label "Base Station." In step 1404, round-robin SPI full-duplex transactions are employed between the router node and each base station node. In step 1406, the routing table for forwarding data to each base station node is maintained at the router node. In some examples, empty packets are provided by the protocol to signal data non-availability. In various examples, the round-robin transactions between the router node and each base station node are considered peer-to-peer bidirectional communication.

[0124] According to various examples, the efficiency of round-robin transactions is enhanced by two mechanisms. Firstly, in the case of general-purpose input / output (GPIO) over a certain distance, each base station node signals to the router node about nearby data. Secondly, each base station node provides in-band signaling to the router node regarding the level of data packets. For example, each base station node can provide a "transmit full" signal indicating the level of the transmitted data packet and / or a "receive full" signal indicating the level of the received data packet. When the router node receives the "transmit full" and / or "receive full" signals from the base station node, the router node analyzes the needs of the base station node and modifies the round-robin frequency of the base station node as needed.

[0125] According to various embodiments, the method in flow chart 1400 includes a cache. Specifically, a router node may store information about base station nodes and tag the information with a unique hardware ID that identifies each base station node. In some examples, during an "on" power cycle, a router base station can query for a base station node-specific hardware ID and use the information stored for each base station node.

[0126] Figures 15-19 are block diagrams of systems for asynchronous device networking over a two-wire bus in various configurations.

[0127] Figure 15 shows various topologies of network bus asynchronous devices. In various examples, the MIDI endpoint 1510 may be an electric guitar, keyboard, amplifier, microphone, or other asynchronous device, connected to the network bus submode S1520, then through the network bus main node M1530 to the network bus MDI card / gateway 1540, and then to the PC-MIDI server 1550.

[0128] Figure 16 shows network bus asynchronous device interfaces, including SPI and data tunnels, in various configurations. M is the network bus main node, and each S block is a network bus subnode. SPI full-duplex tunnel transactions include bidirectional transactions with minimal latency. In some examples, round-robin transactions exist between gateway 1540 and subnode 1520. In one example, the MISO data for the gateway is a transaction behind the current target node.

[0129] Figure 17 illustrates an exemplary asynchronous device router according to various aspects of this disclosure. In some examples, Figure 17 shows a routing table that maps asynchronous device groups and channels to each network bus node. A scheduler periodically loops through various asynchronous device nodes. If there are no asynchronous device messages, an empty packet is sent. The empty message triggers the reception of a packet from the previous remote target node (1730). The routing table (1770) takes up a matrix of information about the source node, group & channel to the destination node, group & channel. The routing table can be generated based on a graphical user interface. In some cases, the user interface may extend across devices. The router maintains a set of reserved auxiliary messages to communicate and synchronize routing information over the network. A parsing tool (1760) scans all incoming packets from the data tunnel (1750, 1740) and, for each packet, takes up the source node number, group, and channel. In some cases, in addition to routing, the router performs MIDI applications (1790) to consumer-specific packets. Figure 18 shows exemplary asynchronous device base stations according to various aspects of the present disclosure. Each device can host multiple channels or groups. An SPI driver (1850) on the base station receives packets from the network. A parsing tool ignores irrelevant messages / packets and provides raw MIDI messages for application stripping of network-specific headers. Similarly, application messages are provided to a packetizer before being input to the driver. The driver must be full-duplex and, being a responder to the network, appends empty messages (1730) when there are no valid messages in the queue.

[0130] Figure 19 shows another example of asynchronous device gateway framing. In some examples, the parsing tool performs deframing and the packetizer performs framing. Framing can reduce the number of slots. CPU load may increase slightly. Framing may affect audio bandwidth utilization. The gateway uses a TDM interface (1970, 1950) to communicate with remote devices. It deframes MIDI packets from TDM Rx audio frames (1980) and forms a pool of packets for various remote devices (1990, 1910). The scheduler (1920) selects packets from the pool and adds packet framing to send them out via the TDM interface (1940, 1950). The framing module (1940) inserts empty / unoperated packets (1930) to meet the synchronization needs of the TDM interface. Similarly, device endpoints also interface with TDM Tx and TDM Rx and exchange packets.

[0131] In some examples, flow control and bandwidth allocation are addressed as follows: The router identifies the network bus packet rate for each node and estimates the transmission time for one network bus packet. Tunnel bandwidth and SPI rate may be considered when determining the transmission time. A scheduler is configured to tick the maximum rate. The router performs round-robin SPI full-duplex transactions between sets of nodes on each tick. The allocation rate is set as a portion of the maximum rate. The allocation rate is sent to all nodes. In some examples, the tick guarantees a minimum bandwidth for each node. The router allocates time between ticks for flow control to meet instantaneous bandwidth requests. In some examples, there is guard bandwidth for flow control. A system tick is a unit of time on which OS timers and delays are based. A system tick is a scheduling event, i.e., for example, when a timer expires or a task delay is completed, which can trigger the scheduler and cause a context switch.

[0132] In some examples, all nodes establish links with all other nodes. In some examples, there are no separate "gateways". In some examples, all nodes add two slots (except for the main and last subnodes). In some examples, all MIDI messages are broadcast. In some examples, there is bandwidth for N nodes.

[0133] (N-1)*(DwnSlot_Width+UpSlot_Width)*(SuperframeRate)

[0134] 'N-1' Tx CH&1 Rx Channel @ All Nodes

[0135] In some examples, there are additional complexity endpoints, which are multiple TDM channels.

[0136] In contrast to synchronous slots, data tunnels, along with other systems, involve shared bandwidth and shared time between nodes. Asynchronous data packets are routed through a routing gateway. Adding new nodes makes tunnel configuration and expansion easier. Data tunnels use the more common SPI interface for asynchronous messages. For data tunnels, error detection can be part of the network bus asynchronous device packet. Additionally, for data tunnels, asynchronous device endpoints experience minimal CPU load, and asynchronous device messages are asynchronous with audio frames. In some examples, data tunnels use explicit bridging for branching use cases. Data tunnels have predictable latency that depends on tunnel depth and the number of nodes, and exhibit negligible jitter.

[0137] Figures 20-23 are flowcharts illustrating various methods for data networking.

[0138] Step 2005 provides an asynchronous data device coupled to a master-slave communication protocol interface. The asynchronous data device includes a set of router devices and base station devices.

[0139] In step 2010, data (e.g., synchronous or asynchronous) is transmitted via a two-wire bus between the router device and the base station device through the master-slave communication protocol interface.

[0140] In one embodiment, step 2010 may include one or more of steps 2010A to 2010B.

[0141] Step 2010A transmits data between the router device and at least one base station device through a subset of the set of daisy-chained nodes included in a two-wire bus.

[0142] In step 2010B, all base station devices receive the output data via a two-wire bus within the same superframe formed without device sample delay for the output data introduced by each base station device.

[0143] In one embodiment, step 2010B may include one or more of steps 2010B1 to 2010B5.

[0144] Step 2010B1 sends both a communication from the router device to at least one of the base station devices (including any of the base station devices up to the last one that is within communication time distance from the router device) and an acknowledgment of receipt of the communication from at least one of the base station devices to the router device, all within the same superframe.

[0145] In step 2010B2, communication along the two-wire bus is transmitted in periodic superframes, each periodic superframe is started with a downstream synchronous control frame, and each periodic superframe is terminated immediately before the transmission of another downstream synchronous control frame. Each periodic superframe is divided into a downstream transmission period, an upstream transmission period, and a no-transmission period during which the two-wire bus is not driven.

[0146] In 2010B3, communication transactions are initiated independently by one of the base station devices so that one of the base station devices is assigned a label indicating it is a router, and the remaining base station devices are assigned labels indicating they are base stations relative to the router. Round-robin serial peripheral interface (SPI) full-duplex transactions are employed between the base station devices that have been assigned the base station label.

[0147] Step 2010B4 employs an inter-device transfer mechanism for general-purpose input / output (GPIO) over a certain distance, such that each base station device signals to the router device about nearby data and provides the router device with in-band signaling regarding transmission-related full levels for data packets, and in response to receiving transmission-related full levels from the base station devices, the router device analyzes the needs of the base station devices and changes the round-robin frequency of the base station devices in response to those needs.

[0148] Step 2010B5 employs a flow control and bandwidth allocation scheme by the router device, which includes identifying the network bus packet rate of each base station device and estimating the transmission time of a single network bus packet based on the tunnel bandwidth and serial peripheral interface (SPI) rate.

[0149] In step 2015, the router device and the base station device collaboratively populate the routing table maintained by the router device for forwarding data to each of the base station devices. The collaborative router table population scheme performed collaboratively by the router device and the base station devices includes indicating data non-availability using at least one empty packet sent to the router device by at least one of the base station devices.

[0150] In Step 2020, the router device stores information about each base station device and tags the information with the unique hardware ID of each base station device, which uniquely identifies each base station device.

[0151] In one embodiment, step 2020 may include one or more of steps 2020A to 2020B.

[0152] In step 2020A, the router device queries each base station device for its unique hardware ID during subsequent on-power cycles, and the router device uses the information stored for each base station device that is associated with or indexed by the unique hardware ID of each base station device during subsequent on-power cycles.

[0153] In step 2020B, for each base station device, information is stored in an index-based cache having an index system based on the unique hardware ID of the base station device, in order to facilitate index-based retrieval of information. In one embodiment, the information may include routing information for each base station device. In another embodiment, the information may include operating parameters for each base station device.

[0154] Step 2025 employs a scheduler to tick up to the maximum rate, and with each tick, the router device performs a round-robin SPI full-duplex transaction among the set of base station devices, setting the allocated rate as a portion of the maximum rate and sending the allocated rate to each base station device. In one embodiment, each of the multiple ticks may guarantee the minimum bandwidth for each base station device, the router device may take time between ticks for flow control, and may satisfy instantaneous bandwidth requests made by any of the base station devices.

[0155] Selected Examples Embodiment 1 provides a system for data networking over a network bus, comprising a plurality of asynchronous data devices, including a set of router devices and base station devices, and a serial peripheral interface, each of which asynchronous data devices is coupled to the serial peripheral interface, wherein synchronous data is transmitted via the serial peripheral interface over a two-wire bus between each of the set of router devices and base station devices.

[0156] Embodiment 2 includes the subject matter of either the preceding embodiment and / or the subsequent embodiment, further specifying that the two-wire bus includes a plurality of daisy-chained nodes, and that synchronization data is transmitted between a router node and at least one base station node through a subset of the plurality of daisy-chained nodes.

[0157] Example 3 includes subject matter from either of the preceding and / or subsequent examples, further specifying that the base station device is a peripheral device in any of the two-wire communication systems disclosed herein.

[0158] Example 4 provides the method according to any one of the prior and / or following embodiments, wherein the base station device includes a single microphone.

[0159] Example 5 provides a system according to either the preceding and / or subsequent embodiments, in which the base station device array includes a single microphone.

[0160] Embodiment 6 provides a system according to either the preceding or subsequent embodiment, further comprising a two-wire bus, wherein the memory is located on a subnode of the network bus.

[0161] Additional aspects This disclosure may additionally include one or more of the following aspects:

[0162] Embodiment 1. A system for data networking, Multiple asynchronous data devices, including a set of router devices and base station devices, A master-slave communication protocol interface comprising a master-slave communication protocol interface, wherein each of a plurality of asynchronous data devices is coupled to the master-slave communication protocol interface, A system in which data is transmitted via a two-wire bus between a set of router devices and base station devices through a master-slave communication protocol interface.

[0163] Embodiment 2.2 The system according to Embodiment 1, wherein the wire bus includes a plurality of daisy-chained nodes, and data is transmitted between a router device and at least one base station device through a subset of the plurality of daisy-chained nodes.

[0164] Embodiment 3. The system according to Embodiment 1, wherein the data transmitted via a two-wire bus between a router device and a set of base station devices is synchronization data.

[0165] Embodiment 4. The system according to any one of the preceding embodiments, wherein the data transmitted over a two-wire bus between a set of router devices and base station devices is asynchronous data.

[0166] Embodiment 5. The system according to any one of the prior embodiments, wherein the master-slave communication protocol interface comprises an interface selected from a group consisting of a serial peripheral interface (SPI), an inter-integrated circuit (I2C) interface, an inter-integrated sound (I2S) / time-division multiplexing (TDM) interface, and any combination thereof.

[0167] Embodiment 6. The system according to any one of the preceding embodiments, wherein the master-slave communication protocol interface comprises a serial peripheral interface and a data tunnel having a shared bandwidth and time shared between a set of base station devices.

[0168] Embodiment 7. The system according to any one of the preceding embodiments, wherein all base station devices receive output data via a two-wire bus within the same superframe formed without device sample delay of the output data introduced by each base station device.

[0169] Embodiment 8. The system according to any one of the preceding embodiments, wherein both communication from a router device to at least one of the base station devices and acknowledgment of receipt of communication from at least one of the base station devices to the router device are transmitted within the same superframe, and at least one of the base station devices includes any of the base station devices up to the last base station device that is in a temporal distance from the router device.

[0170] A system according to any one of the preceding embodiments, wherein communication along a two-wire bus occurs in periodic superframes, each of which begins with a downstream synchronous control frame and is divided into a downstream transmission period, an upstream transmission period, and a no-transmission period in which the two-wire bus is not driven.

[0171] Embodiment 10. The system according to any one of the preceding embodiments, wherein each superframe ends immediately before the transmission of another downstream synchronous control frame.

[0172] Embodiment 11. The system according to any one of the preceding embodiments, wherein a set of router devices and base station devices cooperatively populate a routing table maintained by the router devices for forwarding data to each of the base station devices, and a cooperative router table population scheme, performed cooperatively by the set of router devices and base station devices, indicates data non-availability using at least one empty packet sent to the router device by at least one of the base station devices.

[0173] Embodiment 12. The system according to any one of the preceding embodiments, wherein the base station devices independently initiate communication transactions such that one of the base station devices is assigned a label indicating that it is a router, and the remaining base station devices are assigned labels indicating that they are base stations relative to the router, and round-robin serial peripheral interface (SPI) full-duplex transactions are employed between the base station devices that have been assigned the labels indicating that they are base stations.

[0174] Embodiment 13. The system according to any one of the preceding embodiments, wherein the inter-device transfer mechanism is used for general-purpose input / output (GPIO) over a distance such that each base station device signals to a router device about nearby data and provides the router device with in-band signaling regarding transmission-related full levels for data packets, and in response to receiving transmission-related full levels from the base station devices, the router device analyzes the needs of the base station devices and changes the round-robin frequency of the base station devices in response to those needs.

[0175] Embodiment 14. The system according to any one of the preceding embodiments, wherein a router device stores information about each base station device and tags the information with a unique hardware ID of each base station device that uniquely identifies each base station device.

[0176] Embodiment 15. The system according to any one of the preceding embodiments, wherein in a subsequent on-power cycle, the router device queries each base station device for the unique hardware ID of each base station device and uses the information stored for each base station device.

[0177] Embodiment 16. The system according to any one of the preceding embodiments, wherein information is stored in an index-based cache having an index system based on a unique hardware ID of a base station device, in order to facilitate index-based retrieval of information for each base station device.

[0178] Embodiment 17. The system according to any one of the preceding embodiments, wherein the information includes routing information for each base station device.

[0179] Embodiment 18. The system according to any one of the preceding embodiments, wherein the information includes the operating parameters of each base station device.

[0180] Embodiment 19. The system according to any one of the preceding embodiments, wherein at least one of the base station devices is a MIDI endpoint.

[0181] Embodiment 20. The system according to any one of the preceding embodiments, wherein the router device uses a flow control and bandwidth allocation scheme that includes identifying the network bus packet rate of each base station device and estimating the transmission time of a single network bus packet based on the tunnel bandwidth and the serial peripheral interface (SPI) rate.

[0182] Embodiment 21. The system according to any one of the preceding embodiments, wherein the scheduler ticks up to the maximum rate, and with each tick, the router device performs a round-robin SPI full-duplex transaction between a set of base station devices, sets the allocation rate as a portion of the maximum rate, and sends the allocation rate to each of the base station devices.

[0183] Embodiment 22. The system according to any one of the preceding embodiments, wherein each of a plurality of ticks guarantees a minimum bandwidth for each of the base station devices, and a router device takes time between ticks for flow control to satisfy instantaneous bandwidth requests made by any of the base station devices.

[0184] Embodiment 23. A method, The combination of multiple asynchronous data devices, including a set of router devices and base station devices, This includes coupling each of multiple asynchronous data devices to a master-slave communication protocol interface, A method by which data is transmitted via a two-wire bus between a router device and a base station device through a master-slave communication protocol interface.

[0185] Embodiment 24.2 The method according to Embodiment 23, wherein the wire bus includes a plurality of daisy-chained nodes, and data is transmitted between a router device and at least one base station device through a subset of the plurality of daisy-chained nodes.

[0186] Embodiment 25. The method according to any one of the preceding embodiments, wherein the data transmitted over a two-wire bus between a set of router devices and base station devices is synchronization data.

[0187] Embodiment 26. The method according to any one of the preceding embodiments, wherein the data transmitted over a two-wire bus between a set of router devices and base station devices is asynchronous data.

[0188]

[0001] Embodiment 27. The method of any one of the prior embodiments, further comprising providing a master-slave communication protocol interface having a serial peripheral interface and a data tunnel having a shared bandwidth and time shared between a set of base station devices.

[0189]

[0002] Embodiment 28. The method according to any one of the preceding embodiments, further comprising all base station devices receiving output data via a two-wire bus in the same superframe formed without device sample delay of the output data introduced by each base station device.

[0190]

[0003] Embodiment 29. The method of any one of the preceding embodiments, further comprising sending both a communication from a router device to at least one of the base station devices and an acknowledgment of receipt of the communication from at least one of the base station devices to the router device within the same superframe, wherein at least one of the base station devices includes any of the base station devices up to the last one that is within communication time distance of the router device.

[0191]

[0004] Embodiment 30. The method of any one of the preceding embodiments, further comprising generating communication along a two-wire bus in periodic superframes, each of which is divided into a downstream synchronous control frame, a downstream transmission period, an upstream transmission period, and a no-transmission period in which the two-wire bus is not driven.

[0192]

[0005] Embodiment 31. The method according to any one of the preceding embodiments, further comprising terminating each superframe immediately before transmitting another downstream synchronous control frame.

[0193]

[0006] Embodiment 32. The method of any one of the preceding embodiments, further comprising a set of router devices and base station devices cooperatively populating a routing table maintained by the router device for forwarding data to each of the base station devices, wherein the cooperative router table population scheme performed cooperatively by the set of router devices and base station devices indicates data nonavailability using at least one empty packet sent to the router device by at least one of the base station devices.

[0194]

[0007] Embodiment 33. The method according to any one of the preceding embodiments, further comprising the base station devices independently initiating a communication transaction such that one of the base station devices is assigned a label indicating that it is a router, and the remaining base station devices are assigned labels indicating that they are base stations relative to the router, and a round-robin serial peripheral interface (SPI) full-duplex transaction is employed between the base station devices that have been assigned the labels indicating that they are base stations.

[0195]

[0008] Embodiment 34. The method of any one of the prior embodiments, further comprising using an inter-device transfer mechanism for general-purpose input / output (GPIO) over a distance such that each base station device signals to a router device about nearby data and provides the router device with in-band signaling about transmission-related fullness levels of data packets, and (b) in response to receiving transmission-related fullness levels from the base station devices, the router device analyzes the needs of the base station devices and, in response to those needs, changes the round-robin frequency of the base station devices.

[0196]

[0009] Embodiment 35. The method according to any one of the prior embodiments, further comprising: a router device storing information about each base station device; and a router device tagging the information with a unique hardware ID of each base station device that uniquely identifies each base station device.

[0197]

[0010] Embodiment 36. The method according to any one of the preceding embodiments, wherein in a subsequent on-power cycle, the router device queries each base station device for the unique hardware ID of each base station device, and the router device uses the information stored for each base station device.

[0198]

[0011] Embodiment 37. The method according to any one of the preceding embodiments, wherein for each base station device, the information is stored in an index-based cache having an index system based on the unique hardware ID of the base station device in order to facilitate index-based retrieval of the information.

[0199]

[0012] Embodiment 38. The method according to any one of the prior embodiments, further comprising using a flow control and bandwidth allocation scheme by a router device, which includes identifying the network bus packet rate of each base station device and estimating the transmission time of a single network bus packet based on the tunnel bandwidth and the serial peripheral interface (SPI) rate.

[0200]

[0013] Embodiment 39. A system having one or more components configured to perform the functions described in any one of Embodiments 1 to 38.

[0201] Modified forms and embodiments As described above, several embodiments and embodiments of the technology of this application have been described, but those skilled in the art will understand that various changes, modifications, and improvements will readily arise. Such changes, modifications, and improvements are intended to be within the spirit and scope of the technology described herein. For example, those skilled in the art will readily conceive of various other means and / or structures for performing the function and / or obtaining one or more of the results and / or advantages described herein, and each of such variations and / or modifications will be considered within the scope of the embodiments described herein.

[0202] Those skilled in the art will recognize many equivalents to the particular embodiments described herein, or can verify them through simple routine experimentation. Therefore, it should be understood that the embodiments described herein are merely examples, and that the inventive embodiments may be carried out in ways other than those specifically described, within the scope of the appended claims and their equivalents. In addition, any combination of two or more features, systems, articles, materials, kits, and / or methods described herein is included within the scope of this disclosure, provided that such features, systems, articles, materials, kits, and / or methods are not contradictory to each other.

[0203] The foregoing outlines the features of one or more aspects of the subject matter disclosed herein. These aspects are provided to enable a person skilled in the art (PHOSITA) to better understand the various aspects of this disclosure. Certain well-understood terms, as well as underlying art and / or standards, may be referenced without further explanation. It is expected that a PHOSITA will have, or have access to, sufficient background knowledge or information in these arts and standards to implement the teachings of this disclosure.

[0204] PHOSITA will understand that the Disclosure may readily be used as a basis for designing or modifying other processes, structures, or variations to perform the same purposes and / or achieve the same advantages as those described herein. PHOSITA will also recognize that such equivalent structures will not deviate from the spirit and scope of the Disclosure, and that various changes, substitutions, and modifications may be made herein without departing from the spirit and scope of the Disclosure.

[0205] The above embodiments may be implemented in any of many ways. One or more embodiments of this application, including the performance of a process or method, may utilize program instructions executable by a device (e.g., a computer, processor, or other device) to perform or control the performance of the process or method.

[0206] In this regard, various inventive concepts may be embodied as computer-readable storage media (or multiple computer-readable storage media) encoded in one or more programs (e.g., computer memory, one or more floppy disks, compact disks, optical disks, magnetic tapes, flash memory, field-programmable gate arrays or circuit configurations of other semiconductor devices, or other tangible computer storage media), and when one or more programs are executed on one or more computers or other processors, they perform a method of implementing one or more of the various embodiments described above.

[0207] A computer-readable medium may be transportable such that the programs stored therein can be loaded onto one or more different computers or other processors to implement various aspects of those described above. In some aspects, the computer-readable medium may be a non-transient medium.

[0208] It should be noted that the activities discussed above, particularly specialized software programs or algorithms, can be applied to any integrated circuit involving signal processing (e.g., gesture signal processing, video signal processing, audio signal processing, analog-to-digital conversion, digital-to-analog conversion), with reference to the drawings, and some of these may be related to the processing of digitized real-time data.

[0209] In some cases, the teachings of this disclosure may be encoded into one or more tangible, non-transient, computer-readable media that, when executed, store executable instructions that instruct a programmable device (such as a processor or DSP) to perform the methods or functions disclosed herein. If the teachings of this disclosure are at least partially embodied in a hardware device (such as an ASIC, IP block, or SoC), the non-transient media may include a hardware device that is hardware-programmed with logic for performing the methods or functions disclosed herein. The teachings may also be implemented in the form of register transfer level (RTL) or other hardware description languages ​​such as VHDL or Verilog, which can be used to program manufacturing processes for producing the disclosed hardware elements.

[0210] In exemplary implementations, at least some of the processing activities outlined herein may also be implemented in software. In some embodiments, one or more of these features may be implemented in hardware provided outside of the elements of the disclosed figures, or may be integrated in any suitable manner to achieve the intended function. Various components may include software (or interconnected software) that can work together to achieve operations such as those outlined herein. In yet other embodiments, these elements may include any suitable algorithms, hardware, software, components, modules, interfaces, or objects that facilitate their operation.

[0211] Any appropriately configured processor component can execute any type of instruction associated with data to achieve the operations detailed herein. Any processor disclosed herein can transform an element or article (e.g., data) from one state or thing to another. In another example, some of the activities outlined herein may be implemented with fixed logic or programmable logic (e.g., software and / or computer instructions executed by the processor), and the elements identified herein may be ASICs including some types of programmable processors, programmable digital logic (e.g., FPGAs, erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)), digital logic, software, code, electronic instructions, flash memory, optical discs, CD-ROMs, DVD-ROMs, magnetic or optical cards, other types of machine-readable media suitable for storing electronic instructions, or any suitable combination thereof.

[0212] During operation, the processor may store information in any suitable type of non-temporary storage medium (e.g., random access memory (RAM), read-only memory (ROM), FPGA, EPROM, electrically erasable programmable ROM (EEPROM), etc.), software, hardware, or, as necessary and based on specific needs, in any other suitable component, device, element, or object. Furthermore, information that is tracked, sent, received, or stored in the processor may be provided in any database, register, table, cache, queue, control list, or storage structure, based on specific needs and implementation examples, all of which may be referenced within any suitable time frame.

[0213] Any of the memory items discussed herein should be interpreted as being included in the broader definition of “memory.” Similarly, any of the potential processing elements, modules, and machines described herein should be interpreted as being included in the broader definition of “microprocessor” or “processor.” Furthermore, in various embodiments, the processors, memories, network cards, buses, storage devices, associated peripherals, and other hardware elements described herein may be implemented by processors, memories, and other associated devices configured with software or firmware for emulating or virtualizing the functions of those hardware elements.

[0214] Furthermore, it should be understood that computers can be embodied in any of several forms, including, but not limited to, rack-mount computers, desktop computers, laptop computers, or tablet computers. In addition, computers can be embedded in devices with suitable processing power, including personal digital assistants (PDAs), smartphones, mobile phones, iPads®, or any other suitable portable or fixed electronic devices, although these are not generally considered computers.

[0215] Furthermore, a computer may have one or more input and output devices. These devices may, among other things, be used to present a user interface. Examples of output devices that may be used to provide a user interface include a printer or display screen for visual presentation of output, and a speaker or other sound-generating device for audible presentation of output. Examples of input devices that may be used for a user interface include a keyboard, as well as pointing devices such as a mouse, touchpad, and digitizing tablet. As another example, a computer may receive input information through speech recognition or in other audible formats.

[0216] Such computers may be interconnected by one or more networks of any preferred form, including local area networks or wide area networks such as enterprise networks, and intelligent networks (INs) or the Internet. Such networks may be based on any preferred technology, may operate according to any preferred protocol, and may include wireless or wired networks.

[0217] Computer executable instructions can take many forms, such as program modules, that are executed by one or more computers or other devices. Generally, a program module includes routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. Typically, the functionality of a program module may be combined or distributed as desired in various ways.

[0218] The terms “program” or “software” are used herein in a general sense and refer to any type of computer code or set of computer executable instructions employed to program a computer or other processor to implement various aspects of the embodiments described above. Additionally, it should be understood that, according to one embodiment, one or more computer programs that, when executed, implement the method of this application do not need to reside on a single computer or processor, but may be distributed modularly across several different computers or processors to implement various aspects of this application.

[0219] Furthermore, data structures can be stored in a computer-readable medium in any preferred form. For simplicity of explanation, it can be shown that a data structure has fields that are associated through locations within the data structure. Such relationships may also be achieved by allocating storage devices for the fields that have locations in a computer-readable medium that also transmit relationships between the fields. However, relationships between information within the fields of a data structure can be established using any preferred mechanism, including the use of pointers, tags, or other mechanisms for establishing relationships between data elements.

[0220] When implemented in software, the software code can run on any suitable processor or set of processors, whether it is provided on a single computer or distributed across multiple computers.

[0221] Computer program logic that implements all or part of the functions described herein may be implemented in various forms, including, but not limited to, source code, computer executable, hardware description, and various intermediate forms (e.g., mask work, or forms generated by an assembler, compiler, linker, or locator). For example, source code may include a set of computer program instructions implemented in various programming languages, such as object code, assembly language, or high-level languages ​​like OpenCL, RTL, Verilog, VHDL, Fortran, C, C++, Java®, or HTML, for use with various operating systems or operating environments. Source code may define and use various data structures and communication messages. Source code may be computer executable (e.g., via an interpreter), or source code may be converted to computer executable (e.g., via a converter, assembler, or compiler).

[0222] In some embodiments, any number of electrical circuits in the drawing may be mounted on a substrate of the associated electronic device. The substrate can be a general circuit board capable of housing various components of the internal electronic system of the electronic device and further providing connectors for other peripheral devices. More specifically, the substrate can provide electrical connections that enable other components of the system to communicate electrically. Any suitable processor, memory elements, etc. (including digital signal processors, microprocessors, support chipsets, etc.) can be appropriately coupled to the substrate based on specific configuration needs, processing requirements, computer designs, etc.

[0223] Other components, such as external storage, additional sensors, audio / video display controllers, and peripheral devices, may be mounted to the board via cables as plug-in cards, or may be integrated into the board itself. In another exemplary embodiment, the electrical circuits of the drawings may be implemented as standalone modules (e.g., devices having associated components and circuits configured to perform a particular application or function), or as plug-in modules in application-specific hardware for electronic devices.

[0224] It should be noted that in many of the examples provided herein, interactions may be described in relation to two, three, four, or more electrical components. However, this is done for clarification and illustrative purposes only. It should be understood that the system may be established in any preferred manner. In line with similar design alternatives, any of the components, modules, and elements shown in the drawings may be combined in various possible configurations, all of which are clearly within the broad scope of this disclosure.

[0225] In some cases, referring to only a limited number of electrical components can more easily illustrate one or more functions of a given flowset. It should be understood that the electrical circuits and their teachings in the drawings are readily expandable and can accommodate more components, as well as more complex / sophisticated arrangements and configurations. Therefore, the examples provided are not intended to limit the scope or hinder the broader teaching of electrical circuits when potentially applied to countless other architectures.

[0226] Furthermore, as described, several embodiments may be embodied as one or more methods. The actions performed as part of the method may be ordered in any preferred manner. Thus, although the exemplary embodiments are shown as sequential actions, embodiments can be constructed in which actions are performed in a different order than those illustrated, which may include performing several actions simultaneously.

[0227] Interpretation of terms All definitions defined and used herein should be understood to govern dictionary definitions, definitions incorporated by reference in documents, and / or the ordinary meaning of the defined terms. Unless otherwise explicitly requested, throughout this specification and the claims,

[0228] Words like "comprise" and "comprising" should be interpreted in a comprehensive sense, as opposed to an exclusive or exhaustive sense; that is, they should be interpreted as "including, but not limited to."

[0229] "Connected," "coupled," or any variation thereof means any direct or indirect connection or coupling between two or more elements, which may be physical, logical, or a combination thereof.

[0230] When used to describe this specification, the words “this specification,” “above,” “below,” and similar terms refer to this specification as a whole and not to any particular part thereof.

[0231] When "or" is used in relation to a list of two or more items, it encompasses all of the following interpretations of the word, any of the items in the list, all of the items in the list, and any combination of the items in the list.

[0232] The singular forms "a," "an," and "the" also include the meaning of any appropriate plural form.

[0233] The terms used herein to indicate direction, such as "vertical," "transverse," "horizontal," "upward," "downward," "forward," "backward," "inward," "outward," "vertical," "transverse," "left," "right," "front," "back," "top," "bottom," "below," "above," and "under," depend on the specific direction of the apparatus described and illustrated. The subject matter described herein may assume various other directions. Therefore, these directional terms are not strictly defined and should not be interpreted narrowly.

[0234] As used herein and in the claims, the indefinite articles "a" and "an" should be understood to mean "at least one" unless explicitly indicated otherwise.

[0235] As used herein and in the claims, the phrase “and / or” should be understood to mean “either or both” of the elements thus combined, i.e., elements that exist as a combination in some cases and as separate in others. Multiple elements listed using “and / or” should be interpreted in the same way, i.e., “one or more” of the elements thus combined.

[0236] Elements other than those specifically identified by the "and / or" clause may be present at their discretion, regardless of whether they are related to those specifically identified elements. Thus, as an unrestrictive example, when used in combination with unrestrictive language such as "comprising," a reference to "A and / or B" may, in one aspect, refer to A only (optionally including elements other than B), in another aspect, refer to B only (optionally including elements other than A), and in yet another aspect, refer to both A and B (optionally including other elements).

[0237] When used in the specification and claims herein, the phrase “at least one” relating to a list of one or more elements should be understood to mean at least one element selected from any one or more elements in the list of elements, and not necessarily including at least one of each element and all elements specifically listed in the list of elements, nor excluding any combination of elements in the list of elements. This definition also allows for the optional presence of elements other than those specifically identified in the list of elements referred to by the phrase “at least one,” whether related to or unrelated to those specifically identified elements.

[0238] Therefore, as a non-restrictive example, “at least one of A and B” (or equivalently, “at least one of A or B” or equivalently, “at least one of A and / or B”) may, in one embodiment, refer to A which optionally includes at least one or more elements and does not include B (and optionally includes elements other than B); in another embodiment, refer to B which optionally includes at least one or more elements and does not include A (and optionally includes elements other than A); and in yet another embodiment, refer to A which optionally includes at least one or more elements and does not include at least one or more elements and B which optionally includes at least one or more elements (and optionally includes other elements), etc.

[0239] As used herein, the term “between” should be inclusive unless otherwise indicated. For example, “between A and B” includes A and B unless otherwise indicated.

[0240] Furthermore, the terminology and grammar used herein are for illustrative purposes only and should not be considered limiting. The use of “including,” “comprising,” or “having,” “containing,” “involving,” and variations thereof herein means to include the items and their equivalents listed thereafter, as well as any additional items.

[0241] In the claims and the above specification, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” and “composed of” should be understood as open-ended, meaning they include but are not limited to these. Only the transitional phrases “consisting of” and “consisting essentially of” are considered closed or partially closed transitional phrases, respectively.

[0242] Many other changes, substitutions, modifications, alterations and modifications may be apparent to those skilled in the art, and this disclosure is intended to encompass all such changes, substitutions, modifications, alterations and modifications as being included within the scope of the appended claims.

[0243] For the United States Patent and Trademark Office (USPTO) and, additionally, to assist any reader of any patent issued in connection with this application in interpreting the claims attached herein, the Applicant hopes that the Applicant will be deemed to have (a) not intended to exercise any of the attached claims under Section 112(f) of the United States Patent Act as of the filing date of this application unless the words “means for” or “steps for” are specifically used in any particular claim, and (b) not intended to limit the Disclosure in any way not otherwise reflected in the attached claims by any statement herein.

[0244] Therefore, it should be considered that the present invention is not limited to the specific embodiments described above. Various modifications, equivalent processes, and many structures to which the present invention may be applicable will be readily apparent to those skilled in the art through a review of this disclosure.

[0245] While illustrative embodiments of the system and method are provided, please understand that the detailed description and specific examples are for illustrative purposes only and are not intended to limit the scope. These and other features, embodiments, and advantages of the system and method of the present invention can be better understood from the description, the appended claims or embodiments, and the accompanying drawings. Please understand that the drawings are illustrative and not drawn to scale. Also, please understand that the same reference numerals are used throughout the drawings to indicate identical or similar parts.

[0246] Other variations of the disclosed aspects can be understood and realized by those skilled in the art in practicing this disclosure, based on consideration of the drawings, disclosures, and appended aspects or claims. In aspects or claims, the word “comprising” does not exclude other elements or steps, and the indefinite “a” or “an” does not exclude plurals. The mere fact that certain measures are enumerated in different dependent aspects or dependent claims does not imply that combinations of these measures cannot be used for benefit. No reference numeral in the claims should be construed as limiting the scope. [Explanation of Symbols]

[0247] 120 transceivers 1302 Processing device 1304 memory 1306 Display Devices 1308 Audio output device 1310 Other output devices 1312 Other communication chips 1314 Power supply 1318 GPS devices 1320 Other input devices 1322 Antenna 1324 Voice Input Devices

Claims

1. A system for data networking, Multiple asynchronous data devices, including a set of router devices and base station devices, A master-slave communication protocol interface comprising a master-slave communication protocol interface, wherein each of the plurality of asynchronous data devices is coupled to the master-slave communication protocol interface, The master-slave communication protocol interface includes a data tunnel having a shared bandwidth and a time shared between the set of base station devices, A system in which data is transmitted via a two-wire bus between the router device and the base station device set via the master-slave communication protocol interface.

2. The system according to claim 1, wherein the two-wire bus includes a plurality of daisy-chained nodes, and the data is transmitted between the router device and at least one base station device through a subset of the plurality of daisy-chained nodes.

3. The system according to claim 1 or 2, wherein the data transmitted via the two-wire bus between the router device and the base station device set is synchronization data.

4. The system according to claim 1 or 2, wherein the data transmitted via the two-wire bus between the router device and the base station device set is asynchronous data.

5. The system according to claim 1 or 2, wherein the master-slave communication protocol interface further comprises an interface selected from a group consisting of a serial peripheral interface (SPI), an inter-integrated circuit (I2C) interface, an integrated sound (I2S) / time-division multiplexing (TDM) interface, and any combination thereof.

6. The system according to claim 1 or 2, wherein the master-slave communication protocol interface further comprises a serial peripheral interface.

7. The system according to claim 1 or 2, wherein all of the base station devices receive the output data via the two-wire bus within the same superframe formed without device sample delay of the output data introduced by each of the base station devices.

8. The system according to claim 7, wherein both the communication from the router device to at least one of the base station devices and the acknowledgment of receipt of the communication from at least one of the base station devices to the router device are transmitted within the same superframe, and the at least one of the base station devices includes any of the base station devices up to the last of the base station devices that is within communication time distance from the router device.

9. The system according to claim 7, wherein communication along the two-wire bus occurs in periodic superframes, each of which begins with a downstream synchronous control frame and is divided into a downstream transmission period, an upstream transmission period, and a non-transmission period in which the two-wire bus is not driven.

10. The system according to claim 9, wherein each superframe ends immediately before the transmission of another downstream synchronous control frame.

11. The system according to claim 1 or 2, wherein the set of router devices and base station devices collaboratively populate a routing table maintained by the router device for forwarding data to each of the base station devices, and a collaborative router table population scheme, performed collaboratively by the set of router devices and base station devices, indicates data non-availability using at least one empty packet transmitted to the router device by at least one of the base station devices.

12. The system according to claim 1 or 2, wherein the base station devices independently initiate communication transactions such that one of the base station devices is assigned a label indicating that it is a router, and the remaining base station devices are assigned labels indicating that they are base stations relative to the router, and round-robin serial peripheral interface (SPI) full-duplex transactions are employed between the base station devices that have been assigned labels indicating that they are base stations.

13. The system according to claim 1 or 2, wherein the inter-device transfer mechanism is used for general-purpose input / output (GPIO) over a distance such that each of the base station devices signals to the router device about nearby data and provides the router device with in-band signaling regarding transmission-related full levels of data packets, and in response to receiving the transmission-related full levels from the base station devices, the router device analyzes the needs of the base station devices and changes the round-robin frequency of the base station devices in response to those needs.

14. The system according to claim 1 or 2, wherein the router device stores information about each base station device and tags the information with a unique hardware ID of each base station device that uniquely identifies each base station device.

15. The system according to claim 14, wherein in a subsequent on-power cycle, the router device queries each of the base stations for the unique hardware ID of each of the base stations and uses the information stored for each of the base stations.

16. The system according to claim 14, wherein the information is stored in an index-based cache having an index system based on a unique hardware ID of the base station device, in order to facilitate an index-based search of the information for each of the base station devices.

17. The system according to claim 16, wherein the information includes routing information for each of the base station devices.

18. The system according to claim 16, wherein the information includes the operating parameters of each of the base station devices.

19. The system according to claim 1 or 2, wherein at least one of the base station devices is a MIDI endpoint.

20. The system according to claim 1 or 2, wherein the router device uses a flow control and bandwidth allocation scheme that includes identifying the network bus packet rate of each base station device and estimating the transmission time of a single network bus packet based on the tunnel bandwidth and the serial peripheral interface (SPI) rate.

21. The system according to claim 1 or 2, wherein the scheduler ticks up to the maximum rate, and with each tick, the router device executes a round-robin SPI full-duplex transaction among the set of base station devices, sets the allocation rate as a portion of the maximum rate, and sends the allocation rate to each of the base station devices.

22. The system according to claim 21, wherein each of a plurality of ticks guarantees a minimum bandwidth for each of the base station devices, and the router device takes time between ticks for flow control to satisfy instantaneous bandwidth requests made by any of the base station devices.

23. It is a method, The combination of multiple asynchronous data devices, including a set of router devices and base station devices, Each of the aforementioned asynchronous data devices is coupled to a master-slave communication protocol interface, Providing the master-slave communication protocol interface, which includes a data tunnel having shared bandwidth and time shared between the set of base station devices, A method in which data is transmitted via a two-wire bus between the router device and the base station device via the master-slave communication protocol interface.

24. The method according to claim 23, wherein the two-wire bus includes a plurality of daisy-chained nodes, and the data is transmitted between the router device and at least one base station device through a subset of the plurality of daisy-chained nodes.

25. The method according to claim 23 or 24, wherein the data transmitted via the two-wire bus between the router device and the base station device set is synchronization data.

26. The method according to claim 23 or 24, wherein the data transmitted via the two-wire bus between the router device and the base station device set is asynchronous data.

27. ​​The method according to claim 23 or 24, wherein the master-slave communication protocol interface further includes a serial peripheral interface.

28. The method according to claim 23 or 24, further comprising all of the base station devices receiving the output data via the two-wire bus within the same superframe formed without component device sample delay of the output data introduced by each of the base station devices.

29. The method according to claim 28, further comprising transmitting both a communication from the router device to at least one of the base station devices and an acknowledgment of receipt of the communication from at least one of the base station devices to the router device within the same superframe, wherein the at least one of the base station devices includes any of the base station devices up to the last of the base station devices that are within communication time distance from the router device.

30. The method according to claim 28, further comprising generating periodic superframes along the two-wire bus, each of which is divided into a downstream synchronous control frame, a downstream transmission period, an upstream transmission period, and a no-transmission period during which the two-wire bus is not driven.

31. The method according to claim 30, further comprising terminating each superframe immediately before transmitting another downstream synchronous control frame.

32. The method according to claim 23 or 24, further comprising the set of router devices and base station devices cooperatively populating a routing table maintained by the router device for forwarding data to each of the base station devices, wherein the cooperative router table population scheme performed cooperatively by the set of router devices and base station devices includes indicating data non-availability using at least one empty packet transmitted to the router device by at least one of the base station devices.

33. The method according to claim 23 or 24, further comprising the base station devices independently initiating a communication transaction such that one of the base station devices is assigned a label indicating that it is a router, and the remaining base station devices are assigned labels indicating that they are base stations relative to the router, wherein a round-robin serial peripheral interface (SPI) full-duplex transaction is employed between the base station devices that are assigned the labels indicating that they are base stations.

34. The method according to claim 23 or 24, further comprising: (a) each of the base station devices signaling to the router device about nearby data and providing the router device with in-band signaling about transmission-related fullness levels for data packets; and (b) using an inter-device transfer mechanism for general-purpose input / output (GPIO) over a distance such that, in response to receiving the transmission-related fullness levels from the base station devices, the router device analyzes the needs of the base station devices and, in response to those needs, changes the round-robin frequency of the base station devices.

35. The method according to claim 23 or 24, further comprising: the router device storing information about each base station device; and the router device tagging the information with a unique hardware ID of each base station device that uniquely identifies each base station device.

36. The method according to claim 35, wherein in a subsequent on-power cycle, the router device queries each of the base stations for a unique hardware ID of each of the base stations, and the router device uses the information stored for each of the base stations.

37. The method according to claim 35, wherein the information is stored in an index-based cache having an index system based on a unique hardware ID of the base station device, in order to facilitate an index-based lookup of the information for each of the base station devices.

38. The method according to claim 23 or 24, further comprising using a flow control and bandwidth allocation scheme by the router device, which includes identifying the network bus packet rate of each base station device and estimating the transmission time of a single network bus packet based on the tunnel bandwidth and the serial peripheral interface (SPI) rate.

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