Sensor device and semiconductor device requiring said sensor device

Abstract

To provide a sensor device whose circuit occupied area is reduced without impairing the reliability of detection and determination results, and a semiconductor device that comprises the sensor device.SOLUTION: A sensor device 10 determines the detection of a physical quantity by a plurality of times of continuous detection, and comprises: a hall element 20 that outputs a signal S01; a determination circuit 40 that outputs a signal S05 including a signal level that corresponds to a result of determination of whether or not the detection of the physical quantity from a signal S02 continuously matches twice in the current round and the immediately preceding round; a determination circuit 50 that has a counter capable of initializing the counted number when the detection of the physical quantity is not continued twice, and continuing to count until the set number of rounds when it is continued twice, and outputs a signal S08 including the signal level corresponding to whether or not to continuously match until the set number of rounds; and an output register 90 that switches the signal level of an output signal So supplied to an output terminal To, in accordance with a change of the signal level of the signal S08.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a sensor device and a semiconductor device including the sensor device.

Background Art

[0002] According to a sensor device represented by a magnetic sensor and a semiconductor device including the sensor device, fluctuations in a detection determination result due to noise are suppressed by sequentially latching a plurality of logical outputs of a sensor or the like with a register and performing a coincidence determination (see, for example, Patent Document 1). In order to improve the reliability of the detection determination result, it is effective to increase the number of coincidence determinations. In the circuit described in Patent Document 1, the number of coincidence determinations is set to three by a 2-bit register.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] However, when a circuit (hereinafter referred to as a "conventional device") is configured to increase the number of coincidence determinations without any particular modification, the occupied area of the register for latching the logical output is significantly increased. For example, in the circuit described in Patent Document 1, if the number of coincidence determinations is "N" (N is a natural number of 2 or more), an (N - 1)-bit register is required.

[0005] The present invention has been made in view of the above circumstances, and an object thereof is to provide a sensor device with a reduced circuit occupied area and a semiconductor device including the sensor device without impairing the reliability of the detection determination result.

Means for Solving the Problems

[0007] According to the present invention, the circuit occupied area can be reduced without compromising the reliability of the detection and judgment results. [Brief explanation of the drawing]

[0008] [Figure 1] This is a schematic block diagram showing an example of the circuit configuration of a sensor device and a semiconductor device equipped with the sensor device according to an embodiment of the present invention. [Figure 2] This is a schematic block diagram showing an example of the circuit configuration of a sensor device and a first determination circuit of a semiconductor device equipped with the sensor device according to this embodiment. [Figure 3] This is a schematic block diagram showing an example of the circuit configuration of a counter in the second determination circuit of a sensor device and a semiconductor device equipped with the sensor device according to this embodiment. [Figure 4](A) is a diagram showing the relationship between the detection result signal and the magnetic flux density of the sensor device and the semiconductor device equipped with the sensor device according to this embodiment, and (B) is a diagram showing the relationship between the output signal and the magnetic flux density of the semiconductor device according to this embodiment. [Figure 5] This is a timing diagram of the semiconductor device according to this embodiment. [Modes for carrying out the invention]

[0009] Hereinafter, a sensor device and a semiconductor device equipped with the sensor device according to an embodiment of the present invention will be described with reference to the drawings.

[0010] Figure 1 is a block diagram showing an example of the circuit configuration of a sensor device 10 and a semiconductor device 1, which are embodiments of the present invention. Here, the X, Y, and Z axes shown in Figure 1 are the coordinate axes of a three-dimensional Cartesian coordinate system that are mutually orthogonal. The XY plane is a plane parallel to the surface of the semiconductor substrate 2 (the surface on the near side of the paper in Figure 1). That is, the surface of the semiconductor substrate 2 has the Z axis as its normal vector.

[0011] The semiconductor device 1 comprises a semiconductor substrate 2 on which a sensor device 10 is formed in a semiconductor region. The semiconductor substrate 2 is provided with a power terminal 3 connected to a first power supply and a power terminal 4 connected to a second power supply.

[0012] The sensor device 10 is a device that determines the detection of a physical quantity by determining that the physical quantity has been detected multiple times in succession. Here, the number of times set as the upper limit for counting whether the physical quantity has been detected is defined as "N times". N is a natural number of 2 or greater. The sensor device 10 comprises a Hall element 20, a binarization circuit 30, a determination circuit 40, a determination circuit 50, and an output register 90.

[0013] The Hall element 20 as a sensor element is an example of a magnetic sensor element. The illustrated Hall element 20 is a so-called horizontal Hall element that outputs a signal S01 corresponding to the magnetic flux density B acting in the direction perpendicular to the semiconductor substrate 2, that is, in the Z direction.

[0014] The binarization circuit 30 is a circuit that converts, for example, a signal S01 as a detection result signal including a low level (hereinafter referred to as "L level") and a high level (hereinafter referred to as "H level") into a signal S02 obtained by binarizing the signal S01. The signal S02 includes two signal levels corresponding to the signal level of the signal S01, specifically, the signal levels corresponding to whether or not the current pole detection state and the magnetic flux density B match. The binarization circuit 30 has an input terminal connected to the output terminal of the Hall element 20 and an output terminal that outputs the signal S02.

[0015] The determination circuit 40 as the first determination circuit determines whether or not the fact that the magnetic flux density B as a physical quantity has been detected twice continuously in this time and the immediately previous time based on the input signal S02, and outputs a signal S05 including a signal level corresponding to the determined result. The determination circuit 40 has an input terminal 40a to which the signal S02 is supplied, an input terminal 40b to which a clock signal CLK is supplied, an input terminal 40c to which a reset signal RST is supplied, and an output terminal 40d that outputs a signal S05 as an initialization signal. The input terminal 40a is connected to the output terminal of the binarization circuit 30.

[0016] The determination circuit 50 as the second determination circuit outputs a signal S08 as an output latch signal including a signal level corresponding to the result of determining whether or not the number of times the detection of the magnetic flux density B has been continuously performed twice has continuously matched up to the set number of times based on the signal S05. The determination circuit 50 has an input terminal 50a to which the clock signal CLK is supplied, an input terminal 50b connected to the output terminal 40d, a counter 60, a continuous coincidence determination circuit 70, an AND circuit 80, and an output terminal 50c that outputs the signal S08.

[0017] The counter 60 is configured to be able to count the number of times that the detection of the magnetic flux density B has been continuous twice up to a set number of times. The counter 60 includes an input terminal 60a connected to the input terminal 50a, an input terminal 60b connected to the input terminal 50b, and an output terminal 60c that outputs a signal S06 representing the count number of the number of times that the detection of the magnetic flux density B has been continuous twice. The signal S06 is a binary signal having a number of bits corresponding to the set count number.

[0018] The continuous coincidence determination circuit 70 includes an input terminal 70a connected to the output terminal 60c and an output terminal 70b that outputs a signal S07 as a coincidence determination flag signal. The signal S07 includes a signal level corresponding to a determination result as to whether or not the number of times that the detection of the magnetic flux density B has been continuous twice has continuously coincided up to the set number of times. The L level of the signal S07 corresponds to, for example, a state in which the number of times that the detection of the magnetic flux density B has been continuous twice has not continuously coincided up to the set number of times. The H level corresponds to, for example, a state in which the number of times that the detection of the magnetic flux density B has been continuous twice has continuously coincided up to the set number of times.

[0019] The continuous coincidence determination circuit 70 is configured to have, for example, a decoder that outputs the signal S07 according to a preset rule with respect to the input signal S06. In the decoder in the continuous coincidence determination circuit 70, the values of 3 bits (000b) to (111b) grasped from the signal S06 and the signal level of the signal S07 are associated with each other. The decoder in the continuous coincidence determination circuit 70 is configured to output the signal S07 including the signal level corresponding to the value grasped from the signal S06.

[0020] The AND circuit 80 as the first AND circuit includes a first input terminal 80a to which a clock signal CLK is supplied, a second input terminal 80b connected to the output terminal 70b, and an output terminal 80c connected to the output terminal 50c.

[0021] The output register 90 is configured, for example, with a rising edge type D flip-flop (hereinafter referred to as "D-FF") circuit. The D-FF circuit of the output register 90 includes a first input terminal D, a second input terminal C connected to the output terminal 80c, a reset signal input terminal R to which a reset signal RST is supplied, a first output terminal Q that outputs a positive logic signal, and a second output terminal QX that outputs a negative logic signal. The first input terminal D is connected to the second output terminal QX and the output terminal To.

[0022] Next, we will describe a more detailed example of the circuit configuration of the judgment circuit 40 and the counter 60. Figure 2 is a block diagram showing an example of the circuit configuration of the judgment circuit 40. Figure 3 is a block diagram showing an example of the circuit configuration of the counter 60.

[0023] In addition to the input terminals 40a, 40b, 40c and output terminal 40d described above, the determination circuit 40 further includes, for example, rising edge type D-FF circuits 41, 43 and a NAND circuit 45 including a first input terminal 45a, a second input terminal 45b, and an output terminal 45c.

[0024] The D-FF circuit 41, acting as the first flip-flop circuit, outputs a signal S03, which is a first hold signal, containing two signal levels corresponding to the determination result of the detection of magnetic flux density B in the most recent step, based on the signal S02 and the clock signal CLK. The D-FF circuit 43, acting as the second flip-flop circuit, outputs a signal S04, which is a second hold signal, containing two signal levels corresponding to the determination result of the detection of magnetic flux density B in the previous step (hereinafter simply referred to as "the previous step"), based on the signal S03 and the clock signal CLK.

[0025] Here, signal S03 includes, for example, an L level corresponding to a determination result that does not determine that the magnetic flux density B of the most recent measurement was detected, and an H level signal level corresponding to a determination result that determines that the magnetic flux density B of the most recent measurement was detected. Signal S04 includes, for example, an L level corresponding to a determination result that does not determine that the magnetic flux density B of the previous measurement was detected, and an H level signal level corresponding to a determination result that determines that the magnetic flux density B of the previous measurement was detected.

[0026] D-FF circuits 41 and 43 each include a first input terminal D, a second input terminal C, a reset signal input terminal R, a first output terminal Q that outputs a positive logic signal, and a second output terminal QX that outputs a negative logic signal.

[0027] In the D-FF circuit 41, the first input terminal D is connected to input terminal 40a. The second input terminal C is connected to input terminal 40b. The reset signal input terminal R is connected to input terminal 40c. The first output terminal Q, which is the output terminal of the first flip-flop circuit, is connected to the first input terminal D and the first input terminal 45a of the D-FF circuit 43. In the D-FF circuit 43, the first input terminal D is connected to the first output terminal Q and the first input terminal 45a of the D-FF circuit 41. The second input terminal C is connected to input terminal 40b. The reset signal input terminal R is connected to input terminal 40c. The first output terminal Q, which is the output terminal of the second flip-flop circuit, is connected to the second input terminal 45b.

[0028] In the NAND circuit 45, the first input terminal 45a is connected to the first output terminal Q of the D-FF circuit 41 and the first input terminal D of the D-FF circuit 43. The second input terminal 45b is connected to the first output terminal Q of the D-FF circuit 43. The output terminal 45c is connected to the output terminal 40d.

[0029] In addition to the input terminals 60a, 60b and output terminal 60c described above, the counter 60 also has, for example, three falling-edge type D-FF circuits 601 to 603, and is configured as a 3-bit counter. That is, if we explain using a natural number k, when the counter 60 is configured as a k-bit counter, the counter 60 is configured with at least k flip-flop circuits.

[0030] The following relationship (1) holds between a natural number k and a natural number N that represents the upper limit for counting when a physical quantity has been detected. k = ceiling(log2N) --- (1) Here, ceiling(log2N) is the ceiling function that represents the smallest integer greater than or equal to log2N for a real number log2N. For example, when N=3 or 4, k=2. Also, when N=5, 6, 7, or 8, k=3.

[0031] Each of the D-FF circuits 601 to 603 includes a first input terminal D, a second input terminal CX, a reset signal input terminal R, a first output terminal Q that outputs a positive logic signal, and a second output terminal QX that outputs a negative logic signal, respectively. In counter 60, D-FF circuit 601 corresponds to the first bit from the least significant digit, i.e., the least significant bit (LSB). D-FF circuit 602 corresponds to the second bit from the least significant digit, i.e., the middle bit. D-FF circuit 603 corresponds to the third bit from the least significant digit, i.e., the most significant bit (MSB).

[0032] The first output terminal Q of D-FF circuit 601 is connected to output terminal 60c via a signal line that supplies signal S61, which includes a signal level corresponding to the least significant bit (0 or 1). The first output terminal Q of D-FF circuit 602 is connected to output terminal 60c via a signal line that supplies signal S62, which includes a signal level corresponding to the second least significant bit (0 or 1). The first output terminal Q of D-FF circuit 603 is connected to output terminal 60c via a signal line that supplies signal S63, which includes a signal level corresponding to the most significant bit (0 or 1).

[0033] Next, we will explain the characteristics of the sensor device 10 and the semiconductor device 1, specifically the relationship between the signal S02 and the magnetic flux density B, and the relationship between the output signal So and the magnetic flux density B.

[0034] Figure 4(A) is a diagram showing the relationship between the signal S02 and the magnetic flux density B of the sensor device 10 and the semiconductor device 1. Here, the horizontal axis of Figure 4(A) represents the magnetic flux density B, with the south pole as the positive direction. That is, the negative region to the left of the vertical axis (B=0) (B<0) corresponds to the north pole, and the positive region to the right (B>0) corresponds to the south pole. Furthermore, the solid lines L1 and L2 shown in Figure 4(A) correspond to the cases where the output signal So is at an L level and an H level, respectively, i.e., the south pole detection state and the north pole detection state of the sensor device 10. In addition, BRP and BOP are the magnetic flux densities that constitute the return point and the operating point, respectively. In the description of this embodiment, the magnetic flux densities that constitute the return point and the operating point are referred to as the return point BRP and the operating point BOP, respectively.

[0035] According to Figure 4(A), in the S-pole detection state, as shown by the solid line L1, if the magnetic flux density B is less than the return point BRP, that is, if the magnetic flux density B is greater on the N-pole side, an H-level signal S02 corresponding to the detection of magnetic flux density B is output. On the other hand, if the magnetic flux density B is greater than or equal to the return point BRP, that is, if the magnetic flux density B is not greater on the N-pole side, an L-level signal S02 corresponding to the non-detection of magnetic flux density B is output. In short, the S-pole detection state is a state in which the system waits for the detection of a strong magnetic field on the N-pole, which is the opposite pole of the S-pole.

[0036] Furthermore, in the N-pole detection state, as shown by the solid line L2, if the magnetic flux density B is greater than the operating point BOP, an H-level signal S02 corresponding to the detection of magnetic flux density B is output. On the other hand, if the magnetic flux density B is less than or equal to the operating point BOP, an L-level signal S02 corresponding to the non-detection of magnetic flux density B is output. In short, the N-pole detection state is a state in which the device waits for the detection of a strong magnetic field of the S-pole, which is the opposite pole of the N-pole.

[0037] Figure 4(B) is a diagram showing the relationship between the output signal So and the magnetic flux density B of the sensor device 10 and the semiconductor device 1.

[0038] According to Figure 4(B), the negative region to the left of the vertical axis (B=0) (B<0) corresponds to the north pole, and the positive region to the right (B>0) corresponds to the south pole. The north pole detection state corresponds to the high level of the output signal So. While the north pole is detected, the high level of the output signal So, i.e., the north pole detection state, is maintained as long as the operating point BOP located on the south pole side (B>0) is not exceeded. When the magnetic flux density B changes in the increasing direction (to the right in Figure 4(B)) and exceeds the operating point BOP, the state transitions from the north pole detection state to the south pole detection state.

[0039] On the other hand, the south pole detection state corresponds to the low level of the output signal So. While the south pole detection state is active, the low level of the output signal So, i.e., the south pole detection state, is maintained as long as the return point BRP, located on the north pole side (B<0), does not exceed the negative side. When the magnetic flux density B changes in the decreasing direction (to the left in Figure 4(B)) and exceeds the negative side of the return point BRP, the state transitions from the south pole detection state to the north pole detection state.

[0040] Next, the operation of the sensor device 10 and the semiconductor device 1 will be described. First, the general operation of the sensor device 10 and the semiconductor device 1 will be explained with reference to Figures 1 to 4. The semiconductor device 1 operates with power terminals 3 and 4 connected to a first power supply and a second power supply, respectively. The first power supply voltage is supplied from power terminal 3. The second power supply voltage is supplied from power terminal 4. The first and second power supply voltages are supplied to a circuit (not shown) and a sensor device 10 within the semiconductor device 1, respectively.

[0041] In the N - pole detection state where the sensor device 10 detects a strong magnetic field (B > BRP) on the N - pole side, for example, it outputs an output signal So of H level. In the S - pole detection state where it detects a strong magnetic field (B > BOP) on the S - pole side, for example, it outputs an output signal So of L level. In the sensor device 10, a signal S01 corresponding to the magnetic flux density B acting from the outside is output from the Hall element 20. The signal S01 is converted into a binary - coded signal S02 by the binarization circuit 30.

[0042] The two levels included in the signal S02 correspond to whether the current pole detection state and the magnetic flux density B match or not. For example, the L level corresponds to the state where the current pole detection state and the magnetic flux density B match. The H level corresponds to the state where the current pole detection state and the magnetic flux density B do not match. In this example, when the signal S02 transitions from the L level to the H level, the detection determination of the strong magnetic field of the opposite pole is started for the current pole detection state.

[0043] The signal S02, the clock signal CLK, and the reset signal RST are supplied to the determination circuit 40 from the input terminal 40a, the input terminal 40b, and the input terminal 40c, respectively. In the determination circuit 40, the signal S02 is supplied to the first input terminal D of the D - FF circuit 41. The clock signal CLK is supplied to the second input terminal C of each of the D - FF circuit 41 and the D - FF circuit 43. The reset signal RST is supplied to the reset signal input terminal R of each of the D - FF circuit 41 and the D - FF circuit 43.

[0044] The D-FF circuit 41 receives signal S02 and clock signal CLK and supplies signal S03 from its first output terminal Q to the first input terminal D and first input terminal 45a of the D-FF circuit 43. The D-FF circuit 43 receives signal S03 and clock signal CLK and supplies signal S04 from its first output terminal Q to the second input terminal 45b. In other words, the D-FF circuit 41 operates as a shift register that delays the timing of signal S02. The D-FF circuit 43 operates as a shift register that delays the timing of signal S03. The NAND circuit 45 performs a NAND operation on the supplied signals S03 and S04 and supplies signal S05, which includes a signal level corresponding to the operation result, from its output terminal 45c to its output terminal 40d.

[0045] Signal S05 includes an H level signal level if the signal levels of signals S03 and S04 are L levels, and an L level signal level otherwise. For example, an H level of signal S05 corresponds to initialization being performed, and an L level corresponds to initialization not being performed. Signal S05 is supplied from the output terminal 40d to the input terminal 50b. That is, signal S05 is supplied from the decision circuit 40 to the decision circuit 50.

[0046] The determination circuit 50 is supplied with the clock signal CLK and the signal S05 from input terminals 50a and 50b, respectively. In the determination circuit 50, the clock signal CLK and the signal S05 are supplied to the counter 60 via input terminals 60a and 60b, respectively.

[0047] In counter 60, the clock signal CLK is supplied to the second input terminal CX of each D-FF circuit 601 to 603. Signal S05 is supplied to the reset signal input terminal R of each D-FF circuit 601 to 603. Each D-FF circuit 601 to 603 supplies signals S61 to S63 from its first output terminal Q to its output terminal 60c on each falling edge of the clock signal CLK.

[0048] D-FF circuits 601 to 603 continue counting until they receive the H-level signal S05, that is, while they are receiving the L-level signal S05. On the other hand, when D-FF circuits 601 to 603 receive the H-level signal S05, they reset the values ​​of each D-FF circuit 601 to 603. That is, the count of counter 60 returns to 0. Signals S61 to S63 supplied from each first output terminal Q of D-FF circuits 601 to 603 to the output terminal 60c are supplied from the output terminal 60c to the input terminal 70a as a single binary signal, signal S06. That is, signal S06 is supplied from counter 60 to the continuous match determination circuit 70.

[0049] The continuous match determination circuit 70 supplies a signal S07, which includes a signal level corresponding to the value obtained from the signal S06 supplied from the input terminal 70a, from its output terminal 70b to the second input terminal 80b. In other words, the signal S07 is supplied from the continuous match determination circuit 70 to the AND circuit 80.

[0050] The AND circuit 80 receives the clock signal CLK and signal S07 from the first input terminal 80a and the second input terminal 80b, respectively. The AND circuit 80 performs an AND operation on the supplied clock signal CLK and signal S07, and supplies a signal S08, which includes a signal level corresponding to the calculation result, from the output terminal 80c to the output terminal 50c.

[0051] According to the example of signal S07 described above, the L level corresponds to a state where the number of consecutive occurrences of the detection of magnetic flux density B has not reached the set number of occurrences. Therefore, the L level of signal S08 indicates that the number of consecutive occurrences of the detection of magnetic flux density B has not reached the set number of occurrences. On the other hand, the H level of signal S08 indicates that the number of consecutive occurrences of the detection of magnetic flux density B has reached the set number of occurrences. The signal S08 supplied to the output terminal 50c is supplied from the output terminal 50c to the output register 90, and more specifically, to the second input terminal C of the D-FF circuit of the output register 90.

[0052] The output register 90 toggles when the signal level of the supplied signal S08 is at a high level, and maintains its current state when the signal level of signal S08 is at a low level. That is, if the signal level of signal S08 is at a high level and the output signal So is at a low level, the output register 90 transitions the output signal So to a high level, and if the signal level of signal S08 is at a high level and the output signal So is at a high level, the output signal So transitions to a low level. The low and high levels of the output signal So correspond to the south pole detection state and the north pole detection state, respectively, as illustrated in Figure 4(B).

[0053] Next, the operating timing of the sensor device 10 and the semiconductor device 1 will be explained. Figure 5 is a timing diagram for the sensor device 10 and the semiconductor device 1. The timing diagram in Figure 5 has 13 graphs with a common axis where the horizontal axis represents time starting from t=0. For the 13 graphs included in Figure 5, the vertical axis represents, from top to bottom, magnetic flux density B, reset signal RST, signal S02, clock signal CLK, signal S03, signal S04, signal S05, signal S61, signal S62, signal S63, signal S07, signal S08, and output signal So.

[0054] Here, before explaining, we will refer to the value at t=0 as the initial value. We will also refer to the time from when the magnetic flux density B exceeds the operating point BOP until it actually transitions to the S-pole detection state, and the time from when the magnetic flux density B exceeds the return point BRP until it actually transitions to the S-pole detection state as the "delay time tD". Furthermore, in Figure 5, the magnetic flux density B, which is a function of time t, will be denoted as "B(t)". ​​As shown in Figure 5, we will explain the operation and timing of the Hall element 20, the binarization circuit 30, the determination circuit 40, the determination circuit 50, and the output register 90 using the case where the magnetic flux density B changes with the passage of time t as an example.

[0055] Since the initial value of the output signal So is at the H level, the sensor device 10 is in the N - pole detection state. Also, the initial value of the magnetic flux density B is a weak magnetic field on the N - pole side (BRP < B < 0). The initial values of the reset signal RST, signal S02, clock signal CLK, signal S03, signal S04, signal S05, signal S61, signal S62, signal S63, signal S07, and signal S08 are at the H level, L level, H level, L level, L level, H level, L level, L level, L level, L level, and L level, respectively.

[0056] As time elapses from t = 0 and before reaching t = t1, the reset signal RST transitions from the H level to the L level. At the falling edge, the reset of the D - FF circuits 41, 43 and the D - FF circuit in the output register 90 is released.

[0057] The magnetic flux density B continues to increase from the negative region (N - pole side) towards the positive region (S - pole side). At t = 1, the magnetic flux density B exceeds the operating point BOP. When the magnetic flux density B exceeds the operating point BOP upwards, at t = t2 which is the falling edge of the clock signal CLK immediately after that, the signal S02 transitions from the L level to the H level. When the signal S02 transitions to the H level, at t = t3 which is the rising edge of the clock signal CLK immediately after that, the signal S03 transitions from the L level to the H level. That is, the determination of two - consecutive detections in the determination circuit 40 is started.

[0058] When the signal S03 transitions to the H level while the signal S02 remains at the H level, at t = t4 which is the rising edge of the clock signal CLK immediately after that, the signal S04 transitions from the L level to the H level. Also, at t = t4, since both the signal S03 and the signal S04 are at the H level, the signal S05 transitions from the H level to the L level. That is, the L - level signal S05 is supplied from the determination circuit 40 to the determination circuit 50.

[0059] When signal S05 transitions to a low level, the counter 60, i.e., the D-FF circuits 601-603, starts counting at t=t5, which is the falling edge of the clock signal CLK immediately following. Specifically, at the falling edge of the clock signal CLK at t=t5, D-FF circuit 601 outputs signal S61, which corresponds to a signal level of 1. D-FF circuit 602 outputs signal S62, which corresponds to 0. D-FF circuit 603 outputs signal S63, which corresponds to 0. In other words, if the clock signal CLK is input to counter 60 while signal S05 remains at a low level, the counter 60 will increase its count each time the clock signal CLK falls.

[0060] At t=t6, when the clock signal CLK falls, signals S61, S62, and S63, each with a signal level corresponding to 1, are output from the D-FF circuits 601, 602, and 603, respectively. In other words, counter 60 outputs signal S06, which includes the signal level (111b) corresponding to the count value of 7. The inclusion of the signal level (111b) in signal S06 indicates that the number of times the magnetic flux density B has detected a strong magnetic field on the south pole side (B>BOP) has reached 8. Also, at t=t6, signal S07 transitions from L level to H level.

[0061] At t=t7, immediately after t=t6, when the clock signal CLK rises, signal S08 transitions from L level to H level, and output signal So transitions from H level to L level. That is, the sensor device 10 transitions from the N-pole detection state to the S-pole detection state. At t=t8, when the clock signal CLK is falling immediately after the pole detection state of the sensor device 10 has transitioned, signal S02 transitions from H level to L level. Also at t=t8, since signals S03 and S04 are both maintained at H level, signal S05 is maintained at L level. Since signal S05 is maintained at L level, the counting operation of counter 60 continues, and each of signals S61, S62, and S63 transitions from the signal level corresponding to 1 to the signal level corresponding to 0. Furthermore, at t=t8, signal S08 transitions from H level to L level.

[0062] Immediately after t = t8 when the clock signal CLK rises, at t = t9, the signal S03 transitions from the H level to the L level. On the other hand, the signal S04 maintains the H level. When the signal S03 transitions to the L level, the NAND operation result of the signals S03 and S04 becomes H, so the signal S05 transitions from the L level to the H level. When the signal S05 transitions to the H level, the D-FF circuits 601 to 603 are initialized.

[0063] At t = t10 which is when the clock signal CLK rises following the rising of the clock signal CLK at t = t9, the signal S04 transitions from the H level to the L level. When the signal S04 transitions to the L level, since the NAND operation result of the signals S03 and S04 maintains H, the signal S05 maintains the L level.

[0064] After t = t10, the magnetic flux density B decreases from a state where it exceeds the operating point BOP located in the positive region (S pole side). Then, at t = t11, it crosses the return point BRP located in the negative region (N pole side) from above to below. The magnetic flux density B after t = t11 transitions on the lower side of the return point BRP, that is, on the N pole detection side.

[0065] At t = t12 which is the falling edge of the clock signal CLK immediately after the magnetic flux density B crosses below the return point BRP, the signal S02 transitions from the L level to the H level. The operation from t = t12 to before t = t16 is the same as the operation from t = t2 to before t = t​​​As described above, according to the present embodiment of the invention, the register configuration for making N matching judgments comprises a first judgment circuit for making a first-stage judgment and a second judgment circuit for making a second-stage judgment. The first-stage judgment is to determine whether the detected state of the physical quantity matches for two consecutive times. The second-stage judgment is to determine whether the number of times the detected state of the physical quantity matches for two consecutive times is set to a certain number of consecutive matches. Therefore, if N is a power of 2, that is, using a natural number m, N=2 m If the result can be expressed in terms of times, a register for performing N matching checks can be constructed using 2+m flip-flop circuits.

[0067] On the other hand, in the conventional device described above, the register for performing N matching checks can be constructed using N-1 flip-flop circuits. Here, we will compare the invention according to this embodiment with the conventional device, taking the case m=3 as an example. m=3, i.e., N=2 3 In the case of =8, conventional devices require 7 (=8-1) flip-flop circuits. In contrast, the invention according to this embodiment can be constructed using 5 (=3+2) flip-flop circuits. Thus, according to the invention according to this embodiment, the number of circuits required for matching can be reduced while maintaining at least the number of matching judgments. Therefore, according to the invention according to this embodiment, the circuit occupied area can be reduced without impairing the reliability of the detection judgment result.

[0068] According to the invention of this embodiment, compared to conventional devices, the effect of reducing the circuit occupied area becomes more pronounced as the natural number N, which is the number of matching judgments, increases. To explain using the cases m=4 and m=5 as examples, in the case of m=4, that is, N=2 4 When m=16, conventional devices require 15 (=16-1) flip-flop circuits. On the other hand, the invention according to this embodiment can be constructed using 6 (=4+2) flip-flop circuits. When m=5, that is, N=2 5In the case of =32, a conventional device would require 31 (=32-1) flip-flop circuits. On the other hand, the invention according to this embodiment can be constructed using 7 (=5+2) flip-flop circuits.

[0069] According to the invention of this embodiment, when the same number of flip-flop circuits as a conventional device are used, the number of determinations can be increased compared to a conventional device. For example, when the sensor device 10 is configured using 7 flip-flop circuits, the number of determinations can be increased up to N=32.

[0070] It should be noted that the present invention is not limited to the embodiments described above, and in practice, it can be implemented in various forms other than those described above, and various omissions, additions, substitutions, or modifications can be made without departing from the spirit of the invention.

[0071] For example, logic circuits applied to the sensor device and semiconductor device according to this embodiment, such as the NAND circuit 45 or the AND circuit 80, are not limited to the exemplary configuration, as long as the output signal for the input signal, i.e., the result of the logical operation, is the same. In other words, the logic circuits applied to the sensor device and semiconductor device according to this embodiment are not limited to their internal configuration, as long as the result of the logical operation is the same.

[0072] In the embodiment described above, the continuous match determination circuit 70 was shown to be configured with a decoder, but it is not limited to this example. A natural number N greater than or equal to 2 is a power of 2, that is, a natural number m can be used to determine N=2 m If it can be expressed as such, the continuous match determination circuit 70 may be configured to have an AND circuit as a second AND circuit that includes m input terminals.

[0073] Since AND gates can be constructed more simply than decoders, a continuous match determination circuit 70 having AND gates instead of decoders can be constructed in a smaller area than a continuous match determination circuit 70 having a decoder. Also, N=2 mIf this condition holds, the natural number N becomes the maximum value that can be counted by m flip-flop circuits, thus maximizing the number of counts that a counter 60 of the same area can perform.

[0074] In the embodiments described above, a semiconductor device including a horizontal Hall element was explained, but the sensor element is not limited to a horizontal Hall element or a magnetic sensor. In this embodiment, the sensor element is not limited to a horizontal Hall element, but may be a vertical Hall element (vertical Hall element) that outputs a signal S01 corresponding to the magnetic flux density B in a direction parallel to the XY plane, such as the X direction. Furthermore, the sensor element is not limited to a Hall element, and may be composed of magnetic sensor elements other than Hall elements, such as a magnetoresistive (MR) element, a magnetic impedance (MI) element, or a fluxgate type sensor. In addition, the sensor element may be various sensor elements capable of detecting physical quantities other than magnetism, such as temperature, humidity, pressure, light such as ultraviolet rays, visible light, and infrared rays, and radiation.

[0075] These embodiments and their variations are included within the scope and essence of the invention, as well as within the scope of the invention and its equivalents as described in the claims. [Explanation of symbols]

[0076] 1 Semiconductor device 2 Semiconductor substrates 10 Sensor device 20 Hall elements (sensor elements) 30. Binary Conversion Circuit 40 Judgment circuit (first judgment circuit) 40a Input terminal 40d output terminal 41. First Flip-Flop Circuit 43. Second Flip-Flop Circuit 50 Judgment circuit (second judgment circuit) 60 counter 601-603 D-FF circuit (Flip-flop circuit) 70. Continuous Match Detection Circuit (Decoder, 2nd AND Circuit) 70a Input terminal 70b output end 80 AND gate (1st AND gate) 80a First input terminal 80b Second input terminal 80c output end 90 Output Registers

Claims

1. A sensor device that determines the detection of a physical quantity by detecting that physical quantity multiple times in succession, A first determination circuit determines whether the detection of the physical quantity has occurred twice in a row, including the current and the previous instance, based on the signal level of the detection result signal output from a sensor element that outputs a detection result signal representing the detection result of the physical quantity, and outputs an initialization signal including the signal level corresponding to the determination result. A second determination circuit has a counter that initializes the count if the initialization signal indicates that the physical quantity has not been detected twice in a row, and continues counting up to a set number of times if the physical quantity has been detected twice in a row, and outputs an output latch signal that includes a signal level corresponding to whether the count of the counter has continuously matched up to the set number of times, An output register that switches the signal level of the output signal supplied to the output terminal in accordance with the change in the signal level of the output latch signal, A sensor device characterized by comprising the following features.

2. The first determination circuit is, An input terminal to which a binarized signal is supplied according to the signal level of the detection result signal, The output terminal that outputs the initialization signal, A first flip-flop circuit includes a first input terminal connected to the input terminal of the first determination circuit, a second input terminal to which a clock signal is supplied, and an output terminal that outputs a signal including a signal level corresponding to the signal levels of the signals supplied to its own first and second input terminals. A second flip-flop circuit includes a first input terminal connected to the output terminal of the first flip-flop circuit, a second input terminal to which a clock signal is supplied, and an output terminal that outputs a signal including a signal level corresponding to the signal levels of the signals supplied to its own first and second input terminals. A logic circuit including a first input terminal connected to the output terminal of the first flip-flop circuit and the first input terminal of the second flip-flop circuit, a second input terminal connected to the output terminal of the second flip-flop circuit, and an output terminal connected to the output terminal of the first decision circuit, A sensor device according to claim 1, having the following features.

3. The second determination circuit described above is: The output terminal connected to the aforementioned output register, The counter includes an output terminal that outputs a signal representing the count obtained by counting the number of times the above two matches occurred consecutively, A continuous match determination circuit includes an input terminal connected to the output terminal of the counter, and an output terminal that outputs a match determination flag signal including a signal level corresponding to the determination result of whether or not a continuous match has occurred up to the number of times set based on the count, A first AND circuit includes a first input terminal to which a clock signal is supplied, a second input terminal connected to the output terminal of the continuous match determination circuit, and an output terminal connected to the output terminal of the second determination circuit, and supplies a signal including a signal level corresponding to the result of an AND operation between the supplied match determination flag signal and the clock signal as an output latch signal from the output terminal to the output terminal of the second determination circuit, A sensor device according to claim 1 or claim 2, having the following features.

4. The sensor device according to claim 3, wherein the continuous match determination circuit has a correspondence between the signal level of the match determination flag signal and the count number obtained from the signal representing the count number, and has a decoder that outputs the output latch signal including the signal level corresponding to the count number according to the correspondence.

5. If the number of times mentioned above is a power of 2 or more, The sensor device according to claim 3, wherein the continuous match determination circuit is connected to the output terminal of the counter and has a second AND circuit including the same number of input terminals as the number of bits of the counter and an output terminal that performs an AND operation on the signals supplied to each input terminal and outputs the result.

6. The counter has at least k flip-flop circuits, If k is a natural number and N is a natural number representing the number of times, The aforementioned k is calculated using the ceiling function ceiling(log2N), which represents the smallest integer greater than or equal to log2N for a real number log2N. k=ceiling(log2N) A sensor device according to any one of claims 1 to 5, represented by [the specified formula].

7. A semiconductor device comprising a semiconductor substrate on which a sensor device according to any one of claims 1 to 6 is formed.

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