Display device and method for manufacturing the same

Abstract

To provide a display that can improve reliability, and a method for manufacturing the same.SOLUTION: A display according to an embodiment comprises: a lower electrode; a rib having a pixel opening overlapping the lower electrode; a partition wall arranged on the rib; an upper electrode opposite to the lower electrode; and an organic layer located between the lower electrode and the upper electrode and emitting light according to the potential difference between the lower electrode and the upper electrode. The partition wall has an insulating first portion, a conductive second portion arranged on the first portion and in contact with the upper electrode, and a third portion arranged on the second portion. A lower end of the second portion projects in a width direction of the partition wall beyond the first portion. The third portion projects in the width direction beyond an upper end of the second portion.SELECTED DRAWING: Figure 5

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the same.

Background Art

[0002] In recent years, a display device applying an organic light-emitting diode (OLED) as a display element has been put into practical use. This display element includes a lower electrode, an organic layer covering the lower electrode, and an upper electrode covering the organic layer.

[0003] In manufacturing the display device as described above, a technique for suppressing a decrease in reliability is required.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0005] An object of the present invention is to provide a display device and a method for manufacturing the same that can improve reliability.

Means for Solving the Problems

[0006] A display device according to one embodiment includes a lower electrode, a rib having a pixel aperture that overlaps with the lower electrode, a partition wall disposed on the rib, an upper electrode facing the lower electrode, and an organic layer located between the lower electrode and the upper electrode that emits light in accordance with the potential difference between the lower electrode and the upper electrode. The partition wall has an insulating first portion, a conductive second portion disposed on the first portion and in contact with the upper electrode, and a third portion disposed on the second portion. The lower end of the second portion protrudes in the width direction of the partition wall more than the first portion, and the third portion protrudes in the width direction more than the upper end of the second portion.

[0007] In a method for manufacturing a display device according to one embodiment, a lower electrode is formed, a rib is formed covering at least a part of the lower electrode, a partition wall is formed on the rib having an insulating first portion, a conductive second portion disposed on the first portion, and a third portion disposed on the second portion, wherein the lower end of the second portion protrudes in the width direction more than the first portion, and the third portion protrudes in the width direction more than the upper end of the second portion, an organic layer is formed to cover the lower electrode through a pixel aperture provided in the rib, and an upper electrode is formed that covers the organic layer and is in contact with the second portion. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 shows an example of the configuration of a display device according to the first embodiment. [Figure 2] Figure 2 shows an example of the sub-pixel layout according to the first embodiment. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view of the partition wall according to the first embodiment. [Figure 5] Figure 5 is a schematic cross-sectional view of the rib, partition wall, organic layer, and upper electrode according to the first embodiment. [Figure 6A] Figure 6A shows the process of forming a partition wall according to the first embodiment. [Figure 6B] Figure 6B is a diagram showing the process following Figure 6A. [Figure 6C] Figure 6C is a diagram showing the process following Figure 6B. [Figure 6D] Figure 6D is a diagram showing the process following Figure 6C. [Figure 7A] Figure 7A is a diagram showing the process of forming a display element according to the first embodiment. [Figure 7B] Figure 7B is a diagram showing the process following Figure 7A. [Figure 7C] Figure 7C is a diagram showing the process following Figure 7B. [Figure 8] Figure 8 is a schematic cross-sectional view of a partition wall according to the second embodiment. [Figure 9A] Figure 9A is a diagram showing the process of forming a partition wall according to the second embodiment. [Figure 9B] Figure 9B is a diagram showing the process following Figure 9A. [Figure 9C] Figure 9C is a diagram showing the process following Figure 9B. [Figure 9D] Figure 9D is a diagram showing the process following Figure 9C. [Figure 9E] Figure 9E is a diagram showing the process following Figure 9D. [Figure 10] Figure 10 is a schematic cross-sectional view of a partition wall according to the third embodiment. [Figure 11A] Figure 11A is a diagram showing the process of forming a partition wall according to the third embodiment. [Figure 11B] Figure 11B is a diagram showing the process following Figure 11A. [Figure 11C] Figure 11C is a diagram showing the process following Figure 11B. [Figure 11D] Figure 11D is a diagram showing the process following Figure 11C. [Figure 12] Figure 12 is a schematic cross-sectional view of a partition wall according to the fourth embodiment. [Figure 13A] Figure 13A is a diagram showing the process of forming a partition wall according to the fourth embodiment. [Figure 13B]Figure 13B shows the process that follows Figure 13A. [Figure 13C] Figure 13C shows the process that follows Figure 13B. [Figure 13D] Figure 13D shows the process that follows Figure 13C. [Figure 13E] Figure 13E shows the process that follows Figure 13D. [Figure 14] Figure 14 is a schematic cross-sectional view of the partition wall according to the fifth embodiment. [Figure 15A] Figure 15A shows the process of forming a partition wall according to the fifth embodiment. [Figure 15B] Figure 15B shows the process that follows Figure 15A. [Figure 15C] Figure 15C shows the process that follows Figure 15B. [Figure 15D] Figure 15D shows the process that follows Figure 15C. [Figure 16] Figure 16 is a schematic cross-sectional view of the partition wall according to the sixth embodiment. [Figure 17A] Figure 17A shows the process of forming a partition wall according to the sixth embodiment. [Figure 17B] Figure 17B shows the process that follows Figure 17A. [Figure 17C] Figure 17C shows the process that follows Figure 17B. [Figure 17D] Figure 17D shows the process that follows Figure 17C. [Figure 17E] Figure 17E shows the process that follows Figure 17D. [Figure 18] Figure 18 is a schematic cross-sectional view of the partition wall according to the seventh embodiment. [Figure 19A] Figure 19A shows the process of forming a partition wall according to the seventh embodiment. [Figure 19B] Figure 19B shows the process that follows Figure 19A. [Figure 19C] Figure 19C shows the process that follows Figure 19B. [Figure 19D] Figure 19D shows the process that follows Figure 19C. [Figure 20] Figure 20 is a schematic cross-sectional view of the partition wall according to the eighth embodiment. [Figure 21A] Figure 21A shows the process of forming a partition wall according to the eighth embodiment. [Figure 21B] Figure 21B shows the process that follows Figure 21A. [Figure 21C] Figure 21C shows the process that follows Figure 21B. [Figure 21D] Figure 21D shows the process that follows Figure 21C. [Figure 21E] Figure 21E shows the process that follows Figure 21D. [Figure 22] Figure 22 is a schematic cross-sectional view of the partition wall according to the ninth embodiment. [Figure 23A] Figure 23A shows the process of forming a partition wall according to the ninth embodiment. [Figure 23B] Figure 23B shows the process that follows Figure 23A. [Figure 23C] Figure 23C shows the process that follows Figure 23B. [Figure 23D] Figure 23D shows the process that follows Figure 23C. [Figure 23E] Figure 23E shows the process that follows Figure 23D. [Modes for carrying out the invention]

[0009] Several embodiments will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0010] Furthermore, the drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis will be referred to as the first direction, the direction along the Y axis as the second direction, and the direction along the Z axis as the third direction. Viewing the various elements parallel to the third direction Z is called a plan view.

[0011] Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted in televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and the like.

[0012] [First Embodiment] Figure 1 shows an example configuration of a display device DSP according to the first embodiment. The display device DSP has a display area DA for displaying an image and a peripheral area SA around the display area DA, on an insulating substrate 10. The substrate 10 may be glass or a flexible resin film.

[0013] In this embodiment, the shape of the substrate 10 in plan view is rectangular. However, the shape of the substrate 10 in plan view is not limited to a rectangle; it may be a square, a circle, an ellipse, or other shape.

[0014] The display area DA comprises multiple pixels PX arranged in a matrix in the first direction X and the second direction Y. Each pixel PX includes multiple sub-pixels SP. In one example, pixel PX includes a first sub-pixel SP1 which is red, a second sub-pixel SP2 which is green, and a third sub-pixel SP3 which is blue. Pixel PX may also include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of SP1, SP2, or SP3.

[0015] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0016] The gate electrode of pixel switch 2 is connected to the scan line GL. One of the source and drain electrodes of pixel switch 2 is connected to the signal line SL, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to the power line PL and capacitor 4, and the other is connected to display element DE. Display element DE is an organic light-emitting diode (OLED) as a light-emitting element.

[0017] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0018] Figure 2 shows an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, the first sub-pixel SP1 and the third sub-pixel SP3 are aligned in the first direction X. The second sub-pixel SP2 and the third sub-pixel SP3 are also aligned in the first direction X. Furthermore, the first sub-pixel SP1 and the second sub-pixel SP2 are aligned in the second direction Y.

[0019] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP1 and SP2 are alternately arranged in the second direction Y, and columns in which multiple third sub-pixels SP3 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X.

[0020] Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2. Another example is that the sub-pixels SP1, SP2, and SP3 in each pixel PX may be arranged sequentially in the first direction X.

[0021] The display area DA has ribs 5 and partition walls 6. Ribs 5 have a first pixel aperture AP1 in the first sub-pixel SP1, a second pixel aperture AP2 in the second sub-pixel SP2, and a third pixel aperture AP3 in the third sub-pixel SP3. In the example in Figure 2, the second pixel aperture AP2 is larger than the first pixel aperture AP1, and the third pixel aperture AP3 is larger than the second pixel aperture AP2.

[0022] The partition wall 6 is positioned at the boundary between adjacent subpixels SP and overlaps with the rib 5 in a plan view. The partition wall 6 has a plurality of first partition walls 6x extending in the first direction X and a plurality of second partition walls 6y extending in the second direction Y. The plurality of first partition walls 6x are positioned between adjacent pixel apertures AP1 and AP2 in the second direction Y, and between two adjacent third pixel apertures AP3 in the second direction Y. The second partition walls 6y are positioned between adjacent pixel apertures AP1 and AP3 in the first direction X, and between adjacent pixel apertures AP2 and AP3 in the first direction X.

[0023] In the example shown in Figure 2, the first partition wall 6x and the second partition wall 6y are connected to each other. As a result, the partition wall 6 as a whole forms a grid surrounding the pixel apertures AP1, AP2, and AP3. It can also be said that the partition wall 6, like the rib 5, has apertures in the sub-pixels SP1, SP2, and SP3.

[0024] The first sub-pixel SP1 comprises a first lower electrode LE1, a first upper electrode UE1, and a first organic layer OR1, which overlap with the first pixel aperture AP1. The second sub-pixel SP2 comprises a second lower electrode LE2, a second upper electrode UE2, and a second organic layer OR2, which overlap with the second pixel aperture AP2. The third sub-pixel SP3 comprises a third lower electrode LE3, a third upper electrode UE3, and a third organic layer OR3, which overlap with the third pixel aperture AP3.

[0025] The first lower electrode LE1, the first upper electrode UE1, and the first organic layer OR1 constitute the first display element DE1 of the first sub-pixel SP1. The second lower electrode LE2, the second upper electrode UE2, and the second organic layer OR2 constitute the second display element DE2 of the second sub-pixel SP2. The third lower electrode LE3, the third upper electrode UE3, and the third organic layer OR3 constitute the third display element DE3 of the third sub-pixel SP3. Display elements DE1, DE2, and DE3 may include a cap layer, as described later.

[0026] For example, the first display element DE1 emits light in the red wavelength range, the second display element DE2 emits light in the green wavelength range, and the third display element DE3 emits light in the blue wavelength range.

[0027] The first lower electrode LE1 is connected to the pixel circuit 1 of the first sub-pixel SP1 (see Figure 1) through the first contact hole CH1. The second lower electrode LE2 is connected to the pixel circuit 1 of the second sub-pixel SP2 through the second contact hole CH2. The third lower electrode LE3 is connected to the pixel circuit 1 of the third sub-pixel SP3 through the third contact hole CH3.

[0028] In the example in Figure 2, the contact holes CH1 and CH2 completely overlap with the first partition wall 6x between adjacent pixel apertures AP1 and AP2 in the second direction Y. Similarly, the third contact hole CH3 completely overlaps with the first partition wall 6x between two adjacent third pixel apertures AP3 in the second direction Y. In another example, at least a portion of the contact holes CH1, CH2, and CH3 may not overlap with the first partition wall 6x.

[0029] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1.

[0030] The circuit layer 11 is covered by an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11. Although not shown in the cross-section of Figure 3, the aforementioned contact holes CH1, CH2, and CH3 are all provided in the organic insulating layer 12.

[0031] The lower electrodes LE1, LE2, and LE3 are positioned on top of the organic insulating layer 12. The ribs 5 are positioned on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the ribs 5.

[0032] The bulkhead 6 includes a first portion 61 positioned on the rib 5, a second portion 62 positioned on the first portion 61, and a third portion 63 positioned on the second portion 62.

[0033] The first organic layer OR1 covers the first lower electrode LE1 through the first pixel aperture AP1. The first upper electrode UE1 covers the first organic layer OR1 and faces the first lower electrode LE1. The second organic layer OR2 covers the second lower electrode LE2 through the second pixel aperture AP2. The second upper electrode UE2 covers the second organic layer OR2 and faces the second lower electrode LE2. The third organic layer OR3 covers the third lower electrode LE3 through the third pixel aperture AP3. The third upper electrode UE3 covers the third organic layer OR3 and faces the third lower electrode LE3.

[0034] In the example shown in Figure 3, the first cap layer CP1 is placed on the first upper electrode UE1, the second cap layer CP2 is placed on the second upper electrode UE2, and the third cap layer CP3 is placed on the third upper electrode UE3. The cap layers CP1, CP2, and CP3 adjust the optical properties of the light emitted by the organic layers OR1, OR2, and OR3, respectively.

[0035] A portion of the first organic layer OR1, the first upper electrode UE1, and the first cap layer CP1 is located above the third portion 63. This portion is separated from the other portions of the first organic layer OR1, the first upper electrode UE1, and the first cap layer CP1. Similarly, a portion of the second organic layer OR2, the second upper electrode UE2, and the second cap layer CP2 is located above the third portion 63, and this portion is separated from the other portions of the second organic layer OR2, the second upper electrode UE2, and the second cap layer CP2. Furthermore, a portion of the third organic layer OR3, the third upper electrode UE3, and the third cap layer CP3 is located above the third portion 63, and this portion is separated from the other portions of the third organic layer OR3, the third upper electrode UE3, and the third cap layer CP3.

[0036] The first sub-pixel SP1 is covered with the first sealing layer SE1, the second sub-pixel SP2 is covered with the second sealing layer SE2, and the third sub-pixel SP3 is covered with the third sealing layer SE3. The first sealing layer SE1 continuously covers the first cap layer CP1 and the partition wall 6 surrounding the first sub-pixel SP1. The second sealing layer SE2 continuously covers the second cap layer CP2 and the partition wall 6 surrounding the second sub-pixel SP2. The third sealing layer SE3 continuously covers the third cap layer CP3 and the partition wall 6 surrounding the third sub-pixel SP3.

[0037] The sealing layers SE1, SE2, and SE3 are covered by a resin layer 13. The resin layer 13 is covered by a sealing layer 14. Furthermore, the sealing layer 14 is covered by a resin layer 15.

[0038] The organic insulating layer 12 and the resin layers 13 and 15 are formed from organic materials. The sealing layers 14, SE1, SE2, and SE3 are formed from inorganic materials such as silicon nitride (SiN), silicon oxide (SiO), or silicon oxynitride (SiON).

[0039] The lower electrodes LE1, LE2, and LE3 each have an intermediate layer formed of, for example, silver (Ag), and a pair of conductive oxide layers covering the upper and lower surfaces of this intermediate layer, respectively. Each conductive oxide layer can be formed of a transparent conductive oxide such as ITO (IndiumTin Oxide), IZO (IndiumZinc Oxide), or IGZO (IndiumGalliumZinc Oxide). The upper electrodes UE1, UE2, and UE3 are formed of a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0040] As will be explained in more detail later, the organic layers OR1, OR2, and OR3 have a layered structure including a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer.

[0041] The cap layers CP1, CP2, and CP3 are formed, for example, by a multilayer structure of multiple transparent thin films. The multilayer structure may include thin films formed from inorganic materials and thin films formed from organic materials. These multiple thin films have different refractive indices. The materials of the thin films constituting the multilayer structure are different from the materials of the upper electrodes UE1, UE2, and UE3, and also different from the materials of the sealing layers SE1, SE2, and SE3. Note that the cap layers CP1, CP2, and CP3 may be omitted.

[0042] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the side surface of the second portion 62. Pixel voltages are supplied to the lower electrodes LE1, LE2, and LE3 through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0043] When a potential difference is formed between the first lower electrode LE1 and the first upper electrode UE1, the light-emitting layer of the first organic layer OR1 emits light in the red wavelength range. When a potential difference is formed between the second lower electrode LE2 and the second upper electrode UE2, the light-emitting layer of the second organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the third lower electrode LE3 and the third upper electrode UE3, the light-emitting layer of the third organic layer OR3 emits light in the blue wavelength range.

[0044] Figure 4 is a schematic cross-sectional view of the partition wall 6 according to this embodiment. In this figure, the partition wall 6 and rib 5 are shown, and other elements are omitted. The width direction WD in the figure is the direction perpendicular to the extension direction of the partition wall 6 and the third direction Z. For example, the width direction WD of the first partition wall 6x shown in Figure 2 corresponds to the second direction Y, and the width direction WD of the second partition wall 6y corresponds to the first direction X. Both the first partition wall 6x and the second partition wall 6y have the cross-sectional structure shown in Figure 4.

[0045] The first portion 61 has a pair of ends 61a in the width direction WD. The second portion 62 has a lower end 62a (bottom surface) that contacts the first portion 61, an upper end 62b (top surface) that contacts the third portion 63, and a pair of sides 62c in the width direction WD. The third portion 63 has a pair of ends 63a in the width direction WD.

[0046] In the example shown in Figure 4, the second portion 62 has a shape that tapers from the lower end 62a to the upper end 62b, causing the side surface 62c to be inclined with respect to the third direction Z. In another example, the side surface 62c may be substantially parallel to the third direction Z.

[0047] The width of the lower end 62a is greater than the width of the first portion 61. As a result, the lower end 62a protrudes more on both sides in the width direction WD than the first portion 61. Also, the width of the upper end 62b is smaller than the width of the third portion 63. As a result, the third portion 63 protrudes more on both sides in the width direction WD than the upper end 62b.

[0048] In other words, in this embodiment, a pair of first overhang structures OH1 are formed by the lower end 62a, and a pair of second overhang structures OH2 are formed by the third portion 63. Near each side surface 62c, a gap GP is formed between the lower end 62a and the rib 5.

[0049] Figure 5 is a schematic cross-sectional view of the rib 5, partition wall 6, first organic layer OR1, and first upper electrode UE1. Although omitted in Figure 5, a portion of the first organic layer OR1 and the first upper electrode UE1 are positioned on the third portion 63 (see Figure 3).

[0050] In the example shown in Figure 5, the first organic layer OR1 has a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, an emission layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL, all stacked in the third direction Z. Of these layers, the hole transport layer HTL is the thickest. The thickness of the hole transport layer HTL accounts for more than half of the total thickness of the first organic layer OR1, for example.

[0051] The hole injection layer (HIL) covers the rib 5 and also covers the first lower electrode LE1 through the first pixel aperture AP1 shown in Figures 2 and 3. The thicknesses of the hole injection layer (HIL), hole transport layer (HTL), electron blocking layer (EBL), light emission layer (EML), hole blocking layer (HBL), electron transport layer (ETL), and electron injection layer (EIL) near the partition wall 6 decrease as they approach the side surface 62c.

[0052] The hole injection layer HIL is not in contact with the partition wall 6. Specifically, the hole injection layer HIL is spaced apart from the lower end 62a and side surface 62c of the first portion 61 and the second portion 62. A thin film of the same material as the hole injection layer HIL may be attached to the side surface 62c near the lower end 62a, and this thin film may be spaced apart from the hole injection layer HIL.

[0053] In the example of FIG. 5, a part of the hole injection layer HIL and the hole transport layer HTL has entered the gap GP. Further, the entrance of the gap GP (directly below the corner formed by the lower end 62a and the side surface 62c) is blocked by a layer (such as the hole transport layer HTL) disposed above the hole injection layer HIL among the layers of the first organic layer OR1. The first upper electrode UE1 continuously covers a part of the first organic layer OR1 and the side surface 62c.

[0054] The first portion 61 has insulating properties. The second portion 62 and the third portion 63 have conductive properties. However, the third portion 63 may have insulating properties. In order to exhibit etching selectivity in the manufacturing process described later, the first portion 61 and the rib 5 are formed of different types of insulating inorganic materials. In the present embodiment, the first portion 61 is formed of silicon nitride, the second portion 62 is formed of aluminum (Al), and the third portion 63 is formed of titanium (Ti). Also, the rib 5 is formed of silicon oxide or silicon oxynitride.

[0055] The thickness T1 of the first portion 61 is sufficiently smaller than the thickness T2 of the second portion 62 (T1 < T2). The thickness T3 of the third portion 63 is larger than the thickness T1 and smaller than the thickness T2 (T1 < T3 < T2). As an example, the thickness T1 is 20 nm, the thickness T2 is 500 nm, and the thickness T3 is 100 nm. Note that the thickness T1 corresponds to the height of the gap GP.

[0056] The thickness T1 is larger than the thickness T4 of the hole injection layer HIL (T4 < T1). The thickness T4 is the thickness of the hole injection layer HIL excluding the portion that becomes thinner in the vicinity of the partition wall 6. The thickness T4 can also be said to be the thickness of the portion of the hole injection layer HIL that covers the first lower electrode LE1.

[0057] In the example of FIG. 5, the length D1 by which the lower end 62a of the second portion 62 protrudes from the end 61a of the first portion 61 is smaller than the length D2 by which the third portion 63 protrudes from the upper end 62b of the second portion 62 (D1 < D2). However, this is not limited to this example, and the length D1 may be equal to or greater than the length D2. The length D1 is preferably at least twice the thickness T1 (2 × T1 < D1).

[0058] The organic layers OR2, OR3 and the upper electrodes UE2, UE3 have the same structure as the first organic layer OR1 and the first upper electrode UE1 shown in FIG. 5. However, the thicknesses of the respective layers included in the organic layers OR1, OR2, OR3 may be different.

[0059] Next, a method for manufacturing the display device DSP will be described. FIGS. 6A to 6D are schematic cross-sectional views showing the steps mainly for forming the partition wall 6 in the method for manufacturing the display device DSP. First, a circuit layer 11, an organic insulating layer 12, lower electrodes LE1, LE2, LE3 and ribs 5 are sequentially formed above the substrate 10.

[0060] Next, as shown in FIG. 6A, a first layer 61s serving as a base of the first portion 61, a second layer 62s serving as a base of the second portion 62, and a third layer 63s serving as a base of the third portion 63 are sequentially formed on the rib 5. The first layer 61s, the second layer 62s and the third layer 63s are formed at least over the entire display area DA. Further, a resist R1 is formed on the third layer 63s. The resist R1 is patterned in the shape of the partition wall 6 in a plan view.

[0061] Next, anisotropic dry etching using, for example, a chlorine-based etching gas is performed with the resist R1 as a mask, and the portion of the third layer 63s exposed from the resist R1 is removed as shown in FIG. 6B. Thereby, the third portion 63 having the shape shown in FIG. 4 is formed. In this dry etching, the thickness of the portion of the second layer 62s exposed from the resist R1 is also reduced.

[0062] Next, isotropic wet etching is performed, and as shown in Figure 6C, all portions of the second layer 62s exposed from the resist R1 are removed. In this wet etching, the sides of the second layer 62s are also eroded, reducing the width of the second layer 62s. As a result, the second portion 62 and the second overhang structure OH2 with the shape shown in Figure 4 are formed.

[0063] Subsequently, isotropic dry etching is performed using a fluorine-based etching gas, and as shown in Figure 6D, the portion of the first layer 61s exposed from the second portion 62 is removed. In this dry etching, the width of the first layer 61s is reduced below the second portion 62, and the first portion 61 and the first overhang structure OH1 with the shape shown in Figure 4 are formed. As described above, if the rib 5 is formed of silicon oxide or silicon oxynitride, damage to the rib 5 in this dry etching can be suppressed.

[0064] Furthermore, the processing method for the first layer 61s is not limited to isotropic dry etching using a fluorine-based etching gas. The processing of the first layer 61s may be carried out by other methods, such as wet etching using an etching solution containing dilute hydrofluoric acid (HF).

[0065] For example, the pixel apertures AP1, AP2, and AP3 of the rib 5 are formed by dry etching after the first layer 61s is formed but before the second layer 62s is formed. In this dry etching, the first layer 61s and the rib 5 may be eroded simultaneously. As another example, the pixel apertures AP1, AP2, and AP3 may be formed after the partition wall 6.

[0066] After the first part 61, the second part 62, and the third part 63 are formed, the partition wall 6 is completed by removing the resist R1. Subsequently, a process is carried out to form the display elements DE1, DE2, and DE3 on the sub-pixels SP1, SP2, and SP3.

[0067] Figures 7A to 7C are schematic cross-sectional views showing the process for manufacturing a display device DSP, mainly for forming the display elements DE1, DE2, and DE3. Here, as an example, we assume that the third display element DE3 is formed first, the second display element DE2 is formed next, and the first display element DE1 is formed last. However, the formation order of the display elements DE1, DE2, and DE3 is not limited to this example.

[0068] First, as shown in Figure 7A, the third organic layer OR3, the third upper electrode UE3, the third cap layer CP3, and the third sealing layer SE3 are sequentially formed on the entire substrate by vapor deposition. At this time, the second overhang structure OH2 of the partition wall 6 separates the third organic layer OR3, the third upper electrode UE3, and the third cap layer CP3 formed on each sub-pixel SP1, SP2, and SP3. The third sealing layer SE3 continuously covers the third cap layer CP3 and the partition wall 6.

[0069] The process for forming the third organic layer OR3 includes the sequential deposition of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emission layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). Of these layers constituting the third organic layer OR3, the hole transport layer (HTL), which is formed after the hole injection layer (HIL), blocks the entrance to the gap GP shown in Figure 5.

[0070] Next, as shown in Figure 7B, a resist R2 is formed on the third sealing layer SE3. The resist R2 is patterned to overlap with the third subpixel SP3. The resist R2 is also located directly above the portion of the third organic layer OR3, the third upper electrode UE3, and the third cap layer CP3 on the partition wall 6 surrounding the third subpixel SP3 that is closest to the third subpixel SP3.

[0071] Furthermore, etching using the resist R2 as a mask removes the portions of the third organic layer OR3, third upper electrode UE3, third cap layer CP3, and third sealing layer SE3 that are exposed from the resist R2, as shown in Figure 7C. As a result, a substrate is obtained in which a third display element DE3, including the third lower electrode LE3, third organic layer OR3, third upper electrode UE3, and third cap layer CP3, is formed on the third sub-pixel SP3, while no display elements are formed on the sub-pixels SP1 and SP2.

[0072] Subsequently, the resist R2 is removed, and the following steps are performed in sequence: forming the second display element DE2 on the second sub-pixel SP2, and forming the first display element DE1 on the first sub-pixel SP1. These steps are the same as those for forming the third display element DE3.

[0073] After forming the display elements DE1, DE2, and DE3, the process of forming the resin layer 13, the sealing layer 14, and the resin layer 15 is carried out. This completes the display device DSP with the structure shown in Figure 3.

[0074] In this embodiment, as shown in Figure 4, by providing a partition wall 6 having a first portion 61, a second portion 62, and a third portion 63 at the boundary between sub-pixels SP1, SP2, and SP3, various desirable effects can be obtained to improve the reliability of the display device DSP.

[0075] For example, the peripheral edges of the organic layers OR1, OR2, OR3, the upper electrodes UE1, UE2, UE3, and the cap layers CP1, CP2, CP3 are separated by the second overhang structure OH2, in which the third portion 63 protrudes beyond the upper end 62b of the second portion 62. As a result, when the display elements DE1, DE2, DE3 are formed using the method shown in Figures 7A to 7C, the sealing layers SE1, SE2, SE3 can effectively seal the display elements DE1, DE2, DE3. Consequently, the intrusion and diffusion of moisture into the display elements DE1, DE2, DE3 are suppressed.

[0076] Furthermore, if the hole injection layers HIL of the organic layers OR1, OR2, OR3 were to come into contact with the conductive second portion 62, a leakage current could flow from the lower electrodes LE1, LE2, LE3 to the second portion 62 via the hole injection layers HIL without passing through layers such as the light-emitting layer EML, potentially causing display defects. In contrast, in this embodiment, the partition wall 6 has a first overhang structure OH1 in which the lower end 62a of the second portion 62 protrudes more than the first portion 61. That is, because the lower part of the partition wall 6, to which the hole injection layers HIL are likely to adhere, is recessed in the width direction WD, the hole injection layers HIL are less likely to come into contact with the partition wall 6 during deposition. Even if the material of the hole injection layers HIL comes into contact with the side surface 62c of the second portion 62, that portion is separated from the display elements DE1, DE2, DE3 by the first overhang structure OH1. These factors prevent the hole injection layer HIL from contacting the partition wall 6, and as a result, display malfunctions caused by leakage current can be suppressed.

[0077] As described above, when the thickness T1 of the first portion 61 is greater than the thickness T4 of the hole injection layer HIL, contact between the hole injection layer HIL and the second portion 62 can be more reliably suppressed.

[0078] As in this embodiment, if the first portion 61 is insulating, even if the hole injection layer HIL enters the gap GP and comes into contact with the first portion 61, the second portion 62 and the hole injection layer HIL will not be electrically conductive.

[0079] As shown in Figure 5, when the entrance to the gap GP is blocked by the hole transport layer HTL or the like, the separation of the upper electrodes UE1, UE2, and UE3 by the first overhang structure OH1 can be suppressed. This enables good power supply from the partition wall 6 to the upper electrodes UE1, UE2, and UE3.

[0080] Even if the partition wall 6 does not have the first overhang structure OH1, contact between the hole injection layer HIL and the second part 62 can be suppressed by appropriately adjusting the thickness T2 of the second part 62 and the protruding length D2 of the third part 63. However, in this case, precise control of the thickness T2 and length D2 is required when manufacturing the display device DSP.

[0081] In contrast, with the configuration of the partition wall 6 according to this embodiment, the function of suppressing contact between the hole injection layer HIL and the second portion 62 can be entrusted to the first overhang structure OH1. As a result, the tolerance range for the dimensions of thickness T2 and length D2 is increased, and the restrictions on variations in the shape of the partition wall 6 during manufacturing can be relaxed.

[0082] The configuration of the partition wall 6 having the first overhang structure OH1 and the second overhang structure OH2, and the process for forming the partition wall 6, are not limited to those disclosed in this embodiment. The second to ninth embodiments described below disclose other examples of the configuration of the partition wall 6 and the process for forming the partition wall 6. Configurations not specifically mentioned in these embodiments can be the same as those in the first embodiment.

[0083] [Second Embodiment] Figure 8 is a schematic cross-sectional view of the partition wall 6 according to the second embodiment. The partition wall 6 according to this embodiment has a first portion 61, a second portion 62, and a third portion 63, similar to the first embodiment. However, in this embodiment, the third portion 63 includes a titanium layer 631 formed of titanium and a conductive oxide layer 632 formed of a conductive oxide such as ITO, IZO, and IGZO. For example, as in the first embodiment, the first portion 61 is formed of silicon nitride, the second portion 62 is formed of aluminum, and the rib 5 is formed of silicon oxide or silicon oxynitride.

[0084] The titanium layer 631 is positioned on the upper end 62b of the second portion 62. The conductive oxide layer 632 is positioned on top of the titanium layer 631. The conductive oxide layer 632 is formed to be thinner than the titanium layer 631.

[0085] For example, the thickness of the first part 61 is 20 nm, the thickness of the second part 62 is 500 nm, the thickness of the titanium layer 631 is 100 nm, and the thickness of the conductive oxide layer 632 is 50 nm.

[0086] Figures 9A to 9E show an example of the process for forming the partition wall 6 according to this embodiment. First, as shown in Figure 9A, a first layer 61s which forms the basis of the first portion 61, a second layer 62s which forms the basis of the second portion 62, a third layer 63s which forms the basis of the third portion 63, and a resist R1 are formed sequentially on the rib 5. The third layer 63s includes a titanium layer 631s and a conductive oxide layer 632s.

[0087] Next, wet etching is performed using the resist R1 as a mask, and as shown in Figure 9B, the portion of the conductive oxide layer 632s exposed from the resist R1 is removed. This forms a conductive oxide layer 632 with the shape shown in Figure 8.

[0088] Furthermore, anisotropic dry etching is performed using, for example, a chlorine-based etching gas with the resist R1 as a mask, and the portion of the titanium layer 631s exposed from the resist R1 is removed, as shown in Figure 9C. This forms a titanium layer 631 with the shape shown in Figure 8. In this dry etching process, the thickness of the portion of the second layer 62s exposed from the resist R1 is also reduced. In the example in Figure 9C, the width of the resist R1 is slightly reduced in this dry etching process.

[0089] Next, isotropic wet etching is performed, and as shown in Figure 9D, all portions of the second layer 62s exposed from the resist R1 are removed. In this wet etching, the sides of the second layer 62s are also eroded, reducing the width of the second layer 62s. As a result, the second portion 62 and the second overhang structure OH2 with the shape shown in Figure 8 are formed.

[0090] Subsequently, isotropic dry etching is performed using a fluorine-based etching gas, and as shown in Figure 9E, the portion of the first layer 61s exposed from the second portion 62 is removed. In this dry etching, the width of the first layer 61s is reduced below the second portion 62, and the first portion 61 and the first overhang structure OH1 with the shape shown in Figure 8 are formed. The first layer 61s may also be processed by other methods, such as wet etching using an etching solution containing dilute hydrofluoric acid. After the first portion 61, the second portion 62, and the third portion 63 are formed in this way, the partition wall 6 is completed by removing the resist R1.

[0091] In the configuration of the partition wall 6 according to this embodiment, a stable shape of the second overhang structure OH2 can be formed. That is, even if the width of the resist R1 is reduced as shown in Figure 9C when etching the titanium layer 631s and the second layer 62s, the conductive oxide layer 632 acts as a mask. As a result, the titanium layer 631 and the second portion 62 can be formed with high precision, and the shape of the second overhang structure OH2 is stabilized.

[0092] [Third Embodiment] Figure 10 is a schematic cross-sectional view of the partition wall 6 according to the third embodiment. The partition wall 6 according to this embodiment has a first portion 61, a second portion 62, and a third portion 63, similar to the first embodiment. However, in this embodiment, the second portion 62 includes an aluminum alloy layer 621 formed of an aluminum alloy and an aluminum layer 622 formed of aluminum (pure aluminum). As the material for the aluminum alloy layer 621, for example, an aluminum-neodymium alloy (AlNd) or an aluminum-silicon alloy (AlSi) can be used.

[0093] The aluminum alloy layer 621 is placed on top of the first portion 61. The aluminum layer 622 is placed on top of the aluminum alloy layer 621. The aluminum alloy layer 621 is formed to be thinner than the aluminum layer 622.

[0094] For example, as in the first embodiment, the first portion 61 is made of silicon nitride, the third portion 63 is made of titanium, and the rib 5 is made of silicon oxide or silicon oxynitride.

[0095] For example, the thickness of the first part 61 is 20 nm, the thickness of the aluminum alloy layer 621 is 50 nm, the thickness of the aluminum layer 622 is 450 nm, and the thickness of the third part 63 is 100 nm.

[0096] Figures 11A to 11D show an example of the process for forming the partition wall 6 according to this embodiment. First, as shown in Figure 11A, a first layer 61s which forms the basis of the first portion 61, a second layer 62s which forms the basis of the second portion 62, a third layer 63s which forms the basis of the third portion 63, and a resist R1 are formed sequentially on the rib 5. The second layer 62s includes an aluminum alloy layer 621s and an aluminum layer 622s.

[0097] Next, anisotropic dry etching is performed using, for example, a chlorine-based etching gas with the resist R1 as a mask, and the portion of the third layer 63s exposed from the resist R1 is removed, as shown in Figure 11B. This forms the third portion 63 with the shape shown in Figure 10. In this dry etching, the portion of the aluminum layer 622s exposed from the resist R1 is also removed. The aluminum alloy layer 621s functions as an etching stopper for this dry etching.

[0098] Next, isotropic wet etching is performed, and as shown in Figure 11C, the portion of the aluminum alloy layer 621s exposed from the resist R1 is removed. In this wet etching, the sides of the aluminum alloy layer 621s and the aluminum layer 622s are also eroded, reducing their width. As a result, a second portion 62 including the aluminum alloy layer 621 and the aluminum layer 622 with the shape shown in Figure 10, and a second overhang structure OH2 are formed.

[0099] Subsequently, isotropic dry etching is performed using a fluorine-based etching gas, and the portion of the first layer 61s exposed from the second portion 62 is removed, as shown in Figure 11D. In this dry etching, the width of the first layer 61s is reduced below the second portion 62, and the first portion 61 and the first overhang structure OH1 with the shape shown in Figure 10 are formed. The first layer 61s may also be processed by other methods, such as wet etching using an etching solution containing dilute hydrofluoric acid. After the first portion 61, the second portion 62, and the third portion 63 are formed in this way, the partition wall 6 is completed by removing the resist R1.

[0100] In the configuration of the partition wall 6 according to this embodiment, the aluminum alloy layer 621s acts as an etching stopper against dry etching of the third layer 63s and the aluminum layer 622s, thereby suppressing the erosion of the first layer 61s and the rib 5 by dry etching.

[0101] [Fourth Embodiment] Figure 12 is a schematic cross-sectional view of the partition wall 6 according to the fourth embodiment. In this partition wall 6, as in the second embodiment, the third portion 63 includes a titanium layer 631 and a conductive oxide layer 632, and as in the third embodiment, the second portion 62 includes an aluminum alloy layer 621 and an aluminum layer 622. For example, as in the first embodiment, the first portion 61 is formed of silicon nitride, and the rib 5 is formed of silicon oxide or silicon oxynitride.

[0102] For example, the thickness of the first section 61 is 20 nm, the thickness of the aluminum alloy layer 621 is 50 nm, the thickness of the aluminum layer 622 is 450 nm, the thickness of the titanium layer 631 is 100 nm, and the thickness of the conductive oxide layer 632 is 50 nm.

[0103] Figures 13A to 13E show an example of the process for forming the partition wall 6 according to this embodiment. First, as shown in Figure 13A, a first layer 61s which forms the basis of the first portion 61, a second layer 62s which forms the basis of the second portion 62, a third layer 63s which forms the basis of the third portion 63, and a resist R1 are formed sequentially on the rib 5. The second layer 62s includes an aluminum alloy layer 621s and an aluminum layer 622s. The third layer 63s includes a titanium layer 631s and a conductive oxide layer 632s.

[0104] Next, wet etching is performed using the resist R1 as a mask, and as shown in Figure 13B, the portion of the conductive oxide layer 632s exposed from the resist R1 is removed. This forms a conductive oxide layer 632 with the shape shown in Figure 12.

[0105] Furthermore, anisotropic dry etching is performed using, for example, a chlorine-based etching gas with the resist R1 as a mask, and as shown in Figure 13C, the portion of the titanium layer 631s exposed from the resist R1 is removed. This forms the titanium layer 631 with the shape shown in Figure 12. In this dry etching process, the portion of the aluminum layer 622s exposed from the resist R1 is also removed. The aluminum alloy layer 621s functions as an etching stopper for this dry etching process.

[0106] Next, isotropic wet etching is performed, and as shown in Figure 13D, the portion of the aluminum alloy layer 621s exposed from the resist R1 is removed. In this wet etching, the sides of the aluminum alloy layer 621s and the aluminum layer 622s are also eroded, reducing their width. As a result, a second portion 62 including the aluminum alloy layer 621 and the aluminum layer 622 with the shape shown in Figure 12, and a second overhang structure OH2 are formed.

[0107] Subsequently, isotropic dry etching is performed using a fluorine-based etching gas, and the portion of the first layer 61s exposed from the second portion 62 is removed, as shown in Figure 13E. In this dry etching, the width of the first layer 61s is reduced below the second portion 62, and the first portion 61 and the first overhang structure OH1 with the shape shown in Figure 12 are formed. The first layer 61s may also be processed by other methods, such as wet etching using an etching solution containing dilute hydrofluoric acid. After the first portion 61, the second portion 62, and the third portion 63 are formed in this way, the partition wall 6 is completed by removing the resist R1.

[0108] [Fifth Embodiment] Figure 14 is a schematic cross-sectional view of the partition wall 6 according to the fifth embodiment. The partition wall 6 according to this embodiment has a first portion 61, a second portion 62, and a third portion 63, similar to the first embodiment. However, in the example of Figure 14, the side surface 62c of the second portion 62 is substantially parallel to the third direction Z. For example, as in the first embodiment, the first portion 61 is made of silicon nitride, the second portion 62 is made of aluminum, the third portion 63 is made of titanium, and the rib 5 is made of silicon oxide or silicon oxynitride.

[0109] For example, the thickness of the first part 61 is 20 nm, the thickness of the second part 62 is 500 nm, and the thickness of the third part 63 is 100 nm.

[0110] Figures 15A to 15D show an example of the process for forming the partition wall 6 according to this embodiment. First, as shown in Figure 15A, the first layer 61s which will form the basis of the first portion 61, the second layer 62s which will form the basis of the second portion 62, the third layer 63s which will form the basis of the third portion 63, and the resist R1 are formed sequentially on the rib 5.

[0111] Next, anisotropic dry etching is performed using, for example, a chlorine-based etching gas with the resist R1 as a mask, and the portion of the third layer 63s exposed from the resist R1 is removed, as shown in Figure 15B. This forms the third portion 63 with the shape shown in Figure 14. In this dry etching, the portions of the first layer 61s and the second layer 62s exposed from the resist R1 are also removed. The rib 5 functions as an etching stopper for this dry etching.

[0112] Next, isotropic wet etching is performed, reducing the width of the second layer 62s as shown in Figure 15C. This forms the second portion 62 with the shape shown in Figure 14 and the second overhang structure OH2.

[0113] Subsequently, isotropic dry etching is performed using a fluorine-based etching gas, and the portion of the first layer 61s exposed from the second portion 62 is removed, as shown in Figure 15D. In this dry etching, the width of the first layer 61s is reduced below the second portion 62, and the first portion 61 and the first overhang structure OH1 with the shape shown in Figure 14 are formed. The first layer 61s may also be processed by other methods, such as wet etching using an etching solution containing dilute hydrofluoric acid. After the first portion 61, the second portion 62, and the third portion 63 are formed in this way, the partition wall 6 is completed by removing the resist R1.

[0114] [Sixth Embodiment] Figure 16 is a schematic cross-sectional view of the partition wall 6 according to the sixth embodiment. In the partition wall 6 according to this embodiment, as in the second embodiment, the third portion 63 has a titanium layer 631 and a conductive oxide layer 632. In the example in Figure 16, the side surface 62c of the second portion 62 is substantially parallel to the third direction Z. For example, as in the first embodiment, the first portion 61 is formed of silicon nitride, the second portion 62 is formed of aluminum, and the rib 5 is formed of silicon oxide or silicon oxynitride.

[0115] For example, the thickness of the first part 61 is 20 nm, the thickness of the second part 62 is 500 nm, the thickness of the titanium layer 631 is 100 nm, and the thickness of the conductive oxide layer 632 is 50 nm.

[0116] Figures 17A to 17E show an example of the process for forming the partition wall 6 according to this embodiment. First, as shown in Figure 17A, a first layer 61s which forms the basis of the first portion 61, a second layer 62s which forms the basis of the second portion 62, a third layer 63s which forms the basis of the third portion 63, and a resist R1 are formed sequentially on the rib 5. The third layer 63s includes a titanium layer 631s and a conductive oxide layer 632s.

[0117] Next, wet etching is performed using the resist R1 as a mask, and as shown in Figure 17B, the portion of the conductive oxide layer 632s exposed from the resist R1 is removed. This forms a conductive oxide layer 632 with the shape shown in Figure 16.

[0118] Furthermore, anisotropic dry etching is performed using, for example, a chlorine-based etching gas with the resist R1 as a mask, and the portion of the titanium layer 631s exposed from the resist R1 is removed, as shown in Figure 17C. This forms the third portion 63 with the shape shown in Figure 16. In this dry etching, the portions of the second layer 62s and the first layer 61s exposed from the resist R1 are also removed. The rib 5 functions as an etching stopper for this dry etching.

[0119] Next, isotropic wet etching is performed, reducing the width of the second layer 62s as shown in Figure 17D. This forms the second portion 62 with the shape shown in Figure 16 and the second overhang structure OH2.

[0120] Subsequently, isotropic dry etching is performed using a fluorine-based etching gas, and the portion of the first layer 61s exposed from the second portion 62 is removed, as shown in Figure 17E. In this dry etching, the width of the first layer 61s is reduced below the second portion 62, and the first portion 61 and the first overhang structure OH1 with the shape shown in Figure 16 are formed. The first layer 61s may also be processed by other methods, such as wet etching using an etching solution containing dilute hydrofluoric acid. After the first portion 61, the second portion 62, and the third portion 63 are formed in this way, the partition wall 6 is completed by removing the resist R1.

[0121] [Seventh Embodiment] Figure 18 is a schematic cross-sectional view of the partition wall 6 according to the seventh embodiment. The partition wall 6 according to this embodiment has a first portion 61, a second portion 62, and a third portion 63, similar to the first embodiment. However, in this embodiment, the second portion 62 includes an aluminum layer 622 formed of aluminum (pure aluminum) and a titanium layer 623 formed of titanium. For example, as in the first embodiment, the first portion 61 is formed of silicon nitride, the third portion 63 is formed of titanium, and the rib 5 is formed of silicon oxide or silicon oxynitride.

[0122] The titanium layer 623 is positioned on top of the first portion 61. The aluminum layer 622 is positioned on top of the titanium layer 623. The titanium layer 623 protrudes on both sides in the width direction WD more than the first portion 61 and the aluminum layer 622. This forms the first overhang structure OH1.

[0123] The titanium layer 623 is formed to be thinner than the aluminum layer 622. For example, the thickness of the first portion 61 is 20 nm, the thickness of the titanium layer 623 is 100 nm, the thickness of the aluminum layer 622 is 500 nm, and the thickness of the third portion 63 is 100 nm.

[0124] Figures 19A to 19D show an example of the process for forming the partition wall 6 according to this embodiment. First, as shown in Figure 19A, a first layer 61s which forms the basis of the first portion 61, a second layer 62s which forms the basis of the second portion 62, a third layer 63s which forms the basis of the third portion 63, and a resist R1 are formed sequentially on the rib 5. The second layer 62s includes an aluminum layer 622s and a titanium layer 623s.

[0125] Next, anisotropic dry etching is performed using, for example, a chlorine-based etching gas with the resist R1 as a mask, and the portion of the third layer 63s exposed from the resist R1 is removed, as shown in Figure 19B. This forms the third portion 63 with the shape shown in Figure 18. In this dry etching, the portions of the aluminum layer 622s, titanium layer 623s, and first layer 61s exposed from the resist R1 are also removed. The rib 5 functions as an etching stopper for this dry etching.

[0126] Next, isotropic wet etching is performed, reducing the width of the aluminum layer 622s as shown in Figure 19C. This forms the second portion 62 and the second overhang structure OH2, which have the shape shown in Figure 18.

[0127] Subsequently, isotropic dry etching is performed using a fluorine-based etching gas, and as shown in Figure 19D, the portion of the first layer 61s exposed from the titanium layer 623 is removed. In this dry etching, the width of the first layer 61s is reduced below the titanium layer 623, and the first portion 61 and the first overhang structure OH1 with the shape shown in Figure 18 are formed. The first layer 61s may also be processed by other methods, such as wet etching using an etching solution containing dilute hydrofluoric acid. After the first portion 61, the second portion 62, and the third portion 63 are formed in this way, the partition wall 6 is completed by removing the resist R1.

[0128] Even when the first overhang structure OH1 is formed by the titanium layer 623 of the second portion 62, as in this embodiment, the same effects as in the first embodiment can be obtained.

[0129] [Eighth Embodiment] Figure 20 is a schematic cross-sectional view of the partition wall 6 according to the eighth embodiment. In this embodiment, the partition wall 6, like in the second embodiment, has a third portion 63 which includes a titanium layer 631 and a conductive oxide layer 632, and like in the seventh embodiment, has a second portion 62 which includes an aluminum layer 622 and a titanium layer 623. For example, the first portion 61 is formed of silicon nitride, and the ribs 5 are formed of silicon oxide or silicon oxynitride.

[0130] For example, the thickness of the first section 61 is 20 nm, the thickness of the titanium layer 623 is 100 nm, the thickness of the aluminum layer 622 is 500 nm, the thickness of the titanium layer 631 is 100 nm, and the thickness of the conductive oxide layer 632 is 50 nm.

[0131] Figures 21A to 21E show an example of the process for forming the partition wall 6 according to this embodiment. First, as shown in Figure 21A, a first layer 61s which forms the basis of the first portion 61, a second layer 62s which forms the basis of the second portion 62, a third layer 63s which forms the basis of the third portion 63, and a resist R1 are formed sequentially on the rib 5. The second layer 62s includes an aluminum layer 622s and a titanium layer 623s. The third layer 63s includes a titanium layer 631s and a conductive oxide layer 632s.

[0132] Next, wet etching is performed using the resist R1 as a mask, and as shown in Figure 21B, the portion of the conductive oxide layer 632s exposed from the resist R1 is removed. This forms a conductive oxide layer 632 with the shape shown in Figure 20.

[0133] Furthermore, anisotropic dry etching is performed using, for example, a chlorine-based etching gas with the resist R1 as a mask, and as shown in Figure 21C, the portion of the titanium layer 631s exposed from the resist R1 is removed. This forms the titanium layer 631 with the shape shown in Figure 21. In this dry etching process, the portions of the aluminum layer 622s, titanium layer 623s, and the first layer 61s exposed from the resist R1 are also removed. The rib 5 functions as an etching stopper for this dry etching process.

[0134] Next, isotropic wet etching is performed, reducing the width of the aluminum layer 622s as shown in Figure 21D. This forms a second portion 62 containing the aluminum layer 622 and titanium layer 623 in the shape shown in Figure 20, and a second overhang structure OH2.

[0135] Subsequently, isotropic dry etching is performed using a fluorine-based etching gas, and as shown in Figure 21E, the portion of the first layer 61s exposed from the titanium layer 623 is removed. In this dry etching, the width of the first layer 61s is reduced below the titanium layer 623, and the first portion 61 and the first overhang structure OH1 with the shape shown in Figure 21 are formed. The first layer 61s may also be processed by other methods, such as wet etching using an etching solution containing dilute hydrofluoric acid. After the first portion 61, the second portion 62, and the third portion 63 are formed in this way, the partition wall 6 is completed by removing the resist R1.

[0136] [Ninth Embodiment] Figure 22 is a schematic cross-sectional view of the partition wall 6 according to the ninth embodiment. In the partition wall 6 according to this embodiment, the second portion 62 includes an aluminum layer 622 and a titanium layer 623, similar to the partition wall 6 according to the seventh embodiment shown in Figure 18. Furthermore, in this embodiment, the second portion 62 includes a conductive oxide layer 624 formed of a conductive oxide such as ITO, IZO, and IGZO. For example, as in the first embodiment, the first portion 61 is formed of silicon nitride, the third portion 63 is formed of titanium, and the rib 5 is formed of silicon oxide or silicon oxynitride.

[0137] The conductive oxide layer 624 is located on top of the first portion 61. The titanium layer 623 is located on top of the conductive oxide layer 624. The aluminum layer 622 is located on top of the titanium layer 623. The titanium layer 623 and the conductive oxide layer 624 protrude on both sides in the width direction WD from the first portion 61, forming the first overhang structure OH1. In the example in Figure 22, the width of the conductive oxide layer 624 is smaller than the width of the titanium layer 623.

[0138] For example, the thickness of the first section 61 is 20 nm, the thickness of the conductive oxide layer 624 is 50 nm, the thickness of the titanium layer 623 is 100 nm, the thickness of the aluminum layer 622 is 500 nm, and the thickness of the third section 63 is 100 nm.

[0139] Figures 23A to 23E show an example of the process for forming the partition wall 6 according to this embodiment. First, as shown in Figure 23A, a first layer 61s which forms the basis of the first portion 61, a second layer 62s which forms the basis of the second portion 62, a third layer 63s which forms the basis of the third portion 63, and a resist R1 are formed sequentially on the rib 5. The second layer 62s includes an aluminum layer 622s, a titanium layer 623s, and a conductive oxide layer 624s.

[0140] Next, anisotropic dry etching is performed using, for example, a chlorine-based etching gas with the resist R1 as a mask, and the portion of the third layer 63s exposed from the resist R1 is removed, as shown in Figure 23B. This forms the third portion 63 with the shape shown in Figure 22. In this dry etching, the portions of the aluminum layer 622s and the titanium layer 623s exposed from the resist R1 are also removed. The conductive oxide layer 624s functions as an etching stopper for this dry etching.

[0141] Next, wet etching is performed, and as shown in Figure 23C, the portion of the conductive oxide layer 624s exposed from the titanium layer 623 is removed. This forms a conductive oxide layer 624 with the shape shown in Figure 22. In the example in Figure 23C, the width of the conductive oxide layer 624 is slightly reduced compared to the width of the titanium layer 623 by this wet etching.

[0142] Subsequently, isotropic wet etching is performed, reducing the width of the aluminum layer 622s as shown in Figure 23D. This forms a second portion 62 including the aluminum layer 622, titanium layer 623, and conductive oxide layer 624, as shown in Figure 22.

[0143] Furthermore, isotropic dry etching is performed using a fluorine-based etching gas, and as shown in Figure 23E, the portion of the first layer 61s exposed from the conductive oxide layer 624 is removed. In this dry etching, the width of the first layer 61s is reduced below the conductive oxide layer 624, and the first portion 61 and the first overhang structure OH1 with the shape shown in Figure 22 are formed. The first layer 61s may also be processed by other methods, such as wet etching using an etching solution containing dilute hydrofluoric acid. After the first portion 61, the second portion 62, and the third portion 63 are formed in this way, the partition wall 6 is completed by removing the resist R1.

[0144] In this embodiment, if the second portion 62 includes a conductive oxide layer 624, even if the titanium layer 623 is damaged through each etching process, the conductive oxide layer 624 can maintain the first overhang structure OH1.

[0145] In addition to those disclosed in the first to ninth embodiments, the first overhang structure OH1 and the second overhang structure OH2 can be formed on the partition wall 6 by various methods.

[0146] All display devices and manufacturing methods thereof that can be implemented by those skilled in the art by appropriately modifying the design based on the display devices and manufacturing methods thereof described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0147] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or change the design of any of the above-described embodiments, or to add, omit, or change the conditions of any process, are also included within the scope of the present invention, as long as they retain the essence of the present invention.

[0148] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of Symbols]

[0149] DSP... Display device, DA... Display area, SA... Peripheral area, PX... Pixel, SP... Sub-pixel, LE1, LE2, LE3... First to third lower electrodes, OR1, OR2, OR3... First to third organic layers, UE1, UE2, UE3... First to third upper electrodes, SE1, SE2, SE3... First to third sealing layers, DE1, DE2, DE3... First to third display elements, 5... Rib, 6... Partition, 61... First part of partition, 62... Second part of partition, 63... Third part of partition.

Claims

1. The lower electrode and, A rib having a pixel aperture that overlaps with the lower electrode, A partition wall positioned above the rib, An upper electrode facing the lower electrode, The system comprises an organic layer located between the lower electrode and the upper electrode, which emits light in accordance with the potential difference between the lower electrode and the upper electrode, The aforementioned partition wall is The first insulating part, A conductive second portion is positioned on the first portion and in contact with the upper electrode, A third part positioned on top of the second part, It has, The lower end of the second portion protrudes more than the first portion in the width direction of the partition wall, The third portion protrudes in the width direction more than the upper end of the second portion. Display device.

2. The partition wall surrounds the pixel aperture. The display device according to claim 1.

3. The organic layer is composed of a plurality of layers, including a hole injection layer covering the lower electrode. The hole injection layer is spaced apart from the second portion. The display device according to claim 1.

4. The first portion is thicker than the hole injection layer. The display device according to claim 3.

5. The first part is thinner than the second part. The display device according to claim 4.

6. The length by which the lower end of the second portion protrudes from the first portion is at least twice the thickness of the first portion. The display device according to claim 3.

7. The gap between the lower end of the second portion and the rib is blocked by a layer among the plurality of layers that is placed on top of the hole injection layer. The display device according to claim 3.

8. The plurality of layers include a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer, each disposed on top of the hole injection layer. The display device according to claim 7.

9. The ribs and the first portion are formed of different types of insulating inorganic materials. The display device according to any one of claims 1 to 8.

10. The aforementioned ribs are formed from silicon oxide or silicon oxynitride. The first part is formed of silicon nitride. The display device according to claim 9.

11. The second part is made of aluminum, The aforementioned third part is made of titanium. The display device according to claim 9.

12. The second part is made of aluminum, The third portion includes a titanium layer and a conductive oxide layer disposed on the titanium layer. The display device according to claim 9.

13. The second portion includes a titanium layer and an aluminum layer disposed on the titanium layer. The aforementioned third part is made of titanium. The display device according to claim 9.

14. Form the lower electrode, A rib is formed to cover at least a portion of the lower electrode, A partition wall is formed on the rib, having an insulating first portion, a conductive second portion positioned above the first portion, and a third portion positioned above the second portion, wherein the lower end of the second portion protrudes in the width direction more than the first portion, and the third portion protrudes in the width direction more than the upper end of the second portion. An organic layer covering the lower electrode is formed through the pixel aperture provided in the rib, An upper electrode is formed that covers the organic layer and contacts the second portion. A method for manufacturing a display device.

15. The aforementioned organic layer is formed by stacking multiple layers, including a hole injection layer. The hole injection layer is spaced apart from the second portion. A method for manufacturing a display device according to claim 14.

16. The gap between the lower end of the second portion and the rib is sealed by a layer formed after the hole injection layer among the plurality of layers. A method for manufacturing a display device according to claim 15.

17. The formation of the aforementioned partition wall is Forming the first layer which forms the basis of the first portion, A second layer, which will serve as the base for the second portion, is formed on the first layer. A third layer, which will serve as the base for the third portion, is formed on top of the second layer. A resist is placed on the third layer, By etching, the portions of the first layer, the second layer, and the third layer exposed from the resist are removed, and the widths of the first layer and the second layer are reduced, thereby forming the first portion, the second portion, and the third portion. Including, A method for manufacturing a display device according to any one of claims 14 to 16.

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