Manufacturing method for railway devices

Abstract

A process and structure for fabricating a line device structure that allows for miniaturization of the spacing between stress relief and contact window structures is provided. [Solution] The device comprises a substrate, a first metal pillar (68), and a second metal pillar, wherein the first metal pillar (68) is located on the substrate, and the maximum lateral dimension (Hw) of the first metal pillar (68) divided by the height (Ht) of the first metal pillar (68) is less than 4, and the height of the first metal pillar (68) is between 20 μm and 300 μm, and the second metal pillar is located on the substrate, and the maximum lateral dimension (Hw) of the second metal pillar (68) divided by the height of the second metal pillar (68) is less than 4, and the distance (Hb) from the center point of the first metal pillar to the center point of the second metal pillar (68) is between 10 μm and 250 μm.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a circuit device, and more particularly to a method for manufacturing a circuit device that effectively improves the performance of an IC.

Background Art

[0002] Semiconductor wafers are used in the manufacture of ICs with continuously increasing density and shrinking geometric patterns, and through the structure of multiple conductive and insulating layers, provide internal connections and isolation effects between semiconductor devices in different layers. For example, in large ICs such as active and passive devices, thin film transistors, complementary metal-oxide-semiconductor (CMOS), capacitors, chokes, resistors, etc., an increase in several electromagnetic characteristic connection parts is required between different layered structures and semiconductor devices. At the same time, for assembled ICs, a large increase in wires is also required. Therefore, these wires pass through the protective layer in the IC chip, are exposed to the outside, and finally are connected to the input / output pads. This wire is used to connect to the external contact structure of the chip packaging.

[0003] Wafer-level chip scale packaging (WLCSP) is a technology for packaging IC chips in a so-called wafer-level manner, which is different from the traditional single-unit package manufacturing process after chip cutting. Therefore, before cutting the chip into single units and before performing the final chip carrier package, such as a ball grid array (BGA) package, WLCSP can integrate wafer manufacturing, packaging, testing, and wafer-level burn-in (WLBI). Its advantages are that by reducing the occupied volume and thickness, smaller dimensions, lighter weight, a relatively simple assembly process, reduced overall production costs, and better electromagnetic characteristics can be obtained. And WLCSP simplifies the transportation process of a device from the silicon material to the customer, increases the production volume of IC chip packaging, and at the same time reduces costs. However, due to the relationship with manufacturing capabilities and structural reliability, it is facing very big challenges.

[0004] WLCSP can be extended to the bonding device fabrication process and device protection fabrication process during wafer fabrication. In the first step of WLCSP, post-passivation is formed through reconfigurable semiconductor IC line technology, widening the distance between standard pads. This allows for the formation of low-cost solder stencils, enabling sil or aligned soldering. Regarding the announcement of reconfigurable technology, for example, the applicants of Patent Documents 1-3 are the same as the applicants of this invention. As announced in this patent, a single line arrangement layer connects to the output and input pads of the semiconductor structure. This RDL layer is formed on the post-passivation polymer layer or elastic material layer, and post-shaped contact windows manufactured using the mask fabrication process are formed on this RDL layer. The lateral direction of the post-shaped contact windows formed after this reaction is independent and not supported at all. Furthermore, using flip-chip assembly technology, the structure formed after the above reaction is further assembled into a chip carrier package. Even if this post-passivation structure and its corresponding manufacturing process can solve and improve the problem of spacing within IC packages, ICs required to sustainably increase in integrated scale should be subject to more stringent limitations, and there is also a potential risk of damage caused by stress induction.

[0005] Patent Document 4 includes a WLCSP with a post-passivation structure for another RDL layer. This RDL layer is formed on a polymer layer above the post-passivation, and another polymer layer is placed over the RDL layer. Micro-vias are formed in this polymer layer by etching or drilling, and metal is used to fill the holes in the micro-vias to form internal connections, creating a so-called conductive column. However, the upper and lower polymer layers are separated by a chromium-copper layer to prevent contact with the RDL layer, and the other is bonded to a non-electroplated, screen-printed, or stenciled tin-lead at the protruding tail end of the conductive column. Since the conductive column extends outside the polymer layer and the top surface of the structure is not smooth, high-resolution lithography cannot be achieved. As a result, the formation of micro-vias in the conductive column and the formation of tin-lead by electroplating are not achieved, and ultimately the spacing distance of the contact windows in the IC package is limited. Moreover, this limitation becomes increasingly noticeable as the thickness of the polymer layer increases. However, increasing the thickness of the polymer layer provides satisfactory stress relief.

[0006] This point will be discussed below. Furthermore, as mentioned above, because the lower polymer layer is isolated from the upper polymer layer, the lower polymer layer cannot provide better stress relief on its own. In addition, the current thickness of the lower polymer layer is manufactured to be thin in order to reduce lateral movement of the RDL layer, so the stress relief is somewhat weaker, and this problem will be discussed below.

[0007] One challenge in ensuring structural reliability is supplying the multilayer structure formed by the WLCSP described above by providing sufficient stress relief. This includes semiconductor IC chips and non-fixed post-passivation structures. For example, a thin film bonded to a protective layer is affected by bishear stress, and this stress is thermally induced. Equation (1) shows a mathematical theoretical simulation equation for the bishear stress in the post-passivation, and provides the physical parameters of the silicon substrate structure within the IC chip.

number

[0008] σppt: Bishear stress in post-passivation thin film R: Radius of curvature of the silicon substrate due to heat. Ys: Young's modulus of silicon substrate vsi: Poisson's ratio of silicon substrate xSi: Thickness of the silicon substrate xppt: Post-passivation thin film thickness From the above equation, in addition to increasing the Poisson's ratio of the silicon substrate, the bishear stress can be reduced in two other ways. (a) Reduce xSi. This means making the silicon substrate thinner. Or (b) Increase xppt. This means increasing the thickness of the post-passivation structure.

[0009] Figure 1 shows a well-known post-passivation structure 10, which includes one RDL layer 12 and one stress-relieving polymer layer 14. This stress-relieving polymer layer 14 is also called a stress buffer layer. It is formed on the protective layer 16 on the surface of the semiconductor IC chip 18, and the polymer layer 14 within it can be made of an elastic material, epoxy resin, low dielectric constant material, or other polymer material. The elastic material is mainly used to provide sufficient mechanical elasticity to the bonding structure. As inferred from equation (1) above, when the polymer layer 14 is placed on the IC chip 18, all stress formed on the structure on the IC chip 18 is absorbed or buffered, thereby reducing local damage to the IC chip 18. This increases the reliability of the post-passivation structure 10, especially for precise and complex IC chip 18 circuits. Furthermore, according to the relationship in equation (1), the expression of the buffering effect improves as the thickness of the polymer layer 14 increases.

[0010] However, when using a thick polymer layer 14, one problem often arises. The RDL layer 12 shown in Figure 1 is usually made of copper and connects the output input pads 20 of the IC chip 18 to the external circuit. When a tin-lead protrusion or copper conductive column is formed simultaneously or separately at the top of the pad 20, the RDL layer 12 is very tightly connected to the package structure of the layer directly below it, and the package structure within it may be a single chip carrier. Therefore, the RDL layer 12 is defined by the polymer layer 14 as a slope 22 with a certain degree of inclination. This RDL layer 12 gradually rises from one lower IC plane forming the output input pads 20 to one higher IC plane. For example, the slope 22 at the top of the polymer layer 14 is determined by overlapping the openings of the thick polymer layer 14 during the metallization step. In practical applications, the degree of inclination of the slope 22 varies depending on the different openings of each polymer layer 14, and each opening is determined by the conditions of the actual manufacturing process and the fundamental physical properties and characteristics of the polymer body. For example, regarding the wetting contact angle related to the energy on the material surface, to illustrate with an example, in many situations, the inclination of the slope 22 of the polymer layer 14 on the IC protective layer 16 is approximately 45 degrees, so the RDL layer 12 extends from the pad 20 in the IC to the top edge of the polymer layer 14 with a certain amount of lateral movement. Therefore, this lateral movement allows for a certain amount of tolerance when the RDL layer 12 is constructed. Ultimately, this tolerated tolerance allows for different inclinations of each type of slope 22 formed by polymer layers 14 with different openings, and since the lateral movement of each RDL layer is different, the spacing distance between adjacent contact windows is limited, and these contact windows are defined jointly or separately as tin-lead protrusions or copper bodies, and the distance between the contact window structure and the opening on the protective layer increases accordingly, so a minute spacing distance is not maintained between the post-passivation structure and the package structure directly below. Conversely, if a thick polymer layer 14 is not used, the electrical circuits within the precise IC chip will be damaged by stress induction due to insufficient stress buffering. Also, for large conductive columns, the lateral support force is insufficient, limiting the spacing between output and input structures.However, a large conductive column structure is necessary because it can provide sufficient distance and reduce the coupling capacitance produced between the output / input pads 20 and the electromagnetic characteristic circuit in the IC chip 18.

[0011] The proposed solutions presented above are feasible to address the problems arising from reducing the distance between the post-passivation structure and the contact window structure, and this is why the integrated scale within the IC is being hindered.

[0012] Taking this into consideration, by submitting WLCSP and its corresponding fabrication process, we aim to improve stress relief while simultaneously miniaturizing the spacing distance of the contact window structure. [Patent Document 1] U.S. Patent No. 6,645,136 [Patent Document 2] U.S. Patent No. 6,784,087 [Patent Document 3] U.S. Patent No. 6,818,545 [Patent Document 4] U.S. Patent No. 6,103,552 [Disclosure of the Invention] [Problems that the invention aims to solve]

[0013] The main objective of the present invention is to provide a method for manufacturing a track device that can provide stress relief and miniaturization of the spacing distance of the contact window structure. Based on the present invention, it is possible to achieve a spacing distance of 250 μm or less and to limit the number of pinholes to 400 or less.

[0014] Another object of the present invention is to provide a method for manufacturing a track device which includes a post-passivation structure supported by one RDL, wherein a support layer with a relatively thinner relative thickness is formed on a protective layer, for example by a polymer layer, to support the gaps between RDL structures, and a support layer with a relatively thicker relative thickness is formed. For example by a polymer layer, the gaps between RDL structures between adjacent layered packing structures are supported. [Means for solving the problem]

[0015] For the above purpose, the present invention provides a method for manufacturing a railway device. The manufacturing process provides a semiconductor substrate, a metal layer located on the semiconductor substrate, and a first polymer layer located on the semiconductor substrate and the metal layer. The first polymer layer is polished. A second polymer layer is formed on the first polymer layer, and the metal layer is exposed in one opening in the second polymer layer.

[0016] The present invention provides a method for manufacturing a transmission line device for the above-mentioned purpose. The manufacturing process involves providing a semiconductor substrate and a metal column located on the semiconductor substrate, wherein the maximum width of the metal column divided by the heights of the first and second metal columns is less than 4, and the height of the first metal column is between 20 μm and 300 μm. A first insulating layer is formed on the semiconductor substrate and covers the metal column. A second insulating layer is formed on the first insulating layer, and the first metal column is exposed at an opening in the second insulating layer.

[0017] For the above purpose, this invention provides a manufacturing process and structure for a type of transmission line device structure, and the manufacturing process provides a semiconductor wafer, a first metal layer located on the semiconductor wafer, and a polymer layer located on the semiconductor wafer and the first metal layer, wherein the semiconductor wafer contains a number of transistors, and the number of transistors mix trivalent and pentavalent ions into the semiconductor wafer. The polymer layer is polished. A second metal layer is formed on the polymer layer and the first metal layer. A pattern-defining layer is formed on the second metal layer, and the second metal layer is exposed in an opening in the pattern-defining layer. A third metal layer is formed on the second metal layer exposed in the opening. The pattern-defining layer is removed. The second metal layer is removed except for the layer beneath the third metal layer.

[0018] For the above purpose, the present invention provides a manufacturing process and structure for a type of transmission line device structure, wherein the manufacturing process provides a semiconductor wafer and a metal column located on the semiconductor wafer, the maximum width of the metal column divided by its height being less than 4, and the height of the metal column being between 20 μm and 300 μm, the semiconductor wafer containing a number of transistors, the number of transistors mixing trivalent and pentavalent ions into the semiconductor wafer. An insulating layer is formed on the semiconductor wafer and covers the metal column. A first metal layer is formed on the insulating layer and the metal column. A pattern-defining layer is formed on the first metal layer and the first metal layer is exposed at an opening in the pattern-defining layer. A second metal layer is formed on the first metal layer exposed at the opening. The pattern-defining layer is removed. The first metal layer is removed except for the layer beneath the second metal layer.

[0019] For the above object, the present invention provides a manufacturing process and structure of a kind of circuit device structure. In the manufacturing process, a semiconductor base, a first metal layer located on the semiconductor base, and a polymer layer on the semiconductor base and the first metal layer are provided. The polymer layer is polished. A protruding block is formed on the first metal layer, and the formed protruding block includes a second metal layer on the polymer layer and the first metal layer. A pattern definition layer is formed on the second metal layer, and a second metal layer is exposed in an opening in the pattern definition layer. A third metal layer is formed on the second metal layer exposed in the opening. The pattern definition layer is removed. The second metal layer except under the third metal layer is removed.

[0020] For the above object, the present invention provides a manufacturing device process and structure of a kind of circuit structure. In the manufacturing process, a semiconductor base and a metal pillar located on the semiconductor base are provided. When the maximum width of the metal pillar is divided by the height of the metal pillar, the result is less than 4, and the height of the metal pillar is from 20 μm to 300 μm. An insulating layer is formed on the semiconductor base and covers the metal pillar. An opening is formed inside the insulating layer to expose the metal pillar.

[0021] For the above object, the present invention provides a manufacturing process and structure of a kind of circuit device structure. In the manufacturing process, a semiconductor base, a first metal layer located on the semiconductor base, and a polymer layer located on the semiconductor base and the metal layer are provided. The polymer layer is polished. An opening is formed inside the polymer layer to expose the metal layer.

[0022] For the above object, the present invention provides a manufacturing process and structure of a kind of circuit device structure. In the manufacturing process, a semiconductor base and a metal pillar located on the semiconductor base are provided. When the maximum width of the metal pillar is divided by the height of the metal pillar, the result is less than 4, and the height of the metal pillar is from 20 μm to 300 μm. An insulating layer is formed on the semiconductor base and covers the metal pillar. The insulating layer is etched.

[0023] For the above purpose, the present invention provides a manufacturing process and structure for a type of track device structure, and provides a semiconductor base, a metal column located on the semiconductor base, and a polymer layer located on the semiconductor base and the metal column in the manufacturing process. The polymer layer is removed, exposing one top surface of the metal column, and the height between the top surface and the polymer layer is 10 μm to 150 μm.

[0024] For the above purpose, the present invention provides a manufacturing process and structure for a type of track device structure, and provides a semiconductor substrate, a metal layer located on the semiconductor substrate, and a polymer layer located on the semiconductor substrate and the metal layer for the manufacturing process. The polymer layer is polished. The polymer layer is etched.

[0025] For the above purpose, this invention provides a manufacturing process and structure for a type of transmission line device structure, and provides a semiconductor substrate for the manufacturing process. A polymer layer is provided on the semiconductor substrate, and the depth of one opening in the polymer layer is 10 μm to 300 μm. A metal layer is formed on the polymer layer and in its opening, and the metal layer is removed except for the opening.

[0026] For the above purpose, the present invention provides a manufacturing process and structure for a type of line device structure, the manufacturing process providing a semiconductor substrate and a metal column positioned on the semiconductor substrate, wherein the maximum width of the metal column divided by its height is less than 4, and the height of the metal column is between 20 μm and 300 μm. An insulating layer is formed on the semiconductor substrate and covers the metal column. A protruding mass is formed on the metal layer. The protruding mass is connected to an external circuit. A second insulating layer is formed between the semiconductor substrate and the external circuit.

[0027] For the above purpose, the present invention provides a manufacturing process and structure for a type of transmission line device structure, and provides a semiconductor substrate, a metal layer located on the semiconductor substrate, and a first polymer layer located on the semiconductor substrate and the metal layer in the manufacturing process. The first polymer layer is polished. A protruding mass is formed on the metal layer. The protruding mass is connected to an external circuit. A second polymer layer is formed between the semiconductor substrate and the external circuit.

[0028] For the above purpose, the present invention provides a manufacturing process and structure for a type of line device structure, and provides a semiconductor substrate, a metal layer located on the semiconductor substrate, and a first polymer layer located on the semiconductor substrate and the metal layer in the manufacturing process. The first polymer layer is polished. A protruding mass is formed on the metal layer, and the protruding mass includes an electroplating manufacturing process.

[0029] For the above purpose, the present invention provides a manufacturing process and structure for a type of line device structure, the manufacturing process providing a semiconductor substrate and a metal column positioned on the semiconductor substrate, wherein the maximum width of the metal column divided by its height is less than 4, and the height of the metal column is between 20 μm and 300 μm. An insulating layer is formed on the semiconductor substrate and covers the metal column. A protruding mass is formed on the metal column. The protruding mass includes an electroplating manufacturing process.

[0030] For the above purpose, this invention provides a manufacturing process and structure for a type of track device structure, and provides a semiconductor base, a metal layer located on the semiconductor base, and a polymer layer located on the semiconductor base and the metal layer in the manufacturing process. The polymer layer is polished. A wire is formed in a wire manufacturing process and connected on the metal layer.

[0031] For the above purpose, this invention provides a manufacturing process and structure for a type of line device structure, the manufacturing process providing a semiconductor base and a metal column positioned on the semiconductor base, wherein the maximum width of the metal column divided by its height is less than 4, and the height of the metal column is between 20 μm and 300 μm. An insulating layer is formed on the semiconductor base and covers the metal column. A wire is formed in a wire manufacturing process and connected on the metal column.

[0032] For the above purpose, this invention provides a manufacturing process and structure for a type of railway device structure, and provides a substrate for the manufacturing process. A first metal column is placed on the substrate, and when the maximum width of the first metal column is divided by its height, the result is less than 4, and the height of the first metal column is between 20 μm and 300 μm. A second metal column is placed on the substrate, and when the maximum width of the second metal column is divided by its height, the result is less than 4, and the height of the second metal column is between 20 μm and 300 μm. The distance from the center point of the first metal column to the center point of the second metal column is between 10 μm and 250 μm.

[0033] For the above purpose, the present invention provides a manufacturing process and structure for a type of line device structure, and provides a semiconductor substrate for the manufacturing process. A first metal column is placed on the semiconductor substrate, and when the maximum width of the first metal column is divided by its height, it is less than 4, and the height of the first metal column is between 20 μm and 300 μm. A second metal column is placed on the semiconductor substrate, and when the maximum width of the second metal column is divided by its height, it is less than 4, and the height of the second metal column is between 20 μm and 300 μm. A second metal column is placed between 20 μm and 300 μm. An insulating layer is placed on the semiconductor substrate and covers the first and second metal columns. A first protruding mass is formed on the first metal column. A second protruding mass is formed on the second metal column, and the distance from the center point of the first protruding mass to the center point of the second protruding mass is between 10 μm and 250 μm.

[0034] For the above purpose, this invention provides a manufacturing process and structure for a type of transmission line device structure, and provides a semiconductor substrate for the manufacturing process. A first metal column is placed on the semiconductor substrate, and when the maximum width of the first metal column is divided by its height, the result is less than 4, and the height of the first metal column is between 20 μm and 300 μm. A second metal column is placed on the semiconductor substrate, and when the maximum width of the second metal column is divided by its height, the result is less than 4, and the height of the second metal column is between 20 μm and 300 μm. The top surfaces of the first metal column and the second metal column are connected by a metal transmission line, and the material of the metal transmission line contains gold.

[0035] For the above purpose, this invention provides a manufacturing process and structure for a type of transmission line device structure, and provides a semiconductor substrate for the manufacturing process. A first metal column is placed on the semiconductor substrate, and when the maximum width of the first metal column is divided by its height, the result is less than 4, and the height of the first metal column is between 20 μm and 300 μm. A second metal column is placed on the semiconductor substrate, and when the maximum width of the second metal column is divided by its height, the result is less than 4, and the height of the second metal column is between 20 μm and 300 μm. The top surfaces of the first metal column and the second metal column are connected by a metal transmission line. A polymer layer is placed on the metal transmission line.

[0036] For the above purpose, the present invention provides a manufacturing process and structure for a type of railway device structure, and provides a semiconductor base for the manufacturing process. A metal column is placed on the semiconductor base, and when the maximum width of the metal column is divided by its height, the result is less than 4, and the height of the metal column is between 20 μm and 300 μm. A wire is formed in a wire manufacturing process and connected to the metal column and its polymer layer.

[0037] For the above purpose, the present invention provides a manufacturing process and structure for a type of transmission line device structure, and provides a semiconductor substrate for the manufacturing process. A metal column is placed on the semiconductor substrate, and when the maximum width of the metal column is divided by its height, it is less than 4, and the height of the metal column is between 20 μm and 300 μm. A polymer layer is placed on the metal transmission line and covers the metal column. A protruding mass is formed on the metal column, with a thickness between 10 μm and 150 μm.

[0038] For the above purpose, this invention provides a manufacturing process and structure for a type of transmission line device structure, and provides a semiconductor substrate for the manufacturing process. A metal column is placed on the semiconductor substrate, and when the maximum width of the metal column is divided by its height, it is less than 4, and the height of the metal column is between 20 μm and 300 μm. A polymer layer is placed on the semiconductor substrate and covers the metal column. A metal coil is placed on the semiconductor substrate, and the thickness of the metal coil is between 1 μm and 15 μm.

[0039] For the purposes described above, the present invention provides a manufacturing process and structure for a type of transmission line device structure, and provides a semiconductor substrate therefor. A metal column is placed on the semiconductor substrate, and when the maximum width of the metal column is divided by its height, the result is less than 4, and the height of the metal column is between 20 μm and 300 μm. A protruding mass is formed on the metal column, and the thickness of the protruding mass includes a gold layer between 10 μm and 30 μm.

[0040] For the purposes described above, the present invention provides a manufacturing process and structure for a type of transmission line device structure, and provides a semiconductor substrate therefor. A metal column is placed on the semiconductor substrate, and when the maximum width of the metal column is divided by its height, the result is less than 4, and the height of the metal column is between 20 μm and 300 μm. A protruding mass is formed on the metal column, and this protruding mass contains a titanium-containing gold layer.

[0041] For the purposes described above, the present invention provides a manufacturing process and structure for a type of transmission line device structure, and provides a semiconductor substrate therefor. A metal column is placed on the semiconductor substrate, and when the maximum width of the metal column is divided by its height, the result is less than 4, and the height of the metal column is between 20 μm and 300 μm. A protruding mass is formed on the metal column, and this protruding mass contains a chromium-containing gold layer.

[0042] For the purposes described above, the present invention provides a manufacturing process and structure for a type of transmission line device structure, and provides a semiconductor substrate therefor. A metal column is placed on the semiconductor substrate, and when the maximum width of the metal column is divided by its height, the result is less than 4, and the height of the metal column is between 20 μm and 300 μm. A protruding mass is formed on the metal column, and this protruding mass contains a tantalum-containing gold layer.

[0043] For the above purpose, the present invention provides a manufacturing process and structure for a type of transmission line device structure, and provides a semiconductor substrate therefor. A metal column is placed on the semiconductor substrate, and when the maximum width of the metal column is divided by its height, the result is less than 4, and the height of the metal column is between 20 μm and 300 μm. A first polymer layer is placed on the semiconductor substrate and covers the metal column. A substrate is placed. A protruding mass is located between the metal column and the substrate, and a second polymer layer is located between the substrate and the semiconductor substrate and covers the protruding mass.

[0044] The following detailed explanation, using specific examples and attached diagrams, will make it easier to understand the purpose, technical content, features, and effects achieved by this invention. [Best Mode for Carrying Out the Invention]

[0045] The present invention relates to a manufacturing process and structure of a type of transmission line device structure, wherein numerous metal post structures are formed on a semiconductor substrate, and the distance between adjacent metal posts is reduced to 250 μm or less. Several different embodiments are described below.

[0046] (First example) The manufacturing process of the track device structure of the first embodiment is shown in Figure 2. First, a semiconductor substrate 30 is provided, the form of which is a silicon substrate, a gallium arsenide substrate (GAAS), or a silicon germanium substrate, which is a silicon-on-insulator (SOI) substrate, and in this embodiment the semiconductor substrate 30 is a circular semiconductor wafer, and this semiconductor wafer 30 has a single active surface, which, through pentavalent or trivalent ions (e.g., boron ions or phosphate ions, etc.), forms several electronic devices 32, which are metal oxide semiconductors such as MOS devices, p-channel MOS devices, n-channel MOS devices, BICMOS devices, bipolar junction transistors (BJT), diffusion areas, resistors, capacitors, and CMOS.

[0047] Refer to Figure 3. A thin connection structure 34 is formed on the active surface of the semiconductor wafer 30. This thin connection structure 34 is composed of multiple thin insulating layers 36 with a thickness of 3 μm or less and thin line layers 38 with a thickness of 3 μm or less. The thin line layers 38 are made of copper or aluminum metal. The thin insulating layer 36 is also called a dielectric barrier and is usually formed by chemical vapor deposition. This thin insulating layer 36 can be silicon oxide, tetraethoxysilane (TEOS) oxide formed by chemical vapor deposition, SiwCxOyHz, silicon nitride compounds or silicon nitride compounds, or glass (SOG), glass fluoride (FSG), silk layer (SiLK), black diamond thin film, polyarylene ether, polybenzoxazole (PBO), or porous silica formed by spin coating. Alternatively, the thin insulating layer 36 is made of a material with a dielectric constant (FPI) of 3 or less.

[0048] During the formation of multiple thin line layers 38 in the semiconductor wafer 30 process, in the metal damascene fabrication process, one diffusion blocking layer is first sputtered onto the bottom and side walls of the opening of one thin film insulating layer 36 and onto the surface of the thin film insulating layer 36. For example, a copper seed layer is sputtered onto the diffusion blocking layer, and then a copper layer is electroplated onto this seed layer. Alternatively, the copper layer, seed layer, and diffusion blocking layer outside the opening of the thin film insulating layer 36 are removed using the optical CMP (chemical mechanical polishing, CMP) method until the upper surface of the thin film insulating layer 36 is exposed. Another method involves first sputtering an aluminum layer or aluminum alloy layer onto the thin film insulating layer 36, and then etching the aluminum layer or aluminum alloy layer using the lithography etching method. These thin line layers 38 connect to each other or to electronic devices 32 by passing through holes 40 in the thin insulating layer 36. The typical thickness of the thin line layers 38 is 0.1 μm to 0.5 μm. In the lithography fabrication process, the thin line layers 38 are fabricated using 5X steppers, scanners, or other superior machines.

[0049] Next, a protective layer 42 is placed on the surface of the semiconductor substrate 30 using chemical vapor deposition (CVD). Multiple cracks in this protective layer 42 expose the pad 44, protecting the electronic devices 32 within the semiconductor substrate 30 from damage by moisture and foreign ion contamination. In other words, the protective layer 42 prevents damage to the electronic devices 32, such as transistors, polycrystalline silicon resistors, or polycrystalline silicon capacitors, or to thin metal wires, by penetration by mobile ions (e.g., sodium ions), moisture, transition metals (e.g., gold, silver, copper), and other impurities. To achieve the protective purpose, the protective layer 42 is usually composed of silicon oxide, silicon oxide compounds, silicon phosphide glass, silicon oxide, and silicon oxy-nitride.

[0050] The first method for fabricating the protective layer 42 involves first forming a silicon monoxide layer with a thickness of 0.2 μm to 1.2 μm using a chemical vapor phase method, and then forming another silicon monoxide layer with a thickness of 0.2 μm to 1.2 μm on top of that silicon oxide layer using a chemical vapor phase method.

[0051] The second method for fabricating the protective layer 42 involves first forming a silicon monoxide layer with a thickness of 0.2 μm to 1.2 μm using a chemical vapor phase method, and then forming a silicon monoxide layer with a thickness of 0.05 μm to 0.15 μm on top of that silicon monoxide layer using a plasma-enhanced chemical vapor phase method.

[0052] The third method for fabricating the protective layer 42 involves first forming a silicon mononitride layer with a thickness of 0.05 μm to 0.15 μm using a chemical vapor phase method, then forming a silicon monoxide layer with a thickness of 0.2 μm to 1.2 μm on the silicon mononitride layer using a chemical vapor phase method, and finally forming a silicon mononitride layer with a thickness of 0.2 μm to 1.2 μm on the silicon oxide layer using a chemical vapor phase method.

[0053] The fourth method for fabricating the protective layer 42 involves first forming a silicon monoxide layer with a thickness of 0.2 μm to 0.5 μm using a chemical vapor phase method, then forming a silicon dioxide layer with a thickness of 0.5 μm to 1 μm on the silicon monoxide layer using a spin-coating method, and finally forming a silicon trinitride layer with a thickness of 0.2 μm to 1.2 μm on the silicon dioxide layer using a chemical vapor phase method.

[0054] The fifth method for fabricating the protective layer 42 involves first forming a silicon monoxide layer with a thickness of 0.5 μm to 2 μm using high-density plasma chemical vapor deposition (HDP-CVD), and then forming a silicon mononitride layer with a thickness of 0.2 μm to 1.2 μm on top of the silicon oxide layer using chemical vapor deposition.

[0055] The sixth type of fabrication method for protective layer 42 involves first forming an unimpregnated silicon glass (USG) with a thickness of 0.2 μm to 3 μm, then forming an insulating layer with a thickness of 0.5 μm to 3 μm on top of the unimpregnated silicon glass, such as tetraethoxysilane (TEOS) oxide borophosphosilicate glass (BPSG) or phosphosilicate glass (PSG), and finally forming a silicon mononitride layer with a thickness of 0.2 μm to 1.2 μm on top of the insulating layer using a chemical vapor phase method.

[0056] The seventh method for fabricating the protective layer 42 involves selectively first forming a silicon mononitride layer with a thickness of 0.05 μm to 0.15 μm using a chemical vapor phase method, then forming a silicon mononitride layer with a thickness of 0.2 μm to 1.2 μm on the silicon dinitride layer or the silicon oxide layer using a chemical vapor phase method, or selectively first forming a silicon trinitride layer with a thickness of 0.05 μm to 0.15 μm on the silicon nitride layer using a chemical vapor phase method, and then forming a silicon monoxide layer with a thickness of 0.2 μm to 1.2 μm on the silicon trinitride layer or the silicon nitride layer using a chemical vapor phase method.

[0057] The eighth type of fabrication method for protective layer 42 involves first forming a silicon monoxide layer with a thickness of 0.2 μm to 1.2 μm using chemical vapor deposition (PECVD), then forming a silicon dioxide layer with a thickness of 0.5 μm to 1 μm on the silicon monoxide layer using spin-coating, then forming a silicon trinitride layer with a thickness of 0.2 μm to 1.2 μm on the silicon dioxide layer using chemical vapor deposition, then forming a silicon mononitride layer with a thickness of 0.2 μm to 1.2 μm on the silicon trioxide layer using chemical vapor deposition, and finally forming a silicon tetroxide layer with a thickness of 0.2 μm to 1.2 μm on the silicon nitride layer using chemical vapor deposition.

[0058] The ninth type of fabrication method for protective layer 42 involves first forming a silicon monoxide layer with a thickness of 0.2 μm to 2 μm using high-density plasma chemical vapor deposition (HDP-CVD), then forming a silicon mononitride layer with a thickness of 0.2 μm to 1.2 μm on top of the silicon monoxide layer using chemical vapor deposition, and finally forming a silicon dioxide layer with a thickness of 0.5 μm to 2 μm on top of the silicon nitride layer using high-density plasma chemical vapor deposition (HDP-CVD).

[0059] The tenth type of fabrication method for the protective layer 42 involves first forming a silicon monoxide layer with a thickness of 0.2 μm to 1.2 μm using a chemical vapor phase method, then forming another silicon monoxide layer with a thickness of 0.2 μm to 1.2 μm on the silicon mononitride layer using the chemical vapor phase method, and finally forming a silicon dinitride layer with a thickness of 0.2 μm to 1.2 μm on the silicon oxide layer using the chemical vapor phase method.

[0060] The thickness of the protective layer 42 is generally 0.35 μm or more, and under favorable conditions, the thickness of the silicon nitride layer is generally 0.3 μm or more.

[0061] After the protective layer 42 is completed, as shown in Figure 4a, a first polymer layer 46 with a thickness of 3 μm to 50 μm is formed on the protective layer 42. This first polymer layer 46 has an insulating function, and its material is selected from thermoplastic plastics, thermosolid plastics, polyimide (PI), benzo-cyclo-butene (BCB), polyurethane, epoxy resin, poly-p-xylene polymers, welding mask materials, elastic materials, or porous dielectric materials. The installation method for this first polymer layer 46 includes hot lamination dry film method, screen printing, or spin coating method. Then, as shown in Figure 4b, an etching method is used to create a design on this first polymer layer 46, exposing numerous openings 48 on the pad 44 on the semiconductor substrate 30. It should be noted that if the first polymer layer 46 is a photosensitive material, the first polymer layer 46 is stylized using a photolithography process. If the first polymer layer 46 is not a photosensitive material, the first polymer layer 46 is stylized using a photolithography process and etching process.

[0062] After the first polymer layer 46 is shaped, it is heated to a temperature of 200°C to 320°C by baking, microwave heating, or infrared heating, or heated to a temperature of 320°C to 450°C, to cure the first polymer layer 46. After curing, the volume of the first polymer layer 46 is reduced, and the water content of the first polymer layer 46 is 1% or less. This water content is such that the weight change rate of the first polymer layer 46 at a temperature of 425°C to 450°C is 1% or less.

[0063] As shown in Figure 5, a first adhesion / barrier / seed layer 50 with a thickness of 400 Å to 7000 Å is formed on the first polymer layer 46 and the pad using a sputtering method. The material of this first adhesion / barrier layer 50 is one or a combination of titanium metal, titanium nitride, titanium tungsten alloy, tantalum metal layer, chromium, chromium copper alloy, or tantalum nitride, and at least one of these is used. A seed layer is formed on top of the first adhesion / barrier layer 50. This seed layer is useful for installing the next metal wire, so the material of the seed layer changes depending on the material of the next metal wire. A seed layer is formed on top of all adhesion / barrier layers in subsequent embodiments.

[0064] For metal wires with a copper seed layer formed by electroplating, copper is the best material for the seed layer. When electroplating silver metal wires, silver is the best material for the seed layer. When electroplating palladium metal wires, palladium is the best material for the seed layer. When electroplating platinum metal wires, platinum is the best material for the seed layer. When electroplating rhodium metal wires, rhodium is the best material for the seed layer. When electroplating ruthenium metal wires, ruthenium is the best material for the seed layer. When electroplating rhenium metal wires, rhenium is the best material for the seed layer. When electroplating nickel metal wires, nickel is the best material for the seed layer.

[0065] Next, as shown in Figure 6a, a first stylized hardened photoresist layer 54 is formed on the seed layer on the first adhesion / inhibition layer 50, and this first stylized hardened photoresist layer 54 is exposed on the seed layer on the first adhesion / inhibition layer 50 in part by several openings 56, and this first stylized hardened photoresist layer 54 is removed by forming these openings 56 using a 1X stepper or scanner or better machine. Then, the seed layer on the first adhesive / inhibiting layer 50 within the opening 36 is exposed, and a first metal layer 58 with a thickness of 1 μm to 50 μm is electroplated onto it. A better thickness for this first metal layer 58 is between 2 μm and 30 μm. The first metal layer 58 is connected to the thin connecting structure 34. The material of this first metal layer 58 is one or a combination of gold, copper, silver, palladium, platinum, rhodium, ruthenium, rhenium, or nickel, or at least one of these materials. When this first stylized hardened photoresist layer 54 is removed, a first RDL line layer 60 is formed. It should be noted that this first RDL line layer 60 is mainly formed on the first metal layer 58 above the opening 48, and also extends onto part of the first polymer layer 46. Rather than simply being formed on the opening 48, the extended first metal layer 58 helps in the installation of the next line.

[0066] As shown in Figure 6b, a second stylized hardened photoresist layer 62 is then formed on the seed layer on the first RDL line layer 60 and the first adhesion / inhibition layer 50, and this second stylized hardened photoresist layer 62 exposes the first metal layer 58 of the first RDL line layer 60 through several openings 64. Then, as shown in Figure 6c, a second metal layer 66 with a thickness of 20 μm to 300 μm, formed by electroplating, is formed within these openings 64, and the maximum width of this second metal layer 66 is 3 μm to 50 μm, and the material of this second metal layer 66 is one or a combination of gold, copper, silver, palladium, platinum, rhodium, ruthenium, rhenium, or nickel, or at least one of these, and the better thickness of this second metal layer 66 is between 30 μm and 100 μm.

[0067] The material of this second metal layer 66 is copper, and the best first layer of the first RDL transmission layer 60 is copper; the material of this second metal layer 66 is silver, and the best first layer of the first RDL transmission layer 60 is silver; the material of this second metal layer 66 is palladium, and the best first layer of the first RDL transmission layer 60 is palladium; the material of this second metal layer 66 is platinum, and the best first layer of the first RDL transmission layer 60 is platinum; the material of this second metal layer 66 is rhodium, and the best first layer of the first RDL transmission layer 60 is rhodium; the material of this second metal layer 66 is ruthenium, and the best first layer of the first RDL transmission layer 60 is ruthenium; the material of this second metal layer 66 is rhenium, and the best first layer of the first RDL transmission layer 60 is rhenium; the material of this second metal layer 66 is nickel, and the best first layer of the first RDL transmission layer 60 is nickel.

[0068] As shown in Figure 6d, the next step is to remove the second patterned hardened photoresist layer 62, and similarly, use hydrogen peroxide to etch away the first tack / inhibitory layer 50 beneath the first metal layer 58. In addition to hydrogen peroxide, an iodine-containing etching solution, such as potassium iodide, may also be used. As shown in Figure 6e, this step of removing the seed layer and the first tack / inhibitory / seed layer 50 beneath the first metal layer 58 may be performed after removing the second patterned hardened photoresist layer 62 or the first patterned hardened photoresist layer 54.

[0069] As shown in Figures 7a and 7b, after removing the first adhesive / inhibiting layer 50 beneath the first metal layer 58, each second metal layer 66, i.e., the metal column 68 defining the cost invention, has a maximum width Hw divided by its height Ht, which is less than 4, and this value can also be less than 3 or 2. The maximum width of this metal column 68 is between 3 μm and 50 μm. This metal column 68 is a small column, unlike the metal layer or track layer described above, and the distance Hb between the centers of adjacent metal columns 68 is between 10 μm and 250 μm, and it is also possible to reduce it to better spacing distances of 10 μm to 200 μm, 10 μm to 175 μm, and 10 μm to 150 μm. Figure 7b shows a top view of this metal column 68 installed in the second metal layer 66. As is clearly visible in the diagram, this metal column 68 is not formed on the RDL track layer 60 above the opening 48, but rather on an area extending from the RDL track layer 60.

[0070] As shown in Figure 8a, a second polymer layer 70 covers the metal column 68 on the semiconductor substrate 30. The material of this second polymer layer 70 is selected from thermoplastic plastics, thermosolid plastics, polyimide (PI), benzo-cyclo-butene (BCB), polyurethane, epoxy resin, poly-p-xylene polymers, welding mask materials, elastic materials, or porous dielectric materials. The installation method for this second polymer layer 70 is either screen printing or spin coating. Referring to Figure 8b, when installed by screen printing, numerous openings 72 are directly formed within the second polymer layer 70 and exposed at the top of the metal column 68. When the second polymer layer 70 is installed by spin coating, numerous openings 72 are formed through a single stylization step before being exposed at the top of the metal column 68. When the second polymer layer 70 is installed by spin coating, the openings 72 are formed by lithography etching. As shown in Figure 8c, in addition to the opening 72, the metal column 68 can also be exposed by polishing. However, before performing the polishing step, the second polymer layer 70 is first cured, and then the second polymer layer 70 is polished by chemical physical polishing (CMP) to expose the metal column 68. The curing step can be performed using baking, microwave heating, or infrared heating.

[0071] It should be explained beforehand that many of the embodiments are extensions of the structures shown in Figures 8b and 8c. For the present invention, these two figures show a large number of metal columns 68 formed on the semiconductor base 30, with a fine pitch between adjacent metal columns, where the spacing is between 10 μm and 250 μm, and when the maximum width Hw of the metal column 68 is divided by its height Ht, it is less than 4. Therefore, all of the following embodiments involve modifications to these metal columns 68, and the first embodiment is based on the structure shown in Figure 8c.

[0072] As shown in Figure 9, a third polymer layer 74 is formed on the second polymer layer 70 using a coating method, and multiple openings 72 are formed in this third polymer layer 74 in a stylization step. This stylization step of the third polymer layer 74 is performed using lithography or lithography etching. Alternatively, the third polymer layer 74, stylized in dry film form, is hot-laminated onto the second polymer layer 70, or the third polymer layer 74 is formed on the second polymer layer 70 using a screen printing method. The material of this third polymer layer 74 is selected from thermoplastic plastics, thermosolid plastics, polyimide (PI), benzo-cyclo-butene (BCB), polyurethane, epoxy resin, poly-p-xylene polymers, welding mask materials, elastic materials, or porous dielectric materials.

[0073] As shown in Figure 10a, a second tack / inhibitory layer 78 with a thickness of 400 Å to 7000 Å is formed on the surface of the third polymer layer 74 and the top end of the metal column 68 by sputtering. The material of this second tack / inhibitory layer 78 is one of the following, or a combination thereof: titanium metal, titanium nitride, titanium tungsten alloy, tantalum metal layer, chromium, chromium copper alloy, or tantalum nitride. At least one of these materials is used as a seed layer formed on top of the second tack / inhibitory layer 78. Next, as shown in Figure 10b, a third stylized hardened photoresist layer 82 is formed as a seed layer for the second tack / inhibitory layer 78. This third stylized hardened photoresist layer 82 is of positive photoresist type, and several openings 83 of this third stylized hardened photoresist layer 82 are exposed on and around the openings 76 to the seed layer of the second tack / inhibitory layer 78.

[0074] Next, as shown in Figure 10c, a third metal layer 84 is formed on a seed layer on the second adhesive / inhibiting layer 78, exposed within the opening 83, using an electroplating method. The material of this third metal layer 84 is one of gold, copper, silver, palladium, platinum, rhodium, ruthenium, rhenium, or nickel, or a combination thereof, with at least one of these materials being used. Next, as shown in Figure 10d, the second adhesive / inhibiting layer 78 beneath the third metal layer 84 is etched away using hydrogen peroxide. In addition to hydrogen peroxide, an iodine-containing etching solution, such as potassium iodide, may also be used. It should be noted that the thickness of this third metal layer 84 formed by plating varies. Differences in the material and thickness of the third metal layer 84 result in different types and applications when the semiconductor substrate 30 is connected to an external circuit. In other words, the thickness of the third stylized hardened photoresist layer 82, the width of the aperture 83, and the formation position of the aperture 82 will change depending on the application, and the third metal layer 84 will have different thickness, position, and material due to electroplating. The above external circuitry includes flexible substrates, semiconductor chips, printed circuit boards, ceramic substrates, or glass substrates.

[0075] In this embodiment, the third metal layer 84 is formed in the form of a bump, pad, RDL, or solder. As shown in Figure 10d above, the material of the third metal layer 84 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, and the thickness (Ha) of the formed third metal layer 84 is between 5 μm and 30 μm. A better thickness is between 10 μm and 25 μm, so this third metal layer 84 is defined as a bump 86. The distance between the centers of adjacent bumps 86 is between 250 μm, and it is also possible to reduce the distance to a better distance of 200 μm or 150 μm. Also, as shown in Figure 11, the semiconductor base 30 is cut, and the semiconductor base 30 is formed into multiple semiconductor units 88, and the bumps 86 on each semiconductor unit 88 can be connected to an external circuit by forming an ACF.

[0076] As shown in Figures 12a and 12b, the material of the third metal layer 84 is one of solder, tin-lead alloy, tin-silver-copper alloy, or lead-free solder, and the thickness (Ha) of the formed third metal layer 84 is between 20 μm and 150 μm, with a better thickness being between 30 μm and 105 μm. Next, as shown in Figure 12c, when the semiconductor substrate 30 is heated and the third metal layer 84 is heated, it melts into a spherical shape, and this spherically molten third metal layer 84 is defined as a tin ball 92, and the distance between the centers of adjacent tin balls 92 is between 250 μm, and it is also possible to reduce the distance to a better distance of 200 μm or 150 μm. The third method for the third metal layer 84 involves forming a copper layer with a thickness of 1 μm to 100 μm, formed by electroplating, within the opening 83 of the third stylized hardened photoresist layer 82; then, a nickel layer with a thickness of 1 μm to 10 μm, formed by electroplating, is located above the copper layer; and finally, a tin layer, tin-silver layer, or tin-silver-copper alloy layer with a thickness of 20 μm to 150 μm, formed by electroplating, is located above the nickel layer.

[0077] Then, the semiconductor base 30 is cut as shown in Figure 12d to form a plurality of semiconductor units 88, and the tin balls 92 on each semiconductor unit 88 can be bonded to an external substrate 94, which is a semiconductor chip, printed circuit board, ceramic substrate or glass substrate.

[0078] As shown in Figure 12e, when the tin balls 92 on the semiconductor unit 88 are bonded to the external substrate 94, a fourth polymer layer 96 is first formed on the substrate 94 before the semiconductor unit 88 is bonded to the external substrate 94. The material of this fourth polymer layer 96 is selected from thermoplastic plastics, thermosolid plastics, polyimide (PI), benzo-cyclo-butene (BCB), polyurethane, epoxy resin, poly-p-xylene polymers, welding mask materials, elastic materials, or porous dielectric materials. The fourth polymer layer 96 is formed by hot laminating a stylized dry film onto the substrate 94, or by hot laminating a photosensitive dry film onto the substrate 94 and then stylizing the photosensitive dry film using a lithography method, or by screen printing to form the fourth polymer layer 96 on the substrate 94, or by spin coating to form a photosensitive thin film on the substrate 94, or by lithography to form a photosensitive dry film or by spin coating to form a non-photosensitive thin film on the substrate 94 and then stylizing the non-photosensitive thin film using a lithographic etching method. After the tin balls 92 on the semiconductor unit 88 are bonded to the substrate 94, they are heated to cure the fourth polymer layer 96, and this heating step can be performed using methods such as baking, microwave heating, or infrared heating.

[0079] As shown in Figures 13a and 13b, the material of the third metal layer 84 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, and the thickness (Ha) of the formed third metal layer 84 is between 1 μm and 15 μm, with a better thickness being between 2 μm and 10 μm. This third metal layer 84 is defined as a pad 98, and the distance between the centers of adjacent pads 98 is between 250 μm, and it is also possible to reduce the distance to a better 200 μm or 150 μm. This pad 98 forms a single wire during the wire manufacturing process and connects to an external circuit.

[0080] As shown in Figures 14a and 14b, the material of the third metal layer 84 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, and the thickness (Ha) of the formed third metal layer 84 is between 5 μm and 30 μm, with a better thickness being between 10 μm and 25 μm. Furthermore, the third metal layer 84 is formed not only on the opening 76 of the third polymer layer 74, but also on the second adhesive / inhibiting layer 78 to the side of the opening 76. This third metal layer 84 is defined as the RDL layer 100, and this RDL layer 100 forms a single wire during the wire fabrication process and connects to the external circuit. It should be emphasized that the third metal layer 84 to the side of the opening 76 functions similarly to a pad 98, and this eccentric design prevents the wire fabrication process from becoming difficult due to insufficient wire area when the dimensions of the pad 98 are too small.

[0081] The applications of bumps, pads, RDLs, and solder shown in Figures 9 to 14b of this embodiment are all extensions of the structure in Figure 8c. However, these applications can also be directly extended from the structure in Figure 8c in the same way. This is because the structure in Figure 9 is formed from the third polymer layer 74 of the structure in Figure 8c, and this third polymer layer 74 is stylized with numerous openings. However, in the structure in Figure 8b, the metal column 68 is not exposed by polishing, but rather exposed with numerous openings in a stylized manner, and there is no need to install the third polymer layer 74. In other words, the structure in Figure 8b appears to be the structure in Figure 8c with the third polymer layer 74 added. Therefore, the explanation of the applications of bumps, pads, RDLs, and solder shown in Figures 10a to d, 11, 12a to e, 13a to b, and 14a to b, which are extensions of Figure 9, will be omitted.

[0082] (Second embodiment) This embodiment is an extension of Figure 8c of the first embodiment. Referring to Figure 15a, the top of the metal column 68 in this embodiment is a single gold layer 102, with a thickness of 1 μm to 30 μm. A single wire 104 is formed on the metal 102 of the metal column 68 during the wire manufacturing process and connected to the external circuit. It should be noted that the metal below the gold layer 102 is a copper layer 104 and a nickel layer 106 (copper-nickel-gold structure), with a thickness of 10 μm to 100 μm for the copper layer 104 and a thickness of 1 μm to 30 μm for the nickel layer 106. Alternatively, as shown in Figure 15b, the gold layer 102 is on top of the copper layer 104, with a thickness of 1 μm to 30 μm. Or, as shown in Figure 15c, the material of the entire metal column 68 is gold, with a thickness of 10 μm to 100 μm.

[0083] (Third embodiment) This embodiment is an extension of the first embodiment shown in Figure 8c. Referring to Figure 16a, one third adhesive / inhibitory layer 105 is formed on the second polymer layer 70, a seed layer is formed on the third adhesive / inhibitory layer 105, as shown in Figure 16b, one fourth stylized hardened photoresist layer 110 is formed on the third adhesive / inhibitory layer 105, and this fourth stylized hardened photoresist layer 110 has a number of openings 112, of which at least one opening 112 is located above the metal column 68, and as shown in Figure 16c, this opening 112 is electroplated in a coil shape to form a fourth metal layer 114. The fourth metal layer 114, formed within the opening 112 of the photoresist layer 110, is made of gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, with a thickness of 1 μm to 30 μm. This fourth metal layer 114 is a composite metal layer, consisting of one copper layer with a thickness of 1 μm to 30 μm formed by electroplating, followed by one nickel layer with a thickness of 1 μm to 10 μm formed by electroplating on top of the copper layer, and finally, one gold layer with a thickness of 1 μm to 10 μm formed by electroplating on top of the nickel layer.

[0084] As shown in Figure 16d, after removing the fourth stylized hardened photoresist layer 110 and similarly removing the third adhesive / inhibiting layer 105 beneath the fourth stylized hardened photoresist layer 110 using a hydrogen peroxide or iodine-containing etching solution, as shown in Figure 16e, this fourth metal layer 114 takes on a coiled shape. This fourth metal layer 114 is defined as a first coil metal layer 116, and this first coil metal layer 116 is connected to the semiconductor substrate 30 through a metal column 68. As shown in Figure 16f, in addition to connecting to the semiconductor substrate 30, it is also possible to connect to an external circuit through the wire fabrication process (not shown). Furthermore, to protect this first coil metal layer 116 from damage and moisture intrusion, a protective layer 117 can be formed, the thickness of which the protective layer 117 is 5 μm to 25 μm. The material of this protective layer 117 is an organic or inorganic compound, composed of, for example, thermoplastic plastics, thermosolid plastics, polyimide (PI), benzo-cyclo-butene (BCB), polyurethane, epoxy resin, poly-p-xylene polymers, welding mask materials, elastic materials, porous dielectric materials, silicon oxide, silicon oxide compounds, silicon-phosphorus glass, silicon nitride, and silicon oxy-nitride (SiON). This first coil metal layer 116 is applied in the field of passive devices such as inductors, capacitors, and resistors.

[0085] Here, we list the applications of this first coil metal layer 116 in a capacitor passive device. Referring to Figure 16g, the first coil metal layer 116 covers a fifth polymer layer 118, the thickness of which is between 20 μm and 300 μm, and the material of this fifth polymer layer 118 is polyimide (PI). This second coil metal layer 120 can be connected to an external circuit. When a change occurs in the current of the external circuit, an induced electromotive force is generated through the second coil metal layer 120, and the first coil metal layer 116 senses this and transmits the resulting signal to the semiconductor substrate 30. This concludes the explanation of the fabrication of this passive device.

[0086] Using the electroplating method described above, it is also possible to form a single capacitor device 121 on the second polymer layer 70. As shown in Figure 16h, a low dielectric layer 121a with a thickness of 500 Å to 5000 Å is provided on the second polymer layer 70, and the material of this low dielectric layer 121a is titanium-titanium-tungsten alloy, tantalum, or tantalum nitride, and this low dielectric layer 121a is connected to a single metal column 68, and a high dielectric layer 121b is coated on the low dielectric layer 121a, and the material of this high dielectric layer 121b is a nitrogen oxide compound, silicon oxide (silicon The low-resistance metal layer 121c is formed on adjacent metal columns 68 by electroplating using an oxide compound or polyimide (PI). The low-dielectric layer 121a is formed in two ways: one method involves forming a tack / inhibitory layer with a thickness of 400 Å to 7500 Å on top of the second polymer layer 70 and the high-dielectric layer 121b, the tack / inhibitory layer being made of titanium, titanium-tungsten alloy, tantalum, or tantalum nitride; the other method involves forming a seed layer with a thickness of 500 Å to 5000 Å on top of the tack / inhibitory layer, followed by a copper layer with a thickness of 1 μm to 30 μm formed by electroplating on top of the seed layer, and then a nickel layer with a thickness of 1 μm to 10 μm formed by electroplating on top of the copper layer.

[0087] Alternatively, one adhesive / inhibiting layer with a thickness of 400 Å to 7500 Å is placed above the second polymer layer 70 and the high dielectric layer 121b, followed by another seed layer with a thickness of 500 Å to 5000 Å above the adhesive / inhibiting layer, and finally a gold layer with a thickness of 1 μm to 30 μm formed by electroplating is placed above the gold material seed layer. When a voltage is applied to adjacent metal columns 68, a large voltage difference is formed above and below the high dielectric layer 121b, and this structure has a capacitor function. Finally, to protect this capacitor device 121 from damage, a protective layer 121d can be applied over the low-resistance metal layer 121c and the second polymer layer 70.

[0088] (Fourth embodiment) This embodiment is an extension of the first embodiment shown in Figure 8b, and as shown in Figure 17a, a fourth adhesion / inhibition layer 122 is formed on the second polymer layer 70, the material of which the fourth adhesion / inhibition layer 122 is titanium, titanium-tungsten alloy, tantalum, or tantalum nitride, the material of which the seed layer is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, and as shown in Figure 17b, a fifth stylized hardened photoresist layer 126 is formed on the fourth adhesion / inhibition layer A fifth stylized hardened photoresist layer 126 is formed on 122, and there are numerous openings 128 within this fifth stylized hardened photoresist layer 126, two of which are located above the metal column 68. As shown in Figure 17c, a fifth metal layer 130 with a thickness of 30 μm to 120 μm, formed by electroplating, is formed on the fourth adhesive / inhibiting / seed layer 122 within the openings 128 of the fifth stylized hardened photoresist layer 126, and this fifth metal layer 130 has low resistance and is made of gold, silver, or copper, for example. Next, as shown in Figure 17d, the fifth stylized hardened photoresist layer 126 is removed, and similarly, the fourth adhesive / inhibiting layer 122 beneath the fifth stylized hardened photoresist layer 110 is removed using hydrogen peroxide or an iodine-containing etching solution. Then, this fifth metal layer 130 is connected to the two metal columns 68, and this fifth metal layer 130 is the current path between the two metal columns 68. A protective layer 132 is also added to protect against damage and moisture ingress. A double composite layer 70 and a fifth metal layer 130 can be formed on the fifth metal layer 130, the fifth metal layer 130 having a thickness of 1 μm to 30 μm, the fifth metal layer 130 being a composite metal layer, consisting of one copper layer with a thickness of 1 μm to 30 μm formed by electroplating, followed by one nickel layer with a thickness of 1 μm to 10 μm formed by electroplating on top of the copper layer, and finally one gold layer with a thickness of 1 μm to 10 μm formed by electroplating on top of the nickel layer.

[0089] The fifth metal layer 130 can be extended not only to form a continuous line but also to a multilayer line structure. As shown in Figure 17e, after forming a sixth polymer layer 134 on the second polymer layer 70 and the fifth metal layer 130, as shown in Figure 17f, the numerous openings of this sixth polymer layer 134 are stylized to expose the fifth metal layer 130, and as shown in Figure 17g, a fifth adhesive / inhibiting layer 136 is sputtered in sequence, the material of this fifth adhesive / inhibiting layer 136 is titanium, titanium-tungsten alloy, tantalum or tantalum nitride, etc., the material of this seed layer is gold, copper, silver, palladium, platinum, rhodium, ruthenium, rhenium, and as shown in Figure 17h, a sixth stylized hardened photoresist layer 140 is formed on top of this sixth stylized hardened photoresist Multiple openings in the photoresist layer 140 are exposed to the openings in the sixth polymer layer 134, and as shown in Figure 17i, a sixth metal layer 142 is formed on the sixth stylized hardened photoresist layer 140. The material of this sixth metal layer 142 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, and the thickness of this sixth metal layer 142 is from 1 μm to 30 μm. This sixth metal layer 142 is a composite metal layer, consisting of one copper layer with a thickness of 1 μm to 30 μm formed by electroplating, followed by one nickel layer with a thickness of 1 μm to 10 μm formed by electroplating on top of the copper layer, and finally one gold layer with a thickness of 1 μm to 10 μm formed by electroplating on top of the nickel layer.

[0090] As shown in Figure 17j, after removing the sixth stylized hardened photoresist layer 140 and the sixth metal layer 142, as well as the fifth adhesive / inhibiting layer 136 and the seed layer, as shown in Figure 17k, one seventh polymer layer 144 is formed on the sixth polymer layer 134 and the sixth metal layer 142. One of the seventh polymer layer 144, with a thickness of 10 μm to 25 μm, is stylized so that multiple openings in this seventh polymer layer 144 are exposed to the sixth metal layer 142, as shown in Figure 17l. As shown in Figure 17m, one wire is exposed to the sixth metal layer 142 during the wire fabrication process and connected to an external circuit.

[0091] (Fifth embodiment) This embodiment is an extension of Figure 8b of the first embodiment, and this embodiment is similar to the fourth embodiment. As shown in Figure 18, the formation method of this embodiment is the same as that of the fourth embodiment. The difference is that in the fourth embodiment, the fifth metal layer 130 is made of a low-resistance material, so current can flow through the fifth metal layer 130 quickly. However, in the fifth embodiment (see Figure 18), the seventh metal layer 146 is made of a high-resistance material, such as chromium / nickel alloy (Cr / Ni), titanium, or tungsten. Furthermore, the thickness of the seventh metal layer 146 is 1 μm to 3 μm. Therefore, in this embodiment, the seventh metal layer 146 is used as a resistive device.

[0092] (Sixth embodiment) The first to fifth embodiments described above are extensions of the structures shown in Figures 8b and 8c, while this embodiment is an extension of the structure shown in Figure 8a. As shown in Figures 19a and 19b, this embodiment utilizes an etching method to remove a portion of the second polymer layer 70 until a metal column 68 with a height of 1 μm to 150 μm is exposed. This exposed height is the distance from the top surface of the metal column to the top surface of the second polymer layer 70. If the material of the metal column 68 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, the optimal exposed height of the metal column 68 is between 15 μm and 30 μm. This metal column 68 is used as a protruding mass, and as shown in Figure 19c, the same cutting step is performed to cut this semiconductor base 30 into multiple semiconductor units 88. Similarly, the protruding mass 86 on each semiconductor unit 88 can be connected to an external circuit by forming an ACF.

[0093] If the material of the metal column 68 is solder, tin-lead alloy, tin-silver alloy, tin-silver-copper alloy, or lead-free solder, the optimal exposed height of the metal column 68 is between 50 μm and 100 μm. As shown in Figure 19d, the metal column 68 exposed to the outside is melted into a ball shape (solder-tin ball) in the same heating step, and then, as shown in Figure 19e, the same cutting step is performed to cut the semiconductor base 30 into multiple semiconductor units 88, the protruding masses 86 on each semiconductor unit 88 are joined to the external substrate, and a single eighth polymer layer 148 is formed between the semiconductor unit and the substrate to cover each ball-shaped protruding mass.

[0094] As shown in Figure 19f, if the material of the metal column 68 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, the optimal exposed height of the metal column 68 is between 1 μm and 15 μm. This exposed metal column 68 is used as a pad, which forms a single wire during the wire manufacturing process and connects to its metal layer and its polymer layer.

[0095] As shown in Figure 19g, if the material of the exposed metal column 68 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, and the exposed height is between 5000 Å and 10 μm, then a sixth tack / inhibitory layer 150 is formed on the second polymer layer 70 and the exposed surface of the metal column 68, the material of which this sixth tack / inhibitory layer 150 is titanium, titanium-tungsten alloy, tantalum, or tantalum nitride, and this seed layer is located above the sixth tack / inhibitory layer 150, the material of which this seed layer is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, and this sixth tack / inhibitory layer 150 has a thickness of 1000 Å to 7500 Å.

[0096] As shown in Figure 19h, one seventh stylized hardened photoresist layer 152 is formed on the sixth adhesive / inhibitory layer 150, with multiple openings in the seventh stylized hardened photoresist layer 152 exposed to the sixth adhesive / inhibitory layer 150. As shown in Figure 19i, one eighth metal layer 154 is formed within the openings of the seventh stylized hardened photoresist layer 152. As shown in Figure 19j, the seventh stylized hardened photoresist layer 152 is removed, and the sixth adhesive / inhibitory / seed layer 150 is also removed except for the area under the eighth metal layer 154. This eighth metal layer 154 connects the metal lines and connects between the two metal columns 68. The eighth metal layer 154 is made of gold, copper, silver, palladium, platinum, rhodium, ruthenium, and rhenium, with a thickness of 1 μm to 30 μm. This eighth metal layer 154 is a composite metal layer, consisting of one copper layer with a thickness of 1 μm to 30 μm formed by electroplating, followed by one nickel layer with a thickness of 1 μm to 10 μm formed by electroplating on top of the copper layer, and finally, one gold layer with a thickness of 1 μm to 10 μm formed by electroplating on top of the nickel layer.

[0097] As shown in Figure 19k, the final layer is a protective layer 154 to protect the eighth metal layer 154 and the second polymer layer 70 from damage. The material of the protective layer 154 is selected from thermoplastic plastics, thermosolid plastics, polyimide (PI), benzo-cyclo-butene (BCB), polyurethane, epoxy resin, poly-p-xylene polymers, welding mask materials, elastic materials, porous dielectric materials, silicon oxide, silicon oxide compounds, silicon phosphide glass, silicon oxide, and silicon oxy-nitride.

[0098] This etching method, which exposes the metal column 68, can be applied not only to the connection of the aforementioned protruding blocks, pads, and metals along the lines, but also to coil structures, capacitor structures, and resistor structures. The manufacturing steps are similar to those of the above embodiment and will not be explained again.

[0099] (Seventh Example) The structure of this embodiment is similar to that of Figure 8c, the only difference being the manufacturing process of the metal column 68 and the second polymer layer 70. As shown in Figure 20a, after forming the first RDL layer 60 on the semiconductor substrate 30, a ninth patterned hardened photoresist layer 158 is formed on the first RDL layer 60 and the first adhesive / inhibiting / seed layer 50. Multiple openings of this ninth patterned hardened photoresist layer 158 are exposed on the first RDL layer 60, and the opening depth of the ninth patterned hardened photoresist layer 158 is between 20 μm and 300 μm.

[0100] The material of this ninth stylized hardened photoresist layer 158 is selected from thermoplastic plastics, thermosolid plastics, polyimide (PI), benzo-cyclo-butene (BCB), polyurethane, epoxy resin, poly-p-xylene polymers, welding mask materials, elastic materials, or porous dielectric materials. Furthermore, the method for forming the ninth patterned hardened photoresist layer 158 involves hot laminating a patterned dry film onto the semiconductor substrate 30, or hot laminating a photosensitive dry film onto the semiconductor substrate 30 and then patterning the photosensitive dry film using a lithography method, or hot laminating a non-photosensitive thin film onto the semiconductor substrate 30 and then patterning the non-photosensitive thin film using a lithography method, or forming the ninth patterned polymer layer 158 on the semiconductor substrate 30 using a screen printing method, or forming a photosensitive thin film on the semiconductor substrate 30 using a spin coating method, or forming a photosensitive dry film or a non-photosensitive thin film on the semiconductor substrate 30 using a lithography method, or patterning the non-photosensitive thin film using a lithography etching method.

[0101] As shown in Figure 20b, a seventh tack / inhibitory layer 160 with a thickness of 400 Å to 7000 Å is formed on the ninth stylized polymer layer 158 and the first RDL layer 60 within the opening of the ninth stylized polymer layer 158. The material of this seventh tack / inhibitory layer 160 is titanium, titanium-tungsten alloy, tantalum, or tantalum nitride, and this seed layer is located above the seventh tack / inhibitory layer 160. The material of this seed layer is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium, and this sixth tack / inhibitory layer 150 has a thickness of 1000 Å to 7500 Å.

[0102] As shown in Figure 20c, a ninth metal layer 162 is formed on the seventh adhesive / inhibiting / seed layer 160 using the damascene method, and then the openings of the ninth patterned polymer layer 158 are filled. The material of this eighth metal layer 154 is gold, copper, silver, palladium, platinum, rhodium, ruthenium, or rhenium. The thickness of this ninth metal layer 162 is 1 μm to 30 μm. This ninth metal layer 162 is a composite metal layer, consisting of one copper layer with a thickness of 1 μm to 30 μm formed by electroplating, followed by one nickel layer with a thickness of 1 μm to 10 μm formed by electroplating on top of the copper layer, and finally one gold layer with a thickness of 1 μm to 10 μm formed by electroplating on top of the nickel layer.

[0103] As shown in Figure 20d, the ninth metal layer 162 and the seventh adhesive / inhibiting layer 160 are removed in a single polishing step, except for the openings in the ninth stylized polymer layer 158, completing the installation of the metal column 68. When the maximum width Hw of this metal column 68 is divided by its height Ht, the column is less than 4, and the maximum width of this metal column 68 is between 3 μm and 50 μm. Furthermore, the distance Hb between adjacent metal columns 68 is between 10 μm and 250 μm.

[0104] Since the structure of the metal column 68 formed by the damascene method is very similar to the structure shown in Figure 8c above, the subsequent steps for fabricating the ninth stylized polymer layer 158 and other devices on the metal column 68 are the same.

[0105] As shown in Figures 21a to 21d, this figure shows the fabrication of the protruding mass, pad, tin ball and RDL layer on the ninth stylized polymer layer 158 and the metal column 68. The fabrication process was explained in the above example, so here only the final completed structure is shown, and the fabrication process is omitted.

[0106] As shown in Figures 22 to 25, this figure shows the ninth stylized polymer layer 158 and the metal column 68 with metal interconnecting coils, capacitor devices, and resistor devices attached. The manufacturing process was explained in the above example, so here only the final completed structure is shown, and the manufacturing process is omitted.

[0107] This invention provides stress relief and miniaturization of the contact window structure spacing. Based on this invention, it is possible to achieve a spacing of 250 μm or less and limit the number of pinholes to 400 or less. Furthermore, improvements in IC function are observed, and the resistance and load of the IC metal connection lines of low-power IC elements can be significantly reduced.

[0108] The above discussion has been used to illustrate the features of the present invention through examples, and its purpose is merely to enable those familiar with this art to fully understand the content of the present invention and implement it accordingly, without limiting the scope of the claims. Therefore, any completed equivalent invention, achieved through modifications or alterations without departing from the spirit set forth in other inventions, should be included in the claims described below. [Brief explanation of the drawing]

[0109] [Figure 1] Cross-sectional diagram of the conventional technology. [Figure 2] A cross-sectional diagram illustrating a semiconductor substrate according to the first embodiment of the present invention. [Figure 3] A cross-sectional diagram illustrating the installation of a thin connection structure and protective layer on a semiconductor substrate according to the first embodiment of the present invention. [Figure 4a] A cross-sectional diagram illustrating the first polymerized layer formed in the first embodiment of the present invention. [Figure 4b]A cross-sectional diagram illustrating the first polymerized layer formed in the first embodiment of the present invention. [Figure 5] A cross-sectional diagram illustrating the first adhesive / inhibiting layer formed in the first embodiment of the present invention. [Figure 6a] A cross-sectional diagram illustrating the first RDL layer and metal column formed in the first embodiment of the present invention. [Figure 6b] A cross-sectional diagram illustrating the first RDL layer and metal column formed in the first embodiment of the present invention. [Figure 6c] A cross-sectional diagram illustrating the first RDL layer and metal column formed in the first embodiment of the present invention. [Figure 6d] A cross-sectional diagram illustrating the first RDL layer and metal column formed in the first embodiment of the present invention. [Figure 6e] A cross-sectional diagram illustrating the first RDL layer and metal column formed in the first embodiment of the present invention. [Figure 7a] An explanatory diagram of the physical properties of a metal column formed in the first embodiment of the present invention. [Figure 7b] A plan view of the physical properties of a metal column formed according to the first embodiment of the present invention. [Figure 8a] A cross-sectional diagram illustrating the second polymer layer formed in the first embodiment of the present invention. [Figure 8b] A cross-sectional diagram illustrating the opening of the second polymer layer formed in the first embodiment of the present invention. [Figure 8c] A cross-sectional diagram illustrating the polished second polymer layer according to the first embodiment of the present invention. [Figure 9] A cross-sectional diagram illustrating the third polymer layer formed in the first embodiment of the present invention. [Figure 10a] A cross-sectional diagram illustrating the third metal layer formed in the first embodiment of the present invention. [Figure 10b] A cross-sectional diagram illustrating the third metal layer formed in the first embodiment of the present invention. [Figure 10c] A cross-sectional diagram illustrating the third metal layer formed in the first embodiment of the present invention. [Figure 10d] A cross-sectional diagram illustrating the third metal layer formed in the first embodiment of the present invention. [Figure 11] A cross-sectional diagram illustrating the semiconductor substrate cutting process in the first embodiment of the present invention. [Figure 12a]A cross-sectional diagram illustrating the tin ball formed in the first embodiment of the present invention. [Figure 12b] A cross-sectional diagram illustrating the tin ball formed in the first embodiment of the present invention. [Figure 12c] A cross-sectional diagram illustrating the tin ball formed in the first embodiment of the present invention. [Figure 12d] A cross-sectional diagram illustrating the cutting of the semiconductor substrate and bonding to the substrate according to the first embodiment of the present invention. [Figure 12e] A cross-sectional diagram illustrating the cutting of the semiconductor substrate and bonding to the substrate according to the first embodiment of the present invention. [Figure 13a] A cross-sectional diagram illustrating the manufacturing process of a metal columnar wire according to the first embodiment of the present invention. [Figure 13b] A cross-sectional diagram illustrating the manufacturing process of a metal columnar wire according to the first embodiment of the present invention. [Figure 14a] A cross-sectional diagram illustrating the RDL layer formed in the first embodiment of the present invention on a metal column. [Figure 14b] A cross-sectional diagram illustrating the RDL layer formed in the first embodiment of the present invention on a metal column. [Figure 15a] A cross-sectional diagram illustrating the fabrication of a copper / nickel / gold or copper / gold metal columnar wire according to a second embodiment of the present invention. [Figure 15b] A cross-sectional diagram illustrating the fabrication of a copper / nickel / gold or copper / gold metal columnar wire according to a second embodiment of the present invention. [Figure 15c] A cross-sectional diagram illustrating the fabrication of a copper / nickel / gold or copper / gold metal columnar wire according to a second embodiment of the present invention. [Figure 16a] A cross-sectional diagram illustrating the first coil metal layer formed in the third embodiment of the present invention on a metal column. [Figure 16b] A cross-sectional diagram illustrating the first coil metal layer formed in the third embodiment of the present invention on a metal column. [Figure 16c] A cross-sectional diagram illustrating the first coil metal layer formed in the third embodiment of the present invention on a metal column. [Figure 16d] A cross-sectional diagram illustrating the first coil metal layer formed in the third embodiment of the present invention on a metal column. [Figure 16e] A cross-sectional diagram illustrating the first coil metal layer formed in the third embodiment of the present invention on a metal column. [Figure 16f] A cross-sectional diagram illustrating the first coil metal layer formed in the third embodiment of the present invention on a metal column. [Figure 16g] A cross-sectional diagram illustrating the second coil metal layer formed in the third embodiment of the present invention. [Figure 16h] This is a cross-sectional diagram illustrating a capacitor device formed according to the third embodiment of the present invention on a metal column. [Figure 17a] A cross-sectional diagram illustrating the connection between the metal layer and two metal columns formed according to the fourth embodiment of the present invention. [Figure 17b] A cross-sectional diagram illustrating the connection between the metal layer and two metal columns formed according to the fourth embodiment of the present invention. [Figure 17c] A cross-sectional diagram illustrating the connection between the metal layer and two metal columns formed according to the fourth embodiment of the present invention. [Figure 17d] A cross-sectional diagram illustrating the connection between the metal layer and two metal columns formed according to the fourth embodiment of the present invention. [Figure 17e] A cross-sectional diagram illustrating the multilayer track layer formed in the fourth embodiment of the present invention on a metal column. [Figure 17f] A cross-sectional diagram illustrating the multilayer track layer formed in the fourth embodiment of the present invention on a metal column. [Figure 17g] A cross-sectional diagram illustrating the multilayer track layer formed in the fourth embodiment of the present invention on a metal column. [Figure 17h] A cross-sectional diagram illustrating the multilayer track layer formed in the fourth embodiment of the present invention on a metal column. [Figure 17i] A cross-sectional diagram illustrating the multilayer track layer formed in the fourth embodiment of the present invention on a metal column. [Figure 17j] A cross-sectional diagram illustrating the multilayer track layer formed in the fourth embodiment of the present invention on a metal column. [Figure 17k] A cross-sectional diagram illustrating the multilayer track layer formed in the fourth embodiment of the present invention on a metal column. [Figure 17l] A cross-sectional diagram illustrating the multilayer track layer formed in the fourth embodiment of the present invention on a metal column. [Figure 17m] A cross-sectional diagram illustrating the multilayer track layer formed in the fourth embodiment of the present invention on a metal column. [Figure 18]A cross-sectional diagram illustrating a resistive device formed according to the fifth embodiment of the present invention on a metal column. [Figure 19a] A cross-sectional diagram showing the removal of a portion of the second polymer layer using the etching method employed in the sixth embodiment of the present invention. [Figure 19b] A cross-sectional diagram showing the removal of a portion of the second polymer layer using the etching method employed in the sixth embodiment of the present invention. [Figure 19c] A cross-sectional diagram illustrating the semiconductor substrate cutting process in the sixth embodiment of the present invention. [Figure 19d] A cross-sectional diagram illustrating the tin ball and cut step formed in the sixth embodiment of the present invention. [Figure 19e] A cross-sectional diagram illustrating the tin ball and cut step formed in the sixth embodiment of the present invention. [Figure 19f] A cross-sectional diagram illustrating a pad formed according to the sixth embodiment of the present invention. [Figure 19g] A cross-sectional diagram illustrating the connection between the metal layer and two metal columns formed according to the sixth embodiment of the present invention. [Figure 19h] A cross-sectional diagram illustrating the connection between the metal layer and two metal columns formed according to the sixth embodiment of the present invention. [Figure 19i] A cross-sectional diagram illustrating the connection between the metal layer and two metal columns formed according to the sixth embodiment of the present invention. [Figure 19j] A cross-sectional diagram illustrating the connection between the metal layer and two metal columns formed according to the sixth embodiment of the present invention. [Figure 19k] A cross-sectional diagram illustrating the connection between the metal layer and two metal columns formed according to the sixth embodiment of the present invention. [Figure 20a] This is a cross-sectional diagram illustrating the ninth stylized polymer layer formed in the seventh embodiment of the present invention on a semiconductor substrate. [Figure 20b] A cross-sectional diagram illustrating a metal column formed by the damascene method according to the seventh embodiment of the present invention. [Figure 20c] A cross-sectional diagram illustrating a metal column formed by the damascene method according to the seventh embodiment of the present invention. [Figure 20d] A cross-sectional diagram illustrating a metal column formed by the damascene method according to the seventh embodiment of the present invention. [Figure 21a]A cross-sectional diagram illustrating the protruding mass, pad, tin ball, and RDL layer structure formed in another embodiment of the present invention. [Figure 21b] A cross-sectional diagram illustrating the protruding mass, pad, tin ball, and RDL layer structure formed in another embodiment of the present invention. [Figure 21c] A cross-sectional diagram illustrating the protruding mass, pad, tin ball, and RDL layer structure formed in another embodiment of the present invention. [Figure 21d] A cross-sectional diagram illustrating the protruding mass, pad, tin ball, and RDL layer structure formed in another embodiment of the present invention. [Figure 22] A cross-sectional diagram illustrating a freeway, coil, capacitor, and resistor device structure formed according to another embodiment of the present invention. [Figure 23] A cross-sectional diagram illustrating a freeway, coil, capacitor, and resistor device structure formed according to another embodiment of the present invention. [Figure 24] A cross-sectional diagram illustrating a freeway, coil, capacitor, and resistor device structure formed according to another embodiment of the present invention. [Figure 25] A cross-sectional diagram illustrating a freeway, coil, capacitor, and resistor device structure formed according to another embodiment of the present invention. [Explanation of Symbols]

[0110] 10: Post-passivation structure, 12: RDL layer, 14: Polymer layer, 16: Protective layer, 18: Semiconductor IC chip, 20: Pad, 22: Bevel, 30: Semiconductor base, 32: Electronic element, 34: Thin connection structure, 36: Thin insulating layer, 38: Thin line layer, 40: Through hole, 42: Protective layer, 44: Pad, 46: First polymer layer, 48: Opening, 50: First adhesive / inhibiting layer, 54: First stylized hardened photoresist layer, 56: Opening, 58: First metal layer, 60: First RDL layer, 62: Second stylized hardened photoresist layer, 64: Opening, 66: Second metal layer, 68: Metal column, 70: Second polymer layer, 72: Opening, 74: Third polymer layer, 76: Opening, 78: Second adhesive / inhibiting layer, 82: Third stylized hardened photoresist layer, 83: Opening, 84: Third metal layer, 86: Protruding mass, 88: Semiconductor unit, 92: Tin ball, 94: Substrate, 96: Fourth polymer layer, 98: Pad, 100: RDL layer, 102: Gold layer, 10 4: Copper layer, 105: Third tack / inhibition layer, 106: Nickel layer, 110: Fourth stylized hardened photoresist layer, 112: Aperture, 114: Fourth metal layer, 116: First coil metal layer, 117: Protective layer, 118: Fifth polymer layer, 120: Second coil metal layer, 121: Capacitor device, 121a: Low dielectric layer, 121b: Insulating layer, 121c: Low resistance metal layer, 121d: Protective layer, 122: Fourth tack / inhibition layer, 126: Fifth stylized hardened photoresist layer, 128: Opening, 130: Fifth metal layer, 132: Protective layer, 134: Sixth polymer layer, 136: Fifth tack / inhibitory layer, 140: Sixth stylized hardened photoresist layer, 142: Sixth metal layer, 144: Seventh polymer layer, 146: Seventh metal layer, 148: Eighth polymer layer, 150: Sixth tack / inhibitory layer, 152: Seventh stylized hardened photoresist layer, 154: Eighth metal layer, 156: Protective layer, 158: Ninth stylized polymer layer, 160: Seventh tack / inhibitory layer, 162: Ninth metal layer The invention described in the original claims of this application is listed below. [C1] A track device structure, It comprises a substrate, a first metal column, and a second metal column. The first metal column is located on a substrate, and when the maximum width of the first metal column is divided by the height of the first metal column, it is less than 4, and the height of the first metal column is between 20 μm and 300 μm. A line device structure characterized in that the second metal column is located on a substrate, the maximum width of the second metal column divided by the height of the second metal column is less than 4, the height of the first metal column is between 20 μm and 300 μm, and the distance from the center point of the first metal column to the center point of the second metal column is between 10 μm and 250 μm. [C2] The line device structure according to C1, characterized in that a first polymer layer having a thickness of 20 μm to 300 μm is formed on the substrate and covers the first metal column and the second metal column. [C3] The line device structure according to C1, characterized in that the first metal column comprises a gold layer with a thickness of 30 μm to 100 μm. [C4] The line device structure according to C1, characterized in that the first metal column comprises a copper layer with a thickness of 30 μm to 100 μm. [C5] The transmission line device structure according to C1, characterized in that a first metal column and a second metal column are connected by a metal connecting line. [C6] The substrate comprises a semiconductor substrate, a first metallic structure located on the semiconductor substrate, a protective layer located on a metal line and containing a silicon nitride compound, a second metallic structure located on the protective layer, and a first pad located within the protective layer through which an opening exposes the first metallic structure. The track device structure according to C1, wherein the second metal structure includes a second pad connected to the first pad, and the position of the first pad as seen from a top-down view is different from the position of the second pad as seen from a top-down view, and the first metal column is located on the second pad. [C7] The line device structure according to C1, comprising a protruding mass located on the first metal column, wherein the protruding mass is connected to a pre-formed external circuit, and the protruding mass comprises a gold layer with a thickness of 10 μm to 30 μm. [C8] The line device structure according to C1, comprising a protruding mass located on the first metal column, wherein the protruding mass is connected to a pre-formed external circuit, and the protruding mass comprises a tin solder layer with a thickness of 10 μm to 150 μm. [C9] The track device structure according to C1, comprising a pad located on the first metal column, wherein the maximum width of the pad is greater than the maximum width of the first metal column, and the pad is used to connect with a wire manufactured during the wire manufacturing process. [C10] The track device structure according to C1, characterized in that the top surface of the first metal column is used to connect with a wire manufactured during the wire manufacturing process. [C11] The line device structure according to C1, characterized by comprising a metal coil connecting the first metal column and the second metal column. [C12] The line device structure according to C1, comprising a second metal structure and a protruding mass, wherein the second metal structure comprises a pad connected to the first metal column, and the position of the pad as viewed from above is different from the position of the first metal column as viewed from above, the protruding mass is located on the pad and connected to a pre-formed external circuit, and the protruding mass comprises a gold layer with a thickness of 10 μm to 30 μm. [C13] The line device structure according to C1, comprising a second metal structure and a protruding mass, wherein the second metal structure is located on a substrate, the second metal structure includes a pad that connects to the first metal column, the position of the pad as viewed from above is different from the position of the first metal column as viewed from above, the protruding mass is located on the pad and connects to a pre-formed external circuit, and the protruding mass includes a tin solder layer with a thickness of 10 μm to 30 μm. [C14] The track device structure according to C1, comprising a second metal structure located on a substrate, wherein the second metal structure includes a pad that connects to the first metal column, and the position of the pad as seen from a top-down view is different from the position of the first metal column as seen from a top-down view, and the pad is used to connect to a wire manufactured during the wire manufacturing process. [C15] A track device structure, It comprises a semiconductor substrate, a first metal column, a second metal column, an insulating layer, a first protruding mass, and a first protruding mass. The first metal column is located on the semiconductor substrate, and when the maximum width of the first metal column is divided by the height of the first metal column, it is less than 4, and the height of the first metal column is between 20 μm and 300 μm. The second metal column is located on the semiconductor substrate, and when the maximum width of the second metal column is divided by the height of the second metal column, it is less than 4, and the height of the first metal column is between 20 μm and 300 μm. The insulating layer is located on the semiconductor substrate and covers the first metal column and the second metal column. The first protruding mass is located on the first metal column and the insulating layer, and is suitable for connection to a pre-formed external circuit. A line device structure characterized in that the second protruding mass is located on the second metal column and the insulating layer and is suitable for connection to a pre-formed external circuit, and the distance from the center point of the first protruding mass to the center point of the second protruding mass is between 10 μm and 250 μm. [C16] The line device structure according to C15, characterized in that the distance from the center point of the first protruding mass to the center point of the second protruding mass is between 100 μm and 200 μm. [C17] The line device structure according to C15, characterized in that the first metal column comprises a gold layer with a thickness of 20 μm to 300 μm. [C18] The line device structure according to C15, characterized in that the first metal column comprises a copper layer with a thickness of 20 μm to 300 μm. [C19] The line device structure according to C15, characterized in that the first metal column is provided with a gold layer between 10 μm and 30 μm in thickness. [C20] The line device structure according to C15, characterized in that the first metal column comprises a tin solder layer with a thickness of 10 μm to 150 μm. [C21] The line device structure according to C15, characterized in that the material of the first insulating layer contains polyimide. [C22] The line device structure according to C15, comprising a first metal structure located on a conductor base, a protective layer containing a silicon nitride compound located on the first metal structure, a second metal structure located on the protective layer, and a first pad located within the protective layer whose opening exposes the first metal structure, wherein the second metal structure comprises a second pad connected to the first pad, and the position of the first pad as seen from a top view is different from the position of the second pad as seen from a top view, and the first metal column is located on the second pad. [C23] The line device structure according to C15, comprising a first metal structure located on the first insulating layer and the first metal column, wherein the metal structure includes a pad connected to the first metal column, and the position of the pad as seen from a top view is different from the position of the second pad as seen from a top view, and the first protruding mass is located on the pad.

Claims

1. A circuit structure, Semiconductor substrate and A number of transistors on the aforementioned semiconductor substrate, A connection structure bonded to the semiconductor substrate, wherein the connection structure comprises a plurality of dielectric layers and a plurality of line layers. An insulating layer bonded to the uppermost of the plurality of dielectric layers comprising the connection structure, wherein the insulating layer comprises a nitride layer, and wherein a first opening in the insulating layer exposes the contact point of the connection structure. A first conductive layer bonded to the insulating layer on the contact point, wherein the first conductive layer is bonded to the contact point through the first opening, and wherein the first conductive layer has a thickness between 2 micrometers and 30 micrometers, is bonded to the contact point, and is bonded to the insulating layer. A first conductive column on the first conductive layer, wherein the first conductive column is in contact with the first conductive layer, and wherein the first conductive column is coupled to the contact point through the first conductive layer. A first polymer material on the first conductive layer, wherein the first polymer material is in contact with the side wall of the first conductive column, and wherein the first polymer material has a first surface at the same level as the second surface of the first conductive column. A second polymer material on the first polymer material, wherein the opening in the second polymer material exposes the second surface of the first conductive column. A second conductive layer bonded to the second surface of the first conductive column, on the surface of the second polymer material around the opening, and on the inner wall of the opening that exposes the second surface of the first conductive column, wherein the second conductive layer has a thickness between 400 Å and 7000 Å. The tin-containing solder on the second conductive layer, wherein the tin-containing solder is connected to the second conductive layer and connected to the first conductive layer through the first conductive column, and at least a portion of the tin-containing solder is in the opening that exposes the second surface of the first conductive column. The insulating layer further comprises a polymer layer, wherein a second opening in the polymer layer exposes the contact point, and the first conductive layer further comprises the polymer layer and the second opening. A circuit structure that includes the following features.

2. The circuit structure according to claim 1, further comprising a second conductive column bonded to the semiconductor substrate and located in the first polymer material, wherein the second conductive column has a third surface at the same horizontal level as the first and second surfaces, and the distance between the first conductive column and the second conductive column is between 10 micrometers and 250 micrometers.

3. The circuit structure according to claim 1, wherein the second circuit layer comprises electroplated copper.

4. The circuit structure according to claim 1, wherein the nitride layer has a thickness between 0.2 micrometers and 1.2 micrometers.

5. The circuit structure according to claim 1, wherein the first conductive layer is bonded to the insulating layer and further comprises a titanium-containing layer on the contact point, wherein the first conductive layer is further bonded to the titanium-containing layer.

6. The circuit structure according to claim 1, further comprising a copper layer and a nickel layer on the second surface, wherein the tin-containing solder is further bonded to the nickel layer.

7. The circuit structure according to claim 6, wherein the nickel layer has a thickness between 1 micrometer and 10 micrometers.

8. The circuit structure according to claim 1, wherein the tin-containing solder comprises a tin-silver alloy.

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