Conversion circuit

Abstract

To provide a conversion circuit that can reduce the layout area occupied by a latch circuit.SOLUTION: An A / D conversion circuit 1 converts an analog input signal Vin into numerical data using a pulse delay circuit 2, which is made up of multiple delay units DU connected in series, each of which inverts and delays a pulse signal to output it. Master latch circuits 21m, ..., and 24m hold the states of the delayed pulse group outputs P1, P2, P3, ..., and Pn output from the pulse delay circuit 2 using different clocks CK1, ..., and CK4. The slave latch circuits 21s, ..., and 24s hold the outputs of the master latch circuits 21m, ..., and 24m using a clock CK1.SELECTED DRAWING: Figure 1

Description

Technical Field

[0005] , , ,

[0001] The present disclosure relates to a conversion circuit that converts an analog input signal into numerical data using a pulse delay circuit formed by connecting a plurality of pulse delay units that output a delayed pulse signal.

Background Art

[0002] Conventionally, development of A / D conversion circuits has been underway to obtain high-resolution digital values and numerical data while simplifying their configurations (see, for example, Patent Document 1). The A / D conversion device described in Patent Document 1 constitutes a pulse delay circuit by serially connecting a plurality of delay units composed of various gate circuits, and supplies an analog input signal to be A / D converted as a power supply voltage to this delay unit, thereby configuring it as a time-domain processing type A / D conversion circuit.

[0003] ​​​​​​​​​​​​​​​​​​​​​​​​The A / D conversion circuit described in Patent Document 1 includes multiple latch circuits operating with a plurality of m (for example, 4) sampling clocks as a pulse position reading and holding unit, and each latch circuit controls the address of an encoder that digitizes the pulse position.

[0006] This A / D conversion circuit uses master-slave type D flip-flops as latch circuits, each operating independently with multiple sampling clocks. However, because each operates with its own separate clock signal, the number of clock wires increases, and the layout area occupied by the latch circuit increases. As a result, the circuit area occupied by the IC chip becomes larger.

[0007] In other words, a large layout area occupied by the latch circuit results in longer reading lines for the delayed pulse group, leading to increased parasitic components due to parasitic capacitance and resistance. As a result, the rise time of the latch input signal increases, the delayed pulse output waveform becomes blunted, and the latch circuit operates unstably. Miniaturization of CMOS process manufacturing technology can sometimes hinder the performance improvement effects of A / D conversion circuits.

[0008] The object of the present invention is to provide a conversion circuit that can reduce the layout area occupied by the latch circuit. [Means for solving the problem]

[0009] The invention described in claim 1 is a conversion circuit that converts an analog input signal into numerical data using a pulse delay circuit configured by connecting a plurality of delay units in series, which output a delayed pulse group from the delay units.

[0010] Multiple latch circuits each comprise a master latch circuit and a slave latch circuit. The master latch circuit maintains the output state of the delayed pulse group output from the pulse delay circuit using two distinct first clocks. The slave latch circuit maintains the output of the master latch circuit using a second clock. The conversion unit converts the output data from multiple slave latch circuits into numerical data.

[0011] Because multiple latch circuits are used, the increase in circuit area and power consumption can be suppressed without increasing the number of pulse delay circuits or the number of delay units within the pulse delay circuits. In this case, at least two of the multiple slave latch circuits are configured to hold output data by receiving a common input of a second clock based on a first clock. Since the slave latch circuits output data by receiving a common input of a second clock based on a first clock, the wiring of the second clock based on the wiring of the first clock can be used, and the number of clock wirings can be greatly reduced. This reduces the layout area occupied by the latch circuits. [Brief explanation of the drawing]

[0012] [Figure 1] Block diagram 1 schematically showing a part of the A / D conversion circuit according to the first embodiment. [Figure 2] An electrical diagram schematically showing the clock generation circuit used in the first embodiment. [Figure 3] Block diagram 2 schematically showing a part of the A / D conversion circuit according to the first embodiment. [Figure 4] Electrical configuration and wiring diagram of the latch circuit according to the first embodiment [Figure 5] Electrical configuration diagram of a master-slave type latch circuit used in the first embodiment [Figure 6] Time chart illustrating the operation of the latch circuit in the first embodiment [Figure 7] Electrical configuration and wiring diagram of a latch circuit in a comparative example. [Figure 8] Electrical configuration diagram of a master-slave type latch circuit used in the second embodiment [Figure 9]FIG. 1 of a block diagram schematically showing a partial configuration of an A / D conversion circuit according to the third embodiment [Figure 10] Timing chart for explaining the operation of the latch circuit in the third embodiment [Figure 11] FIG. 2 of a block diagram schematically showing a partial configuration of an A / D conversion circuit according to the third embodiment

Embodiments for Carrying Out the Invention

[0013] Hereinafter, some embodiments of the conversion circuit will be described with reference to the drawings. In each embodiment, substantially the same or similar parts are denoted by the same or similar reference numerals. For example, the same reference numerals are attached to the units and tens places, and other reference numerals are attached to the hundreds place, and the description thereof will be omitted as necessary. Each embodiment will be described centering on the characteristic parts.

[0014] (First Embodiment) The first embodiment will be described with reference to FIGS. 1 to 7. FIGS. 1 to 5 schematically show a time A / D (TAD: Time Analog to Digital Converter) type A / D conversion circuit 1. The A / D conversion circuit 1 is configured using a CMOS manufacturing process inside a semiconductor integrated circuit device such as a SoC (System On Chip) of a 5G communication device, and further, an IoT application system, in addition to a microcomputer mounted on an electronic control unit (hereinafter, ECU) of an automobile or a sensor product having a digital communication function with the ECU.

[0015] As shown in FIGS. 1 and 3, the A / D conversion circuit 1 includes a pulse delay circuit 2, a clock generation circuit 3, a pulse position digitization unit 4, and an adder 5. The A / D conversion circuit 1 inputs an analog input signal Vin output from a sensor or the like, and converts the analog input signal Vin into numerical data DTA having a digital value and outputs it. The pulse position digitization unit 4 is called L&E / S: Latch-&-Encoder and Subtractor.

[0016] <Description of the configuration of the pulse delay circuit 2> The pulse delay circuit 2 is configured by arranging only a plurality of n delay units DU that invert and delay a pulse in a ring shape and output it in series, and is called a ring delay line. n is an odd number, for example, 15.

[0017] Each delay unit DU is composed of gates G1 to Gn that each delay a pulse by a predetermined delay time Td and output it. Therefore, in the following description, one or more delay units may be denoted as "DU" or "G1"..."Gn". The pulse delay circuit 2 is configured to output the output of each delay unit DU to the pulse position digitizing unit 4.

[0018] An analog input signal Vin to be subjected to A / D conversion is input to each of the gates G1 to Gn as a power supply voltage, and each of the gates G1 to Gn outputs a signal that changes according to the analog input signal Vin. Any gate can be used as long as its delay time Td changes according to the analog input signal Vin, but as shown in FIG. 1, it is desirable to configure it using NAND gate G1, NOT gates G2...Gn.

[0019] The even-numbered NOT gates G2...Gn shown in FIG. 1 are connected in cascade, and the NAND gate G1 is connected to input the signal EN and the output of the last-stage NOT gate Gn.

[0020] The NOT gates G2...G15 are configured using a single-stage CMOS inverter in order to simplify the circuit configuration and shorten the delay time Td as much as possible to improve the time resolution.

[0021] When the signal EN is switched from the L level to the H level, the outputs of the odd-stage NAND gate G1, NOT gates G3, G5... switch from the H level to the L level, and the outputs of the even-stage NOT gates G2, G4... switch from the L level to the H level.

[0022] The delay unit DU is configured in a loop with only an odd number of stages overall, so the timing of the switch from L level to H level and from H level to L level shifts sequentially. By using this configuration, the pulse cycle speed can be changed in response to changes in the analog input signal Vin.

[0023] <Configuration of Clock Generation Circuit 3> As shown in Figure 2, the clock generation circuit 3 is configured by connecting inverter M1 to the front stage and inverters M2a...M2d to the rear stage in parallel, thereby outputting multiple sampling clocks CK1...CKm. Hereafter, sampling clocks CK1...CKm will be abbreviated as "clocks CK1...CKm". In this embodiment, the configuration m=4 is shown. In the configuration of Figure 2, inverter M1 is the first stage and inverters M2a...M2d are the second stage.

[0024] These multi-stage inverters M1, M2a…M2d are supplied with an analog input signal Vin as the power supply voltage. The clock generation circuit 3 generates multiple clocks CK1…CKm based on the sampling clock reference signals CKs, which are input as the reference clock and master clock. The sampling clock reference signals CKs are the main sampling clocks input from an external source.

[0025] The first-stage inverter M1 receives a sampling clock reference signal CKs, transmits pulses, and outputs them to the second-stage inverters M2a...M2d, which in turn transmit and output pulses. The gate widths and gate lengths of the p-channel and n-channel transistors in inverters M2a...M2d are different, so as to relatively change the rise time difference ΔTs of the clock edge. The clocks CK1, CK2...CKm are adjusted so that the rise time of the clock edge becomes progressively slower in this order.

[0026] Furthermore, the period Ts of clocks CK1…CKm is set to a constant time that is longer than the delay time Td of each delay unit DU, for example, several times longer than the delay time Td of one delay unit DU. Each clock CK1…CKm is set such that four times (=m times) the phase difference time Δt (see Figure 6) between adjacent clocks is equivalent to the delay time Td.

[0027] <Configuration of the pulse position digitization unit 4> As shown in Figure 1, the pulse position digitization unit 4 includes a NOT gate 20, latch circuits 21...24, and encoders 31...34. Also, as shown in Figure 3, the pulse position digitization unit 4 includes latches 41...44 and subtractors 51...54.

[0028] The NOT gates 20 shown in Figure 1 consist of n gates, each receiving the outputs P1…Pn of the n delay units DU as inputs. The latch circuits 21…24 have their inputs connected in common to the outputs of the NOT gates 20, and there are n sets of latch circuits, the same number as the outputs P1…Pn of the delay pulse group from the delay units DU. There are m latch circuits per set of latch circuits 21…24.

[0029] By providing m sets of latch circuits 21…24 in parallel for each of the outputs P1…Pn, each output P1…Pn can be held at timings of +Δt, +Δt×2, +Δt×3, and +Δt×4, which are further subdivided to 1 / m of the delay time Td of the delay unit DU. Therefore, by parallelizing the latch circuits 21…24 and holding the outputs P1…Pn at the timing of the generation of different clocks CK1…CK4, the time resolution can be increased without increasing the number of pulse delay circuits 2 or the number n of delay units DU within the pulse delay circuits 2.

[0030] Multiple latch circuits 21...24 are configured to hold the outputs P1...Pn of n delay units DU via NOT gates 20. Each of these multiple latch circuits 21...24 is configured by cascading master latch circuits 21m...24m and slave latch circuits 21s...24s, and latches the state of the output P1, P2, ..., Pn of the delayed pulse group output from the pulse delay circuit 2 via NOT gates 20 at the timing of the generation of m clocks CK1...CKm.

[0031] In particular, the master latch circuits 21m...24m maintain the state of the output P1, P2, ..., Pn of the delayed pulse group using different clocks CK1...CK4. These clocks CK1...CK4 correspond to the first clock. The slave latch circuits 21s...24s maintain the output Dm1...Dm4 of the master latch circuits 21m...24m at the timing of the generation of clock CK1. That is, the slave latch circuits 21s...24s maintain the state at the timing of the generation of clock CK1, which is included in a part of clock CK1...CK4. The clock CK1 used by the slave latch circuits 21s...24s corresponds to the second clock. Specific examples will be described later.

[0032] There are a total of m encoders 31...34. In this embodiment, there are four encoders 31...34. Encoder 31 encodes output data Do1, which has its outputs P1...Pn held by the latch circuit 21, at the timing of the generation of the sampling clock reference signal CKs. Encoder 32 encodes output data Do2, which has its outputs P1...Pn held by the latch circuit 22, at the timing of the generation of the sampling clock reference signal CKs. Encoder 33 encodes output data Do3, which has its outputs P1...Pn held by the latch circuit 23, at the timing of the generation of the sampling clock reference signal CKs.

[0033] Encoder 34 encodes output data Do4, which has been held by the latch circuit 24 with outputs P1...Pn, at the timing of the generation of sampling clock reference signals CKs. At this time, encoders 31...34 use the sampling clock reference signals CKs, which are the source of the clocks CK1...CKm, as the clock for reading the output data Do1...Do4 from the latch circuits 21...24. As a result, encoders 31...34 can quantify and output the arrival position of the pulses transmitted by the delay unit DU based on the outputs P1...Pn.

[0034] As shown in Figure 3, latches 41…44 are configured downstream of encoders 31…34. Latches 41…44 hold the output data O1…O4 from encoders 31…34 at the timing of the generation of the sampling clock reference signal CKs. Latches 41…44 store the data O1…O4 output from encoders 31…34 as the previous value by latching it.

[0035] Furthermore, subtractors 51…54 are configured after each of the encoders 31…34. The subtractors 51…54 subtract the previous value held in the latches 41…44 from the current value output from the encoders 31…34 and output the difference as numerical data DT1…DT4 to the adder 5. The adder 5 adds these numerical data DT1…DT4 and outputs numerical data DTA. The adder 5 generates "n+log2m" bit numerical data DTA by adding the m numerical data DT1…DT4 output by the pulse position digitization unit 4. Note that various processing units may be provided instead of the adder 5, and these processing units only need to output some numerical data DTA based on the subtraction results of the subtractors 51…54.

[0036] The conversion unit 60 is composed of the encoders 31...34, latches 41...44, and subtractors 51...54 mentioned above. The conversion unit 60 subtracts the previous output data and the current output data for the output data Do1...Do4 of the slave latch circuits 21s...24s and outputs the result to the adder 5 as numerical data DT1...DT4.

[0037] In the A / D conversion circuit 1 configured in this way, the delay time Td of each delay unit DU changes according to the magnitude of the signal voltage level of the analog input signal Vin. The higher the signal voltage level of the analog input signal Vin, the lower the on-resistance of the transistors constituting each delay unit DU, and therefore the shorter the delay time Td. Conversely, the lower the signal voltage level of the analog input signal Vin, the higher the on-resistance of the transistors constituting each delay unit DU, and therefore the longer the delay time Td. Consequently, the numerical data DT1...DT4 digitized by the pulse position digitization unit 4 also changes according to the magnitude of the signal voltage level of the analog input signal Vin, and numerical data DTA based on the numerical data DT1...DT4 corresponding to the analog input signal Vin can be obtained as A / D conversion data.

[0038] <Explanation of the significance of this embodiment> This embodiment is characterized by the configuration of the latch circuits 21...24, and therefore the significance of the configuration of the latch circuits 21...24 will be explained here. An enlarged view of the configuration of the latch circuits 21...24 is shown in Figure 4, and a specific example is shown in Figure 5. Here, the output level of the NOT gate 20 will be referred to as level Din. As shown in Figures 4 and 5, the multiple latch circuits 21...24 are each configured in a master-slave type, comprising a preceding master latch circuit 21m...24m and a succeeding slave latch circuit 21s...24s. Level Din is input to the master latch circuits 21m...24m.

[0039] The preceding master latch circuits 21m...24m are configured as static types that hold outputs Dm1...Dm4 with a feedback circuit using a NOT gate Gb. Since the element configurations of the master latch circuits 21m...24m are identical, they are denoted by the same reference numerals in Figure 5. In this embodiment, the subsequent slave latch circuits 21s...24s are also configured as static types that hold output data Do1...Do4 with a feedback circuit. Since the element configurations of the subsequent slave latch circuits 21s...24s are identical, they are denoted by the same reference numerals in Figure 5.

[0040] In the following, we will explain the wiring of the master latch circuit 21m and the slave latch circuit 21s as representative examples, and omit the wiring explanations for the other master latch circuits 22m...24m and the slave latch circuits 22s...24s.

[0041] The master latch circuit 21m comprises switches SW1 and SW2, and NOT gates Ga and Gb. One end of switch SW1 is input to level Din, and the other end of switch SW1 is connected to the input of NOT gate Ga. The output of NOT gate Ga is connected to the input of NOT gate Gb and is also input to one end of switch SW3 of the subsequent slave latch circuit 21s.

[0042] The output of the NOT gate Gb of the master latch circuit 21m is connected to one end of switch SW2, and the other end of switch SW2 is connected to the input of the NOT gate Ga. Switch SW1 is turned on by the negative edge CK1n of clock CK1 and turned off by the positive edge CK1p. Switch SW2 is turned on by the positive edge CK1p of clock CK1 and turned off by the negative edge CK1n.

[0043] Therefore, switches SW1 and SW2 operate complementaryly. When switch SW1 is ON, it outputs an inverted level of level Din to the subsequent slave latch circuit 21s, and when switch SW2 is ON, it turns off switch SW1. As a result, while switch SW1 is OFF, the master latch circuit 21m can maintain the level of output Dm1 regardless of changes in level Din.

[0044] On the other hand, the slave latch circuit 21s includes switches SW3 and SW4, and NOT gates Gc and Gd. One end of switch SW3 is connected to the output Dm1 of the preceding master latch circuit 21m, and the other end of switch SW3 is connected to the input of NOT gate Gc. The output of NOT gate Gc is connected to the input of NOT gate Gd, and its output is input to encoder 31 as output data Do1.

[0045] The output of the NOT gate Gd of the slave latch circuit 21s is connected to one end of switch SW4, and the other end of switch SW4 is connected to the input of the NOT gate Gc. Switch SW3 is turned on by the positive edge CK1p of clock CK1 and turned off by the negative edge CK1n. Switch SW4 is turned on by the negative edge CK1n of clock CK1 and turned off by the positive edge CK1p.

[0046] Therefore, switches SW3 and SW4 operate complementaryly. When switch SW3 is ON, the output data Do1 is the inverted level of the output Dm1 of the preceding master latch circuit 21m, and when switch SW4 is ON, switch SW3 is turned OFF. Therefore, while switch SW3 is OFF, the level of the output data Do1 of the slave latch circuit 21s can be maintained regardless of the output change of the master latch circuit 21m. The connections of the other master latch circuits 22m...24m and slave latch circuits 22s...24s are the same as described above, so their explanation is omitted.

[0047] As shown in Figure 5, all switches SW3 and SW4 in the slave latch circuits 21s to 24s are input to a common clock CK1, so all switches SW3 and SW4 in the slave latch circuits 21s to 24s operate synchronously on and off. On the other hand, each switch SW1 and SW2 in the master latch circuits 21m to 24m are input to different clocks CK1 and CK4, respectively.

[0048] Specifically, switch SW1 of the master latch circuit 22m is turned on by the negative edge CK2n of the clock CK2 and turned off by the positive edge CK2p. Switch SW2 of the master latch circuit 22m is turned on by the positive edge CK2p of the clock CK2 and turned off by the negative edge CK2n.

[0049] Furthermore, switch SW1 of the master latch circuit 23m is turned on by the negative edge CK3n of clock CK3 and turned off by the positive edge CK3p. Switch SW2 of the master latch circuit 23m is turned on by the positive edge CK3p of clock CK3 and turned off by the negative edge CK3n.

[0050] Furthermore, switch SW1 of the master latch circuit 24m is turned on by the negative edge CK4n of clock CK4 and turned off by the positive edge CK4p. Switch SW2 of the master latch circuit 24m is turned on by the positive edge CK4p of clock CK4 and turned off by the negative edge CK4n.

[0051] The preceding master latch circuits 21m...24m receive level Din at the timing of the negative edges CK1n...CK4n of the clocks CK1...CK4. Then, as shown in Figure 6, they hold level Din at the timing of the positive edges CK1p...CK4p of the clocks CK1...CK4, tlm1...tlm4. Subsequently, the slave latch circuits 21s...24s of each latch circuit 21...24 simultaneously latch the output data Do1...Do4 at timing tls.

[0052] Since the master latch circuits 21m...24m each hold their levels Din at the timings tlm1...tlm4 of the positive edges CK1p...CK4p of their respective clocks CK1...CK4, all the subsequent slave latch circuits 21s...24m will be able to hold their levels Din at their respective timings +Δt, +Δt×2, +Δt×3, and +Δt×4, even if they all share the same clock CK1 as input. This allows each latch circuit 21...24 to operate stably.

[0053] Furthermore, as mentioned above, encoders 31...34 use sampling clock reference signals CKs, which are the source of multiple clocks CK1...CKm, as the read clock. The output data Do1...Do4 of slave latch circuits 21s...24s is determined at timing tls. Therefore, encoders 31...34 can stably read the output data Do1...Do4 at the subsequent timing tEn and stably encode the output data Do1...Do4. All processing of the output data Do1...Do4 in the subsequent stages of encoders 31...34 can be performed using sampling clock reference signals CKs.

[0054] <Explanation of the comparative example> Figure 7 shows a comparative example corresponding to Figure 4. In this example, the same clocks CK1…CK4 as the operating clocks of the master latch circuits 21m…24m are used as the clocks that determine the latch timing of the slave latch circuits 21s…24s. With this configuration, it is necessary to provide four (=m) wires to connect the clock generation circuit 3 to the slave latch circuits 21s…24s. As a result, the number of wires connecting the clock generation circuit 3 to the latch circuits 21…24 becomes large and long, and these connection wires occupy a large amount of layout area.

[0055] In particular, with recent miniaturized CMOS process technologies, when using, for example, three-dimensional transistors (e.g., FinFETs, GAAs, etc.), the proportion of the clock wiring area in the total circuit increases as the CMOS process manufacturing technology becomes more miniaturized. Consequently, the area occupied by latch circuits 21...24 becomes relatively larger compared to the circuit area of ​​pulse delay circuit 2, which can lead to a decrease in operating performance and an increase in manufacturing costs.

[0056] <This embodiment> In contrast, in this embodiment, the clock CK1 is supplied so as a common input to all slave latch circuits 21s...24s that constitute the multiple latch circuits 21...24. Therefore, the single clock CK1 can be shared by all slave latch circuits 21s...24s. The output node of the clock CK1 can be connected to the slave latch circuits 21s...24s with a single wire.

[0057] This reduces the number of clock wires extending from the clock generation circuit 3 to the latch circuits 21...24, thereby reducing the layout area occupied by these clock wires, enabling miniaturization, and effectively improving pulse delay characteristics. Consequently, yield can be improved and costs can be reduced. Furthermore, adverse effects from parasitic components in the transmission wiring of clocks CK1...CK4 can be prevented, maintaining high operational reliability. In addition, the influence of parasitic elements associated with the reading wiring of the output P1...Pn of the delayed pulse group of the pulse delay circuit 2 can be reduced and prevented, allowing the latch circuit 21 to stably read the state of the output P1...Pn of the delayed pulse group.

[0058] According to this embodiment, since the pulse delay circuit is configured as a ring delay line in a ring shape, it can be miniaturized and the pulse delay characteristics can be improved.

[0059] Furthermore, since encoders 31...34 read data using the sampling clock reference signals CKs, which are the basis for the clocks CK1...CK4, they can stably read and encode the output data Do1...Do4 from the slave latch circuits 21s...24s.

[0060] (Second Embodiment) A second embodiment will be described with reference to Figure 8. The latch circuits 221...224 shown in Figure 8 include master latch circuits 21m...24m and slave latch circuits 221a...224a. In this embodiment, the subsequent slave latch circuits 221s...224s are configured as dynamic types that hold output data Do1...Do4 without a feedback circuit.

[0061] The slave latch circuits 221s...224s each include a switch SW3, a capacitor C1, and a NOT gate Gc. One end of the switch SW3 is connected to the output of the preceding master latch circuit 21m, and the other end of the switch SW3 is connected to the input of the NOT gate Gc. The output of the NOT gate Gc in each slave latch circuit 221s...224s is input to the subsequent encoders 31...34 as output data Do1...Do4, respectively.

[0062] Here, the NOT gate Gc is constructed, for example, by a CMOS inverter, and therefore has parasitic capacitance at its input. Although Figure 8 clearly shows the symbol for capacitor C1, capacitor C1 is a capacitance based on the gate input capacitance of the NOT gate Gc and the parasitic capacitance that occurs in the wiring from switch SW3 to the input of the NOT gate Gc. For this reason, it is not necessary to intentionally create a large layout area for capacitor C1.

[0063] This reduces the number of elements constituting the slave latch circuits 221s...224s compared to the previously described embodiment. In other words, the layout area occupied can be reduced by the amount of the constituent elements of the NOT gate Gd and switch SW4 described in the first embodiment. Moreover, the layout area occupied can be reduced by the amount of wiring connecting these constituent elements compared to the configuration of the first embodiment. This improves yield and reduces costs. Furthermore, it prevents adverse effects from parasitic components that parasitize the transmission wiring of clocks CK1...CK4, and maintains high operational reliability. Conversely, if there is sufficient layout area, the circuit arrangement can be modified to increase the capacitance of capacitor C1 and stabilize the output level voltage.

[0064] (Third embodiment) A third embodiment will be described with reference to Figures 9 to 11. In the first embodiment described above, the pulse delay circuit 2 was shown as a configuration in which delay units DU consisting of NAND gates G1 and NOT gates G2 to G15 were connected in a ring shape, but it is not limited to this configuration.

[0065] The delay units DU can be connected in series, and do not need to be connected in a ring shape. In other words, as illustrated in Figure 9 for the pulse delay circuit 302, it can be configured with an open delay line in which the delay units DU are arranged in a non-ring shape. The pulse delay circuit 302 is configured by connecting NOT gates G1a, G2...Gn in cascade, and these NOT gates G1a, G2...Gn are supplied with an analog input signal Vin as the power supply voltage.

[0066] When using such a pulse delay circuit 302, as illustrated in Figure 10, a pulse signal PA is transmitted from the first-stage delay unit DU for each period Ts of the clock reference signal CKs.

[0067] In this embodiment, each encoder 31...34 of the pulse position digitization unit 304 digitizes and outputs the number of delay units DU through which the pulse signal PA has passed, according to the phase difference between the generation timing of the input pulse signal PA that activates the pulse delay circuit 302 and the generation timing of each clock CK1...CK4.

[0068] Therefore, as shown in Figure 11, it is no longer necessary to provide the latches 41...44 and subtractors 51...54 described in the first embodiment in the pulse position digitization unit 304, allowing for a simpler circuit configuration. The other configurations are the same as those in the first or second embodiment described above, so their configuration descriptions are omitted. The conversion unit 360 in this embodiment is composed of encoders 31...34. As a result, the number of elements can be further reduced compared to the previously described embodiment, and the layout area for mounting the elements can be reduced.

[0069] According to this embodiment, since the pulse delay circuit is configured as an open-type open delay line, it is possible to miniaturize the circuit by eliminating the need for components used when it is configured in a ring shape (e.g., NAND gates, subtractors) and improve the pulse delay characteristics. This provides the same effects as the previously described embodiment, as well as additional advantages.

[0070] (Other embodiments) The embodiment is not limited to the one described above, and for example, the following modifications or extensions are possible. In the embodiment described above, gates G2 to G15 are shown as being composed of a single-stage CMOS inverter, but two CMOS inverters may be connected in cascaded order. In this case, the variation in the A / D conversion result can be suppressed compared to the configuration with a single-stage CMOS inverter.

[0071] In the first to third embodiments described above, a configuration was shown in which one clock CK1 is selected from a plurality of clocks CK1...CKm (where m=4) and supplied as a common input to all slave latch circuits 21s...24m, 221s...224s as the "second clock". However, it is also possible to provide multiple clocks for common input to the slave latch circuits 21s...24s, 221s...224s.

[0072] In other words, for example, one clock CK1 may be supplied to several slave latch circuits 21s and 22s, while another clock CK2 may be supplied to several other slave latch circuits 23s and 24s.

[0073] Alternatively, one clock (e.g., CK1) can be used to supply m-1 slave latch circuits (e.g., 21s, 22s, 23s), while another clock (e.g., CK2) can be used to supply another slave latch circuit (e.g., 24s). In other words, it is possible to supply up to m-1 slave latch circuits from one clock (e.g., CK1).

[0074] In the first embodiment, the master latch circuits 21m...24m hold the states of the delayed pulse group outputs P1, P2, ..., Pn using different clocks CK1...CK4, and the slave latch circuits 21s...24s hold the output of the master latch circuits 21m...24m using clock CK1. However, the invention is not limited to this configuration. Any clock based on clocks CK1...CK4 can be applied as the "second clock" for the common input according to the present invention. That is, as the "second clock" according to the present invention, one of the clocks CK1...CK4 may be used after undergoing a shaping process such as inversion.

[0075] To put it another way, any configuration is acceptable as long as at least two or more slave latch circuits (e.g., 21s, 22s) have a common input of a "second clock" based on a "first clock" and hold output data Do1...Do4.

[0076] When the number of parallel connections of latch circuits 21...24 per delay unit DU, i.e., m, is increased, the configuration of the above embodiment can be realized by shortening the time Δt, which corresponds to the phase difference between clocks CK1...CKm, according to the value of m. Since increasing m improves the resolution and accuracy, it is better to increase m as much as possible.

[0077] As described in Patent Document 1, a pulse count counter is provided after the pulse delay circuits 2 and 302 to count the number of pulse cycles. The difference between the numerical value of the previous pulse position and the numerical value of the current pulse position is calculated using subtractors 51...54, taking into account the value of the pulse count counter, to obtain the numerical data DTA.

[0078] The configurations and functions of the multiple embodiments described above may be combined. Embodiments in which some of the aforementioned embodiments are omitted to the extent that the problem is solved can also be considered embodiments. Furthermore, any conceivable embodiment that does not deviate from the essence of the invention as defined by the claims can also be considered embodiments.

[0079] This disclosure is described in accordance with the embodiments described above, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include one, more, or fewer of those elements, fall within the scope and concept of this disclosure. [Explanation of Symbols]

[0080] In the diagram, 2 is the pulse delay circuit, 3 is the clock generation circuit, 4 is the pulse position digitization unit, 60 and 360 are the conversion units, CK1 to CK4 are the sampling clocks, CKs are the sampling clock reference signals (master clock), and DU is the delay unit.

Claims

1. A conversion circuit that converts voltage (Vin) into numerical data (DTA) using a pulse delay circuit (2) which is configured by connecting a plurality of delay units (DU) in series to output a delayed pulse signal, and outputs a group of delayed pulses from the plurality of delay units, A plurality of latch circuits (21, 22, 23, 24) each comprising a master latch circuit (21m...24m) that holds the state of the output of the delayed pulse group (P1, P2, P3, ..., Pn) output from the pulse delay circuit using mutually different first clocks (CK1...CK4), and a slave latch circuit (21s...24s) that holds the output of the master latch circuit using a second clock (CK1), The system includes an encoder located downstream of the multiple slave latch circuits, and a conversion unit (60; 360) that converts the output data of the multiple slave latch circuits into numerical data, At least two of the plurality of slave latch circuits hold the output data by receiving the second clock based on the first clock as a common input. The plurality of latch circuits are a conversion circuit in which the slave latch circuits are immediately connected in cascading order after the master latch circuit.

2. The conversion circuit according to claim 1, wherein the master latch circuit is configured as a static type that holds the output with a feedback circuit, and the slave latch circuit is configured as a dynamic type that holds the output data without the feedback circuit.

3. The conversion circuit according to claim 1 or 2, wherein the pulse delay circuit is configured by a ring delay line in which the plurality of delay units are arranged in a ring shape.

4. The conversion circuit according to claim 1 or 2, wherein the pulse delay circuit is configured by an open delay line in which the plurality of delay units are arranged in a non-ring shape.

5. The conversion circuit according to any one of claims 1 to 4, wherein the second clock is supplied as a common input to all of the slave latch circuits constituting the plurality of latch circuits.

6. The conversion circuit according to any one of claims 1 to 5, wherein the encoder uses the first clock (CK1, CK2, ..., CKm) or the master clock (CKs) which is the source of the second clock (CK1) as the clock on which the encoder reads the output data.

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