High-speed multi-phase clock generation circuit and electronic equipment

Abstract

The utility model discloses a high-speed multi-phase clock generation circuit and electronic equipment, and belongs to the technical field of wired optical communication. The high-speed multi-phase clock generation circuit comprises a ring oscillator group 1, a phase insertion resistor group 2 and a bridging resistor group 3, the ring oscillator group 1 comprises four ring oscillators 10, and each ring oscillator 10 comprises four phase inverters 100 which are connected end to end and form a closed loop; in a ring oscillator 10, the output end of each phase inverter 100 is connected with a phase node, and the phase difference of clocks output by two adjacent phase nodes is 90 degrees; four phase insertion resistors 20 which are connected in series are inserted between the input end and the output end of each phase inverter 100, a phase node between every two adjacent phase insertion resistors 20 generates a clock phase, and the difference between the clock phases generated by every two adjacent phase nodes is 22.5 degrees; and phase nodes for outputting corresponding clock phases in the four ring oscillators 10 are connected and coupled through a bridging resistor 30.

Description

Technical Field

[0001] This application relates to the field of wired optical communication technology, and in particular to a high-speed multi-phase clock generation circuit and electronic device. Background Technology

[0002] Multiphase clock signal generation circuits have wide and important applications in analog and mixed-signal circuits. From RF transceivers, analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and ultra-high-speed analog-to-digital / digital-to-analog converters (ADDAs) to high-speed serializer-deserializer (SerDes) systems (e.g., 224G SerDes), many fields require high-speed, high-quality multiphase clock signals. For example, ultra-high-speed ADDAs and high-speed SerDes systems require sampling rates of 100 GS / s or higher, typically necessitating multiphase clock generation circuits to generate clocks with, for example, 8-phase, 16-phase, or 32-phase signals.

[0003] Traditional multi-phase clock generation circuits suffer from insufficient clock phase accuracy, introducing significant clock errors. Furthermore, limitations imposed by the minimum delay of a single inverter in the applied manufacturing process (e.g., a certain FinFET / CMOS process) restrict the maximum achievable sampling rate. Therefore, existing multi-phase clock generation circuits struggle to meet the demands of high sampling rates for multi-phase clocks. Utility Model Content

[0004] This application provides a high-speed multi-phase clock generation circuit and electronic device, which can solve the problem that existing multi-phase clock generation circuits are unable to cope with the high sampling rate multi-phase clock requirements.

[0005] To solve the above-mentioned technical problems, this application is implemented as follows:

[0006] In a first aspect, a high-speed multi-phase clock generation circuit is provided, comprising: a ring oscillator group 1, a phase-intercalation resistor group 2, and a bridging resistor group 3. The ring oscillator group 1 includes: four ring oscillators 10, each ring oscillator 10 including: four inverters 100 connected end-to-end to form a closed loop; the phase-intercalation resistor group 2 includes: multiple phase-intercalation resistors 20 with the same resistance value; and the bridging resistor group 3 includes: multiple bridging resistors 30; wherein:

[0007] In a ring oscillator 10:

[0008] The output of each inverter 100 is connected to a phase node, and each phase node outputs a clock phase. The clock phases output by two adjacent phase nodes are 90° out of phase.

[0009] Four interpolation resistors 20 connected in series are inserted between the input and output terminals of each inverter 100. The phase node between every two adjacent interpolation resistors 20 generates a clock phase, and the clock phases generated by two adjacent phase nodes between the four interpolation resistors 20 differ by 22.5°. Furthermore, the phase node between every two adjacent interpolation resistors 20 is connected to the corresponding phase nodes in the other three ring oscillators 10.

[0010] The phase nodes of the four ring oscillators 10 that output corresponding clock phases are connected and coupled through bridging resistors 30; wherein, the clock phases output by the phase nodes connected to the output terminals of the first inverters 100 in each of the four ring oscillators 10 are 0°, 22.5°, 45° and 67.5° respectively, and the output terminals of the inverters 100 of the four ring oscillators 10 are connected to the external output terminals, outputting 16 clock phases.

[0011] Secondly, an electronic device is provided, including: the high-speed multi-phase clock generation circuit as described above.

[0012] The high-speed multi-phase clock generation circuit and electronic device provided in this application embodiment consist of an inverter, resistor interpolation, and bridging resistor connected end to end, forming a 4-ring coupled + 4-resistor interpolation ring oscillator structure. Through the 4 interpolation resistors, the sampling period of the ADC / DAC corresponding to the delay of the inverter is increased from 2×Unit Interval (UI) to 4×UI, thereby significantly improving the sampling rate corresponding to the multi-phase clock generation circuit under the same process, which can meet the requirements of high sampling rate. In addition, the 4 inverters of each ring oscillator directly drive 4 phase nodes. After each ring oscillator rotates 22.5°, it outputs 4 clock phases. The 4 ring oscillators generate 16 uniform clock phases (interval of 22.5°), ensuring high-precision phase generation.

[0013] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description

[0014] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0015] Figure 1 A structural diagram of a high-speed multi-phase clock generation circuit provided in an exemplary embodiment of this application is shown;

[0016] Figure 2 A structural diagram of a high-speed multi-phase clock generation circuit provided in an application example of this application is shown;

[0017] Figure 3 A structural diagram of a high-speed multi-phase clock generation circuit provided in another application example of this application is shown;

[0018] Figure 4 A structural diagram of a high-speed multi-phase clock generation circuit provided in another application example of this application is shown. Detailed Implementation

[0019] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0020] To address the issue that existing multi-phase clock generation circuits suffer from insufficient clock phase accuracy, leading to significant clock errors, and the limitation imposed by the minimum delay of a single inverter in the applied process (e.g., a certain FinFET / CMOS process), the maximum achievable sampling rate is limited. Therefore, existing multi-phase clock generation circuits struggle to meet the demands of high sampling rates for multi-phase clocks. This application provides a high-speed multi-phase clock generation circuit and an electronic device including this circuit.

[0021] Figure 1 A structural diagram of a high-speed multi-phase clock generation circuit according to an exemplary embodiment of this application is shown. This high-speed multi-phase clock generation circuit is applied to an electronic device, which may be a wired optical digital signal processing (oDSP) device. For ease of description, the embodiments of this application use... Figure 1 Taking the high-speed multi-phase clock generation circuit shown as an example, this application will describe the high-speed multi-phase clock generation circuit. Those skilled in the art will understand that the embodiments of this application use... Figure 1 The high-speed multi-phase clock generation circuit shown is used as an example for illustration only and does not limit the scope of protection of the corresponding claims.

[0022] like Figure 1As shown, this high-speed multi-phase clock generation circuit includes: a ring oscillator group 1, a phase-intercalation resistor group 2, and a bridging resistor group 3. The ring oscillator group 1 includes four ring oscillators 10, each ring oscillator 10 including four inverters 100 connected end-to-end to form a closed loop. For example, the four inverters 100 of one ring oscillator 10 may be inverter A, inverter B, inverter C, and inverter D. The four inverters being connected end-to-end to form a closed loop means that the input terminal of inverter A is connected to the output terminal of inverter B, the input terminal of inverter B is connected to the output terminal of inverter C, the input terminal of inverter C is connected to the output terminal of inverter D, and the input terminal of inverter D is connected to the output terminal of inverter A, thus forming a closed loop. The phase-intercalation resistor group 2 includes multiple phase-intercalation resistors 20 with the same resistance value. The bridging resistor group 3 includes multiple bridging resistors 30.

[0023] In this embodiment, each ring oscillator 10 has the same structure. The following describes the process in conjunction with... Figure 1 The structure of one of the ring oscillators 10 is described in detail.

[0024] like Figure 1 As shown, in a ring oscillator 10:

[0025] The output of each inverter 100 is connected to a phase node, and each phase node outputs a clock phase. The clock phases output by two adjacent phase nodes differ by 90°. Thus, the four inverters 100 of a ring oscillator 10 directly drive the four phase nodes to generate four quadrature clock phases.

[0026] Four interpolation resistors 20 connected in series are inserted between the input and output of each inverter 100. A phase node between any two adjacent interpolation resistors 20 generates one clock phase, and the clock phases generated by two adjacent phase nodes of the four interpolation resistors 20 differ by 22.5°. Furthermore, the phase nodes between any two adjacent interpolation resistors 20 are connected to corresponding phase nodes in the other three ring oscillators 10. Compared to existing technologies, in this embodiment, inserting four interpolation resistors 20 between the input and output of each inverter 100 generates three clock phases, increasing the ADC / DAC sampling period corresponding to the inverter 100's delay from 2×UI to 4×UI, thereby meeting the requirements for a high sampling rate.

[0027] A ring oscillator 10 can generate 16 clock phases. Four clock phases are directly driven by four inverters 100, and 12 clock phases are generated by voltage division using interpolation resistors 20. Because of the different amplitudes and driving capabilities, using these 16 phases as a 16-phase clock would introduce a significant clock skew. Therefore, in this embodiment, the four ring oscillators 10, interpolated by interpolation resistors 20, are connected and coupled together through bridging resistors 30. The phase nodes between every two adjacent interpolation resistors 20 are connected to the corresponding phase nodes of the other three ring oscillators 10, and are directly driven by inverters 100. In this way, the slope, amplitude, and driving capability of the 16 phases generated by the four coupled ring oscillators 10 are all the same (without considering injection points), making it suitable as a 16-phase clock for ultra-high-speed ADDA.

[0028] The following is combined Figure 1 The connection structure of the four ring oscillators 10 is described in detail.

[0029] like Figure 1 As shown, the phase nodes of the four ring oscillators 10 that output corresponding clock phases are connected and coupled through bridging resistors 30. The clock phases output by the phase nodes connected to the outputs of the first inverters 100 in each of the four ring oscillators 10 are 0°, 22.5°, 45°, and 67.5°, respectively. The outputs of the inverters 100 of the four ring oscillators 10 are connected to an external output terminal, outputting 16 clock phases. In one application example, such as... Figure 2 As shown, the four ring oscillators 10 include: a first ring oscillator 11, a second ring oscillator 12, a third ring oscillator 13, and a fourth ring oscillator 14; the first inverter 101 is the first inverter of the first ring oscillator 11, and the clock phase output of the phase node connected to its output terminal is 0°; the fifth inverter 105 is the first inverter of the second ring oscillator 12, and the clock phase output of the phase node connected to its output terminal is 45°; the ninth inverter 109 is the first inverter of the third ring oscillator 13, and the clock phase output of the phase node connected to its output terminal is 22.5°; the thirteenth inverter 113 is the first inverter of the fourth ring oscillator 14, and the clock phase output of the phase node connected to its output terminal is 67.5°.

[0030] In one application example, the first ring oscillator 10 remains stationary, while the other three ring oscillators 10 are successively rotated by 22.5°. Specifically, the second ring oscillator 100 rotates 22.5° counterclockwise, and the clock phase output of the phase node connected to the output of its first inverter 100 is 22.5°. The third ring oscillator 10 continues to rotate counterclockwise by 22.5° based on the second ring oscillator 10, and the clock phase output of the phase node connected to the output of its first inverter 100 is 45°. The fourth ring oscillator 10 continues to rotate counterclockwise by 22.5° based on the third ring oscillator 10, and the clock phase output of its first inverter 100 is 45°. The clock phase output of the phase node connected to the output terminal 0 is 67.5°. Therefore, the clock phases of the first ring oscillator 10 are 0°, 90°, 180°, and 270°; the clock phases of the second ring oscillator 10 are 22.5°, 112.5°, 202.5°, and 292.5°; the clock phases of the third ring oscillator 10 are 45°, 135°, 225°, and 315°; and the clock phases of the fourth ring oscillator 10 are 67.5°, 157.5°, 247.5°, and 337.5°. This eliminates the phase competition problem between adjacent rings and reduces the overall phase error.

[0031] In this embodiment, the order of the four rings of the ring oscillator 10 is not limited, as long as the rotation angle of the four rings satisfies the clock phase configuration. In one application example, the clock phase output of the phase node connected to the output of the first inverter 100 of the first ring oscillator 10 can be 22.5°, the clock phase output of the phase node connected to the output of the first inverter 100 of the second ring oscillator 10 can be 0°, the clock phase output of the phase node connected to the output of the first inverter 100 of the third ring oscillator 10 can be 45°, and the clock phase output of the phase node connected to the output of the first inverter 100 of the fourth ring oscillator 10 can be 67.5°.

[0032] In the high-speed multi-phase clock generation circuit provided in this embodiment, a 4-ring coupled + 4-resistor interpolated ring oscillator structure is formed by inverters 100 connected end to end, resistor interpolation 20 and bridging resistor 30. The four inverters 100 of each ring oscillator 10 directly drive four phase nodes, and each ring oscillator 10 outputs four clock phases. The four ring oscillators generate 16 uniform clock phases (22.5° interval), ensuring high-precision phase generation.

[0033] In some embodiments, such as Figure 1As shown, the high-speed multi-phase clock generation circuit provided in this embodiment further includes an injection buffer 4. The injection buffer 4 is composed of two inverters. In some embodiments, the injection buffer 4 includes a first injection inverter 41 and a second injection inverter 42; the output terminal of the first injection inverter 41 is connected to the first injection terminal 10a of the target ring oscillator 10, and is used to send a first clock differential signal CKP to the first injection terminal 10a; the output terminal of the second injection inverter 42 is connected to the second injection terminal 10b of the target ring oscillator 10, and is used to send a second clock differential signal CKN to the second injection terminal 10b.

[0034] In this embodiment, the clock phases of the first clock differential signal CKP and the second clock differential signal CKN differ by 180°. The target ring oscillator 10 is any one of the four ring oscillators 10, and the first injection terminal 10a and the second injection terminal 10b are the phase nodes connected to the output terminals of any two inverters 100 in the target ring oscillator 10 whose output clock phases differ by 180°. Figure 1 The diagram shows that a first clock differential signal CKP is input at the first injection terminal 10a (output clock phase 0°) of the first ring oscillator, and a second clock differential signal CKN is input at the second injection terminal (output clock phase 180°) of the first ring oscillator. Those skilled in the art will understand that the embodiments of this application use... Figure 1 The differential signal injection method shown is used as an example for illustration only, and the embodiments of this application do not limit this.

[0035] In this embodiment, the injection buffer 4 can inject differential clock signals into the phase nodes connected to the outputs of any two inverters 100 whose output clock phases differ by 180° in any of the four ring oscillators 10. For example, a pair of clock differential signals can be injected into the phase nodes connected to the outputs of inverters 100 with output clock phases of 0° and 180°, or into the phase nodes connected to the outputs of inverters 100 with output clock phases of 90° and 270°, or into the phase nodes connected to the outputs of inverters 100 with output clock phases of 22.5° and 202.5°. This embodiment does not impose any limitations on this. By injecting differential clock signals into the phase nodes connected to the outputs of any two inverters 100 whose output clock phases differ by 180° in the ring oscillators 10 through the injection buffer 4, it can be ensured that the frequency of the ring oscillator is locked to an external clock source, and that the output phase is synchronized with the reference clock.

[0036] In some embodiments, the injection buffer 4 includes one or more. In this embodiment, a differential clock signal can be injected into one ring oscillator 10, or differential clock signals can be injected into four ring oscillators 10 simultaneously; this application embodiment does not impose any limitations on this. The advantage of injecting a differential clock signal into only one ring oscillator 10 is that it simplifies the injection control of the entire clock generation circuit. For example, when the first ring oscillator 10 receives an external differential clock injection, it is connected to the second ring oscillator 10, the second ring oscillator 10 and the third ring oscillator 10, and the third ring oscillator 10 and the fourth ring oscillator 10 through the bridging resistor 30. After receiving the external differential clock injection and being locked to a specific frequency and phase, the first ring oscillator 10 can transmit this frequency and phase information to other ring oscillators 10 through the coupling effect between the ring oscillators 10. This coupling mechanism allows the other three ring oscillators 10 to operate in a relatively stable and coordinated manner under the drive of the first ring oscillator 10, ultimately outputting a stable 16-phase clock signal with uniform phase distribution.

[0037] In some embodiments, such as Figure 1 As shown, the high-speed multi-phase clock generation circuit provided in this application embodiment further includes a latch circuit unit 5. In some embodiments, the latch circuit unit 5 is connected between two target phase nodes in each ring oscillator 10, and is used to lock the clock phase difference between the two target phase nodes in a steady state of 180°. The two target phase nodes are phase nodes connected to the output terminals of two inverters 100 in each ring oscillator 10 whose output clock phases differ by 180°. In this embodiment, each ring oscillator 10 has two sets of phase nodes connected to the output terminals of inverters 100 whose output clock phases differ by 180°. Therefore, each ring oscillator 10 requires two latch circuit units 5. For example, in the first ring oscillator 10, a latch circuit unit 5 is connected in series between the phase nodes connected to the output terminals of inverters 100 whose output clock phases are 0° and 180°, and another latch circuit unit 5 is connected in series between the phase nodes connected to the output terminals of inverters 100 whose output clock phases are 90° and 270°. Similarly, in the other three ring oscillators 10, latch circuit units 5 are also connected in series between the phase nodes connected to the output terminals of the inverters 100 with a 180° phase difference in their output clocks; this will not be elaborated further here. In some embodiments, the latch circuit unit 5 includes two latch inverters connected end-to-end to form a closed loop. The latch circuit unit 5, formed by connecting two latch inverters end-to-end, helps ensure a 180° phase difference between the target phase nodes in the ring oscillators 10, playing a crucial role in the stable oscillation and accurate phase output of the ring oscillators.

[0038] In some embodiments, the strength of the inverter 100 and the latch inverter in the latch circuit unit 5 are designed according to a preset ratio. For example, the strength ratio of the inverter 100 to the latch inverter is 4 / 1, which helps the ring oscillator 10 in this embodiment to start oscillating.

[0039] In some embodiments, the interpolation resistor 20 includes at least one of the following types: polysilicon resistor, MOSFET on-resistance, and layout trace parasitic resistance. In some embodiments, the bridging resistor 30 includes at least one of the following types: polysilicon resistor, MOSFET on-resistance, and layout trace parasitic resistance. A smaller bridging resistor 30 value helps to enhance the coupling between the four rings and resolve the problem of asynchrony among the four ring oscillators. In one application example, in a layout design of the high-speed multi-phase clock generation circuit provided in this application embodiment on a 4nm FinFET process, the bridging resistor 30 can be implemented using the trace parasitic resistance from layer M0 to layer M7 to minimize the inter-ring coupling resistance, thereby enhancing the coupling between the four rings and resolving the problem of asynchrony among the four ring oscillators.

[0040] In one application example, generally, after the high-speed multi-phase clock generation circuit provided in the embodiments of this application is initialized, such as Figure 1 The 4-ring coupled + 4-resistor interpolated ring oscillator shown initially starts oscillating (injection buffer 4 is closed at this time). After oscillation stabilizes, injection buffer 4 is opened, and injection locking is enabled. After injection locking stabilizes, as shown... Figure 1 The 4-ring coupled + 4-resistor phase-intercalation injection-locked ring oscillator shown can generate a 16-phase clock.

[0041] In the high-speed multi-phase clock generation circuit provided in this embodiment, a 4-ring coupled + 4-resistor interpolation ring oscillator structure is formed by inverters 100 connected end to end, resistor interpolation 20, and bridging resistors 30. Each ring oscillator 10's four inverters 100 directly drive four phase nodes, and each ring oscillator 10 outputs four clock phases. The four ring oscillators generate 16 uniform clock phases (22.5° intervals), ensuring high-precision phase generation. The four interpolation resistors 20 increase the ADC / DAC sampling period corresponding to the delay of the inverters 100 from 2×UI to 4×UI, thereby meeting the requirements of a high sampling rate.

[0042] Figure 2 A structural diagram of a high-speed multi-phase clock generation circuit provided in an application example of this application is shown below. Figure 2 In one application example, the high-speed multi-phase clock generation circuit provided in this application example is described in detail.

[0043] like Figure 2As shown, the four ring oscillators 10 include: a first ring oscillator 11, a second ring oscillator 12, a third ring oscillator 13, and a fourth ring oscillator 14; the four inverters 100 in the first ring oscillator 11 include: a first inverter 101, a second inverter 102, a third inverter 103, and a fourth inverter 104; the four inverters 100 in the second ring oscillator 12 include: a fifth inverter 105, a sixth inverter 106, a seventh inverter 107, and an eighth inverter 108; the four inverters 100 in the third ring oscillator 13 include: a ninth inverter 109, a tenth inverter 110, an eleventh inverter 111, and a twelfth inverter 112; and the four inverters 100 in the fourth ring oscillator 14 include: a thirteenth inverter 113, a fourteenth inverter 114, a fifteenth inverter 115, and a sixteenth inverter 116.

[0044] Each ring oscillator 10 includes 16 phase nodes, wherein the clock phases of two adjacent phase nodes differ by 22.5°.

[0045] The phase nodes in the first ring oscillator 11 are, in sequence, phase node CKA0, phase node CKA1, phase node CKA2, phase node CKA3, phase node CKA4, phase node CKA5, phase node CKA6, phase node CKA7, phase node CKA8, phase node CKA9, phase node CKA10, phase node CKA11, phase node CKA12, phase node CKA13, phase node CKA14, and phase node CKA15;

[0046] The phase nodes in the second ring oscillator 12 are, in order: phase node CKB0, phase node CKB1, phase node CKB2, phase node CKB3, phase node CKB4, phase node CKB5, phase node CKB6, phase node CKB7, phase node CKB8, phase node CKB9, phase node CKB10, phase node CKB11, phase node CKB12, phase node CKB13, phase node CKB14, and phase node CKB15.

[0047] The phase nodes in the third ring oscillator 13 are, in order: phase node CKC0, phase node CKC1, phase node CKC2, phase node CKC3, phase node CKC4, phase node CKC5, phase node CKC6, phase node CKC7, phase node CKC8, phase node CKC9, phase node CKC10, phase node CKC11, phase node CKC12, phase node CKC13, phase node CKC14, and phase node CKC15.

[0048] The phase nodes in the fourth ring oscillator 12 are, in order: phase node CKD0, phase node CKD1, phase node CKD2, phase node CKD3, phase node CKD4, phase node CKD5, phase node CKD6, phase node CKD7, phase node CKD8, phase node CKD9, phase node CKD10, phase node CKD11, phase node CKD12, phase node CKD13, phase node CKD14, and phase node CKD15.

[0049] The input terminal of the first inverter 101 is connected to the output terminal of the second inverter 102, the input terminal of the second inverter 102 is connected to the output terminal of the third inverter 103, the input terminal of the third inverter 103 is connected to the output terminal of the fourth inverter 104, and the input terminal of the fourth inverter 104 is connected to the output terminal of the first inverter 101; the output terminal of the first inverter 101 is connected to the phase node CKA0, and the output clock phase is 0°; the output terminal of the second inverter 102 is connected to the phase node CKA4, and the output clock phase is 90°; the output terminal of the third inverter 103 is connected to the phase node CKA8, and the output clock phase is 180°; the output terminal of the fourth inverter 104 is connected to the phase node CKA12, and the output clock phase is 270°.

[0050] The input of the fifth inverter 105 is connected to the output of the sixth inverter 106. The input of the sixth inverter 106 is connected to the output of the seventh inverter 107. The input of the seventh inverter 107 is connected to the output of the eighth inverter 108. The input of the eighth inverter 108 is connected to the output of the fifth inverter 105. The output of the fifth inverter 105 is connected to phase node CKB2, and the output clock phase is 45°. The output of the sixth inverter 106 is connected to phase node CKB6, and the output clock phase is 135°. The output of the seventh inverter 107 is connected to phase node CKB10, and the output clock phase is 225°. The output of the eighth inverter 108 is connected to phase node CKB14, and the output clock phase is 315°.

[0051] The input of the ninth inverter 109 is connected to the output of the tenth inverter 110. The input of the tenth inverter 110 is connected to the output of the eleventh inverter 111. The input of the eleventh inverter 111 is connected to the output of the twelfth inverter 112. The input of the twelfth inverter 112 is connected to the output of the ninth inverter 109. The output of the ninth inverter 109 is connected to phase node CKC1, and the output clock phase is 22.5°. The output of the tenth inverter 110 is connected to phase node CKC5, and the output clock phase is 112.5°. The output of the eleventh inverter 111 is connected to phase node CKC9, and the output clock phase is 202.5°. The output of the twelfth inverter 112 is connected to phase node CKC13, and the output clock phase is 292.5°.

[0052] The output of the thirteenth inverter 113 is connected to the input of the fourteenth inverter 114. The output of the fourteenth inverter 114 is connected to the input of the fifteenth inverter 115. The output of the fifteenth inverter 115 is connected to the input of the sixteenth inverter 116. The output of the sixteenth inverter 116 is connected to the input of the thirteenth inverter 113. The output of the thirteenth inverter 113 is connected to phase node CKD3, and the output clock phase is 67.5°. The output of the fourteenth inverter 114 is connected to phase node CKD7, and the output clock phase is 157.5°. The output of the fifteenth inverter 115 is connected to phase node CKD11, and the output clock phase is 247.5°. The output of the sixteenth inverter 116 is connected to the fifteenth phase node CKD15, and the output clock phase is 337.5°.

[0053] In some embodiments, the interpolation resistors 20 in the first ring oscillator 11 include 16. In this embodiment, four interpolation resistors 20 are inserted between the input and output terminals of the first inverter 101, and the phase nodes between two adjacent interpolation resistors 20 are phase nodes CKA1, CKA2, and CKA3; four interpolation resistors 20 are inserted between the input and output terminals of the second inverter 102, and the phase nodes between two adjacent interpolation resistors 20 are phase nodes CKA5, CKA6, and CKA7; four interpolation resistors 20 are inserted between the input and output terminals of the third inverter 103, and the phase nodes between two adjacent interpolation resistors 20 are phase nodes CKA9, CKA10, and CKA11; four interpolation resistors 20 are inserted between the input and output terminals of the fourth inverter 104, and the phase nodes between two adjacent interpolation resistors 20 are phase nodes CKA13, CKA14, and CKA15.

[0054] In some embodiments, the interpolation resistors 20 in the second ring oscillator 12 include 16. In this embodiment, four interpolation resistors 20 are inserted between the input and output terminals of the fifth inverter 105, and the phase nodes between two adjacent interpolation resistors 20 are phase nodes CKB3, CKB4, and CKB5; four interpolation resistors 20 are inserted between the input and output terminals of the sixth inverter 106, and the phase nodes between two adjacent interpolation resistors 20 are phase nodes CKB7, CKB8, and CKB9; four interpolation resistors 20 are inserted between the input and output terminals of the seventh inverter 107, and the phase nodes between two adjacent interpolation resistors 20 are phase nodes CKB11, CKB12, and CKB13; four interpolation resistors 20 are inserted between the input and output terminals of the eighth inverter 108, and the phase nodes between two adjacent interpolation resistors 20 are phase nodes CKB15, CKB0, and CKB1.

[0055] In some embodiments, the interpolation resistors 20 in the third ring oscillator 13 include 16. In this embodiment, four interpolation resistors 20 are inserted between the input and output terminals of the ninth inverter 109, and the phase nodes between two adjacent interpolation resistors 20 are phase nodes CKC2, CKC3, and CKC4; four interpolation resistors 20 are inserted between the input and output terminals of the tenth inverter 110, and the phase nodes between two adjacent interpolation resistors 20 are phase nodes CKC6, CKC7, and CKC8; four interpolation resistors 20 are inserted between the input and output terminals of the eleventh inverter 111, and the phase nodes between two adjacent interpolation resistors 20 are phase nodes CKC10, CKC11, and CKC12; four interpolation resistors 20 are inserted between the input and output terminals of the twelfth inverter 112, and the phase nodes between two adjacent interpolation resistors 20 are phase nodes CKC14, CKC15, and CKC0.

[0056] In some embodiments, the fourth ring oscillator 14 includes 16 intercalation resistors 20. In this embodiment, four intercalation resistors 20 are inserted between the input and output terminals of the thirteenth inverter 113, and the phase nodes between two adjacent intercalation resistors 20 are phase nodes CKD4, CKD5, and CKD6; four intercalation resistors 20 are inserted between the input and output terminals of the fourteenth inverter 114, and the phase nodes between two adjacent intercalation resistors 20 are phase nodes CKD8, CKD9, and CKD10; four intercalation resistors 20 are inserted between the input and output terminals of the fifteenth inverter 115, and the phase nodes between two adjacent intercalation resistors 20 are phase nodes CKD12, CKD13, and CKD14; four intercalation resistors 20 are inserted between the input and output terminals of the sixteenth inverter 116, and the phase nodes between two adjacent intercalation resistors 20 are phase nodes CKD0, CKD1, and CKD2.

[0057] like Figure 2 As shown, the four ring oscillators need to be connected by bridging resistor 30. The 16 phase nodes (CKA0 - CKA15) of the first ring oscillator 11 and the corresponding 16 phase nodes (CKB0 - CKB15) of the second ring oscillator 12 are connected by bridging resistor 30 respectively. Figure 2 Only four connections are shown in the diagram; in reality, there are 16 connections between the first ring oscillator 11 and the second ring oscillator 12. Similarly, the 16 phase nodes (CKB0-CKB15) of the second ring oscillator 12 are connected to the corresponding 16 phase nodes (CKC0-CKC15) of the third ring oscillator 13 via bridging resistor 30; and the 16 phase nodes (CKC0-CKC15) of the third ring oscillator 13 are connected to the corresponding 16 phase nodes (CKD0-CKD15) of the fourth ring oscillator 14 via bridging resistor 30.

[0058] like Figure 2As shown, the 16 phase nodes of the second ring oscillator 12, the third ring oscillator 13, and the fourth ring oscillator 14 are connected to the inverters at positions that are "rotated" compared to the first ring oscillator 11. They are rotated counterclockwise by 45°, 22.5°, and 67.5° respectively. Specifically, the clock phase output from the phase node connected to the first inverter (first inverter 101) of the first ring oscillator 11 is 0°, the clock phase output from the phase node connected to the first inverter (fifth inverter 105) of the second ring oscillator 12 is 45°, the clock phase output from the phase node connected to the first inverter (ninth inverter 109) of the third ring oscillator 13 is 22.5°, and the clock phase output from the phase node connected to the first inverter (thirteenth inverter 113) of the fourth ring oscillator 14 is 67.5°. Figure 2 As shown, in the first ring oscillator 11, the clock phases output by phase nodes CKA0, CKA4, CKA8, and CKA12 are directly driven by the first inverter 101, the second inverter 102, the third inverter 103, and the fourth inverter 104; in the second ring oscillator 12, the clock phases output by phase nodes CKB2, CKB6, CKB10, and CKB14 are directly driven by the fifth inverter 105, the sixth inverter 106, the seventh inverter 107, and the eighth inverter 108; in the third ring oscillator 13, the clock phases output by phase nodes CKC1, CKC5, and CKA4 are directly driven by the first inverter 101, the second inverter 102, the third inverter 103, and the fourth inverter 104; The clock phases output by CKC9 and CKC13 are directly driven by the ninth inverter 109, the tenth inverter 110, the eleventh inverter 111, and the twelfth inverter 112. In the fourth ring oscillator 14, the clock phases output by phase nodes CKD3, CKD7, CKD11, and CKD15 are directly driven by the thirteenth inverter 113, the fourteenth inverter 114, the fifteenth inverter 115, and the sixteenth inverter 116. These 16 clock phases, directly driven by inverters, have essentially the same signal amplitude, slope, and driving capability, constituting the 16 output clocks of this 4-ring coupled + 4-resistor interpolation injection-locked ring oscillator.

[0059] In this application example, two inverters INJ form an injection buffer, injecting a pair of differential clocks (CKP, CKN) into the two phase nodes CK0 and CK8 in the first ring oscillator 1. It should be noted that because phase nodes CK0 and CK8 are injection phases (i.e., the two inverters INJ inject differential clocks into CK0 and CK8 in the first ring oscillator 1), the signal amplitude of the clock phase generated by these two phase nodes is slightly higher than the signal amplitude of the other 14 output clock phases. However, this slight difference does not affect the application of this multi-phase clock generation circuit in ultra-high-speed ADDA (or ultra-high-speed SerDes) circuits.

[0060] In some embodiments, in a specific circuit implementation, the interpolation resistor 20 and the bridging resistor 30 can be poly resistors, the on-resistance of a MOSFET, or parasitic resistance of the layout traces. Additionally, Figure 2 The high-speed multi-phase clock generation circuit shown is only one possible implementation of the embodiments of this application. Other implementations are also feasible. For example, the connection order of the four ring oscillators can be different. The embodiments of this application do not limit this.

[0061] Figure 3 A structural diagram of a high-speed multi-phase clock generation circuit, illustrating another application example of this application, is shown below. Figure 3 In one application example, the high-speed multi-phase clock generation circuit provided in this application example is described in detail.

[0062] like Figure 3 This paper illustrates a 16-phase clock generation circuit utilizing a 4-ring coupled + 4-resistor phase-intercalation injection-locked ring oscillator, comprising four ring oscillators: ring A, ring B, ring C, and ring D. Two inverters INJ form an injection buffer, injecting a pair of differential clocks (CKP, CKN) into the phase node CKA of ring A of the ring oscillators. <0> and CKA <8> These two phases.

[0063] The four ring oscillators have the same structure. The structure of the ring oscillator will be described below using ring A as an example.

[0064] Four inverters D connected end-to-end form the main body of ring oscillator A. Two pairs of inverters F connected end-to-end are connected in series at phase nodes CKA. <0> with CKA <8> Between and phase nodes CKA <4> with CKA <12> Between, used to ensure phase node CKA <0> with CKA <8> The clock phases between them are 180° apart, and this ensures the phase node CKA. <4> with CKA <12> The clock phases are 180° apart. The addition of two pairs of inverters F helps this ring oscillator start oscillating. Here, the phase node CKA... <0> CKA <4> CKA <8> CKA <12> The output clock phases are 0°, 90°, 180°, and 270°. At the phase node CKA... <0> and CKA <4> Four resistors R1 of the same value are used for phase interpolation, at phase node CKA. <1> CKA <2> CKA <3> Three clock phases are generated, corresponding to 22.5°, 45°, and 67.5° respectively. Similarly, at the phase node CKA... <4> and CKA <8> Between, phase node CKA <8> and CKA <12> Between, and phase node CKA <12> and CKA <0> Four resistors R1 were also inserted between them for phase insertion. There are a total of 16 phase insertion resistors R1 in ring A. The 16 phase nodes of ring A (CKA) <0> CKA <1> , ..., CKA <15> A total of 16 clock phases are generated, with a phase difference of 22.5° between any two adjacent clock phases.

[0065] like Figure 3 As shown, these four ring oscillators need to be connected together via bridging resistor R2. The 16 phase nodes of ring A (CKA) <0> - CKA <15> The 16 phase nodes corresponding to the B ring (CKB) <0> - CKB <15> They are connected respectively through bridging resistor R2. Figure 3 Only four connections are shown in the diagram; there are actually 16 connections between ring A and ring B. Similarly, ring B has 16 phase nodes (CKB). <0> - CKB <15> The 16 phase nodes corresponding to the C ring (CKC) <0> - CKC <15> The 16 clock phases of ring C (CKC) are connected via bridging resistor R2. <0> - CKC <15> The 16 phase nodes corresponding to the D ring (CKD) <0> - CKD <15> They are connected respectively through bridging resistor R2. For example... Figure 3 As shown, the 16 phase nodes of rings B, C, and D, along with the position of their inverter D, are "rotated" compared to ring A (i.e., rings B, C, and D are "rotated" by 45°, 22.5°, and 67.5° respectively compared to ring A). Figure 3As shown, in ring A, phase node CKA <0> CKA <4> CKA <8> CKA <12> Directly driven by four inverters D in ring A; in ring B, phase node CKB <2> CKB <6> CKB <10> CKB <14> Directly driven by the four inverters D in ring B; in ring C, the phase node CKC <1> CKC <5> CKC <9> CKC <13> Directly driven by inverter D in ring C; in ring D, phase node CKD <3> CKD <7> CKD <11> CKD <15> The clock phases of the 16 phase nodes directly driven by inverters D in the D-ring are directly driven by inverters D. These 16 output clocks have essentially the same signal amplitude, slope, and driving capability, forming the 16 output clocks of this 4-ring coupled + 4-resistor interpolation injection locked ring oscillator. It should be noted here that, due to CKA... <0> and CKA <8> These are the injected phases. The amplitude of the clock signal output by these two phase nodes is slightly higher than that of the clock signal output by the other 14 phase nodes. However, this slight difference does not affect the application of the high-speed multi-phase clock generation circuit provided in this application example in ultra-high-speed ADDA (or ultra-high-speed Serdes) circuits.

[0066] In some embodiments, in a specific circuit implementation, resistors R1 and R2 can be poly resistors, the on-resistance of a MOSFET, or parasitic resistance of layout traces. Additionally, Figure 3 This is just one possible implementation of the embodiment of this application. Other implementations are also possible. For example, the connection order of ring A, ring B, ring C, and ring D can be different.

[0067] Figure 3 In the high-speed multi-phase clock generation circuit shown, if the resistance of R2 is large (approximately 500Ω - 1000Ω), the simulation reveals a problem of the four ring oscillators being out of sync (i.e., the four ring oscillators have different oscillation frequencies). Therefore, in one application example, another high-speed multi-phase clock generation circuit is provided. Figure 4 A structural diagram of a high-speed multi-phase clock generation circuit, illustrating another application example of this application, is shown below. Figure 4 In one application example, the high-speed multi-phase clock generation circuit provided in this application example is described in detail.

[0068] like Figure 4 As shown, the inter-ring coupling resistor R2 is replaced by the trace parasitic resistors R2a, R2b, R2c, R2d, R2ab, R2bc, and R2cd. Figure 4In the diagram, the vertical lines R2ab, R2bc, and R2cd represent three parasitic resistances of a trace, signifying a relatively upper-layer, wider trace (e.g., a 0.5µm wide M7 layer). This design results in relatively low resistance values ​​for R2ab, R2bc, and R2cd. Using a 4nm FinFET process, in a... Figure 4 In the layout design of the high-speed multi-phase clock generation circuit shown, the parasitic resistances of the traces R2ab, R2bc, and R2cd are all in the range of 15Ω - 20Ω. R2a, R2b, R2c, and R2d represent the parasitic resistance of the traces from layer M0 to layer M7 (excluding layer M7, but including the VIA resistor between layers M6 and M7). The parasitic resistances of the traces R2a, R2b, R2c, and R2d are approximately in the range of 80Ω - 100Ω. Figure 3 Compared to the high-speed multi-phase clock generation circuit shown, Figure 4 The high-speed multi-phase clock generation circuit shown has two advantages: (1) The inter-ring coupling resistors are composed of parasitic trace resistances, which can minimize the resistance value of the inter-ring coupling resistors, thereby enhancing the coupling between the four rings and solving the problem of asynchronous operation of the four ring oscillators. (2) Since the parasitic trace resistances R2ab, R2bc, and R2cd are relatively small (e.g., in the range of 15Ω - 20Ω), the coupling resistance values ​​between ring A and ring B, ring A and ring C, and ring A and ring D are close. Thus, the four rings (ring A, ring B, ring C, and ring D) are basically symmetrical, and their symmetry is higher than that of the rings in the range of 15Ω - 20Ω. Figure 3 The high-speed multi-phase clock generation circuit shown (assuming R2 has a resistance of approximately 500Ω - 1000Ω) is better, as it helps synchronize the four ring oscillators, and Figure 4 The high-speed multi-phase clock generation circuit shown outputs a 16-phase clock with a smaller phase error.

[0069] In specific implementation, adopt Figure 4 Simulation results of the layout design of the high-speed multi-phase clock generation circuit shown indicate that it can operate normally under typical conditions at an input clock frequency of 20 GHz, outputting a 16-phase 20 GHz clock, which can generate the 16-phase clock required for an ADC / DAC with a sampling rate of 320 GS / s. Under the same process, the high-speed multi-phase clock generation circuit provided in this application embodiment can significantly improve the sampling rate corresponding to the multi-phase clock generation circuit.

[0070] Furthermore, this embodiment also provides an electronic device, including: such as Figures 1 to 4 The high-speed multi-phase clock generation circuit shown in any embodiment. This electronic device is capable of achieving, for example... Figures 1 to 4 The high-speed multi-phase clock generation circuit shown in any embodiment achieves the same technical effect, and will not be described again here to avoid repetition.

[0071] The high-speed multi-phase clock generation circuit and electronic equipment provided in this embodiment constitute a 4-ring coupled + 4-resistor interpolation ring oscillator structure, consisting of inverters connected end-to-end, resistor interpolation, and bridging resistors. Through the 4 interpolation resistors, the sampling period of the ADC / DAC corresponding to the delay of the inverter is increased from 2×UI to 4×UI, thereby significantly improving the sampling rate corresponding to the multi-phase clock generation circuit under the same process, which can meet the requirements of high sampling rate. In addition, the 4 inverters of each ring oscillator directly drive 4 phase nodes. After each ring oscillator rotates 22.5°, it outputs 4 clock phases. The 4 ring oscillators generate 16 uniform clock phases (22.5° intervals), ensuring high-precision phase generation.

[0072] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the utility model disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the claims.

[0073] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A high-speed multiple-phase clock generation circuit, characterized by comprising: include: The ring oscillator group (1), the intercalation resistor group (2), and the bridging resistor group (3) are provided. The ring oscillator group (1) includes four ring oscillators (10), each ring oscillator (10) including four inverters (100) connected end-to-end to form a closed loop. The intercalation resistor group (2) includes multiple intercalation resistors (20) with the same resistance value. The bridging resistor group (3) includes multiple bridging resistors (30). In one of the ring oscillators (10): The output of each inverter (100) is connected to a phase node, and each phase node outputs a clock phase. The clock phases output by two adjacent phase nodes are 90° out of phase. Four interpolation resistors (20) connected in series are inserted between the input and output of each inverter (100). The phase node between every two adjacent interpolation resistors (20) generates a clock phase, and the clock phases generated by two adjacent phase nodes between the four interpolation resistors (20) differ by 22.5°. Furthermore, the phase node between every two adjacent interpolation resistors (20) is connected to the corresponding phase nodes in the other three ring oscillators (10). The phase nodes of the four ring oscillators (10) that output corresponding clock phases are connected and coupled through the bridge resistor (30); wherein, the clock phases output by the phase nodes connected to the output terminals of the first inverters (100) of the four ring oscillators (10) are 0°, 22.5°, 45° and 67.5° respectively, and the output terminals of the inverters (100) of the four ring oscillators (10) are connected to the external output terminals, outputting 16 clock phases.

2. The high-speed multi-phase clock generation circuit according to claim 1, characterized in that, Also includes: Inject buffer (4), where: The injection buffer (4) includes: a first injection inverter (41) and a second injection inverter (42); The output of the first injection inverter (41) is connected to the first injection terminal (10a) of the target ring oscillator (10) and is used to send a first clock differential signal to the first injection terminal (10a). The target ring oscillator (10) is any one of the four ring oscillators (10). The output of the second injection inverter (42) is connected to the second injection terminal (10b) of the target ring oscillator (10) for sending a second clock differential signal to the second injection terminal (10b); Wherein, the clock phase of the first clock differential signal and the clock phase of the second clock differential signal differ by 180°; the first injection terminal and the second injection terminal are phase nodes connected to the output terminals of the two inverters (100) in the target ring oscillator (10) whose output clock phases differ by 180°.

3. The high-speed multi-phase clock generation circuit according to claim 2, characterized in that, The injection buffer (4) includes one or more.

4. The high-speed multiphase clock generation circuit of claim 1, wherein, Also includes: A latching circuit unit (5) is connected between two target phase nodes in each of the ring oscillators (10) to lock the clock phase difference between the two target phase nodes in a steady state at 180°. The two target phase nodes are phase nodes connected to the output terminals of two inverters (100) in each ring oscillator (10) whose output clock phases differ by 180°.

5. The high-speed multi-phase clock generation circuit according to claim 4, characterized in that, The latch circuit unit (5) includes two latch inverters connected end to end to form a closed loop.

6. The high-speed multi-phase clock generation circuit according to claim 5, characterized in that, The strengths of the inverter (100) and the latch inverter are designed according to a preset ratio.

7. The high-speed multi-phase clock generation circuit according to claim 1, characterized in that, The type of the intercalation resistor (20) includes at least one of the following: polysilicon resistor, MOSFET on-resistance, and layout trace parasitic resistance.

8. The high-speed multi-phase clock generation circuit according to claim 1, characterized in that, The type of the bridging resistor (30) includes at least one of the following: polysilicon resistor, MOSFET on-resistance, and layout trace parasitic resistance.

9. The high-speed multi-phase clock generation circuit according to claim 1, characterized in that, The four ring oscillators (10) include: a first ring oscillator (11), a second ring oscillator (12), a third ring oscillator (13), and a fourth ring oscillator (14). The four inverters (100) in the first ring oscillator (11) include: first inverter (101), second inverter (102), third inverter (103), and fourth inverter (104). The four inverters (100) in the second ring oscillator (12) include: the fifth inverter (105), the sixth inverter (106), the seventh inverter (107), and the eighth inverter (108). The four inverters (100) in the third ring oscillator (13) include: the ninth inverter (109), the tenth inverter (110), the eleventh inverter (111), and the twelfth inverter (112). The four inverters (100) in the fourth ring oscillator (14) include: the thirteenth inverter (113), the fourteenth inverter (114), the fifteenth inverter (115), and the sixteenth inverter (116). Each of the ring oscillators (10) comprises 16 phase nodes, wherein the clock phases of two adjacent phase nodes differ by 22.5°. The input terminal of the first inverter (101) is connected to the output terminal of the second inverter (102), the input terminal of the second inverter (102) is connected to the output terminal of the third inverter (103), the input terminal of the third inverter (103) is connected to the output terminal of the fourth inverter (104), and the input terminal of the fourth inverter (104) is connected to the output terminal of the first inverter (101). The output of the first inverter (101) is connected to the phase node CKA0, and the output clock phase is 0°. The output of the second inverter (102) is connected to the phase node CKA4, and the output clock phase is 90°. The output of the third inverter (103) is connected to the phase node CKA8, and the output clock phase is 180°. The output of the fourth inverter (104) is connected to the phase node CKA12, and the output clock phase is 270°. The input terminal of the fifth inverter (105) is connected to the output terminal of the sixth inverter (106), the input terminal of the sixth inverter (106) is connected to the output terminal of the seventh inverter (107), the input terminal of the seventh inverter (107) is connected to the output terminal of the eighth inverter (108), and the input terminal of the eighth inverter (108) is connected to the output terminal of the fifth inverter (105). The output of the fifth inverter (105) is connected to the phase node CKB2, and the output clock phase is 45°. The output of the sixth inverter (106) is connected to the phase node CKB6, and the output clock phase is 135°. The output of the seventh inverter (107) is connected to the phase node CKB10, and the output clock phase is 225°. The output of the eighth inverter (108) is connected to the phase node CKB14, and the output clock phase is 315°. The input terminal of the ninth inverter (109) is connected to the output terminal of the tenth inverter (110), the input terminal of the tenth inverter (110) is connected to the output terminal of the eleventh inverter (111), the input terminal of the eleventh inverter (111) is connected to the output terminal of the twelfth inverter (112), and the input terminal of the twelfth inverter (112) is connected to the output terminal of the ninth inverter (109). The output of the ninth inverter (109) is connected to the phase node CKC1, and the output clock phase is 22.5°. The output of the tenth inverter (110) is connected to the phase node CKC5, and the output clock phase is 112.5°. The output of the eleventh inverter (111) is connected to the phase node CKC9, and the output clock phase is 202.5°. The output of the twelfth inverter (112) is connected to the phase node CKC13, and the output clock phase is 292.5°. The output terminal of the thirteenth inverter (113) is connected to the input terminal of the fourteenth inverter (114), the output terminal of the fourteenth inverter (114) is connected to the input terminal of the fifteenth inverter (115), the output terminal of the fifteenth inverter (115) is connected to the input terminal of the sixteenth inverter (116), and the output terminal of the sixteenth inverter (116) is connected to the input terminal of the thirteenth inverter (113). The output of the thirteenth inverter (113) is connected to the phase node CKD3, and the output clock phase is 67.5°. The output of the fourteenth inverter (114) is connected to the phase node CKD7, and the output clock phase is 157.5°. The output of the fifteenth inverter (115) is connected to the phase node CKD11, and the output clock phase is 247.5°. The output of the sixteenth inverter (116) is connected to the fifteenth phase node CKD15, and the output clock phase is 337.5°.

10. The high-speed multi-phase clock generation circuit according to claim 9, characterized in that, The intercalation resistors (20) in the first ring oscillator (11) include 16, of which: Four intercalation resistors (20) are inserted between the input and output terminals of the first inverter (101), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKA1, CKA2, and CKA3; four intercalation resistors (20) are inserted between the input and output terminals of the second inverter (102), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKA5, CKA6, and CKA7; four intercalation resistors (20) are inserted between the input and output terminals of the third inverter (103), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKA9, CKA10, and CKA11; four intercalation resistors (20) are inserted between the input and output terminals of the fourth inverter (104), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKA13, CKA14, and CKA15; The intercalation resistors (20) in the second ring oscillator (12) include 16, of which: Four intercalation resistors (20) are inserted between the input and output terminals of the fifth inverter (105), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKB3, CKB4 and CKB5; four intercalation resistors (20) are inserted between the input and output terminals of the sixth inverter (106), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKB7, CKB8 and CKB9; four intercalation resistors (20) are inserted between the input and output terminals of the seventh inverter (107), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKB11, CKB12 and CKB13; four intercalation resistors (20) are inserted between the input and output terminals of the eighth inverter (108), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKB15, CKB0 and CKB1; The intercalation resistors (20) in the third ring oscillator (13) include 16, of which: Four intercalation resistors (20) are inserted between the input and output terminals of the ninth inverter (109), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKC2, CKC3 and CKC4; four intercalation resistors (20) are inserted between the input and output terminals of the tenth inverter (110), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKC6, CKC7 and CKC8; four intercalation resistors (20) are inserted between the input and output terminals of the eleventh inverter (111), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKC10, CKC11 and CKC12; four intercalation resistors (20) are inserted between the input and output terminals of the twelfth inverter (112), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKC14, CKC15 and CKC0; The intercalation resistors (20) in the fourth ring oscillator (14) include 16, of which: Four intercalation resistors (20) are inserted between the input and output terminals of the thirteenth inverter (113), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKD4, CKD5 and CKD6; four intercalation resistors (20) are inserted between the input and output terminals of the fourteenth inverter (114), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKD8, CKD9 and CKD10; four intercalation resistors (20) are inserted between the input and output terminals of the fifteenth inverter (115), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKD12, CKD13 and CKD14; four intercalation resistors (20) are inserted between the input and output terminals of the sixteenth inverter (116), and the phase nodes between two adjacent intercalation resistors (20) are phase nodes CKD0, CKD1 and CKD2.

11. An electronic device, comprising: include: The high-speed multi-phase clock generation circuit as described in any one of claims 1 to 10.

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