A rapid detection system and method for zero-crossing of network voltage for motor train units

Abstract

The present application relates to a kind of motor train unit net pressure zero-crossing rapid detection system and method, system includes the net pressure acquisition circuit of acquisition analog net pressure signal, the analog-digital converter of the analog net pressure signal into digital net pressure signal, FPGA;FPGA is sampled to the digital net pressure signal sent by analog-digital converter, and the sampled digital net pressure signal is carried out sliding window filtering and FIR filtering and obtains the sine wave net pressure signal of frequency 50Hz;Zero-crossing detection module is set in FPGA, zero-crossing detection module is set to: when reaching the preset threshold T of continuous net pressure data greater than zero, mark Flag=1;When reaching the preset threshold T of continuous net pressure data less than zero, mark Flag=0;When the continuous preset threshold N packet net pressure data less than zero, then output zero-crossing interrupt signal.The present application can be real-time fast and accurately detect motor train unit net pressure zero-crossing, so that motor train unit still maintains normal operation in the case where net pressure distortion is serious.

Description

Technical Field

[0001] This invention belongs to the field of rail vehicle grid voltage detection technology, and relates to rail vehicle grid voltage zero-crossing detection technology. Specifically, it relates to a rapid detection system and method for grid voltage zero-crossing of EMU trains. Background Technology

[0002] During high-speed train operation, the grid voltage fluctuations are consistently large and significant harmonics exist in certain areas along the train's route (e.g., near Yumen South Station on the Lanzhou-Xinjiang High-Speed ​​Railway, specifically the section between kilometer markers 2440 and 2499). When trains pass through these areas, traction disconnection, flashing red signals, automatic disconnection, and main circuit breaker tripping faults are prone to occur. This is because grid-side harmonics affect the control of the four-quadrant converter. This impact is primarily reflected in the zero-crossing signal, which is crucial for control functions, as grid-side harmonics severely affect the accuracy of the zero-crossing signal. Inaccurate zero-crossing signals not only cause system oscillations but also lead to the failure of multiple four-quadrant controls, further amplifying grid harmonics.

[0003] Existing zero-crossing detection methods typically employ a comparator's zero-crossing detection circuit. This circuit uses voltage divider resistors to attenuate the AC signal to the comparator's positive input. When the AC input exceeds the zero reference voltage, the zero-crossing detection circuit changes the comparator's output state. This method has significant limitations. First, special attention must be paid to the comparator's input voltage range and protection circuitry to prevent hardware damage due to inadequate interface protection. Second, zero-crossing detection is unstable and has a significant delay; when the mains voltage harmonics are high, the zero-crossing point will shift, potentially resulting in multiple zero-crossings or even zero-crossing loss. Therefore, this method is not suitable for high-speed railway scenarios. Summary of the Invention

[0004] To address the aforementioned problems in the prior art, this invention provides a rapid detection system and method for zero-crossing voltage of high-speed trains, which can detect the zero-crossing voltage of high-speed trains in real time, quickly and accurately, with high reliability and stability, enabling high-speed trains to maintain normal operation even under severe voltage distortion.

[0005] In a first aspect, the present invention provides a rapid detection system for zero-crossing voltage of a high-speed train, comprising:

[0006] The mains voltage acquisition circuit is used to acquire the analog mains voltage signal of the EMU in real time.

[0007] Analog-to-digital converter, used to convert the acquired analog network voltage signal of the EMU into a digital network voltage signal;

[0008] FPGA, built-in:

[0009] The sampling module samples the digital mains voltage signal to obtain the sampled mains voltage signal;

[0010] The sliding window filtering module performs sliding window filtering on the sampled main voltage signal to obtain a main voltage signal with stable amplitude.

[0011] The FIR filter module filters the stable amplitude main voltage signal and restores it to a 50Hz sine wave main voltage signal.

[0012] The zero-crossing detection module has a Flag bit. The zero-crossing detection module is configured to: mark Flag = 1 when T consecutive network voltage data points are greater than zero, indicating that the current sine wave network voltage signal is in the rising phase; mark Flag = 0 when T consecutive network voltage data points are less than zero, indicating that the current sine wave network voltage signal is in the falling phase; and output a zero-crossing interrupt signal when N consecutive network voltage data points are less than zero.

[0013] In some embodiments, the mains voltage acquisition circuit includes:

[0014] A current transformer, connected in series with the overhead contact line, is used to detect the current in the contact line.

[0015] Signal processing circuit, including:

[0016] The current-limiting resistor R1 is connected to the current transformer to limit the current.

[0017] The sampling resistor R2 has one end connected to the current-limiting resistor R1 and the other end grounded to form a sampling voltage;

[0018] A low-pass filter circuit is connected to the output of the sampling resistor R2 to perform low-pass filtering on the sampled voltage;

[0019] The voltage conversion circuit is connected to the output of the low-pass filter circuit. Under the action of the reference voltage Vref, it converts the filtered sampled voltage into a voltage signal of 0-+Vref.

[0020] In some embodiments, the low-pass filter circuit is an RC filter circuit composed of a filter resistor R3 and a filter capacitor C1.

[0021] In some embodiments, the voltage conversion circuit includes:

[0022] The first operational amplifier circuit converts the filtered sampled voltage into a voltage signal of ±1 / 2·Vref;

[0023] Resistors R6 and R7 are connected in series. The end of resistor R6 that is not connected to resistor R7 is connected to the output of the first operational amplifier circuit, and the end of resistor R7 that is not connected to resistor R6 is connected to the reference voltage Vref, so as to convert the voltage signal of ±1 / 2·Vref into the voltage signal of 0-+Vref.

[0024] In some embodiments, the first operational amplifier circuit includes a first operational amplifier, the positive input of the first operational amplifier is connected to the output of the low-pass filter circuit and grounded through resistor R4, and the negative input of the first operational amplifier is connected to its output through resistor R5.

[0025] In some embodiments, the system further includes a second operational amplifier with its positive input connected between resistors R6 and R7, its negative input connected to its output, and its output connected to the input of the analog-to-digital converter, to isolate the voltage conversion circuit from the analog-to-digital converter.

[0026] In some embodiments, the FPGA is configured to: use MATLAB's fdatool to set the FIR filter module coefficients, set the FIR filter module coefficients as fixed-point outputs, and export the FIR filter module coefficients to generate a COE file; configure the IP core of the FIR filter module to generate the FIR filter module interface.

[0027] In a second aspect, the present invention provides a method for rapid detection of zero-crossing point of grid voltage in high-speed trains, the specific steps of which are as follows:

[0028] S1. Acquire the analog network voltage signal of the EMU and convert it into a digital network voltage signal;

[0029] S2. Sample the digital mains voltage signal to obtain the sampled mains voltage signal;

[0030] S3. Perform sliding window filtering on the sampled main voltage signal to obtain a main voltage signal with stable amplitude;

[0031] S4. Perform FIR filtering on the stable amplitude main voltage signal to restore the stable amplitude main voltage signal to a 50Hz sine wave main voltage signal;

[0032] S5. Set a Flag bit; when T consecutive network voltage data points reach a preset threshold and are greater than zero, mark Flag = 1 to indicate that the current sine wave network voltage signal is in the rising phase; when T consecutive network voltage data points reach a preset threshold and are less than zero, mark Flag = 0 to indicate that the current sine wave network voltage signal is in the falling phase; when N consecutive preset threshold network voltage data points are less than zero, output a zero-crossing interrupt signal.

[0033] In some embodiments, the specific steps of performing sliding window filtering on the sampled network voltage signal in step S4 are as follows: put the sampled network voltage signal into a window, the window stores n, 10≤n≤16 network voltage signals, remove the maximum and minimum values, and calculate the average value of the remaining n-2 data.

[0034] In some embodiments, the window adopts a data first-in-first-out (FIFO) mode. When a new network voltage signal enters the window, the earliest sampled network voltage signal is simultaneously removed from the window, and the average value of the data in the window at this time is recalculated.

[0035] Compared with the prior art, the advantages and positive effects of the present invention are as follows:

[0036] (1) The present invention provides a rapid detection system and method for zero-crossing of grid voltage for high-speed trains, which can detect the zero-crossing of grid voltage of high-speed trains in real time, quickly and accurately. It has high reliability and stability, and enables high-speed trains to maintain normal operation even when grid voltage distortion is severe.

[0037] (2) The present invention provides a rapid detection system and method for zero-crossing of grid voltage for EMU trains, which combines sliding window filtering and FIR filtering. The sliding window filtering removes noise interference, and the FIR filtering removes high-frequency grid voltage signals. The grid voltage data is stable and smooth, with high reliability. This avoids the occurrence of faults caused by abnormalities in the fixed-point signal required for four-quadrant phase calculation when the grid voltage signal has large harmonics.

[0038] (3) The fast detection system for zero-crossing voltage of the overhead contact line voltage of the EMU uses an analog-to-digital converter and an FPGA to detect the overhead contact line voltage and output the zero-crossing voltage interruption signal. It has a fast response speed, high sampling rate and small delay.

[0039] (4) The grid voltage zero-crossing rapid detection system for EMU trains of the present invention has a grid voltage acquisition circuit designed with resistors and operational amplifiers to sample current values ​​of different ranges. The grid voltage acquisition circuit has strong adaptability. Attached Figure Description

[0040] Figure 1 This is a structural block diagram of the high-speed train voltage zero-crossing rapid detection system according to an embodiment of the present invention;

[0041] Figure 2 This is a circuit diagram of the mains voltage acquisition circuit described in an embodiment of the present invention;

[0042] Figure 3 This is a schematic diagram illustrating the connection status between the analog-to-digital converter and the FPGA according to an embodiment of the present invention;

[0043] Figure 4 This is a flowchart of the sliding window filtering process described in an embodiment of the present invention;

[0044] Figure 5 This is a flowchart illustrating the configuration of the FIR filter module IP core in the FPGA according to an embodiment of the present invention;

[0045] Figure 6 This is a flowchart of the zero-crossing detection process described in an embodiment of the present invention;

[0046] Figure 7 This is a flowchart of the rapid detection method for zero-crossing voltage of the EMU (Electric Multiple Unit) according to an embodiment of the present invention.

[0047] In the diagram, 1 is the mains voltage acquisition circuit, 2 is the analog-to-digital converter, 3 is the FPGA, 4 is the sampling module, 5 is the sliding window filtering module, 6 is the FIR filtering module, and 7 is the zero-crossing detection module. Detailed Implementation

[0048] The present invention will now be described in detail through exemplary embodiments. However, it should be understood that, without further description, elements, structures, and features in one embodiment may be advantageously incorporated into other embodiments.

[0049] Due to the high speed of high-speed trains, the traction control system must also have a fast response speed. The four-quadrant rectifier control algorithm requires that the delay time of the grid voltage zero-crossing interruption signal not exceed 100µs, and there must be no offset, multiple zero-crossings, or loss of zero points. To ensure the real-time performance and accuracy of grid voltage zero-crossing detection, this invention provides a rapid grid voltage zero-crossing detection system and method for high-speed trains. This system can achieve real-time and rapid accurate detection of grid voltage zero-crossings, enabling high-speed trains to maintain normal operation even under severe grid voltage distortion. The following detailed description of the rapid grid voltage zero-crossing detection system and method for high-speed trains, with reference to the accompanying drawings, is provided below.

[0050] See Figure 1 This invention provides a rapid detection system for zero-crossing voltage of a high-speed train.

[0051] The mains voltage acquisition circuit 1 is used to acquire the simulated mains voltage signal of the EMU in real time.

[0052] Analog-to-digital converter 2 is used to convert the acquired analog network voltage signal of the EMU into a digital network voltage signal;

[0053] FPGA 3 includes: a sampling module 4, which samples the digital network voltage signal to obtain a sampled network voltage signal; a sliding window filtering module 5, which performs sliding window filtering on the sampled network voltage signal to obtain a stable amplitude network voltage signal; an FIR filtering module 6, which performs FIR filtering on the stable amplitude network voltage signal to restore the stable amplitude network voltage signal to a 50Hz sine wave network voltage signal; and a zero-crossing detection module 7, which has a Flag bit. The zero-crossing detection module is configured to: mark Flag = 1 when T consecutive network voltage data points are greater than zero, indicating that the current sine wave network voltage signal is in the rising phase; mark Flag = 0 when T consecutive network voltage data points are less than zero, indicating that the current sine wave network voltage signal is in the falling phase; and output a zero-crossing interrupt signal if N consecutive network voltage data points are less than zero.

[0054] It should be noted that since the sampling module samples a mains voltage signal with fluctuating amplitude, a sliding window filter module applies this fluctuating signal to obtain a stable mains voltage signal. Because the stable mains voltage signal has significant harmonics, an FIR filter module performs FIR filtering to restore the normally stable, harmonic-stricken mains voltage signal to a 50Hz sine wave. Combining sliding window filtering and FIR filtering removes noise interference and high-frequency signals, resulting in stable and smooth mains voltage data with high reliability. This avoids the fault caused by abnormalities in the fixed-point signal required for four-quadrant phase calculation when the mains voltage signal has large harmonics, which could lead to a four-quadrant overcurrent tripping of the main circuit breaker.

[0055] See Figure 2 In some embodiments, the mains voltage acquisition circuit includes:

[0056] A current transformer, connected in series with the overhead contact line, is used to detect the current in the contact line.

[0057] The signal processing circuit includes: a current-limiting resistor R1, connected to a current transformer, to limit the current; a sampling resistor R2, one end of which is connected to the current-limiting resistor R1 and the other end is grounded to form a sampling voltage; a low-pass filter circuit, connected to the output of the sampling resistor R2, to perform low-pass filtering on the sampling voltage; and a voltage conversion circuit, connected to the output of the low-pass filter circuit, which converts the filtered sampling voltage into a voltage signal of 0-+Vref under the action of a reference voltage Vref.

[0058] Specifically, the current-limiting resistor R1 is a 1Ω high-power current-limiting resistor. The sampling resistor R2 is a sampling resistor with an accuracy of 0.1%.

[0059] It should be noted that the 50Hz, ±25KV peak-to-peak contact network voltage (AC voltage) is transformed into a small current signal with a 50Hz frequency and ±300mA peak-to-peak value through a current transformer. This signal is the key input signal of the traction controller TCU and the only input signal for the traction controller TCU to detect the zero-crossing point of the network voltage.

[0060] See also Figure 2 In some embodiments, the low-pass filter circuit is an RC filter circuit composed of a filter resistor R3 and a filter capacitor C1. Low-pass filtering using the RC filter circuit removes high-frequency voltage signals from the voltage signal, improving the stability of the voltage signal.

[0061] See also Figure 2 In some embodiments, the voltage conversion circuit includes:

[0062] The first operational amplifier circuit converts the filtered sampled voltage into a voltage signal of ±1 / 2·Vref. The first operational amplifier circuit includes a first operational amplifier U1, the positive input of the first operational amplifier U1 is connected to the output of the low-pass filter circuit and grounded through resistor R4, and the negative input of the first operational amplifier U1 is connected to its output through resistor R5.

[0063] Resistors R6 and R7 are connected in series. The end of resistor R6 that is not connected to resistor R7 is connected to the output of the first operational amplifier circuit, and the end of resistor R7 that is not connected to resistor R6 is connected to the reference voltage Vref, so as to convert the voltage signal of ±1 / 2·Vref into the voltage signal of 0-+Vref.

[0064] The voltage conversion circuit converts the sampled voltage filtered by the low-pass filter circuit into a voltage signal of ±1 / 2·Vref through the first operational amplifier R1 and the configuration resistors R4 and R5. Then, through the configuration resistors R6 and R7, and under the action of the reference voltage Vref, the voltage signal of ±1 / 2·Vref is converted into a voltage signal of 0 to +Vref, ensuring that the complete measurement of the analog-to-digital converter is obtained.

[0065] See also Figure 2 In some embodiments, the detection system further includes a second operational amplifier U2, whose positive input is connected between resistors R6 and R7, whose negative input is connected to its output, and whose output is connected to the analog input of the analog-to-digital converter 2 to isolate the voltage conversion circuit from the analog-to-digital converter.

[0066] Specifically, see Figure 3 The analog input of the analog-to-digital converter (ADC) is connected to the output of the second operational amplifier U2. The reference voltage terminal of the ADC is connected to the reference voltage Verf. The voltage input of the ADC is connected to the power supply voltage Vin. The digital output of the ADC is connected to the input of the FPGA. The voltage input of the FPGA is connected to the power supply voltage Vin, which is the same as the power supply voltage of the ADC.

[0067] In some embodiments, the analog-to-digital converter (ADC) is a 16-bit SAR structure ADC with a 1MSPS sampling rate. This ADC is 50% faster and 3 times more accurate than similar products, and the package size is reduced by 40% for various applications. The current signal is converted into a voltage between 0V and Vref by the signal processing circuit. Vref is also the maximum voltage that the ADC can measure, achieving full-scale measurement and maximizing the utilization of the ADC function.

[0068] In some embodiments, the sampling module is a high-frequency clock, which samples the mains voltage signal at 20MHz.

[0069] SeeFigure 4 In some embodiments, when the FPGA performs sliding window filtering, the data sampled by the sampling module is placed into a window containing n, where 10 ≤ n ≤ 16 mains voltage signals. The maximum and minimum values ​​are removed, and the average of the remaining n-2 data points is calculated. This window uses a first-in, first-out (FIFO) data model. Whenever the FPGA samples a new mains voltage signal into the window, it simultaneously removes the earliest sampled mains voltage signal from the window and recalculates the average value of the data within the current window. Therefore, the FPGA can calculate a new average value with each sampling. Sliding window filtering ensures stable and smooth fluctuations in the sampled mains voltage signal and avoids logic errors caused by pulse interference.

[0070] In some embodiments, the window stores a total of 10 voltage signals. The maximum and minimum values ​​are removed, and the average of the remaining 8 data points is calculated. It should be noted that the number of voltage signals stored in the window is not limited to 10 and can be set according to actual needs to obtain a voltage signal with stable fluctuations.

[0071] In some embodiments, the FPGA is configured to: use MATLAB's fdatool tool to set the FIR filter module coefficients, set the FIR filter module coefficients as fixed-point outputs, and export the FIR filter module coefficients to generate a coe file; configure the IP core of the FIR filter module to generate the FIR filter module interface.

[0072] Specifically, the FIR filter module coefficients include the filter module sampling rate Fs, the filter module passband frequency Fpass, the filter module stopband frequency Fstop, the filter module passband attenuation Apass, and the filter module stopband attenuation Astop.

[0073] It should be noted that when setting the FIR filter module coefficients using MATLAB's fdatool tool, the appropriate filter module sampling rate Fs, passband frequency Fpass, stopband frequency Fstop, passband attenuation Apass, and stopband attenuation Astop should be set according to the actual situation of the EMU's overhead contact line voltage.

[0074] In some embodiments, see Figure 5When configuring the IP core of the FIR filter module, the FPGA loads the COE filter module coefficient file, selects the filter module type (e.g., single rate), configures the sampling frequency of the contact network voltage signal and the system clock frequency, configures the filter module coefficients to be signed numbers with a bit width of 16 bits, configures the filter module structure to be a symmetrical structure, configures the input signal to be signed numbers with a bit width of 8 bits, and finally configures the filter output signal to be full precision. The bit width will be automatically generated to 24 bits (i.e., 8-bit input + 16-bit filter module coefficients), and the FIR filter module interface will be generated.

[0075] By using FIR filtering, the mains voltage signal with severe harmonics is restored to the original 50Hz mains voltage signal.

[0076] See Figure 6 In some embodiments, the zero-crossing detection module 7 performs zero-crossing detection as follows:

[0077] The system evaluates the new data generated by the sliding window filter. When five consecutive network voltage data points (T=5) are greater than zero, a flag of Flag=1 is set, indicating that the current sine wave is in its rising phase. When five consecutive network voltage data points (T=5) are less than zero, a flag of Flag=0 is set, indicating that the current sine wave is in its falling phase. When three consecutive network voltage data points (N=3) are less than zero, a zero-crossing interrupt signal is output. It should be noted that the values ​​of the preset thresholds T and N can be set according to actual needs and are not limited to T=5 and N=3.

[0078] The above-described fast zero-crossing detection system for overhead contact line voltage in high-speed trains can detect the zero-crossing point of the overhead contact line voltage in real time with high reliability and stability, enabling high-speed trains to maintain normal operation even under severe overhead contact line voltage distortion. By combining sliding window filtering and FIR filtering, noise interference is filtered out through sliding window filtering, and high-frequency signals of the overhead contact line voltage are filtered out through FIR filtering. The overhead contact line voltage data is stable and smooth, with high reliability. This avoids the fault of four-quadrant overcurrent tripping due to abnormalities in the fixed-point signal required for four-quadrant phase calculation when the harmonics of the overhead contact line signal are large. The combined use of an analog-to-digital converter and an FPGA detects the overhead contact line voltage and outputs an overhead contact line voltage zero-crossing interrupt signal, resulting in fast response speed, high sampling rate, and low delay.

[0079] See Figure 7 This invention also provides a method for rapid detection of zero-crossing point of grid voltage for high-speed trains, the specific steps of which are as follows:

[0080] S1. Obtain the analog network voltage signal of the EMU and convert it into a digital network voltage signal;

[0081] S2. Sample the digital mains voltage signal to obtain the sampled mains voltage signal;

[0082] S3. Perform sliding window filtering on the sampled main voltage signal to obtain a main voltage signal with stable amplitude;

[0083] S4. Perform FIR filtering on the mains voltage signal to restore the mains voltage signal with stable amplitude to a 50Hz sine wave mains voltage signal;

[0084] S5. Set a Flag bit; when T consecutive network voltage data points reach a preset threshold and are greater than zero, mark Flag = 1, indicating that the current sine wave network voltage signal is in the rising phase; when T consecutive network voltage data points reach a preset threshold and are less than zero, mark Flag = 0, indicating that the current sine wave network voltage signal is in the falling phase; if there are N consecutive preset threshold network voltage data points less than zero, output a zero-crossing interrupt signal.

[0085] Specifically, the grid voltage acquisition circuit described in the above-mentioned high-speed train grid voltage zero-crossing point rapid detection system is used to acquire grid voltage signals. The grid voltage acquisition circuit can sample current values ​​of different ranges by configuring resistors and operational amplifiers, and has strong adaptability.

[0086] Specifically, the analog-to-digital converter described in the above-mentioned high-speed train network voltage zero-crossing rapid detection system is used to convert the network voltage signal into a digital network voltage signal.

[0087] Specifically, steps S2-S5 of the above-mentioned rapid detection system for zero-crossing voltage of high-speed trains are executed using FPGA.

[0088] The method combines analog-to-digital converter and FPGA to detect the contact network voltage and output the zero-crossing interrupt signal of the network voltage, which has a fast response speed, high sampling rate and small delay.

[0089] In some embodiments, in step S3, see Figure 4 The specific steps for sliding window filtering of the sampled network voltage signal are as follows: The sampled network voltage signal is placed into a window containing n network voltage signals. The maximum and minimum values ​​are removed, and the average of the remaining n-2 data points is calculated. For example, if the window contains 10 network voltage signals, the maximum and minimum values ​​are removed, and the average of the remaining 8 data points is calculated. It should be noted that the number of network voltage signals stored in the window is not limited to 10; it can be set according to actual needs to obtain a smooth and stable network voltage signal.

[0090] In some embodiments, the window adopts a first-in, first-out (FIFO) data model. When the FPGA acquires a new mains voltage signal into the window, it simultaneously removes the earliest acquired mains voltage signal from the window and recalculates the average value of the data in the window at that time. Therefore, the FPGA can calculate a new average value every time it performs a sampling.

[0091] Since the sampled network voltage signal is a network voltage signal with fluctuating amplitude, noise interference is filtered out by sliding window filtering. The network voltage signal with fluctuating amplitude is filtered by sliding window to obtain a network voltage signal with stable amplitude, which ensures that the fluctuation of the sampled network voltage signal is stable and smooth, and also avoids logical judgment errors caused by pulse interference.

[0092] Specifically, in some embodiments, an FIR filtering module is used for FIR filtering. During filtering, the filter module coefficients of the FIR filtering module need to be designed first. These coefficients include the filter module sampling rate Fs, the filter module passband frequency Fpass, the filter module stopband frequency Fstop, the filter module passband attenuation Apass, and the filter module stopband attenuation Astop. Then, the IP core of the filtering module is configured. Because the stable amplitude mains voltage signal obtained after sliding window filtering has severe harmonics, FIR filtering removes high-frequency signals, restoring the heavily harmonic mains voltage signal to its original 50Hz sine wave mains voltage signal. Combining sliding window filtering with FIR filtering results in stable and smooth mains voltage data with high reliability. This avoids the fault of four-quadrant overcurrent tripping due to abnormalities in the fixed-point signal required for four-quadrant phase calculation when the mains voltage signal has large harmonics.

[0093] In some embodiments, when setting the FIR filter module coefficients using the fdatool tool in MATLAB, appropriate filter module sampling rate Fs, passband frequency Fpass, stopband frequency Fstop, passband attenuation Apass, and stopband attenuation Astop are set according to the actual situation of the overhead contact line voltage of the EMU.

[0094] In some embodiments, see Figure 5 When configuring the IP core of the FIR filter module, the FPGA loads the COE filter module coefficient file, selects the filter module type (e.g., single rate), configures the sampling frequency of the contact network voltage signal and the system clock frequency, configures the filter module coefficients to be signed numbers with a bit width of 16 bits, configures the filter module structure to be a symmetrical structure, configures the input signal to be signed numbers with a bit width of 8 bits, and finally configures the filter output signal to be full precision. The bit width will be automatically generated to 24 bits (i.e., 8-bit input + 16-bit filter module coefficients), and the FIR filter module interface will be generated.

[0095] In some embodiments, in step S5, see Figure 5The system evaluates the new data generated by FIR filtering. When five consecutive network voltage data points are greater than zero (T=5), it marks Flag=1, indicating that the current sine wave is in its rising phase. When five consecutive network voltage data points are less than zero (T=5), it marks Flag=0, indicating that the current sine wave is in its falling phase. When three consecutive network voltage data points are less than zero (N=3), it outputs a zero-crossing interrupt signal. It should be noted that the values ​​of the preset thresholds T and N can be set according to actual needs, and are not limited to T=5 and N=3, to obtain an accurate zero-crossing interrupt signal.

[0096] The above-mentioned rapid detection method for zero-crossing point of grid voltage in high-speed trains can detect the zero-crossing point of grid voltage in real time with high reliability and stability, enabling high-speed trains to maintain normal operation even under severe grid voltage distortion. By combining sliding window filtering and FIR filtering, noise interference is filtered out through sliding window filtering, and high-frequency signals of the grid voltage are filtered out through FIR filtering. The grid voltage data is stable and smooth, with high reliability. This avoids the fault of four-quadrant overcurrent tripping due to abnormalities in the fixed-point signal required for four-quadrant phase calculation when the grid voltage signal harmonics are large.

[0097] The above embodiments are used to explain the present invention, but not to limit the present invention. Any modifications and changes made to the present invention within the spirit and scope of the claims shall fall within the protection scope of the present invention.

Claims

1. A rapid detection system for zero-crossing voltage of a high-speed train, characterized in that, include: The mains voltage acquisition circuit is used to acquire the analog mains voltage signal of the EMU in real time. Analog-to-digital converter, used to convert the acquired analog network voltage signal of the EMU into a digital network voltage signal; FPGA, built-in: The sampling module samples the digital mains voltage signal to obtain the sampled mains voltage signal; The sliding window filtering module performs sliding window filtering on the sampled main voltage signal to obtain a main voltage signal with stable amplitude. The FIR filter module performs FIR filtering on the stable amplitude main voltage signal to obtain a 50Hz sine wave main voltage signal; The zero-crossing detection module has a Flag bit. The zero-crossing detection module is configured to: mark Flag = 1 when T consecutive network voltage data points are greater than zero, indicating that the current sine wave network voltage signal is in the rising phase; mark Flag = 0 when T consecutive network voltage data points are less than zero, indicating that the current sine wave network voltage signal is in the falling phase; and output a zero-crossing interrupt signal when N consecutive network voltage data points are less than zero.

2. The rapid detection system for zero-crossing voltage of high-speed trains as described in claim 1, characterized in that, The mains voltage acquisition circuit includes: A current transformer, connected in series with the overhead contact line, is used to detect the current in the contact line. Signal processing circuit, including: The current-limiting resistor R1 is connected to the current transformer to limit the current. The sampling resistor R2 has one end connected to the current-limiting resistor R1 and the other end grounded to form a sampling voltage; A low-pass filter circuit is connected to the output of the sampling resistor R2 to perform low-pass filtering on the sampled voltage; The voltage conversion circuit is connected to the output of the low-pass filter circuit. Under the action of the reference voltage Vref, it converts the filtered sampled voltage into a voltage signal of 0-+Vref.

3. The rapid detection system for zero-crossing voltage of high-speed trains as described in claim 2, characterized in that, The low-pass filter circuit is an RC filter circuit composed of filter resistor R3 and filter capacitor C1.

4. The rapid detection system for zero-crossing voltage of high-speed trains as described in claim 2, characterized in that, The voltage conversion circuit includes: The first operational amplifier circuit converts the filtered sampled voltage into a voltage signal of ±1 / 2·Vref; Resistors R6 and R7 are connected in series. The end of resistor R6 that is not connected to resistor R7 is connected to the output of the first operational amplifier circuit, and the end of resistor R7 that is not connected to resistor R6 is connected to the reference voltage Vref, so as to convert the voltage signal of ±1 / 2·Vref into the voltage signal of 0-+Vref.

5. The rapid detection system for zero-crossing voltage of high-speed trains as described in claim 4, characterized in that, The first operational amplifier circuit includes a first operational amplifier. The positive input of the first operational amplifier is connected to the output of the low-pass filter circuit. The negative input of the first operational amplifier is connected to its output through resistor R5 and grounded through resistor R4.

6. The rapid detection system for zero-crossing voltage of high-speed trains as described in claim 5, characterized in that, It also includes a second operational amplifier, whose positive input is connected between resistors R6 and R7, whose negative input is connected to its output, and whose output is connected to the analog input of the analog-to-digital converter to isolate the voltage conversion circuit from the analog-to-digital converter.

7. The rapid detection system for zero-crossing voltage of high-speed trains as described in claim 1, characterized in that, The FPGA is configured to: use MATLAB's fdatool tool to set the FIR filter module coefficients, set the FIR filter module coefficients to fixed-point output, and export the FIR filter module coefficients to generate a coe file; Configure the IP core of the FIR filter module to generate the FIR filter module interface.

8. A method for rapid detection of zero-crossing point of grid voltage in high-speed trains, characterized in that, The specific steps are as follows: S1. Obtain the analog network voltage signal of the EMU and convert it into a digital network voltage signal; S2. Sample the digital mains voltage signal to obtain the sampled mains voltage signal; S3. Perform sliding window filtering on the sampled main voltage signal to obtain a main voltage signal with stable amplitude; S4. Perform FIR filtering on the mains voltage signal to restore the mains voltage signal with stable amplitude to a 50Hz sine wave mains voltage signal; S5. Set a Flag bit; when T consecutive network voltage data points reach a preset threshold and are greater than zero, mark Flag = 1, indicating that the current sine wave network voltage signal is in the rising phase; when T consecutive network voltage data points reach a preset threshold and are less than zero, mark Flag = 0, indicating that the current sine wave network voltage signal is in the falling phase; when N consecutive preset threshold network voltage data points are less than zero, output a zero-crossing interrupt signal.

9. The rapid detection method for zero-crossing point of grid voltage for high-speed trains as described in claim 8, characterized in that, In step S3, the specific steps for performing sliding window filtering on the sampled network voltage signal are as follows: put the sampled network voltage signal into a window, and store n, 10≤n≤16 network voltage signals in the window. Remove the maximum and minimum values, and calculate the average value of the remaining n-2 data.

10. The rapid detection method for zero-crossing point of grid voltage for high-speed trains as described in claim 9, characterized in that, The window adopts a data first-in-first-out (FIFO) mode. When a new network voltage signal enters the window, the earliest sampled network voltage signal is simultaneously removed from the window, and the average value of the data in the window at this time is recalculated.

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